Spatial correlation disordered silicon germanium nanowire thermoelectric refrigeration system for electronic equipment

Abstract

The invention discloses a space correlation disordered silicon germanium nanowire thermoelectric refrigeration system for electronic equipment, belongs to the technical field of heat dissipation of the electronic equipment, and particularly relates to a space correlation disordered silicon germanium (SiGe) nanowire-based thermoelectric refrigeration system. The problems that the bearing capacity of a traditional heat dissipation technology is insufficient, and the heat dissipation requirement of electronic equipment with the increased integration degree cannot be met are solved. The system comprises a hot end 1, a cold end 6 and a thermoelectric conversion module, the thermoelectric material layer 4 is used for responding to the direct current provided by the power supply driving circuit 5, generating a thermoelectric effect to generate a temperature difference at two ends, and enhancing a refrigeration effect; and the temperature difference between the two ends of the thermoelectric material layer 4 is adjusted by adjusting the current value of the direct current provided by the power supply driving circuit 5, so that the temperature difference between the hot end 1 and the cold end 6 is adjusted. The space correlation disordered silicon germanium nanowire thermoelectric refrigeration system for the electronic equipment is suitable for heat dissipation of the electronic equipment.

Description

Technical Field

[0001] The present invention relates to the technical field of heat dissipation of electronic equipment, and in particular to a thermoelectric cooling system based on spatially correlated disordered silicon germanium (SiGe) nanowires. Background Art

[0002] With the rapid development of modern electronic devices, especially high-performance computing devices, integrated circuits, and microelectronic components, the operating frequency and computing power of the devices are constantly increasing, and with it comes a lot of heat generated by the operation of the devices. Although traditional heat dissipation technologies, such as air cooling and liquid cooling, can reduce the temperature of the device to a certain extent, as the integration continues to increase, the heat dissipation demand gradually exceeds the carrying capacity of traditional heat dissipation methods. Therefore, the development of efficient thermoelectric cooling technology has become the key to solving the heat dissipation problem of electronic equipment.

[0003] Silicon-germanium (SiGe) alloy materials have broad application prospects in the field of thermoelectrics. Due to their good thermoelectric properties and compatibility with existing silicon-based devices, they have become a hot topic in current research. However, although traditional silicon-germanium (SiGe) alloy nanowires have certain thermoelectric properties, their relatively high thermal conductivity limits their application in thermoelectric refrigeration. Therefore, the development of new materials that can reduce thermal conductivity without sacrificing thermoelectric performance has become a current research focus. Summary of the invention

[0004] The purpose of the present invention is to provide a spatially correlated disordered silicon germanium nanowire thermoelectric cooling system for electronic devices, so as to solve the problem that the traditional heat dissipation technology has insufficient carrying capacity and cannot meet the heat dissipation needs of electronic devices with increased integration; at the same time, the thermoelectric cooling system adopts spatially correlated disordered silicon germanium nanowires to effectively reduce thermal conductivity, optimize thermoelectric performance, improve thermoelectric cooling efficiency, and is compatible with silicon-based materials, and can be widely used in the heat dissipation system of electronic devices.

[0005] The spatially correlated disordered silicon germanium nanowire thermoelectric cooling system for electronic devices of the present invention comprises a hot end, a cold end and a thermoelectric conversion module:

[0006] The hot end is connected to a heating chip in the electronic device and is used to absorb the heat generated by the electronic device;

[0007] The cold end is connected to the heat sink to absorb the heat from the hot end and dissipate the absorbed heat to the external environment through the heat sink;

[0008] The thermoelectric conversion module is arranged between the hot end and the cold end, and is used to adjust the temperature difference between the hot end and the cold end, so as to realize the heat dissipation and cooling management of the electronic equipment;

[0009] The thermoelectric conversion module comprises a heat-conducting layer, a thermoelectric material layer and a power drive circuit; the thermoelectric material layer is composed of spatially correlated disordered silicon germanium nanowires; in the spatially correlated disordered silicon germanium nanowires, the distribution of germanium atoms is spatially correlated disordered distribution;

[0010] The heat-conducting layer is disposed between the thermoelectric material layer and the hot end, and is used to enhance the transfer of heat from the hot end to the thermoelectric material layer;

[0011] The power drive circuit is used to provide direct current to the thermoelectric material layer;

[0012] The thermoelectric material layer is used to respond to the direct current provided by the power driving circuit, generate a thermoelectric effect to produce a temperature difference at its two ends, and enhance the cooling effect; it is also used to adjust the temperature difference at both ends of the thermoelectric material layer by adjusting the current value of the direct current provided by the power driving circuit, thereby adjusting the temperature difference between the hot end and the cold end.

[0013] Furthermore, a preferred embodiment is provided, in which the contact surface between the hot end and the heat generating chip is designed as a microstructure to increase the heat conduction area.

[0014] Furthermore, a preferred embodiment is provided, wherein the material of the heat conductive layer is a metal film or graphene.

[0015] Furthermore, a preferred embodiment is provided, wherein the diameter of the spatially correlated disordered silicon germanium nanowires is between 10 nm and 20 nm.

[0016] Furthermore, a preferred embodiment is provided, wherein the length of the spatially correlated disordered silicon germanium nanowire is 1 μm.

[0017] Furthermore, a preferred embodiment is provided, wherein the system further comprises a packaging plate; the packaging plate is arranged between the hot end and the thermoelectric conversion module.

[0018] Further, a preferred embodiment is provided, wherein the power driving circuit includes a power supply, an electrode and a current regulating device;

[0019] The power source is electrically connected to the thermoelectric material layer through the electrode, and is used to provide a direct current to the thermoelectric material layer;

[0020] The current regulating device is used to adjust the current value of the direct current provided by the power supply, thereby adjusting the temperature difference between the two ends of the thermoelectric material layer 4 through the thermoelectric effect.

[0021] Further, a preferred embodiment is provided, wherein the distribution of the germanium atoms is spatially correlated disordered distribution:

[0022] The spatial coordinates of germanium atoms are related to the distances between adjacent germanium atoms, and the correlation decays in a power law with the distance between germanium atoms:

[0023] C(r)~|r| -a

[0024] Where a is the correlation parameter and r is the distance between adjacent germanium atoms.

[0025] Furthermore, a preferred embodiment is provided, in the spatially correlated disordered silicon germanium nanowires, the concentration of germanium atoms is 10% to 20%.

[0026] Further, a preferred embodiment is provided, wherein the spatially correlated disordered silicon germanium nanowires are prepared by the following preparation process:

[0027] Materials selection step: Select silicon and germanium as the nanowire alloy components and adjust their ratio to achieve the desired degree of disorder;

[0028] Lattice matching and mismatching step: depositing a silicon-germanium alloy thin film on a substrate by an epitaxial growth method, wherein the lattice constant of the substrate is different from that of the silicon-germanium alloy, so as to introduce a lattice mismatch, thereby generating a spatially correlated disordered structure;

[0029] Heat treatment step: after the growth of the silicon germanium alloy film is completed by the epitaxial growth method, annealing is performed to adjust the disorder degree and correlation;

[0030] Patterning process: using electron beam lithography or nanoimprinting technology to define the nanowire pattern on the silicon germanium alloy film;

[0031] Etching process steps: Reactive ion etching technology is used to etch a nanowire structure on the silicon-germanium alloy film according to the nanowire pattern to complete the production of spatially correlated disordered silicon-germanium nanowires.

[0032] The present invention has the following beneficial effects:

[0033] 1. The spatially correlated disordered silicon-germanium nanowire thermoelectric cooling system for electronic devices described in the present invention uses spatially correlated disordered silicon-germanium alloy nanowires that can significantly reduce thermal conductivity through the design of disordered structures without affecting electrical conductivity, thereby achieving good thermoelectric performance; the thermoelectric cooling system is based on spatially correlated disordered silicon-germanium alloy nanowires, and provides an efficient thermal management solution for electronic devices through lower thermal conductivity, higher thermoelectric efficiency and good compatibility with silicon-based materials.

[0034] 2. The spatially correlated disordered silicon germanium nanowire thermoelectric cooling system for electronic devices described in the present invention uses spatially correlated disordered silicon germanium nanowires with significantly low thermal conductivity. The disordered arrangement structure reduces the thermal conductivity, improves the thermoelectric efficiency, and thus enhances the thermoelectric cooling effect.

[0035] 3. The spatially correlated disordered silicon germanium nanowire thermoelectric cooling system for electronic devices described in the present invention uses spatially correlated disordered silicon germanium nanowires that can achieve a larger temperature difference at a lower power and produce a stronger thermoelectric effect, so that the thermoelectric cooling system can obtain a higher cooling effect at a smaller current; by applying the thermoelectric cooling system to high-power electronic devices, the temperature of the device can be effectively controlled to avoid overheating damage, thereby improving the reliability and service life of the device.

[0036] 4. The spatially correlated disordered silicon germanium nanowire thermoelectric cooling system for electronic devices described in the present invention uses spatially correlated disordered silicon germanium nanowire materials that are compatible with existing silicon-based electronic devices, making them easy to integrate into existing devices, thereby reducing the cost of adapting the materials to traditional silicon-based integrated circuits.

[0037] 5. Compared with traditional heat dissipation methods, the spatially correlated disordered silicon germanium nanowire thermoelectric cooling system for electronic devices described in the present invention has higher cooling efficiency, reduces the demand for external energy, and has strong energy-saving and environmental protection advantages.

[0038] The spatially correlated disordered silicon germanium nanowire thermoelectric refrigeration system for electronic equipment of the present invention is suitable for dissipating heat for electronic equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0040] Figure 1 This is a schematic diagram of the structure of a spatially correlated disordered silicon germanium nanowire thermoelectric cooling system for electronic devices in one embodiment of the present invention;

[0041] Figure 2 A schematic diagram of the distribution of silicon and germanium elements in spatially correlated disordered silicon germanium nanowires in one embodiment of the present invention;

[0042] Figure 3 A schematic diagram showing a comparison of the spectral cumulative thermal conductivity of spatially correlated disordered silicon germanium nanowires and conventional randomly disordered silicon germanium nanowires in one embodiment of the present invention;

[0043] Figure numerals: 1. hot end; 2. packaging board; 3. heat conductive layer; 4. thermoelectric material layer; 5. power driving circuit; 6. cold end. DETAILED DESCRIPTION

[0044] In order to make the technical solutions and advantages of the present invention more clearly described, the specific implementation methods of the present invention will be further described in detail and completely in conjunction with the accompanying drawings. The various implementation methods described below are only part of the preferred solutions of the present invention, rather than all implementation methods; the various implementation methods described below are intended to explain the present invention and cannot be understood as limitations on the present invention; the reasonable combination of technical features defined in the various implementation methods of the present invention, and all other implementation methods obtained by ordinary technicians in the field without creative work based on the implementation methods of the present invention, are within the scope of protection of the present invention.

[0045] In one embodiment, a spatially correlated disordered silicon germanium nanowire thermoelectric cooling system for electronic devices is provided, the system comprising a hot end 1, a cold end 6 and a thermoelectric conversion module:

[0046] The hot end 1 is connected to a heat generating chip (such as a microprocessor or a power amplifier) ​​in an electronic device to absorb the heat generated by the electronic device;

[0047] The cold end 6 is connected to the heat sink, and is used to absorb the heat of the hot end 1 and dissipate the absorbed heat to the external environment through the heat sink;

[0048] The thermoelectric conversion module is arranged between the hot end 1 and the cold end 6, and is used to adjust the temperature difference between the hot end 1 and the cold end 6, so as to realize the heat dissipation and cooling management of the electronic equipment;

[0049] The thermoelectric conversion module comprises a heat conducting layer 3, a thermoelectric material layer 4 and a power driving circuit 5; the thermoelectric material layer is composed of spatially correlated disordered silicon germanium nanowires; in the spatially correlated disordered silicon germanium nanowires, the distribution of germanium atoms is spatially correlated disordered distribution;

[0050] The heat conducting layer 3 is disposed between the thermoelectric material layer 4 and the hot end 1 to enhance the transfer of heat from the hot end 1 to the thermoelectric material layer 4;

[0051] The power drive circuit 5 is used to provide direct current to the thermoelectric material layer 4;

[0052] The thermoelectric material layer 4 is used to respond to the direct current provided by the power driving circuit 5, produce a thermoelectric effect to produce a temperature difference at its two ends, and enhance the cooling effect; it is also used to adjust the temperature difference at both ends of the thermoelectric material layer 4 by adjusting the current value of the direct current provided by the power driving circuit 5, thereby adjusting the temperature difference between the hot end 1 and the cold end 6.

[0053] In this embodiment, efficient heat transfer is ensured by the cold end 6 .

[0054] In this embodiment, the cold end 6 is connected to a heat sink, and the heat sink is usually made of a high thermal conductivity material.

[0055] In this embodiment, the hot end 1 is connected to a heat generating chip in an electronic device. The heat generating chip is usually a power-intensive electronic component, such as a microprocessor, a power amplifier, and the like.

[0056] In this embodiment, the hot end 1 is made of high thermal conductivity material.

[0057] Furthermore, in one embodiment, the hot end 1 is made of copper or aluminum.

[0058] Furthermore, in one embodiment, the contact surface between the hot end 1 and the heat generating chip is designed as a microstructure to increase the heat conduction area.

[0059] In this embodiment, the microstructure refers to some regular or irregular geometric features designed on the surface of the material at the micrometer or nanometer scale, including micro protrusions, micro grooves, rough surfaces, etc., and the size range is usually between 1 micrometer and 100 micrometers. It can usually be achieved by photolithography, chemical etching or laser processing.

[0060] Furthermore, in one embodiment, the material of the heat conducting layer 3 is a metal film or graphene.

[0061] In this embodiment, the design requirement of the heat conducting layer 3 is high heat conduction efficiency to reduce heat loss and ensure that heat can be efficiently transferred to the thermoelectric material layer 4. The heat conducting layer 3 is made of a metal film with high thermal conductivity, or a new type of nanomaterial with high thermal conductivity such as graphene.

[0062] In this embodiment, the spatially correlated disordered silicon germanium nanowires can significantly reduce thermal conductivity while maintaining high thermoelectric performance and enhancing thermoelectric cooling effect. At the same time, the spatially correlated disordered silicon germanium nanowires have good compatibility with silicon-based materials and can be easily integrated with existing silicon-based electronic devices to solve the heat dissipation problem of high-power devices.

[0063] The spatially correlated disordered structure can effectively inhibit heat conduction and improve the thermoelectric conversion efficiency of the system. Specifically, the spatially correlated disordered silicon germanium nanowires achieve lower thermal conductivity by regulating their internal disordered structure.

[0064] The advantage of the spatially correlated disordered distribution structure is that it can effectively isolate heat flow and reduce heat loss, while retaining high electron mobility to achieve efficient thermoelectric conversion.

[0065] Furthermore, in one embodiment, the diameter of the spatially correlated disordered silicon germanium nanowires is between 10 nm and 20 nm, and the specific size is adjusted according to different application requirements.

[0066] Furthermore, in one embodiment, the length of the spatially correlated disordered silicon germanium nanowire is 1 μm, and the specific size is adjusted according to different application requirements.

[0067] Furthermore, in one embodiment, the surface of the cold end 6 is designed to be in the shape of a heat sink, increasing its surface area to improve heat dissipation efficiency.

[0068] Further, in one embodiment, the power drive circuit 5 includes a power supply, an electrode and a current regulating device;

[0069] The power source is electrically connected to the thermoelectric material layer 4 through the electrode, and is used to provide a direct current to the thermoelectric material layer 4;

[0070] The current regulating device is used to adjust the current value of the direct current provided by the power supply, thereby adjusting the temperature difference between the two ends of the thermoelectric material layer 4 through the thermoelectric effect.

[0071] In this embodiment, the power supply is used to stably output a suitable current and voltage to ensure the effective operation of the thermoelectric material layer 4 .

[0072] In this embodiment, the temperature difference between the two ends of the thermoelectric material layer 4 is controlled by adjusting the current value of the direct current, thereby controlling the cooling effect.

[0073] Furthermore, in one embodiment, the system further comprises a packaging plate 2; the packaging plate 2 is arranged between the hot end 1 and the thermoelectric conversion module.

[0074] In this embodiment, the packaging plate 2 is a protective component of the system, which mainly plays a supporting and fixing role. The packaging plate 2 can effectively prevent the influence of external pollution on the internal components of the system (such as the thermoelectric conversion module), and provide a good contact surface between the hot end 1 and the thermoelectric material layer 4, thereby ensuring the stability of the system.

[0075] Furthermore, in one embodiment, the packaging plate 2 is made of high-strength material to ensure structural stability.

[0076] Furthermore, in one embodiment, the packaging board 2 is made of a material with low thermal conductivity, such as ceramics, polymers, etc., which helps to reduce heat accumulation in the system itself.

[0077] In this embodiment, the operating principle of the spatially correlated disordered silicon germanium nanowire thermoelectric cooling system for electronic devices is based on the thermoelectric effect, which is as follows:

[0078] When current passes through the thermoelectric material layer 4, a temperature difference is generated at both ends of the thermoelectric material layer 4;

[0079] The hot end 1 is connected to the heat generating chip to transfer the heat from the chip to the thermoelectric material layer 4; while the cold end 6 is connected to the heat sink to discharge the heat;

[0080] The special disordered arrangement structure of spatially correlated disordered SiGe nanowires effectively suppresses the heat transport of low-frequency phonons, thereby reducing the thermal conductivity (significantly lower than that of traditional randomly disordered SiGe nanowires); at the same time, by adjusting the spatial position of atoms in the nanowires, the thermal conductivity is greatly reduced while the electrical conductivity is less affected, thereby achieving the effect of improving the thermoelectric efficiency, greatly reducing the efficiency of heat transfer in the system, thereby increasing the temperature difference and improving the cooling effect;

[0081] During operation, by adjusting the size of the (DC) current, the thermoelectric effect of the system can be controlled and the temperature difference between the hot end and the cold end can be adjusted, thereby achieving precise heat dissipation management of electronic equipment.

[0082] Further, in one embodiment, the distribution of the germanium atoms is a spatially correlated disordered distribution:

[0083] The spatial coordinates of germanium atoms are related to the distances between adjacent germanium atoms, and the correlation decays in a power law with the distance between germanium atoms:

[0084] C(r)~|r| -a

[0085] Where a is the correlation parameter and r is the distance between adjacent germanium atoms.

[0086] It should be noted that thermoelectric devices play an important role in managing heat and converting waste heat into electrical energy.

[0087] The efficiency of thermoelectric materials is quantified by the thermoelectric figure of merit:

[0088]

[0089] Where σ is the electrical conductivity, S is the Seebeck coefficient, T is the temperature, and κ is the thermal conductivity.

[0090] Improving thermoelectric figures of merit by manipulating electronic properties to change electrical conductivity is often complicated. Reducing lattice thermal conductivity is a simpler and more effective strategy without significantly changing other factors. By alloying with chemically similar elements (such as germanium), the lattice thermal conductivity of silicon can be reduced by at least an order of magnitude without significantly changing the electron transport coefficient.

[0091] It should be noted that the silicon-germanium alloy nanowires in current conventional thermoelectric devices often adopt a random and disordered structure, that is, the germanium atoms are randomly and disorderly distributed in the silicon nanowires. However, in nature, the inhomogeneity is often not completely randomly distributed, and the use of random and disordered distribution cannot truly reflect natural phenomena. At the same time, silicon nanowires with random and disordered distribution structures still have limitations in reducing thermal conductivity, making it difficult to meet the needs of efficient thermoelectric conversion.

[0092] It should be noted that in nature, inhomogeneities are often not completely randomly distributed, but are correlated over larger distances, that is, the correlation decays in a power law with the interatomic distance (such as the distance between adjacent germanium atoms) rather than exponentially; the spatially correlated disordered distribution reflects real natural phenomena.

[0093] In this embodiment, if the correlation parameter a is smaller than the spatial dimension, the correlation is considered to be long-range.

[0094] In this embodiment, germanium atoms with spatially correlated distribution are introduced into pure silicon nanowires to form spatially correlated disordered silicon germanium nanowires.

[0095] Further, in one embodiment, the spatially correlated disordered silicon germanium nanowires are prepared using the following preparation process:

[0096] Material selection step: Select silicon (Si) and germanium (Ge) as the nanowire alloy components and adjust their ratio to achieve the desired degree of disorder;

[0097] Lattice matching and mismatching step: a silicon-germanium alloy thin film is deposited on a substrate with a specific lattice constant by an epitaxial growth method, and a lattice mismatch is introduced on the substrate, thereby generating a spatially correlated disordered structure (i.e., the distribution of germanium atoms is spatially correlated disordered distribution);

[0098] Heat treatment step: after the growth of the silicon germanium alloy film is completed by the epitaxial growth method, annealing is performed to adjust the disorder degree and correlation;

[0099] Patterning process: using electron beam lithography or nanoimprinting technology to define the nanowire pattern on the silicon germanium alloy film;

[0100] Etching process steps: Reactive ion etching (RIE) technology is used, using appropriate gases (such as chlorine or fluoride) to etch a nanowire structure on the silicon-germanium alloy film according to the nanowire pattern, thereby completing the production of spatially correlated disordered silicon-germanium nanowires.

[0101] It should be noted that regarding the lattice matching and mismatching steps: ideally, the lattice constants of the epitaxially grown film and the substrate should be completely matched to avoid stress and defects caused by lattice mismatch. However, in this step, the goal is not to achieve complete lattice matching, but to introduce a disordered structure through a specific mismatch.

[0102] Furthermore, in one embodiment, the lattice mismatch is introduced on the substrate by selecting a substrate with a lattice constant different from that of the silicon-germanium alloy (ie, a substrate with a specific lattice constant), thereby introducing stress and defects to form a spatially correlated disordered structure.

[0103] In this embodiment, by selecting a substrate with a lattice constant different from that of the silicon-germanium alloy (i.e., a substrate with a specific lattice constant), the difference in lattice constants is used to cause stress and defects to be generated between the film and the substrate during the growth process. These stresses and defects propagate in the film to form a spatially correlated disordered structure; it is this disordered structure that gives silicon-germanium nanowires unique physical and chemical properties.

[0104] Further, in one embodiment, in the heat treatment step, the annealing treatment is performed at a temperature ranging from 600° C. to 800° C. and lasts for 30 minutes to 2 hours.

[0105] In this embodiment, the heat treatment step helps to adjust the degree of disorder and correlation to optimize the performance of the nanowires.

[0106] Further, in one embodiment, in the lattice matching and mismatching step, the material of the substrate with the specific lattice constant is silicon or sapphire.

[0107] Further, in one embodiment, in the lattice matching and mismatching steps, the substrate with the specific lattice constant needs to be thoroughly cleaned and surface treated to ensure high-quality epitaxial growth.

[0108] Furthermore, in one embodiment, in the lattice matching and mismatching steps, the epitaxial growth method is molecular beam epitaxy (MBE) or chemical vapor deposition (CVD) technology, and the epitaxial growth is performed under high vacuum conditions.

[0109] In this embodiment, the molecular beam epitaxy (MBE) is a technology that precisely controls the beam of raw material molecules or atoms under ultra-high vacuum conditions to perform epitaxial growth on the substrate surface. In the MBE process, source materials of silicon (Si) and germanium (Ge) (such as silane SiH4 and germanium GeH4, or their cracking products) are heated to evaporate to form molecular beams or atomic beams. These beams are guided and deposited on the substrate that has been cleaned and pre-treated after passing through a precise mass flow controller and shutter system.

[0110] The advantages of MBE technology include:

[0111] High precision: The growth rate and composition of the film can be precisely controlled.

[0112] Low temperature growth: Usually carried out at lower temperatures, which helps to reduce the impact of thermal stress on film quality.

[0113] Good interface control: films with steep interfaces and excellent crystal quality can be grown.

[0114] In this embodiment, the chemical vapor deposition (CVD) is a technology for generating solid materials on the surface of a substrate through chemical reactions. In the CVD process, gaseous precursors containing silicon (Si) and germanium (Ge) elements (such as silane SiH4 and germanium GeH4) are introduced into a reaction chamber and chemically react on the heated substrate surface to generate a solid silicon-germanium alloy film.

[0115] The advantages of CVD technology include:

[0116] High efficiency: thicker films can be grown quickly.

[0117] Flexibility: The composition and properties of the film can be controlled by adjusting the reaction conditions such as temperature, gas flow rate and reaction time.

[0118] Good coverage: Good film coverage can be achieved even on complex-shaped substrates.

[0119] Further, in one embodiment, in the epitaxial growth method of the lattice matching and mismatching steps, the epitaxial growth parameters are as follows:

[0120] The temperature is controlled between 500°C and 700°C to optimize crystal quality and disorder;

[0121] The growth rate is adjusted between 0.1 and 1 nanometer per second to precisely control the thickness and composition of the film;

[0122] For Chemical Vapor Deposition (CVD) technology:

[0123] The gas flow ratio of silane (SiH4) and germanium (GeH4) is precisely controlled to achieve the desired ratio of silicon (Si) to germanium (Ge).

[0124] In this embodiment, the production of a silicon-germanium alloy film (or silicon-germanium alloy material) having a spatially correlated disordered structure is completed through lattice matching and mismatching steps; subsequently, the preparation of nanowires is completed through a graphic processing step and an etching process step.

[0125] Further, in one embodiment, after the spatially correlated disordered silicon germanium nanowires are fabricated, the structure and performance analysis (structure and performance characterization step) may be performed:

[0126] Microstructure analysis: Transmission electron microscopy (TEM) and scanning electron microscopy (SEM) were used to observe the morphology and disordered structure of spatially correlated disordered SiGe nanowires;

[0127] Composition analysis: Energy dispersive X-ray spectroscopy (EDS) or secondary ion mass spectrometry (SIMS) is used to determine the distribution of silicon atoms (Si) and germanium atoms (Ge) in spatially correlated disordered SiGe nanowires;

[0128] Physical property measurements: Electrical and thermal performance tests were performed to evaluate the impact of spatially correlated disordered structures on the performance of nanowires.

[0129] Further, in one embodiment, in order to verify the effect of the spatially correlated disordered silicon germanium nanowires, a comparative experiment is provided to compare the spectrum cumulative thermal conductivity of the spatially correlated disordered silicon germanium nanowires with that of the conventional random disordered silicon germanium nanowires:

[0130] After introducing spatial correlation in SiGe nanowires, the phonon scattering centers have a certain correlation, which leads to a stronger Brillouin zone folding effect, thereby increasing the scattering of low-frequency long-wave phonons. In addition, the spatially correlated disordered structure can change the phonon spectrum characteristics of the material, such as introducing localized modes or suppressing the propagation speed of phonons. This change reduces the thermal transport efficiency of phonons in the entire material.

[0131] Combination Figure 3 It can be seen that for spatially correlated disordered silicon germanium nanowires, the cumulative thermal conductivity is lower than that of random disorder in the entire frequency range, especially in the low-frequency range of 0-2Thz. The long-wavelength phonons carrying a large amount of heat are more effectively scattered by the spatially correlated disordered structure, causing a significant decrease in thermal conductivity.

[0132] Furthermore, in one embodiment, in the spatially correlated disordered silicon germanium nanowires, the concentration of germanium atoms is 10% to 20%.

[0133] In this embodiment, according to the above comparative experiments, when the Ge (germanium atom) concentration is 10% to 20%, the spatially correlated disordered structure has the most significant inhibitory effect on heat transport, and the reduction in thermal conductivity can reach up to 58%. This result shows that within this concentration range, the spatially correlated disordered structure significantly weakens the heat conduction caused by lattice vibration through its special microscopic design, greatly optimizing the thermoelectric performance of the material. The special microstructure of the spatially correlated disordered silicon germanium nanowires effectively enhances the mobility of electrons while reducing thermal conductivity, allowing heat to be retained in the thermoelectric material for a longer time, ensuring that the thermoelectric effect is more durable and stable.

[0134] The technical solution provided by the present invention is further described in detail above through several specific implementation modes in order to highlight the advantages and benefits of the technical solution provided by the present invention. However, the several specific implementation modes described above are not intended to be used as limitations on the present invention. Any reasonable changes and improvements to the present invention, reasonable combinations of implementation modes and equivalent substitutions based on the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A spatially correlated disordered silicon germanium nanowire thermoelectric cooling system for electronic devices, characterized in that: The system includes a hot end, a cold end and a thermoelectric conversion module: The hot end is connected to a heating chip in the electronic device and is used to absorb the heat generated by the electronic device; The cold end is connected to the heat sink to absorb the heat from the hot end and dissipate the absorbed heat to the external environment through the heat sink; The thermoelectric conversion module is arranged between the hot end and the cold end, and is used to adjust the temperature difference between the hot end and the cold end, so as to realize the heat dissipation and cooling management of the electronic equipment; The thermoelectric conversion module comprises a heat-conducting layer, a thermoelectric material layer and a power drive circuit; the thermoelectric material layer is composed of spatially correlated disordered silicon germanium nanowires; in the spatially correlated disordered silicon germanium nanowires, the distribution of germanium atoms is spatially correlated disordered distribution; The heat-conducting layer is disposed between the thermoelectric material layer and the hot end, and is used to enhance the transfer of heat from the hot end to the thermoelectric material layer; The power drive circuit is used to provide direct current to the thermoelectric material layer; The thermoelectric material layer is used to respond to the direct current provided by the power driving circuit, generate a thermoelectric effect to produce a temperature difference at its two ends, and enhance the cooling effect; it is also used to adjust the temperature difference at both ends of the thermoelectric material layer by adjusting the current value of the direct current provided by the power driving circuit, thereby adjusting the temperature difference between the hot end and the cold end.

2. The spatially correlated disordered silicon germanium nanowire thermoelectric cooling system for electronic devices according to claim 1, characterized in that: The contact surface between the hot end and the heat generating chip is designed as a microstructure to increase the heat conduction area.

3. The spatially correlated disordered silicon germanium nanowire thermoelectric cooling system for electronic devices according to claim 1, characterized in that: The material of the heat-conducting layer is a metal film or graphene.

4. The spatially correlated disordered silicon germanium nanowire thermoelectric cooling system for electronic devices according to claim 1, characterized in that: The diameter of the spatially correlated disordered silicon germanium nanowires is between 10 nm and 20 nm.

5. The spatially correlated disordered silicon germanium nanowire thermoelectric cooling system for electronic devices according to claim 4, characterized in that: The length of the spatially correlated disordered silicon germanium nanowire is 1 μm.

6. The spatially correlated disordered silicon germanium nanowire thermoelectric cooling system for electronic devices according to claim 1, characterized in that: The system further comprises a packaging plate; the packaging plate is arranged between the hot end and the thermoelectric conversion module.

7. The spatially correlated disordered silicon germanium nanowire thermoelectric cooling system for electronic devices according to claim 1, characterized in that: The power drive circuit includes a power supply, an electrode and a current regulating device; The power source is electrically connected to the thermoelectric material layer through the electrode, and is used to provide a direct current to the thermoelectric material layer; The current regulating device is used to adjust the current value of the direct current provided by the power supply, thereby adjusting the temperature difference between the two ends of the thermoelectric material layer 4 through the thermoelectric effect.

8. The spatially correlated disordered silicon germanium nanowire thermoelectric cooling system for electronic devices according to claim 1, characterized in that: The distribution of the germanium atoms is spatially correlated and disordered: The spatial coordinates of germanium atoms are related to the distances between adjacent germanium atoms, and the correlation decays in a power law with the distance between germanium atoms: C(r)～|r| -a Where a is the correlation parameter and r is the distance between adjacent germanium atoms.

9. The spatially correlated disordered silicon germanium nanowire thermoelectric cooling system for electronic devices according to claim 8, characterized in that: In the spatially correlated disordered silicon germanium nanowires, the concentration of germanium atoms is 10% to 20%.

10. The spatially correlated disordered silicon germanium nanowire thermoelectric cooling system for electronic devices according to claim 9, characterized in that: The spatially correlated disordered silicon germanium nanowires are manufactured using the following preparation process: Materials selection step: Select silicon and germanium as the nanowire alloy components and adjust their ratio to achieve the desired degree of disorder; Lattice matching and mismatching step: depositing a silicon-germanium alloy thin film on a substrate by an epitaxial growth method, wherein the lattice constant of the substrate is different from that of the silicon-germanium alloy, so as to introduce a lattice mismatch, thereby generating a spatially correlated disordered structure; Heat treatment step: after the growth of the silicon germanium alloy film is completed by the epitaxial growth method, annealing treatment is performed to adjust the disorder degree and correlation; Patterning process: using electron beam lithography or nanoimprinting technology to define the nanowire pattern on the silicon germanium alloy film; Etching process steps: Reactive ion etching technology is used to etch a nanowire structure on the silicon-germanium alloy film according to the nanowire pattern to complete the production of spatially correlated disordered silicon-germanium nanowires.

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