Limited management of processor power distribution networks

Abstract

Aspects relate to restriction management of processor power distribution networks. In one aspect, an electronic device has a processor having a processing core coupled to a power rail. The power rail is external to the processor. A current sensor is associated with an output of the power rail and is configured to generate a current sensor reading. A state space unit is coupled to the current sensor. The state space unit has a predictive model to apply the current sensor readings to the predictive model to predict a current budget for the processing core. A limit manager is configured to generate a current limit in response to the current budget. The limit manager limits a current draw of the processing core in response to the current limit.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority to pending U.S. non-provisional application No. 17 / 941,535, filed on September 9, 2022, which is assigned to the assignee of the present application and is hereby expressly incorporated herein by reference as if fully set forth below and for all applicable purposes. Technical Field

[0003] Aspects of the present disclosure relate generally to power distribution networks for supplying power to processors, and particularly to managing limits, such as current limits, on processing cores. Background Art

[0004] The processor receives power from a power distribution network coupled to a power source and delivers a regulated voltage on a power rail coupled to the processor. The power rail may be powered by a voltage regulator or a power management integrated circuit (PMIC) including a voltage regulator. The PMIC may be coupled to one or more processing cores or other components of the processor. In other specific implementations, each PMIC is coupled to a single processing core so that the processing cores can operate independently. This configuration exists with standalone processors as well as processors that are part of a system on a chip (SoC). Summary of the invention

[0005] The following content presents a summary of one or more implementations in order to provide a basic understanding of such implementations. This summary is not an exhaustive overview of all contemplated implementations, and is not intended to identify key or important elements of all implementations, nor is it intended to delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a preface to the more detailed description that is subsequently presented.

[0006] In one example, an electronic device has limit management for a processor power distribution network. The device has a processor having a processing core coupled to a power rail. The power rail is external to the processor. A current sensor is associated with an output of the power rail and is configured to generate a current sensor reading. A state space unit is coupled to the current sensor. The state space unit has a prediction model to apply the current sensor reading to the prediction model to predict a current budget for the processing core. A limit manager is configured to generate a current limit in response to the current budget. The limit manager limits the current draw of the processing core in response to the current limit.

[0007] Another example provides a method for limit management of a power distribution network, the method comprising reading a first current sensor associated with an output of a first power rail to produce a first current sensor reading, the first power rail being coupled to a first processing core of a processor; applying the first current sensor reading to a predictive model to predict a first current budget for the first processing core; generating a first current limit in response to the first current budget; and limiting a current draw of the first processing core in response to the first current limit.

[0008] Another example provides a non-transitory computer-readable medium having stored therein instructions for causing a processor to perform operations for limit management of a power distribution network. The operations include reading a first current sensor associated with an output of a first power rail to produce a first current sensor reading, the first power rail being coupled to a first processing core of the processor; applying the first current sensor reading to a prediction model to predict a first current budget for the first processing core; generating a first current limit in response to the first current budget; and limiting a current draw of the first processing core in response to the first current limit.

[0009] To achieve the foregoing and related purposes, one or more implementations include the features fully described below and specifically pointed out in the claims. The following description and the accompanying figures set forth in detail certain illustrative aspects of one or more implementations. However, these aspects are merely indicative of several of the various ways in which the principles of each implementation may be employed, and the described implementations are intended to include all such aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A block diagram of a device having a power distribution network for powering multiple processing cores in a package is illustrated in accordance with certain aspects of the present disclosure.

[0011] Figure 2 A functional block diagram of a hierarchical state-space unit is illustrated in accordance with certain aspects of the present disclosure.

[0012] Figure 3 A hardware block diagram illustrating an architecture that implements a state-space control model according to certain aspects of the present disclosure.

[0013] Figure 4 A flow chart illustrating the operation of a restriction management system in accordance with certain aspects of the present disclosure.

[0014] Figure 5 A flow chart is illustrated for creating a predictive model using a designed simulation according to certain aspects of the present disclosure.

[0015] Figure 6A flow chart is illustrated for using empirical results to create or enhance a predictive model according to certain aspects of the present disclosure.

[0016] Figure 7 A flow chart illustrating a method of implementing constraint management for a power distribution network according to certain aspects of the present disclosure is illustrated. DETAILED DESCRIPTION

[0017] The specific embodiments described below in conjunction with the accompanying drawings are intended as descriptions of various configurations and are not intended to represent the only configurations with which the concepts described herein can be practiced. In order to provide a comprehensive understanding of the various concepts, the specific embodiments include specific details. However, it is apparent to those skilled in the art that these concepts can be practiced without these specific details. In some instances, in order to avoid obscuring such concepts, well-known structures and components are shown in block diagram form.

[0018] Modern processors typically have workloads that vary over time and are designed to reduce energy consumption when the workload permits. Therefore, the power drawn by the processor changes over time, and the PMIC supplies different amounts of power over time as the processor workload changes. The PMIC includes a voltage regulator designed to maintain a specific voltage for the processing core. Increased power is provided by increasing the supplied current at a specific voltage. In some instances, the power demand may increase or decrease so quickly that the PMIC and other components of the power supply are unable to provide quality power through changes. In some instances, the power demand may increase or decrease so quickly that the PMIC and other components of the power distribution network are unable to provide quality voltage through changes, resulting in a drop or overshoot in the PMIC regulator output voltage. In some other instances, the power demand changes periodically at a time consistent with the resonant frequency of the power distribution network, causing current oscillations. As an example, when the latency of the power distribution network from the power supply to the processing core is large, and if the throttling management system does not account for the large power distribution network latency when throttling the processing core, the power demand changes caused by throttling the processing core may produce large current oscillations at the power supply. As another example, for an add-in card where power is supplied to the processing core on the card at a connector at the card edge through a power distribution network on the card, the latency from the connector at the card edge to the processing core may be large.

[0019] Limit management (also referred to as a limit management system) can be implemented in hardware or software or both, and is operated by some processors to monitor the required power and then slow down the changes in the power draw of the processor. The limit management system can slow down the processor clock to slow down the increased power demand. In some instances, the limit management system can add dummy instructions to the command queue to reduce the power requirements of the processor. By taking into account the power distribution network delay when throttling the processing core, the power demand of the processing core is changed and the oscillation in the supplied current is reduced in magnitude. This provides improved processor performance using a more stable current. It also provides more efficient power usage by reducing the energy consumed by driving the current oscillation.

[0020] The limit management system can limit peak current and continuous current. Current with peak value higher than the defined limit may cause permanent damage to the circuit or affect circuit performance. For example, excessive current may cause timing errors, including, for example, setup time violations in critical paths. When the current exceeds the peak current limit at the voltage regulator, the voltage may also drop below the specified regulator range. The reduced voltage may also cause hardware, software or processing errors at the IC. Continuous current exceeding the limit may cause overheating, which may eventually cause damage to the IC.

[0021] The limit management system is designed to respond quickly to any limit violation. This allows the system to respond before a process or hardware failure occurs. As an example, the response time of a rail current limit may be on the order of 200 nanoseconds (ns) to 500ns. While this may be sufficient to prevent damage to process operations or physical damage to the IC, the responsive nature of the limit management system means that the current may exceed the limit before the system reacts. The limit must be set low enough to avoid any harm during the time it takes the system to react.

[0022] In some hardware systems, there is some distance between the power supply and the IC that draws power. The power distribution network (PDN) includes some delay in its response to any change in conditions. This delay slows down the response of the power distribution network. This delay reduces the effectiveness of the limit management system to control the average current, peak current, and current slew rate. Oscillations reduce the efficiency of the power distribution network in supplying power to the IC.

[0023] To overcome latency, a predictive model can be used to predict the likely future state of the power distribution network. As used herein, a state space unit uses its predictive model for the power distribution network. By throttling the processing core based on the predicted future state, oscillations in the power supply to the processing core are reduced. The state space unit allows the use of the predictive model with very little hardware and computational complexity.

[0024] Although various aspects and examples are described in this application by illustrating some examples, it will be understood by those skilled in the art that additional specific implementations and use cases can be generated in many different arrangements and scenarios. The innovation described herein can be implemented across many different platform types, devices, systems, shapes, sizes, and packaging arrangements. For example, various aspects or uses can be generated via integrated circuit chip examples and other devices based on non-module components (e.g., end-user devices, vehicles, communication equipment, computing equipment, industrial equipment, retail / shopping equipment, medical equipment, AI-enabled devices, etc.). Although some examples may or may not specifically point to use cases or applications, the applicability of a wide range of described innovations may occur. The scope of specific implementation may be from chip-level or modular components to non-modular non-chip-level specific implementations, and further to aggregated, distributed or OEM (original equipment manufacturer) devices or systems incorporating one or more aspects of the described innovation. In some practical environments, the equipment in combination with the various aspects and features described may also necessarily include additional components and features for implementing and practicing the various aspects claimed and described. For example, temperature and power sensors may use multiple components for analog and digital purposes (e.g., hardware components including power supplies, transducers, detectors, accumulators, digital-to-analog converters, etc.) The innovations described herein are intended to be practiced in a variety of devices, chip-level components, systems, distributed arrangements, end-user devices, etc., having different sizes, shapes, and configurations.

[0025] Figure 11 is a diagram of an add-on card 102, such as a daughter card, an accessory card, or a peripheral component interconnect express (PCIe) card. The add-on card 102 may be formed of a variety of materials. In some examples, the add-on card 102 may include a printed circuit board (PCB) and various components. For example, one or more processing cores may be attached to the PCB. The processing core may be attached in the form of a package 104 containing at least one system on a chip (SOC). The SOC 106 may be coupled to other SOCs 108 in the package 104 or in another package. The SOC 106 includes a first processing core 132, a second processing core 136, and other cores 140 that may include processing cores and other types of cores. Other SOCs 108 may have the same or similar components, depending on the specific implementation. The processing cores 132, 136, 140 may be general-purpose, video, signal processing, communication, transcoding, machine learning, or any other type of processing core. Each processing core is powered by one or more current sources. A current source is an abstract concept of the power consumption of the corresponding processing core. The current source represents the current drawn from the power rail by the processing core at a specific voltage. Each current source 134, 138, 142 is part of a corresponding processing core 132, 136, 140. The first processing core 132 has a first current source 134. The second processing core 136 has a second current source 138, and the other processing cores 140 have current sources 142. More current sources can be used to fit a specific processing core. Specific configurations of processing cores, current sources, SOCs, and packages are provided as examples. The processing cores can be packaged and connected to add-on cards in any suitable manner.

[0026] Power is provided to the add-on card 102 through a high voltage card edge connector 110 and a low voltage card edge connector 114 coupled to a power distribution network. The power distribution network provides different power levels in each processing core. For example, the power distribution network may include voltage regulators (shown as power management integrated circuits (PMICs) 120, 124, and 128) and power rails 162, 164, 166. There may be more or fewer card edge connectors to accommodate different specific implementations. Power from the high voltage card edge connector 110 is provided to the PMICs 120, 124, 128, which provide power to each corresponding current source 132, 134, and 140. For example, the first PMIC 120 provides power to a first power rail 162 of a current source 134 coupled to a first processing core 132, the second PMIC 124 provides power to a second power rail 164 of a current source 138 coupled to a second processing core 136, and the third PMIC 128 provides power to a third power rail 166 of a current source 142 coupled to other processing cores 140. Power rails are indicated as single arrows, which represent one or more power rails. More than one conductor is often used to provide power in a microelectronic device. The PMICs 120, 124, 128 are each coupled to a high voltage card edge connector 110. The high voltage card edge connector 110 is also coupled to other SOCs 108. For simplicity, this connection is shown without the details of the SOC 106. The low voltage card edge connector 114 is also coupled to the SOC 106. For simplicity, specific components for this connection are not shown.

[0027] This description is presented in the context of a power source coupled to a PMIC. However, many different functions and capabilities of some types of PMICs are not necessary to implement the limit management described herein. Various aspects use PMICs to provide a desired voltage to a power rail from a card edge. This function may also be provided by other devices, such as those referred to as voltage regulators or voltage converters. References to PMICs herein should be interpreted as including simpler and more complex devices that perform the same voltage regulation and conversion functions. Some types of PMICs monitor the state of the power rail and report the state through, for example, a power management bus (PMBus) (not shown). In some aspects, a current sensor is integrated into the PMIC. Although multiple PMICs are shown, other components may be used to supply power alternatively. In some aspects, a discrete voltage regulator with a discrete control circuit may be used. Other types of control interfaces may be used instead of PMBus.

[0028] Current sensors are used to measure the state of the incoming power and the state of the voltage regulator. Figure 1In the example shown in FIG. 1 , a first current sensor 122 is coupled to a power rail 162 at the output of a first PMIC 120, a second current sensor 124 is coupled to a second power rail 164 at the output of a second PMIC 124, and a third current sensor 112 is coupled to the output of a high voltage card edge connector 110. The high voltage card edge connector 110 serves as a common power supply at the input to the first PMIC 120 and to the second PMIC 124. In addition, a fourth current sensor 116 is coupled to the output of the low voltage card edge connector 114. The current sensors 122, 124, 112, 116 may be in the form of resistors and voltage sensors to determine the actual current through the resistor to the power consuming device. The resistors may be coupled to the power rails 162, 164, 166, which are the outputs of the respective PMICs 120, 124, 128 or any other type of voltage regulator. More or fewer current sensors may be used to accommodate different add-in cards, different processors, and different power distribution networks. As shown, SOC 106 is in package 104, which may include a package substrate and other substrates carrying the SOC, so that the SOC is on the substrate. PMICs 120, 124, 128 are outside package 106 and may be included on a second substrate (e.g., a package substrate having one or more ICs thereon). Each PMIC may be a discrete IC on its own substrate. Current sensors 112, 122, 126 may be included on an associated PMIC substrate or a different substrate. In some aspects, discrete chiplets are used to implement the current sensors.

[0029] In a reactive power limitation management system, a target current is established at one or more of the current sensors 122, 126, 112, 116. The target may be for peak current, continuous current, and / or other quantities. When the target is exceeded, the affected processing core may be throttled. Figure 1 In the example of , for the first PMIC 120, when the first processing core 132 is drawing more power than the limit allows, the current at the first current sensor 122 will increase. Sometimes, the limit management system can throttle the processing core to reduce the current drawn by the processing core. This can be done for subdivision of the processing core or any other part of the processor. Throttling is usually done by reducing the clock speed or by inserting wait states or dummy instructions into the instruction queue, however other power reduction techniques can also be used.

[0030] There may be large delays in the limiting management of the power distribution network (PDN) from the card edge connectors 110, 114 to the on-die power sources (e.g., current sources 134, 138, 142). In different hardware configurations, the card edge power can be separated from the current source representing the power consumption of the corresponding processing core by a few microseconds to more than ten microseconds. The delay can cause unexpected current oscillations at the card edge. The delay reduces the effectiveness of the limiting management to control the average current, peak current, and even the current slew rate at the card edge. The performance of the on-die power source is reduced due to the inefficient use of the card edge power source. The delay is caused in part by the distance from the power source to the power sink in the processing core. This is also caused by the inherent capacitance and resistance of the electrical system. Inductance also increases the amplitude of the oscillation. For higher power add-in cards, the oscillation is larger.

[0031] In various aspects, the add-on card 102 may also include one or more state space units 154 coupled to each of the current sensors 122, 126, 112, 116 and one or more limit managers 156 coupled to each of the processing cores 132, 136, 140 to throttle the processing cores based on a dynamic current budget of the current drawn by the corresponding processing cores. The state space unit applies a state space model to track and predict the PDN dynamics including its latency. The state space unit (SSU) 154 optimizes the dynamic budget of the SOC power. The dynamic budget is provided to the limit manager 156, which controls the SOC power or SOC current draw, for example, by throttling the relevant processing cores. In some aspects, the limit manager 156 uses dynamic clock frequency limits. The state space unit optimizes the dynamic budget using model trimming, model quantization, and hardware acceleration. The state space unit can be implemented with a very small footprint for computing the dynamic budget. The state space unit overcomes the latency of the PDN by predicting the most likely future state using the current current sensor measurements. As a result, the peak current, current slew rate and current ringing at the card edge are better controlled. This serves to mitigate unintentional card edge current ringing.

[0032] The state space unit 154 uses current sensor readings generated, for example, by current sensors 122, 124, 112, 116 to predict the state of the power distribution network (including each PMIC 120, 124, 128) as it is affected by each respective processing core 132, 134, 140. The state space unit uses a state space model that takes input values ​​u, y, and x(t) representing the actual physical state of the system over time and generates a predicted future state x(t+1). In the state space model, u represents the input to the model and y represents the output. The value x represents a system state that can be used to calculate the system response from the system input u to the system output y. In various aspects described herein, u and y are power values ​​based on the current sensor readings. The value x is not directly measured and is at least in part a function of the total resistance, capacitance, and inductance of the PMIC and PDN. For Figure 2 These values ​​are described in more detail. The state space model uses a type of model predictive control (MPC) for closed loop systems, where calculations are repeated over time to obtain a higher accuracy of the predicted state. The model is formed using simulation data or experimental data or both, and can be improved for a particular device when it is in use. The model is applied as a set of constants that are combined with a sequence of measurements over time as a matrix operation in a multiply-accumulate unit. These results are weighted and then combined through multiple cycles of multiplication and accumulation to estimate possible future states. The best prediction is then selected as the output state, which is indicated as x herein.

[0033] In some instances, the state-space model is a control loop that combines tracking prediction and optimization in a discrete time closed-loop system. It is described as:

[0034] x(t+1)=Ax(t)+Bu(t)

[0035] y(t)=Cx(t)+Du(t)

[0036] where A, B, C, and D are constants of the state-space model.

[0037] As used herein, the state space unit 154 uses its predictive model for the power distribution network. This includes the PMICs 120, 124, 126, 128 and the power rails 162, 164, 166 output by the PMICs, as described above. The power rails have resistive, inductive, and capacitive components that affect the overall system behavior. The state space unit 154 acts through the limit manager 156 to manage the response of the PDN to changes in the current draw at the respective processing cores. The predictive model of the state space unit 154 predicts and optimizes the future state of the PDN response to changes in the current draw at the processing cores 132, 136, 140. The power consumption of the respective processing cores acts as a stimulus to which the PDN responds.

[0038] Figure 2 Is suitable for use as Figure 1 Functional block diagram of a hierarchical state space unit of the state space unit 154. One, two or more state space unit levels may be used to accommodate different specific implementations. The first level 202 is coupled to the second level 204. The first level 202 is a card edge level and receives a current value y{card edge} from a first current sensor 222. The first level is suitable for use with an add-on card, where power is supplied to the system through a connector at the card edge. The power is regulated by the PDN and then supplied to the processing core. The first current sensor 222 measures the power supplied at the card edge and may be measured at the input to the first PMIC. The first level 202 receives a second current value u{card edge} from the second current sensor 224. The second current sensor 224 may be a current sensor at the output of the first PMIC. These are processed by the state space model in the estimator 212 to estimate the state at the card edge as x{card edge}. The estimate is provided to the budget optimizer 214, which generates a budget REGOUT{budget} for the card edge state. This is applied to the corresponding voltage regulator (e.g., Figure 1 The budget indicates an estimated maximum current that can be drawn at the output of the voltage regulator in order to meet the current limit requirement at the card edge. In addition, the first stage 202 considers the voltage difference between the card edge and the output of the voltage regulator when generating the budget. Values ​​x, y, and u are collected over time and used in a state-space model. x corresponds to the system state at each stage for determining the output y from the input u, and represents a vector. u and y represent scalars in a single-input, single-output system (such as a single PMIC providing power to a single processing core). The state-space unit can also simultaneously solve for multiple PMICs that use the same or related PDNs to provide power to different processing cores, in which case the results provide power limit management to different processing cores in different ways. In such a scenario, u represents a vector of multiple processing cores, and y represents a scalar of a shared common power supply in a multiple-input, single-output system (such as a chiplet scenario).

[0039] The voltage regulator budget REGOUT{budget} is provided to the budget optimizer 218 of the second stage 204 and is combined with the state estimate x{regout} from the state estimator 216 of the second stage 204 to generate a current budget SOC{budget} for the connected processing core. The state estimator 216 of the second stage 204 receives the current value y{regout} from the second current sensor 224 and the current value u{SOC} from the third current sensor 226. The third current sensor can be in the SOC, such as a digital power meter or other current or power sensor that measures the power consumption of a particular processing core. As shown, the same current sensor reading from the second current sensor 224 is given different variable names u or y in different levels of the state space model to match their use at that level.

[0040] The first stage 202 may also be coupled to a slew rate limiting module 234. The slew rate of the input current from the card edge provides an indication of how much the power draw has changed for the entire system. The slew rate is also closely related to any oscillations in the power distribution network. The current sensor readings over time can be used to estimate the rate of change of the current over time, which is the slew rate. As with other measurements, when a large slew rate exceeding the limit is observed, any reactive action taken to throttle the processing core is too late to prevent the slew rate from exceeding the limit. This may be because the large slew rate observed is caused by the cumulative effect of the power consumption from the processing core that has been delayed by the power distribution network over the past many microseconds. Due to the power distribution network delay, the effect of any action taken to throttle the processing core to reduce its power becomes observable at the card edge many microseconds later. The state space unit is able to use the state space model to predict when the slew rate will be large, predict future states, and take corrective actions to prevent high slew rates from occurring.

[0041] The current value y{card edge} from the first current sensor 222 is provided to a slew rate limiting module 234. The first current sensor 222 may be a sensor at the card edge, which is an input to the first PMIC. A card edge current limit 232 (limit {card edge}) is also applied to the slew rate limiting module 234. This may be a constant value that is applied only when the space state unit is initialized. These values ​​are applied to derive a slew rate limit 236 in the slew rate limiting module 234, and the slew rate limit 236 is provided to the budget optimizer 214 of the first stage 202. The slew rate limit 236 may be determined as a time-varying limit for adjusting a reference profile of a PDN or system. The effect of the slew rate limit 236 is to limit changes to the voltage regulator output budget REGOUT{budget}. Slowly changing the budget over time reduces the slew rate at many points in the power distribution network.

[0042] The signals going into the budget optimizer 214 of the first stage 202 and the budget optimizer 218 of the second stage 204 are targets or references for limit management. In other words, at the card edge, the target is to limit the card edge current to no more than the value indicated by the slew rate limit 236. This card edge current limit target is achieved under the condition that the current drawn at the output of the voltage regulator (e.g., PMIC) does not exceed the current value indicated by the REGOUT{budget} of the first stage 202 budget optimizer. The first stage 202 calculates REGOUT{budget} so as to meet the slew rate limit 236. Similarly, the second stage 204 budget optimizer 218 calculates SOC{budget} so as to meet the first stage 202 budget optimizer 214 output REGOUT{budget}. If the SOC current draw is limited to a value that does not exceed the SOC{budget}, this will result in the current draw at the output of the voltage regulator being limited to a value that does not exceed the REGOUT{budget}. Therefore, the card edge current does not exceed the slew rate limit 236.

[0043] The above mechanism allows for accommodating high power distribution network latency from the SOC to the card edge when the action of the limit manager system is limited to throttling the processing cores in the SOC. The slew rate limiting module 234 generates a card edge current target by considering the card edge current limit 232 and the card edge current measurement y{card edge}, which is greater than y{card edge} by the amount required for slew rate control per card edge, but does not exceed the card edge current limit 232. This allows for controlling the slew rate at the card edge by throttling the processing cores in the SOC, taking into account the high power distribution network latency.

[0044] Although a two-stage state space unit is shown, a single-stage state space unit may be used instead. In one embodiment, with a single-stage state space unit, one state space unit may be associated with a first current sensor and a second current sensor. In another embodiment, one state space unit may be associated with one current sensor. In other words, a two-stage state space unit may have one or two sensors in each stage. One stage may have one sensor and the other stage may have two sensors. For a two-stage state space unit, as shown, the first state space unit stage is coupled with a first current sensor and a second current sensor. The second state space unit stage is coupled with a second current sensor and a third current sensor. Each state space unit stage is coupled with a pair of current sensors. One sensor is used for system input to the stage and one sensor is used for system output to the stage. Each state space unit stage has an input for a specified current limiting target. By using two sets of current sensors, one set for system input and one set for system output, the result is more robust and less affected by noise. The state space unit stage can also be configured as a multi-input and multi-output system. With the advent of inexpensive chiplets on which state space units can be implemented, many different variants can be supported at low cost. Multiple chiplets can be used within a single package. These can be configured as multiple-input single-output, multiple-input multiple-output, and single-input single-output systems.

[0045] Figure 3 Is achieved as Figure 2 3. The hardware block diagram of the architecture of the state space control model shown. The limit manager 302 receives the dynamic budget 332 from the limit management glue logic 320. The limit manager compares the current power consumption of the processing core to the dynamic budget 332 and applies throttling 304 to the processing core. The dynamic budget 332 is generated in the state space unit 330. The state space unit 330 is controlled by a finite state machine 310 that drives operations in a multiply-accumulate (MAC) array 322. The MAC array 322 is shown as having four computational units, two for the first stage of the state space unit 330 and two for the second stage of the state space unit 330. However, there may be more or fewer computational units and more or fewer stages to accommodate different specific implementations. The finite state machine controls the sequencing of operations to obtain data from registers and memory (e.g., tightly coupled memory (TCM) 314) and to calculate and save results.

[0046] After initialization, configuration settings are stored in a control state register (CSR) 318, and a state space model is stored in a TCM 314. The contents of the CSR 318 and TCM 314 are used by the MAC array 316 during operation. The TCM 314 provides low latency memory that the MAC array 316 can use to quickly access the model without moving values ​​as in a cache. The MAC array accesses the model through a set of read registers 316. Sensor readings 334 are provided by the limit manager 302 to a set of sensor registers 312 through the limit management glue logic 320. The sensor registers 312 can also be used to store intermediate results. The sensor readings 334 stored in the sensor registers 312 are also fed into the MAC array 322 through the read registers 316. The MAC array 320 applies the state space model from the TCM 314 to the sensor readings in the sensor registers 312 and generates a dynamic budget 332 as an output to the limit manager 320. For all iterations of the prediction within the state space unit 330, the finite state machine 310 drives operations in the read registers 316, the MAC array 322, and the limit management glue logic 320. The limit management glue logic connects the MAC array 322 to the limit manager 302 and the sensor registers 312, providing an interface suitable for each purpose.

[0047] Figure 4 Is a restriction management system (e.g. Figure 2 and Figure 3 406. This includes processing operations in the processing core, generating current sensor readings, and regulating power.

[0048] At 408, reading the current sensor is performed to generate a first current sensor reading for the first power rail and additional current sensor readings for any other locations on the power distribution network. The first power rail is coupled to a first processing core of the processor. The sensor reading is received at the space state unit, and at 410, the state space model is executed by applying the sensor reading to the prediction model loaded at 404. At 412, the state space unit generates a dynamic budget using the prediction model. Therefore, the budget is also predictive and reflects the processing core's optimized estimate of future power draw. At 414, the limit manager compares the current core power with the dynamic budget to determine the current limit. At 416, the current draw of the processing core is limited by the limit manager. In some aspects, the operation of the processing core is throttled based on the comparison. The throttling can be increased or decreased based on the most recent iteration of the dynamic budget from the state space unit. The throttling can be performed by controlling the clock frequency at the processing core, by inserting wait states or dummy instructions, and in other ways.

[0049] Figure 5 5 is a process flow diagram for creating a predictive model (e.g., a state-space model) using a simulation of a design (e.g., a SOC design). A SOC design 502 including a PDN and one or more processing cores is provided. At 504, design features are extracted from the design to produce a PDN simulation. The simulation will show how the system responds to a change in current draw from a power source to the SOC current source, which represents the power consumption of the processing core. The simulation may include inherent and discrete inductances, capacitances, and resistances that may cause undesirable oscillations in current and voltage when there is a change in power draw. At 506, the operation of the PDN is simulated to create a predictive model of the PDN.

[0050] At 508, online optimization is used to create a model predictive controller model. Using design simulation to create a dynamic budget involves running an optimization algorithm in real time during simulated system operation. Online optimization records the simulated operation of the system to produce values ​​representing simulated operating conditions. Different simulated stimuli are applied and the simulated responses are measured. At 510, offline optimization is used to create a model predictive controller model. Offline optimization uses the online model predictive controller model created in 508 as input. It does not run the optimization in real time during system operation, but pre-calculates and optimizes a set of optimal solution regions. These regions are defined by a pre-calculated set of constants. Offline optimization estimates the operation of the system based on simulated operation in order to generate possible predicted future states of the PDN. Compared with what is provided by the online model predictive controller model, the pre-calculated constants and regions provide a much simpler calculation for deriving a dynamic budget during operation. The coefficients are saved in a table representing different possible predicted states from online and offline optimization.

[0051] At 512, a control model for hardware acceleration is created using trimming and quantization. Model predictive controller models are very large and require a lot of memory to store all the coefficients and possible states. Through trimming and quantization, the size of the model is significantly reduced. This reduces the processing power required to operate the model and the amount of memory required to store the model. The trimming and quantization operations can be performed and tested iteratively to ensure that the model accurately represents the simulated SOC and PDN. For most specific implementations, the model is not required to be extremely accurate, in part because the operation of the PDN is monitored in real time. In operation, corrective actions can always be taken as the situation changes. At 514, an image of the predictive model has been generated. This can be stored for use in the TCM or elsewhere.

[0052] Figure 6 is a process flow chart for creating or enhancing a predictive model (e.g., a state-space model) using empirical results, such as by operating SOC and PDN. Figure 5 The SOC design is simulated and analyzed in a process flow. When actual devices are available, the simulation-based model can be improved or the model can be created using only actual devices. At 602, a predictive model is optionally provided from the simulation. If no predictive model from the simulation is available or desired, the model can be built entirely from empirical data collected from the physical device. The model is based on the PDN and one or more processing cores. At 604, measurements of the PDN and its response to various stimuli are collected. The measurements are made using actual devices. The measurements show how the actual system responds to changes in the current draw from the power source to the SOC current source. The effects of inherent and discrete inductance, capacitance, and resistance, the PMIC is measured directly in current and voltage under different operating load conditions and power draw of the SOC. At 606, the measurements are used to tune the predictive model to improve the predictive model of the PDN.

[0053] At 608, online optimization is used to create a model predictive controller model. Creating a dynamic budget involves running optimization in real time during system operation. Online optimization records the actual operation of the device to produce values ​​representing measured operating conditions. Different operating stimuli are applied and the responses of the device are measured. At 610, offline optimization is used to create a model predictive controller model. Offline optimization uses the online model predictive controller model created in 608 as input. It does not run optimization in real time during system operation, but pre-calculates and optimizes a set of optimal solution regions. These regions are defined by a pre-calculated set of constants. Offline optimization estimates the operation of the system before the actual operation of the system in order to generate possible predicted future states of the PDN. During system operation, the dynamic budget can be determined using fewer computing resources, using pre-calculated constants and quantization provided by the region. The coefficients are saved in a table representing different possible predicted states from online and offline optimization.

[0054] At 612, a control model is created for hardware acceleration using trimming and quantization. Model predictive controller models are very large and require a lot of memory to store all the coefficients and possible states. Through trimming and quantization, the size of the model is significantly reduced. This reduces the processing power required to operate the model and the amount of memory required to store the model. For most implementations, the model is not required to be extremely accurate, in part because the operation of the PDN is monitored in real time. As conditions change, corrective action can always be taken. At 614, an image of the predictive model has been generated. This can be stored for use in the examples above for Figure 3 or used in a TCM as described elsewhere.

[0055] Figure 7 is a process flow diagram illustrating an example of a method for applying limit management to a power distribution network. The method may be applied to Figure 1 The method may be implemented by the add-on card shown or applied to other devices operating under different power conditions. Figure 3 The method 700 may be performed by hardware configurations, other circuits or other components or processing resources other than those shown and described herein. The method 700 begins at block 702 by reading a first current sensor associated with an output of a first power rail to produce a first current sensor reading, wherein the first power rail is coupled to a first processing core of a processor. In some aspects, a second current sensor, a third current sensor, and additional sensors may be read. In various aspects, the first current sensor is associated with a power rail to the first processing core, and the second current sensor is associated with a power rail to the second processing core. The third current sensor may be coupled between a common power supply (e.g., a card edge connector) and a PMIC that applies power to the power rail.

[0056] In block 704, applying the first current sensor reading to a prediction model to predict a first current budget for a first processing core is performed. As described, an example of a prediction model is a state space model. Such a model can calculate possible future states and select one of the future states as the predicted future state. The selection uses a quadratic optimization operation that can be processed by a multiply-accumulate computation unit.

[0057] In block 706, generating a first current limit in response to the first current budget is performed. In block 708, limiting a current draw of the first processing core in response to the first current limit is performed.

[0058] Figure 7 The process may be executed simultaneously for one or more processing cores. For a multi-core processor, each of the processing cores may be throttled or have a limited current draw independently of the other processing cores. There may be different current budgets and current limits to accommodate the operation of different processing cores and the power distribution network.

[0059] As used herein, "or" is intended to be interpreted as inclusive unless otherwise expressly indicated. For example, "a or b" may include only a, only b, or a combination of a and b. As used herein, a phrase referring to "at least one of" or "one or more of" a list of items refers to any combination of those items, including individual members. For example, "at least one of a, b, or c" is intended to cover the following examples: only a, only b, only c, a combination of a and b, a combination of a and c, a combination of b and c, and a combination of a and b and c.

[0060] The various illustrative components, logical components, logical blocks, modules, circuits, operations, and algorithmic processes described in conjunction with the specific implementations disclosed herein may be implemented as electronic hardware, firmware, software, or a combination of hardware, firmware, or software, including the structures disclosed in this specification and their structural equivalents. This interchangeability of hardware, firmware, and software has been generally described in terms of their functionality and exemplified in the various illustrative components, blocks, modules, circuits, and processes described above. Whether such functionality is implemented in hardware, firmware, or software depends on the specific application and the design constraints imposed on the overall system.

[0061] The various illustrative logical blocks, modules, and circuits described in conjunction with the exemplary aspects disclosed herein may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic components, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in an alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a processor, multiple processors, one or more processors combined with a DSP core, or any other such configuration.

[0062] In one or more exemplary aspects, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored as one or more instructions or codes stored on a computer-readable medium or sent as one or more instructions or codes stored on a computer-readable medium. Computer-readable media include both computer storage media and communication media, including any medium that facilitates the transfer of computer programs from one place to another. Storage media may be any available medium that can be accessed by a computer. By way of example and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM, or other optical disk storage devices or other magnetic storage devices, or any other medium that can be used to carry or store desired program codes in the form of instructions or data structures and can be accessed by a computer. Moreover, any connection is appropriately referred to as a computer-readable medium. For example, if the software is sent from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwaves, coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwaves are included in the definition of the medium. Disk and disc, as used herein, include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc, where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0063] Various modifications to the specific implementations described in this disclosure will be apparent to those of ordinary skill in the art, and the general principles defined herein may be applied to other specific implementations without departing from the spirit or scope of the disclosure. Therefore, the claims are not intended to be limited to the specific implementations shown herein, but are to be accorded the widest scope consistent with the disclosure, the principles and novel features disclosed herein.

[0064] Additionally, various features described in this specification in the context of separate implementations may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented in multiple implementations individually or in any suitable subcombination. Thus, although features may be described above as functioning in a particular combination, and even initially claimed as such, one or more features from a claimed combination may in some cases be deleted from the combination, and a claimed combination may be directed to a subcombination or a variation of a subcombination.

[0065] Similarly, although operations are depicted in a specific order in the figure, this should not be understood as requiring such operations to be performed in the specific order shown or in a sequential order, or to perform all illustrated operations to achieve the desired result. In addition, the accompanying drawings may schematically depict one or more example processes in the form of a flow chart or a flow diagram. However, other operations not depicted can be incorporated into the example processes schematically illustrated. For example, one or more additional operations may be performed before, after, simultaneously or between any operations in the illustrated operations. In some environments, multitasking and parallel processing may be advantageous. In addition, the separation of each system component in the specific implementation described above should not be understood as requiring such separation in all specific implementations, but it should be understood as described program components and systems can usually be integrated together in a single software product, or be packaged in multiple software products.

[0066] The following provides an overview of various embodiments of the disclosure.

[0067] Embodiment 1: An electronic device comprises: a processor having a first processing core and coupled to a first power rail external to the processor; a first current sensor associated with an output of the first power rail and configured to produce a first current sensor reading; a state space unit coupled to the first current sensor and having a memory, the state space unit comprising a prediction model to apply the first current sensor reading to the prediction model to predict a first current budget of the first processing core; and a limit manager configured to generate a first current limit in response to the first current budget and to limit the current draw of the first processing core in response to the first current limit.

[0068] Embodiment 2: The electronic device of Embodiment 1, wherein the limit manager is configured to limit the current draw to be below the first current limit.

[0069] Embodiment 3: The electronic device of Embodiment 1 or 2, wherein the limit manager is configured to limit the current draw by controlling a first input clock frequency to the first processing core.

[0070] Embodiment 4: The electronic device according to any one or more of embodiments 1 to 3, wherein the prediction model comprises a state-space model, and the state-space model is configured to select a predicted future state of the first processing core.

[0071] Embodiment 5: The electronic device according to embodiment 4, wherein the state-space model is configured to select the predicted future state by calculating possible future states using the prediction model and selecting one of the possible future states as the predicted future state.

[0072] Embodiment 6: The electronic device of Embodiment 5, wherein the state-space model is configured to select one of the possible future states by performing a quadratic optimization operation.

[0073] Embodiment 7: The electronic device of Embodiment 5 or 6, wherein the possible future states represent a set of regions, each region corresponding to a range of the first current sensor readings.

[0074] Embodiment 8: An electronic device according to any one or more of embodiments 1 to 7, wherein the state space unit comprises a plurality of multiplication-accumulation computing units, and the plurality of multiplication-accumulation computing units are configured to perform a linear transformation of the first current sensor reading to predict a first current budget.

[0075] Embodiment 9: The electronic device according to embodiment 8, wherein the multiplication-accumulation computing unit is coupled to a register representing a value of the prediction model and a finite state machine to load the first current sensor reading and the value representing the prediction model into the multiplication-accumulation computing unit.

[0076] Embodiment 10: The electronic device according to any one or more of Embodiments 1 to 9 further includes: a first substrate of the system on chip, the first substrate including the processor; and a second substrate separated from the first substrate including the first current sensor.

[0077] Embodiment 11: An electronic device according to any one or more of embodiments 1 to 10, wherein the processor also includes a second processing core and is coupled to a second power rail external to the processor, and wherein the electronic device also includes: a second current sensor, the second current sensor is associated with the output of the second power rail and is configured to produce a second sensor reading, wherein the state space unit is further coupled to the second current sensor to apply the second current sensor reading to the prediction model to predict a second current budget for the second processing core, and wherein the limit manager is further configured to generate a second current limit in response to the second current budget, and to limit additional current draw of the second processing core in response to the second current limit.

[0078] Embodiment 12: An electronic device according to embodiment 11, wherein the first power rail is coupled to a first power management integrated circuit (PMIC) that controls a first voltage on the first power rail, and the second power rail is coupled to a second PMIC that controls a second voltage on the second power rail.

[0079] Embodiment 13: An electronic device according to Embodiment 12 or 13, wherein the first PMIC and the second PMIC are coupled to a common power supply, and the electronic device also includes a third current sensor coupled between the common power supply and the first PMIC and the second PMIC and coupled to the state space unit, wherein the third current sensor is configured to generate a third current sensor reading, and wherein the state space unit is further configured to apply the third current sensor reading to predict the first current budget.

[0080] Embodiment 14: The electronic device of Embodiment 14, wherein the common power supply is on a peripheral component interconnect card and coupled to a peripheral component interconnect card edge power connector.

[0081] Embodiment 15: The electronic device of Embodiment 12, wherein the first PMIC comprises a voltage regulator coupled between the common power supply and the power rail.

[0082] Embodiment 16: An electronic device according to embodiment 14 or 15, wherein the limit manager determines a slew rate as a rate of change of the current of the third current sensor, and wherein the state space unit is further configured to apply the slew rate to predict the first current budget and the second current budget.

[0083] Embodiment 17: The electronic device of Embodiment 16, wherein the state space unit is configured to repeatedly change the first current budget and the second current budget over time and limit the amount of each change to control the slew rate.

[0084] Embodiment 18: A method for limit management of a power distribution network, comprising: reading a first current sensor associated with an output of a first power rail to produce a first current sensor reading, wherein the first power rail is coupled to a first processing core of a processor; applying the first current sensor reading to a predictive model to predict a first current budget for the first processing core; generating a first current limit in response to the first current budget; and limiting the current draw of the first processing core in response to the first current limit.

[0085] Embodiment 19: The method of Embodiment 18, wherein predicting a first current budget comprises using a state-space model to select a predicted future state of the first processing core.

[0086] Embodiment 20: A method according to embodiment 19, wherein selecting the predicted future state includes performing a secondary optimization operation.

[0087] Embodiment 21: The method of Embodiment 19, wherein selecting a predicted future state comprises calculating possible future states using the prediction model and selecting one of the possible future states as the predicted future state.

[0088] Embodiment 22: The method of any one or more of Embodiments 19 to 21, wherein the possible future states represent a set of regions, each region corresponding to a range of first current sensor readings.

[0089] Embodiment 23: A non-transitory computer-readable medium having instructions stored therein, the instructions being used to cause a processor to perform operations for limit management of a power distribution network, the operations comprising: reading a first current sensor associated with an output of a first power rail to produce a first current sensor reading, the first power rail being coupled to a first processing core of a processor; applying the first current sensor reading to a predictive model to predict a first current budget for the first processing core; and generating a first current limit in response to the first current budget; and limiting current draw of the first processing core in response to the first current limit.

[0090] Embodiment 24: The non-transitory computer readable medium of Embodiment 23, wherein predicting a first current budget comprises performing a linear transformation of the first current sensor reading via a plurality of multiply-accumulate computational units.

[0091] Embodiment 25: According to the non-transitory computer-readable medium of embodiment 23 or 24, the operation also includes: reading a second current sensor associated with the output of the second power rail coupled to the second processing core of the processor to produce a second current sensor reading; applying the second current sensor reading to the prediction model to predict a second current budget for the second processing core; generating a second current limit in response to the second current budget; and limiting additional current draw of the second processing core in response to the second current limit.

[0092] Embodiment 26: According to the non-transitory computer-readable medium of any one or more of Embodiments 23 to 25, the operation also includes reading a third current sensor associated with a common power supply to generate a third current sensor reading, wherein the common power supply is coupled to a first power management integrated circuit (PMIC) that controls a first voltage on the first power rail and is coupled to a second PMIC that controls a second voltage on the second power rail; and applying the third current sensor reading to the prediction model to predict the first current budget and the second current budget.

[0093] Embodiment 27: According to the non-transitory computer readable medium described in embodiment 26, the operation also includes: determining a slew rate as a rate of change of the current read by the third current sensor; and applying the slew rate to the prediction model to predict the first current budget and the second current budget.

[0094] Embodiment 28: The non-transitory computer readable medium of Embodiment 27, wherein predicting the first current budget and the second current budget comprises repeatedly changing the first current budget and the second current budget over time and limiting an amount of each change to control the slew rate.

Claims

1. An electronic device, comprising: a processor having a first processing core and coupled to a first power rail external to the processor; a first current sensor associated with an output of the first power rail and configured to generate a first current sensor reading; a state-space unit coupled to the first current sensor and having a memory, the state-space unit including a prediction model to apply the first current sensor reading to the prediction model to predict a first current budget for the first processing core; and A limit manager is configured to generate a first current limit in response to the first current budget and to limit a current draw of the first processing core in response to the first current limit. 2 . The electronic device of claim 1 , wherein the limit manager is configured to limit the current draw to be below the first current limit. 3 . The electronic device of claim 1 , wherein the limit manager is configured to limit the current draw by controlling a first input clock frequency to the first processing core. 4 . The electronic device of claim 1 , wherein the prediction model comprises a state-space model configured to select a predicted future state of the first processing core. 5 . The electronic device of claim 4 , wherein the state-space model is configured to select the predicted future state by calculating possible future states using the prediction model and selecting one of the possible future states as the predicted future state. 6 . The electronic device of claim 5 , wherein the state-space model is configured to select one of the possible future states by performing a quadratic optimization operation. 7 . The electronic device of claim 5 , wherein the possible future states represent a set of regions, each region corresponding to a range of the first current sensor readings. 8 . The electronic device of claim 1 , wherein the state-space unit comprises a plurality of multiply-accumulate computation units configured to perform a linear transformation of the first current sensor reading to predict a first current budget.

9. The electronic device of claim 8, wherein the multiplication-accumulation computing unit is coupled to a register representing a value of the prediction model and a finite state machine to load the first current sensor reading and the value representing the prediction model into the multiplication-accumulation computing unit.

10. The electronic device according to claim 1, further comprising: a first substrate of a system on chip, wherein the first substrate comprises the processor; and A second substrate separated from the first substrate includes the first current sensor.

11. The electronic device of claim 1 , wherein the processor further comprises a second processing core and is coupled to a second power rail external to the processor, and wherein the electronic device further comprises: a second current sensor associated with the output of the second power rail and configured to produce a second sensor reading, wherein the state space unit is further coupled to the second current sensor to apply the second current sensor reading to the prediction model to predict a second current budget for the second processing core, and Wherein the limit manager is further configured to generate a second current limit in response to the second current budget, and to limit additional current draw of the second processing core in response to the second current limit.

12. The electronic device of claim 11, wherein the first power rail is coupled to a first power management integrated circuit (PMIC) that controls a first voltage on the first power rail, and the second power rail is coupled to a second PMIC that controls a second voltage on the second power rail.

13. The electronic device of claim 12, wherein the first PMIC and the second PMIC are coupled to a common power supply, the electronic device further comprising a third current sensor coupled between the common power supply and the first PMIC and the second PMIC and coupled to the state-space unit, wherein the third current sensor is configured to generate a third current sensor reading, and wherein the state-space unit is further configured to apply the third current sensor reading to predict the first current budget.

14. The electronic device of claim 14, wherein the common power supply is on a PCI card and coupled to a PCI card edge power connector.

15. The electronic device of claim 14, wherein the first PMIC comprises a voltage regulator coupled between the common power supply and the power rail. 16 . The electronic device of claim 14 , wherein the limit manager determines a slew rate as a rate of change of the current of the third current sensor, and wherein the state-space unit is further configured to apply the slew rate to predict the first current budget and the second current budget. 17 . The electronic device of claim 16 , wherein the state-space unit is configured to repeatedly change the first current budget and the second current budget over time and to limit an amount of each change to control the slew rate.

18. A method for limiting management of a power distribution network, the method comprising: reading a first current sensor associated with an output of a first power rail coupled to a first processing core of a processor to produce a first current sensor reading; applying the first current sensor reading to a prediction model to predict a first current budget for the first processing core; generating a first current limit in response to the first current budget; as well as A current draw of the first processing core is limited in response to the first current limit.

19. The method of claim 18, wherein predicting a first current budget comprises using a state-space model to select a predicted future state of the first processing core.

20. The method of claim 19, wherein selecting a predicted future state comprises calculating possible future states using the prediction model and selecting one of the possible future states as the predicted future state.

21. The method of claim 20, wherein the possible future states represent a set of regions, each region corresponding to a range of first current sensor readings.

22. The method of claim 19, wherein selecting the predicted future state comprises performing a quadratic optimization operation.

23. A non-transitory computer readable medium having stored therein instructions for causing a processor to perform operations for limit management of a power distribution network, the operations comprising: reading a first current sensor associated with an output of a first power rail coupled to a first processing core of a processor to produce a first current sensor reading; applying the first current sensor reading to a prediction model to predict a first current budget for the first processing core; generating a first current limit in response to the first current budget; as well as A current draw of the first processing core is limited in response to the first current limit. 24 . The non-transitory computer readable medium of claim 23 , wherein predicting a first current budget comprises performing a linear transformation of the first current sensor reading via a plurality of multiply-accumulate computational units.

25. The non-transitory computer readable medium of claim 23, the operations further comprising: reading a second current sensor associated with the output of a second power rail coupled to a second processing core of the processor to produce a second current sensor reading; applying the second current sensor reading to the prediction model to predict a second current budget for the second processing core; generating a second current limit in response to the second current budget; as well as Additional current draw by the second processing core is limited in response to the second current limit.

26. The non-transitory computer readable medium of claim 23, the operations further comprising reading a third current sensor associated with a common power supply to produce a third current sensor reading, wherein the common power supply is coupled to a first power management integrated circuit (PMIC) that controls a first voltage on the first power rail and to a second PMIC that controls a second voltage on the second power rail; and The third current sensor reading is applied to the prediction model to predict the first current budget and the second current budget.

27. The non-transitory computer readable medium of claim 26, the operations further comprising: determining a slew rate as a rate of change of current read by the third current sensor; as well as The slew rate is applied to the prediction model to predict the first current budget and the second current budget. 28 . The non-transitory computer readable medium of claim 27 , wherein predicting the first current budget and the second current budget comprises repeatedly changing the first current budget and the second current budget over time and limiting an amount of each change to control the slew rate.

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