Recording device, non-volatile storage device, and recording method

Abstract

A recording device records data to a non-volatile storage device in a recording mode that ensures a minimum recording speed. The non-volatile memory device has a memory that performs data recording in accordance with an NVMe standard and / or an SD memory card standard. The memory ensures the recording speed for continuous stream recording. A control command transmitted from the recording device to the non-volatile storage device includes information indicating a transition to the optimal performance operation mode, and the non-volatile storage device operates with a required minimum performance corresponding to the guaranteed speed.

Description

Technical Field

[0001] The present disclosure relates to a recording device for recording data to a nonvolatile storage device, a nonvolatile storage device, and a speed-guaranteed recording method to the nonvolatile storage device. Background Art

[0002] Patent Document 1 discloses a technique capable of requiring a memory card to perform data recording at a guaranteed minimum recording speed.

[0003] Patent Document 1 discloses a procedure for reading and writing data between a host device and a memory card.

[0004] Patent Document 1 adopts a structure in which an interface complies with the PCI Express standard and a protocol for accessing a nonvolatile memory complies with the NVM Express standard (hereinafter, abbreviated as “NVMe standard”).

[0005] Specifically, the shooting device as a host device is connected to the memory card via a PCI Express interface (hereinafter referred to as "PCIe interface"), and the NVMe standard protocol is used to read / write data from / to the memory card.

[0006] Prior Art Literature

[0007] Patent Literature

[0008] Patent Document 1: Japanese Patent Application Publication No. 2020-177413 Summary of the invention

[0009] -Problems to be solved by the invention-

[0010] An object of the present disclosure is to provide a technology for suppressing a temperature rise in a nonvolatile memory device when data is recorded in the nonvolatile memory device while guaranteeing a minimum recording speed.

[0011] -Methods for solving problems-

[0012] The recording device disclosed in the present invention records data to a non-volatile storage device at a guaranteed minimum recording speed, and the recording device comprises: an interface unit, which is physically connected to the non-volatile storage device and has a transmission speed faster than the minimum recording speed, and the interface unit is capable of sending data write instructions for data recording and control instructions including instructions for speed-guaranteed recording and instructions for transitioning to an optimal performance operation mode to the non-volatile storage device; after sending the instructions for speed-guaranteed recording and the instructions for transitioning to an optimal performance operation mode, the data write instructions for data recording are sent to the non-volatile storage device.

[0013] In addition, the non-volatile storage device disclosed in the present invention is capable of recording data at a minimum recording speed guaranteed by using a recording device, and the non-volatile storage device comprises: an interface unit, which is physically connected to the recording device and has a transmission speed faster than the minimum recording speed, and the interface unit is capable of receiving a data write instruction for data recording and a control instruction including an instruction for indicating speed-guaranteed recording and an instruction for indicating a transition to an optimal performance operation mode from the recording device, and after receiving the instruction for indicating speed-guaranteed recording and the instruction for indicating a transition to an optimal performance operation mode, receiving a data write instruction for data recording.

[0014] In addition, the recording method disclosed in the present invention is a recording method performed in a recording device that records data at a minimum recording speed in a non-volatile storage device via an interface unit having a transmission speed faster than the guaranteed minimum recording speed. In this recording method, an instruction indicating speed-guaranteed recording and an instruction indicating a transition to an optimal performance operation mode are sent, and a data write instruction for data recording is sent.

[0015] -Effects of the Invention-

[0016] According to the present disclosure, it is possible to provide a technology for suppressing a temperature rise in a nonvolatile memory device when data is recorded in the nonvolatile memory device while guaranteeing a minimum recording speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a structural diagram of the storage system based on the present disclosure.

[0018] Figure 2 It is a block diagram of a storage system according to an exemplary embodiment.

[0019] Figure 3 It is a block diagram of a storage system according to an exemplary embodiment.

[0020] Figure 4 This is a diagram showing an outline of the structure of an input-output stage circuit of a full-duplex interface.

[0021] Figure 5 This is a diagram showing an outline of the structure of an input-output stage circuit of a half-duplex interface.

[0022] Figure 6 It is a diagram showing an example of the shape and structure of a terminal portion of an exemplary memory card.

[0023] Figure 7 FIG. 1 is a diagram showing an example of the shape and structure of a terminal portion of an exemplary memory card.

[0024] Figure 8This is a diagram showing the relationship between the video speed class and the interface speed mode in the SD memory card.

[0025] Fig. 9 This is a diagram showing the relationship between the capacity of an SD memory card and the card type.

[0026] Fig.10 This is a diagram showing the relationship between the video speed class and the clock status in the SD memory card.

[0027] Fig.11 This is a diagram showing the relationship between the video speed class and the data transfer speed in an SD memory card.

[0028] Fig.12 It is a diagram showing the data transmission method of SDR and DDR.

[0029] Fig.13 The figure shows the relationship between the transmission speed (bit rate) and the clock frequency of the UHS-II interface in the SD memory card.

[0030] Fig.14 This is a diagram showing the relationship between the bus speed mode and the maximum power consumption of the SD memory card.

[0031] Fig.15 This is a diagram showing the relationship between the video speed class of an SD memory card and the power consumption limit.

[0032] Fig.16 The figure shows the correspondence between the bus speed mode of the SD Express card and the SD Express speed class.

[0033] Fig.17 This is a diagram showing the data structure of "CMD20" of a conventional SD memory card.

[0034] Fig.18 This is a diagram showing an example of a control command developed by the inventors of the present invention, which transmits information instructing a transition to the best performance operation mode from a recording device to a nonvolatile storage device.

[0035] Fig.19 This is a diagram showing an example of a command sequence during speed-guaranteed recording in a conventional SD memory card.

[0036] Fig. 20 This is a diagram showing an example of a command sequence during speed-guaranteed recording in an SD Express card.

[0037] Fig.21 This is a diagram showing an example of a command sequence developed by the inventors for realizing, in an SD memory card, sending information instructing a transition to a best performance operation mode from a recording device to a nonvolatile storage device.

[0038] Fig. 22 This is a diagram showing an example of a command sequence developed by the inventors for realizing, in an SD Express card, sending information instructing a transition to a best performance operation mode from a recording device to a nonvolatile storage device.

[0039] Fig.23 The diagram shows that, in DSPEC (16 bits) of a data write command of the NVMe standard, 8 bits of DSPEC (stream ID), 4 bits of “SCC” of “CMD20”, and 3 bits of “CNT / ID” are described.

[0040] Fig.24 This is a diagram showing a specific example of parameters when the function of "CMD20" is assigned to a data write instruction of the NVMe standard.

[0041] Fig.25 This is a diagram showing the data structure of a Dataset Management instruction of the NVMe standard.

[0042] Fig.26 This is a diagram showing an example of allocation of the “CMD20” function set based on the parameters of the Dataset Management command of the NVMe standard.

[0043] Fig. 27 This is a diagram showing the data structure of "CMD6" of a conventional SD memory card.

[0044] Fig.28 This is a diagram showing the data structure of the Set Features command of the NVMe standard.

[0045] Fig.29 The figure shows the function (Feature) specified by the feature identifier (Feature Identifier) ​​of the set feature command (Set Features command) of the NVMe standard.

[0046] Fig.30 This is a diagram showing the data structure of a SetFeatures command for setting the power consumption management function of the NVMe standard.

[0047] Fig.31 This is a diagram showing an example of a plurality of Power States (power consumption states) supported by the SD Express card.

[0048] Fig.32The figure shows the structure of the Identify Controller Data Structure of the NVMe standard, the Power State (power consumption state), and the Vendor Specific area.

[0049] Fig.33 The figure shows an example of the Speed ​​Class (speed class) and the Speed ​​Class Power State (speed class power consumption state) notified from the SD Express card to the host device.

[0050] Fig.34 This is a diagram showing an example of the Speed ​​Class Power State (speed class power consumption state) of the SD Express card in a Gen4x1 card.

[0051] Fig.35 This is a diagram showing an example of the Speed ​​Class Power State (speed class power consumption state) of the SD Express card in a Gen4x1 card.

[0052] Fig.36 This is a diagram showing an example of a command sequence for realizing, in an SD Express card, sending information instructing a transition to the best performance operation mode from a recording device to a nonvolatile storage device. DETAILED DESCRIPTION

[0053] The following describes the embodiments in detail with reference to the accompanying drawings as appropriate. However, unnecessary detailed descriptions are sometimes omitted. For example, detailed descriptions of known matters and repeated descriptions of substantially the same structures are sometimes omitted. This is to avoid the following description from becoming unnecessarily lengthy and to make it easy for those skilled in the art to understand.

[0054] In addition, the inventor provides the drawings and the following description in order to enable those skilled in the art to fully understand the present disclosure, and does not intend to limit the subject matter described in the claims thereby.

[0055] [1. Storage system structure]

[0056] Figure 1 The structure of a storage system 1 according to the present disclosure is shown. The storage system 1 includes a recording device 10 as a host device and a nonvolatile storage device 20. In the storage system 1, the recording device 10 can write data to the nonvolatile storage device 20 and can read data stored in the nonvolatile storage device 20.

[0057] For example, consider a storage system 1 that includes a PCIe / NVMe SSD as the nonvolatile storage device 20 and a PC as the recording device 10. The so-called PCIe / NVMe SSD refers to an SSD (Solid State Drive) that adopts the PCIe (PCI Express) standard as a connection interface and the NVMe (Non-Volatile Memory Express) standard as a data transfer protocol.

[0058] Another example is a storage system 1 having an SD Express memory card as a non-volatile storage device 20 and a moving image recording device such as a digital camera or a digital movie as a recording device 10. The SD Express memory card is a memory card having an existing connection interface and a PCIe interface added thereto. The connection interface of the existing SD memory card and the PCIe interface are used exclusively. That is, the SD Express memory card acts as an SD memory card when installed in the SD memory card slot. On the other hand, when the SD Express memory card is installed in an SD Express-compatible device having a PCIe interface, it is connected in accordance with the PCIe standard and data is transferred and received in accordance with the protocol specified by the NVMe standard.

[0059] The recording device 10 includes a system control unit 12, a buffer memory 14, and an interface unit 16. These components are connected to each other via a bus 11, and can transmit and receive data.

[0060] The system control unit 12 is a controller composed of a semiconductor integrated circuit. The system control unit 12 controls the entire recording device 10. The system control unit 12 controls the issuance (transmission) of commands to the nonvolatile storage device 20 via the interface unit 16, and controls the response from the nonvolatile storage device 20. In addition, the system control unit 12 prepares data to be written to the nonvolatile storage device 20, and specifically, accumulates the data to be written to the nonvolatile storage device 20 in the buffer memory 14. The system control unit 12 processes the data read from the nonvolatile storage device 20 and accumulated in the buffer memory 14.

[0061] The buffer memory 14 temporarily stores data written into the nonvolatile storage device 20 and / or data read out from the nonvolatile storage device 20 .

[0062] The interface unit 16 communicates with the interface unit 26 of the nonvolatile storage device 20. Specifically, the interface unit 16 is a general term for an interface that sends commands to the nonvolatile storage device 20, receives responses from the nonvolatile storage device 20, and sends and receives data written to the nonvolatile storage device 20 and / or reads data from the nonvolatile storage device 20.

[0063] The nonvolatile storage device 20 includes a controller 22, a buffer memory 24, an interface unit 26, a memory control unit 28, and a nonvolatile memory 30. These components are connected to each other via a bus 21, and can transmit and receive data.

[0064] The controller 22 controls the overall operation of the nonvolatile storage device 20. The buffer memory 24 is a memory that temporarily stores data received from the recording device 10 and written to the nonvolatile memory 30 and / or data read from the nonvolatile memory 30 and transmitted to the recording device 10.

[0065] The interface unit 26 communicates with the interface unit 16 of the recording device 10. Specifically, the interface unit 26 receives commands from the recording device 10 and sends responses to the recording device 10. In addition, the interface unit 26 sends and receives data to be written and / or data that has been read with the interface unit 16 of the recording device 10. The interface unit 26 is a general term for interfaces that can perform these operations.

[0066] The memory control unit 28 is an integrated circuit that performs writing control of data into the nonvolatile memory 30 and reading control of data from the nonvolatile memory 30 .

[0067] The nonvolatile memory 30 is a nonvolatile memory that can retain data even when power is not supplied, and is, for example, a flash memory.

[0068] Next, refer to Figure 2 A more specific configuration example of the storage system 1 will be described.

[0069] Figure 2 The structure of a storage system 2 according to an exemplary embodiment is shown. The storage system 2 includes a recording device 100 as a host device and an SD Express memory card (hereinafter, simply referred to as “memory card 200”) as a non-volatile storage device. The recording device 100 is, for example, a digital camera, a digital video camera, or a driving recorder.

[0070] As described above, the memory card 200 is formed by further adding a PCIe interface to an SD memory card having a connection interface based on the existing SD standard. The memory card 200 supports the existing SD interface and can be used in an existing SD host device. Furthermore, in order to meet the storage requirements of high speed and large capacity, the memory card 200 adopts a PCIe interface and has a specification that is interchangeable with the PCI Express standard. The specific hardware structure of the memory card 200 will be described later.

[0071] The recording device 100 includes an interface unit 102 , a PCIe / NVMe driver 104 , an SD driver 106 , a file system 108 , and application software 110 . Among these, the PCIe / NVMe driver 104 , the SD driver 106 , the file system 108 , and the application software 110 function as a software layer of the recording device 100 .

[0072] The interface unit 102 corresponds to the hardware of the recording device 100, for example, an interface part in a SoC (System on Chip) which is a semiconductor product such as LSI or VLSI. The interface unit 102 includes a PCIe interface 102a, an SD host 102b, and a selector 102c.

[0073] The PCIe interface 102a is an interface for connection in accordance with the PCIe standard. When transmitting data, the PCIe interface 102a transmits and receives data by following the protocol of the NVMe standard.

[0074] The SD host 102b is an interface for connection in accordance with the SD standard. When transmitting data, the SD host 102b transmits and receives data using a protocol in accordance with the SD standard. The selector 102c is a switch for realizing exclusive use of the PCIe interface 102a and the SD host 102b.

[0075] The memory card 200 has a controller 210 and a NAND flash memory 220 .

[0076] The controller 210 includes a CPU 212 , a PCIe interface 214 a , an SD interface 214 b , a buffer memory 216 , and a NAND control unit 218 .

[0077] CPU212 is equivalent to Figure 1 The controller 22 in the memory card 200 controls the overall operation.

[0078] The PCIe interface 214a is an interface for connection in accordance with the PCIe standard. When transmitting data, the PCIe interface 214a transmits and receives data by following the protocol of the NVMe standard.

[0079] The SD interface 214b is an interface for connection in compliance with the SD standard. When transmitting data, the SD interface 214b transmits and receives data using a protocol in compliance with the SD standard.

[0080] The buffer memory 216 is a memory that temporarily stores data received from the recording device 100 and written to the NAND flash memory 220 and / or data read from the NAND flash memory 220 and transmitted to the recording device 100 .

[0081] The NAND control unit 218 controls writing of data to the NAND flash memory 220 and / or reading of data from the NAND flash memory 220 .

[0082] Next, refer to Figure 6 The specific shapes and structures of the PCIe interface 214a and the SD interface 214b of the memory card 200 will be described.

[0083] Figure 6 FIG. 2 shows an example of a shape structure related to a terminal portion of an exemplary memory card 200. Figure 6 In order to facilitate understanding, the sets of terminals of the respective interfaces are enclosed by dotted lines and represented as terminal group 232 and terminal group 234 .

[0084] The memory card 200 includes a terminal group 232 (terminals “1” to “9”) as a connection interface based on the SD standard and a terminal group 234 (terminals “10” to “17”) as a connection interface based on the PCIe standard. Figure 6 The structure example complies with the SDExpress card standard (SD Ver.7.0).

[0085] Furthermore, when the specification of the UHS-II interface was established according to the SD memory card standard (SD Ver.4.0), in addition to the terminal group for the SD interface (terminal group 232) specified by the standards before SD Ver.4.0, a new terminal group 234 was set up for the UHS-II interface.

[0086] Later, when the specification for introducing the PCIe interface according to the SD Express card standard (SD Ver.7.0) was formulated, the terminal group 234 newly set up for the UHS-II interface according to SD Ver.4.0 was directly used, and the signal of one channel of the PCIe interface was allocated to the terminal group 234.

[0087] In SD Express cards that comply with SD Ver.7.0, due to Figure 6 Terminal group 234 is allocated to the PCIe interface, so the UHS-II interface cannot be used.

[0088] Furthermore, in the SD Express card standard (SD Ver.8.0), in order to allocate the signals of the two channels of the PCIe interface, such as Figure 7 As shown, in addition to the terminal group 232 and the terminal group 234, a terminal group 236 is newly provided.

[0089] Refer again Figure 6 Let's continue with the description of the memory card 200 that complies with the SD Express card standard (SD Ver.7.0). The data bus of the SD interface consists of 4 bits, and the bit "0" (DAT0) of the data line is assigned to the terminal "7", the bit "1" (DAT1) is assigned to the terminal "8", the bit "2" (DAT2) is assigned to the terminal "9", and the bit "3" (DAT3) is assigned to the terminal "1".

[0090] The data bus of the PCIe interface is composed of two sets of transmission paths based on the differential transmission method. The + signal of the Tx transmission path (host device output / card input) is assigned to terminal "11", the - signal of the Tx transmission path (host device output / card input) is assigned to terminal "12", the + signal of the Rx transmission path (host device input / card output) is assigned to terminal "16", and the - signal of the Rx transmission path (host device input / card output) is assigned to terminal "15". These pairs (1 group) of Tx transmission paths and Rx transmission paths are called channels in the PCIe standard. Figure 6 The memory card 200 shown has a PCIe interface with one lane.

[0091] In addition, in the SD Express card standard, in the PCIe interface, a transmission path for performing instructions to a memory card, a response from a memory card, or writing data to a memory card and / or reading data is assigned to terminal group 234, but four signals of a PCIe reset signal called PERST#, a PCIe clock request signal called CLKREQ#, and a PCIe differential clock signal pair called REFCLK+ / REFCLK- are respectively assigned to terminal "1", terminal "9", terminal "16", and terminal "15" of terminal group 232, and become a standard for switching signals used during operations in the SD interface and in the PCIe interface.

[0092] Next, refer to Figure 7 The specific shapes and structures of the PCIe interface 214 a and the SD interface 214 b of the memory card 200 that complies with the SD Express card standard (SD Ver. 8.0) will be described.

[0093] Figure 7 and Figure 6The shape and structure example of the terminal part of the exemplary memory card 200 is also shown. Figure 7 In order to facilitate understanding, the terminals of each interface are surrounded by dotted lines and represented as terminal group 232, terminal group 234, and terminal group 236. The memory card 200 has a terminal group 232 (terminal "1" to terminal "9") as a connection interface based on the SD standard, and a terminal group 234 (terminal "10" to terminal "17") and a terminal group 236 (terminal "20" to terminal "27") as a connection interface based on the PCIe standard.

[0094] and Figure 6 The memory card 200 compliant with the SD Express card standard (SD Ver.7.0) shown in the figure is different in shape and structure in that it has a connection interface based on the PCIe standard with two channels. The memory card 200 compliant with the SD Express card standard (SD Ver.8.0) has two sets (two channels) of Tx transmission paths and one pair (one set) of Rx transmission paths, thereby achieving a transmission speed twice that of the SD Express card standard (SD Ver.7.0).

[0095] Next, refer to Figure 3 Another more specific configuration example of the storage system 1 will be described.

[0096] Figure 3 The structure of the storage system 3 according to the exemplary embodiment is shown. The storage system 3 includes a recording device 100 as a host device and an SD memory card (hereinafter, simply referred to as “memory card 200”) as a non-volatile storage device. The recording device 100 is, for example, a digital camera, a digital video camera, or a driving recorder.

[0097] As described above, the memory card 200 is formed by further adding a UHS-II interface specified by the SD memory card standard (SD Ver.4.0) to the SD memory card having a connection interface based on the existing SD standard. The memory card 200 supports the existing SD interface and can be used in an existing SD host device. Furthermore, in the memory card 200, the UHS-II interface is adopted to meet the storage requirements of high speed and large capacity. The specific hardware structure of the memory card 200 will be described later.

[0098] The recording device 100 includes an interface unit 302 , a UHS-II driver 304 , an SD driver 106 , a file system 108 , and application software 110 . Among these, the UHS-II driver 304 , the SD driver 106 , the file system 108 , and the application software 110 function as a software layer of the recording device 100 .

[0099] The interface unit 302 corresponds to the hardware of the recording device 100, for example, an interface part in a SoC which is a semiconductor product such as LSI or VLSI. The interface unit 302 includes a UHS-II interface 302a, an SD host 302b, and a selector 302c.

[0100] The UHS-II interface 302a is an interface for connection in compliance with the UHS-II Addendum of the SD memory card standard. When transmitting data, the UHS-II interface 302a transmits and receives data using a protocol in compliance with the UHS-II Addendum of the SD memory card standard.

[0101] The SD host 302b is an interface for connection in accordance with the SD standard. When transmitting data, the SD host 302b transmits and receives data using a protocol in accordance with the SD standard. The selector 302c is a switch for realizing exclusive use of the UHS-II interface 302a and the SD host 302b.

[0102] The memory card 200 has a controller 210 and a NAND flash memory 220 .

[0103] The controller 210 includes a CPU 212 , a UHS-II interface 314 a , an SD interface 314 b , a buffer memory 216 , and a NAND control unit 218 .

[0104] CPU212 is equivalent to Figure 1 The controller 22 in the memory card 200 controls the overall operation of the memory card 200. The UHS-II interface 314a is an interface for connection in accordance with the UHS-II annex of the SD memory card standard. When transmitting data, the UHS-II interface 314a transmits and receives data by following the protocol of the UHS-II annex of the SD memory card standard.

[0105] The SD interface 314b is an interface for connection in compliance with the SD standard. When transmitting data, the SD interface 314b transmits and receives data using a protocol in compliance with the SD standard.

[0106] The buffer memory 216 is a memory that temporarily stores data received from the recording device 100 and written to the NAND flash memory 220 and / or data read from the NAND flash memory 220 and transmitted to the recording device 100 .

[0107] The NAND control unit 218 controls writing of data to the NAND flash memory 220 and / or reading of data from the NAND flash memory 220 .

[0108] Next, refer to Figure 6The specific shapes and structures of the UHS-II interface 314 a and the SD interface 314 b of the memory card 200 will be described.

[0109] Figure 6 The figure shows an example of the shape structure of the terminal portion of the exemplary memory card 200. The memory card 200 has a terminal group 232 (terminal "1" to terminal "9") as a connection interface based on the SD standard, and a terminal group 234 (terminal "10" to terminal "17") as a connection interface based on the UHS-II supplement of the SD memory card standard. Figure 6 The structure example complies with the SD memory card standard (SD Ver.4.0 or later).

[0110] The data bus of the SD interface consists of 4 bits, and bit "0" (DAT0) of the data line is assigned to terminal "7", bit "1" (DAT1) is assigned to terminal "8", bit "2" (DAT2) is assigned to terminal "9", and bit "3" (DAT3) is assigned to terminal "1".

[0111] The data bus of the UHS-II interface consists of two sets of transmission paths based on the differential transmission method. The + signal of transmission path "0" is assigned to terminal "11", the - signal of transmission path "0" is assigned to terminal "12", the + signal of transmission path "1" is assigned to terminal "16", and the - signal of transmission path "1" is assigned to terminal "15".

[0112] In addition, in the SD memory card standard, a transmission path for issuing instructions to a memory card, responding from a memory card, or writing data to a memory card and / or reading data through a UHS-II interface is assigned to terminal group 234, but two signals of a differential clock signal pair of UHS-II called RCLK+ / RCLK- are assigned to terminals "7" and "8" of terminal group 232, and a standard is used to switch signals when performing actions through the SD interface and when performing actions through the UHS-II interface.

[0113] exist Figure 6 When the memory card 200 is an SD Express card, the maximum value of the transfer speed is 8 Gbit / s. When the memory card 200 is a UHS-II card, the maximum value of the transfer speed is approximately 3 Gbit / s.

[0114] [2. SD memory card standard speed guarantee]

[0115] The SD memory card standard stipulates specifications related to a minimum recording speed guarantee (hereinafter referred to as "speed guarantee") when recording moving images in order to prevent interruptions in moving image recording due to changes or reductions in the recording speed, or "frame drops", such as failure to record a frame of moving image.

[0116] The latest SD memory card speed guarantee standard is called Video Speed ​​Class (VSC), with "VSC6" guaranteeing a minimum recording speed of 6 megabytes / second, "VSC10" guaranteeing a minimum recording speed of 10 megabytes / second, "VSC30" guaranteeing a minimum recording speed of 30 megabytes / second, "VSC60" guaranteeing a minimum recording speed of 60 megabytes / second, and "VSC90" guaranteeing a minimum recording speed of 90 megabytes / second.

[0117] Figure 8 The relationship between the interface speed mode between the host device (recording device 100 ) and the SD memory card and the video speed class, and the types of SD memory cards supporting the video speed class are shown.

[0118] In the HS mode (High Speed ​​Mode) of the SD interface, VSC6 and VSC10 are supported, that is, a minimum recording speed of 10 megabytes / second (MB / s) can be guaranteed.

[0119] In the UHS-I mode of the SD interface, VSC6, VSC10, and VSC30 are supported, that is, a minimum recording speed of 30 megabytes per second (MB / s) can be guaranteed.

[0120] In addition, in the UHS-II mode based on the UHS-II interface, VSC6, VSC10, VSC30, VSC60, and VSC90 are supported, that is, a minimum recording speed of 90 megabytes / second (MB / s) can be guaranteed.

[0121] like Figure 8 As shown on the right side of , Video Speed ​​Class is supported by SDHC cards, SDXC cards, and SDUC cards, but SD cards are not included.

[0122] Fig. 9 The relationship between the types of SD memory cards and their memory capacities is shown. An SD card has a capacity of up to 2 gigabytes. An SDHC card has a capacity of more than 2 gigabytes and up to 32 gigabytes. An SDXC card has a capacity of more than 32 gigabytes and up to 2 terabytes. An SDUC card has a capacity of more than 2 terabytes and up to 128 terabytes. Video Speed ​​Class is supported by cards with a capacity of more than 2 gigabytes.

[0123] Fig.10 This is a table showing clock conditions for measuring the speed of each video speed level.

[0124] For example, in the case of VSC10, in the HS mode of the SD interface, the guaranteed speed is measured with the clock frequency of the SD clock being 40 MHz, in the UHS-I SDR25 mode and DDR50 mode of the SD interface, the guaranteed speed is measured with the clock frequency of the SD clock being 40 MHz, and in the UHS-I SDR50 mode and SDR104 mode of the SD interface, the guaranteed speed is measured with the clock frequency of the SD clock being 80 MHz.

[0125] In the case of VSC10, in the PLL range A of the FD (Full Duplex) mode of the UHS-II interface, the guaranteed speed is measured with a reference clock (RCLK) of 35 MHz, and in the PLL range B of the FD mode, the guaranteed speed is measured with a reference clock of 26 MHz. In the PLL range A of the HD (Half Duplex) mode, the guaranteed speed is measured with a reference clock of 35 MHz, and in the PLL range B of the HD mode, the guaranteed speed is measured with a reference clock of 26 MHz.

[0126] In other words, Fig.10 The speed of each video speed grade must be guaranteed under the conditions of bus speed mode and clock status (clock frequency) shown.

[0127] In addition, regarding SD Express cards, there is no speed guarantee specification yet, but in order to guarantee the recording speed of 4K moving images (number of pixels: 3,840×2,160) and 8K moving images (number of pixels: 7,680×4,320) with higher resolution and higher image quality in the future, it is considered necessary to Fig.16 The standards for video speed classes, such as 150 Mbyte / s, 300 Mbyte / s, 450 Mbyte / s, and 600 Mbyte / s, which are higher than the existing 90 Mbyte / s, are established.

[0128] [3. PCIe transmission method]

[0129] Here, the transmission method of the PCIe interface is briefly described with reference to the accompanying drawings.

[0130] Figure 4 This is a schematic diagram of the structure of an input-output stage circuit in a general FD interface of a differential transmission method, and is a diagram that is simplified in order to make the characteristics of full-duplex communication easier to understand, with particular attention paid to the transmission direction.

[0131] The transmitting circuit 411 of the recording device 100 sends commands from the recording device 100 to the memory card 200 and / or writes data to the nonvolatile memory, and the receiving circuit 421 of the memory card 200 receives commands sent from the recording device 100 and / or writes data to the nonvolatile memory.

[0132] Figure 4 The case where the transmission via the interface (transmission and reception function) formed by the transmission circuit 411 of the recording device 100 and the reception circuit 421 of the memory card 200 is unidirectional transmission from the recording device 100 to the memory card 200 is shown.

[0133] The sending circuit 422 of the memory card 200 sends a response (completion) to the command and / or the read data from the non-volatile memory from the memory card 200 to the recording device 100, and the receiving circuit 412 of the recording device 100 receives the response (completion) to the command sent from the memory card 200 and / or the read data from the non-volatile memory.

[0134] Figure 4 The transmission performed through the interface (transmission and reception function) composed of the transmission circuit 422 of the memory card 200 and the reception circuit 412 of the recording device 100 is shown as a unidirectional transmission from the memory card 200 to the recording device 100 .

[0135] Regarding the PCIe interface, such an interface (transmitting and receiving functions) composed of a transmitting circuit and a receiving circuit is always oriented in one direction.

[0136] [4. UHS-II transmission method]

[0137] Next, the FD mode and the HD mode of the UHS-II interface are briefly described with reference to the drawings.

[0138] In addition, the structure of the input and output stage circuit of the UHS-II interface in FD mode is shown in FIG. Figure 4 , since the transmission method is the same as the aforementioned PCIe interface, the description is omitted.

[0139] Figure 5 This is a schematic diagram of the structure of an input and output stage circuit in a general HD interface of a differential transmission method, and is a diagram that is simplified in order to make the characteristics of half-duplex communication easier to understand, with particular attention paid to the transmission direction.

[0140] The transmitting circuit 511 of the recording device 100 sends commands from the recording device 100 to the memory card 200 and / or writes data to the nonvolatile memory, and the receiving circuit 521 of the memory card 200 receives commands sent from the recording device 100 and / or writes data to the nonvolatile memory.

[0141] The transmitting circuit 523 of the memory card 200 sends a response to a command and / or read data from the nonvolatile memory from the memory card 200 to the recording device 100 , and the receiving circuit 513 of the recording device 100 receives a response to a command and / or read data from the nonvolatile memory sent from the memory card 200 .

[0142] So far, it has become the same as the above Figure 4 The input and output stage circuits have the same structure and the same function.

[0143] On the other hand, Figure 5 In the HD interface shown, a transmission circuit 511 of the recording device 100 is connected to a reception circuit 512 of the recording device 100 , and a reception circuit 521 of the memory card is connected to a transmission circuit 522 of the memory card 200 .

[0144] In addition, the transmission circuit 523 of the memory card 200 is connected to the reception circuit 524 of the memory card 200 , and the reception circuit 513 of the recording device 100 is connected to the transmission circuit 514 of the recording device 100 .

[0145] Control is performed so that the transmission circuit 511 and the reception circuit 512 of the recording device 100 operate exclusively, and the reception circuit 521 and the transmission circuit 522 of the memory card 200 also operate exclusively.

[0146] In addition, control is performed so that when the transmission circuit 511 of the recording device 100 is operated, the reception circuit 521 of the memory card 200 is operated, and when the transmission circuit 522 of the memory card 200 is operated, the reception circuit 512 of the recording device 100 is operated.

[0147] Similarly, control is performed so that the transmission circuit 523 and the reception circuit 524 of the memory card 200 operate exclusively, and the reception circuit 513 and the transmission circuit 514 of the recording device 100 also operate exclusively.

[0148] In addition, control is performed so that when the transmission circuit 523 of the memory card 200 is operated, the reception circuit 513 of the recording device 100 is operated, and when the transmission circuit 514 of the recording device 100 is operated, the reception circuit 524 of the memory card 200 is operated.

[0149] pass Figure 5 The above-mentioned structure and control shown make it possible to switch the direction of the transmission path in the HD mode of the UHS-II interface.

[0150] Here, the SD memory card protocol of the SD memory card standard will be briefly described by taking the case of writing data to the SD memory card as an example.

[0151] When the host device (recording device 100) issues (sends) a data write command to the SD memory card, a response (Response) to the data write command is returned (sent) from the SD memory card to the host device, and thereafter, according to the issued data write command, data to be written to the non-volatile memory is sent from the host device to the SD memory card.

[0152] Furthermore, until the writing of data based on one data writing command issued (sent) from the host device to the SD memory card is completed, the next command cannot be issued from the host device.

[0153] Therefore, based on Figure 4 In the FD communication having the structure, during the transmission of write data based on the data write command, data transmission through the interface (transmitting and receiving function) composed of the transmitting circuit 422 of the memory card 200 and the receiving circuit 412 of the recording device 100 is not performed at all.

[0154] On the other hand, based on Figure 5 In HD communication having a structure of, during the transmission of write data based on a data write instruction, in addition to data transmission through the interface (transmitting and receiving function) composed of the transmitting circuit 511 of the recording device 100 and the receiving circuit 521 of the memory card 200, data transmission through the interface (transmitting and receiving function) composed of the transmitting circuit 514 of the recording device 100 and the receiving circuit 524 of the memory card 200 can also be performed simultaneously, and the write data transmission speed from the recording device 100 to the memory card 200 can be increased to 1000 based on Figure 4 The FD communication of the structure is about 2 times.

[0155] As shown above, in the UHS-II interface, as a specification for determining the transmission speed, two transmission methods are defined, namely, FD mode transmission and HD mode transmission.

[0156] Next, another specification for determining the transmission speed of the UHS-II interface, namely, PLL range A and PLL range B will be briefly described with reference to the accompanying drawings.

[0157] Fig.13 The relationship between the PLL range of the UHS-II interface, the frequency of the reference clock (RCLK), the multiplication rate of the PLL, and the transmission speed (bit rate) is shown.

[0158] The frequency of the reference clock is variable, and its range is from 26 MHz to 52 MHz in both PLL range A and PLL range B.

[0159] On the other hand, regarding the multiplication rate of the PLL, the PLL range A is 15 times and the PLL range B is 30 times, and regarding the transmission speed (bit rate), the PLL range A is from 390 Mbit / s (= 26 MHz × 15) to 780 Mbit / s (= 52 MHz × 15) and the PLL range B is from 780 Mbit / s (= 26 MHz × 30) to 1.56 Gbit / s (= 52 MHz × 30).

[0160] [5. UHS-I transmission method]

[0161] The above-mentioned UHS-II interface adopts differential transmission mode. Figure 6 The terminal group 234 shown is allocated with differential transmission signals of UHS-II.

[0162] On the other hand, UHS-I uses the same single-ended transmission method as the existing SD interface. Figure 6 The terminal group 232 shown is allocated with the single-ended transmission signal of UHS-I.

[0163] Both UHS-I and the existing SD interface use single-ended transmission, but the signal voltage of the existing SD interface is 3.3V. In contrast, the signal voltage of UHS-I is reduced to 1.8V due to its high speed and reduction of unnecessary radiation.

[0164] Fig.12 It is a diagram showing data transmission in SDR mode and DDR mode of UHS-I.

[0165] exist Fig.12 In the SDR (Single Data Rate) mode shown in (a), data is transmitted at the timing of one edge of the clock. Fig.12 In the DDR (Double Data Rate) mode shown in (b), data is transferred at the timing of both edges of the clock. Therefore, if the clock frequency is the same, data can be transferred at twice the speed in the DDR mode as in the SDR mode.

[0166] [6. SD memory card standard speed guarantee level and interface data transfer speed]

[0167] Fig.11 It is based on the above-mentioned UHS-II transmission method and UHS-I transmission method and Fig.10 The clock state of the video speed level is shown in the figure, and the relationship between the video speed level in the SD memory card and the data transfer speed of the interface is derived and shown.

[0168] exist Fig.11 In the table, the upper part of each cell is Fig.10The clock frequency is shown in megahertz. In addition, the lower part of each cell is the data transfer speed of the interface in megabytes per second.

[0169] The following describes, as an example, the data transfer speed of the interface calculated from the clock state in the case of "VSC10", thereby Fig.11 The overall method of viewing the table is provided.

[0170] In the HS mode of the SD interface, the clock frequency of the SD clock is 40 MHz, so the transmission speed of the SD interface based on the 4-bit bus is 20 Mbytes / second. The UHS-I SDR25 mode is also the same, and the transmission speed is 20 Mbytes / second. In the UHS-IDDR50 mode, since the clock frequency of the SD clock is 40 MHz and Fig.12 The DDR shown performs data transfer, so the transfer speed based on a 4-bit bus is 40 Mbytes / second.

[0171] On the other hand, in the PLL range A of the UHS-II interface FD mode, the reference clock frequency is 35 MHz, and the PLL multiplication rate is 15 times, so a simple calculation results in a transmission speed of 525 Mbit / s. However, the UHS-II interface uses 8b10b encoding to convert (modulate) 8 bits of data into 10 bits for transmission, so the actual data transmission speed is 525 Mbit / s × (8 / 10) = 420 Mbit / s. If converted to bytes / second, the data transmission speed is 420 Mbit / s ÷ 8 bits = 52.5 Mbytes / second.

[0172] In addition, in the PLL range B of the UHS-II interface FD mode, the reference clock frequency is 26 MHz, and the PLL multiplication rate is 30 times, so a simple calculation results in a transmission speed of 780 Mbit / s. However, the UHS-II interface uses 8b10b encoding to convert (modulate) 8 bits of data into 10 bits for transmission, so the actual data transmission speed is 780 Mbit / s × (8 / 10) = 624 Mbit / s. If converted to bytes / second, the data transmission speed becomes 624 Mbit / s ÷ 8 bits = 78 Mbytes / second.

[0173] Regarding the UHS-II interface HD mode, as described in "4. UHS-II transmission method", it can achieve a data transmission speed twice that of the UHS-II interface FD mode. Fig.11 As shown, in PLL range A, the data transfer speed becomes 105 Mbytes / second, and in PLL range B, the data transfer speed becomes 156 Mbytes / second.

[0174] As shown above, for example, if the recording speed guaranteed in "VSC10" is 10 Mbytes / second, and the maximum transfer speed of each bus speed mode of the interface (HS, UHS-I, UHS-II) corresponding to "VSC10" is as follows: Fig.14 As shown, 25 Mbyte / sec to 312 Mbyte / sec, the transfer speed is much faster than the minimum recording speed beyond necessity, specifically, 2.5 to 31 times faster than it.

[0175] [7. Speed ​​guarantee level, power consumption and heat issues of SD memory card standards]

[0176] Fig.14 The relationship between the bus speed mode and the maximum power consumption in the SD memory card standard is shown. Fig.15 The relationship between the video speed class and the power consumption limit in the SD memory card standard is shown.

[0177] Fig.14 It shows that the maximum power consumption increases when the bus speed is high. Fig.15 It is shown that as the guaranteed speed of the video speed class increases, the power consumption limit is relaxed, that is, greater power consumption is permitted.

[0178] When the power consumption of the SD memory card increases, the power supply to the SD memory card Figure 2 , Figure 3 The recording device 100 and the power consumption Figure 2 , Figure 3 The heat generated by the memory card 200 increases.

[0179] As power consumption increases, the heat generated by the recording device 100 and the memory card 200 increases. When the temperature of the memory card 200 exceeds the operable temperature range, interruption of dynamic image recording occurs, such as "frame loss" in which one frame of dynamic image is not recorded. In the worst case, damage may be caused to the controller and NAND flash memory constituting the memory card 200.

[0180] Furthermore, the SD memory card standard defines the operating temperature range of the SD memory card as -25°C to 85°C.

[0181] In the case of a digital camera as an example of a host device (recording device 100), generally when a still image is captured and the image data is recorded on an SD memory card, writing to the SD memory card will not occur temporarily, so the average power consumption of the host device and the SD memory card for a certain period of time is reduced, and an extreme temperature increase of the host device and the SD memory card will not occur.

[0182] On the other hand, when a digital video camera or a digital camera with a video shooting function is used as an example of a host device to continuously record video while maintaining the recording speed, the video is continuously written to the SD memory card during the video recording, so the average power consumption of the host device and the SD memory card increases in a certain period of time. If the shooting is prolonged, the temperature of the host device and the SD memory card will rise. As a result, the temperature exceeds the SD memory card's operable temperature range of 85°C by a large margin, which becomes a problem.

[0183] Regarding digital video cameras and digital cameras, which are examples of host devices, due to the recent trend towards high pixelization and high image quality, large amounts of heat are generated by imaging elements such as CMOS sensors and image processing engines (SoCs, etc., which are semiconductor products such as VLSI that perform image processing). On the other hand, due to the requirement for miniaturization of the equipment, high-density mounting is required, making it difficult to dissipate heat, and thermal design has become a major issue.

[0184] [8. Implementation of the best performance operation instruction method from the host device to the memory card]

[0185] From the above-described background, when performing speed-guaranteed recording, a technique for suppressing power consumption as low as possible is required.

[0186] To this end, the inventors of the present invention focused on the following situation: in the current standard of speed guarantee records, when the guaranteed speed of the speed guarantee record is significantly lower than the maximum bus speed of the memory card, that is, when there is a large margin in the efficiency (performance) of the maximum bus speed, there is no mechanism for reducing it to a sufficient efficiency (performance) to operate to achieve the guaranteed speed.

[0187] For example, in Figure 3 In the recording device 100, a memory card 200 corresponding to VSC90 (Video Speed ​​Class 90) is installed. When recording is performed at a speed guaranteed to reach 90 megabytes / second (MB / s), if the host device selects (sets) the HD mode of the UHS-II interface and selects (sets) the PLL range B, then Fig.14 As shown in the bus speed mode "UHS-II HD312", the UHS-II interface 314a of the memory card 200 operates at a maximum speed of 312 Mbytes / second, and in coordination with this, a high-frequency clock is supplied to the CPU 212, the buffer memory 216, the NAND control unit 218, and the NAND flash memory 220, so that they operate at a performance commensurate with the maximum speed of 312 Mbytes / second, thereby achieving a state of improved processing power.

[0188] On the other hand, the recording device 100 can only record data at a maximum speed of 90 megabytes / second (MB / s), that is, there is a large difference of about 3.5 times between the maximum bus speed and the guaranteed speed of speed-guaranteed recording.

[0189] In addition, according to Fig.10 as well as Fig.11 In the bus speed mode and clock state of VSC90 (Video Speed ​​Class 90) shown in the figure, the FD mode of the UHS-II interface is selected (set), the PLL range B is selected (set), and the RCLK supplied by the recording device 100 to the memory card 200 is set to 47 MHz, so that the speed of 90 megabytes / second (MB / s) can be guaranteed to be recorded at the speed of the UHS-II interface 314a in this case (141 megabytes / second). In other words, the speed of 90 megabytes / second (MB / s) can be guaranteed to be recorded at 141 megabytes / second, which is less than half of 312 megabytes / second. The operation at the maximum processing capacity obtained by supplying a high-frequency clock to the CPU 212, the buffer memory 216, the NAND control unit 218, and the NAND flash memory 220 for operating at an efficiency commensurate with the speed of 312 megabytes / second is obviously excessive efficiency (exceeding the specification).

[0190] In addition, Figure 2 The recording device 100 is equipped with Fig.16 In the case of an SD Express card (memory card 200) corresponding to SD Express speed class 600MB / s shown in the figure, when recording at a guaranteed speed of 600 megabytes / second (MB / s), when a host device uses two lanes of Gen4 (fourth generation) of the PCIe interface to record, as shown in FIG. Fig.14 , Fig.16 As shown in the bus speed mode "Gen4x2", the PCIe interface 214a of the SD Express card (memory card 200) operates at 3,938 Mbytes / second, and in coordination with this, a high-frequency clock is supplied to the CPU 212, the buffer memory 216, the NAND control unit 218, and the NAND flash memory 220, so that they operate at a performance commensurate with the maximum speed of 3,938 Mbytes / second, thereby maximizing the processing capacity.

[0191] On the other hand, the recording device 100 can only record data at a maximum speed of 600 megabytes / second (MB / s), that is, there is a very large difference of about 6.6 times between the maximum bus speed and the guaranteed speed of speed-guaranteed recording.

[0192] In order to solve the above-mentioned problems, the inventors have studied the following technology: by newly setting up a unit that notifies the memory card of information indicating the transition to the optimal performance operation mode from the host device, the memory card can operate at the minimum performance required for recording at the execution speed, thereby suppressing the power consumption of the memory card.

[0193] First, refer to Fig.19 The speed guarantee record achieved by the current SD memory card is explained.

[0194] Fig.19 An example of a command sequence for speed-guaranteed recording on an SD memory card is shown. Fig.19 The horizontal axis of the diagram represents time, and the recording device 100 issues instructions to the memory card 200 in sequence from the left side to the right side of the diagram. Fig.19 In the example shown, a command is written as "CMD" and is sent from the host device to the SD memory card. "CMD20" is a control command issued when speed-guaranteed recording is performed in the SD memory card. Fig.17 The data structure 600 of "CMD20" is shown. The speed guarantee record is implemented by parameters designated by "Speed ​​Class Control (SCC)", "CNT / ID" and "ADDR" in "CMD20".

[0195] For example, through the first "CMD20" 700-1, the host device notifies the SD memory card of the location of the directory entry of the data stream to be written thereafter ( Fig.17 The directory entry records the file name, attributes, etc. of the data stream to be written thereafter. After that, "CMD24" 800-1 is issued to write (record) the data to the directory entry.

[0196] Furthermore, "CMD24" in the SD memory card standard is a command for writing data of a single block (1 block = 512 bytes).

[0197] Next, the host device specifies the location of the allocation unit (AU) for speed-guaranteed recording to the SD memory card through "CMD20" 700-2. Fig.17 "SCC" = 0111b).

[0198] The SD memory card standard stipulates that when recording at a guaranteed speed, the data stream is written in each free allocation unit (free AU). Fig.17 ) specifies the number of free allocation units (free AUs) that can be continuously secured. The maximum number that can be specified is 8, and the "CNT / ID" field is 3 bits long.

[0199] After that, the host device instructs the SD memory card to start speed guaranteed recording via "CMD20" 700-3 ( Fig.17 of the RAID controller card (“SCC”=0000b).

[0200] Later, proceed in Fig.19 In the speed grade recording section, "CMD25" 800-2 and 800-4, which are data writing commands, are sent from the host device to the SD memory card to transfer speed guarantee data such as captured moving image data to be written.

[0201] Furthermore, "CMD25" in the SD memory card standard is a command for writing data of a plurality of blocks (n blocks = 512 x n bytes).

[0202] In addition, while the speed of writing the captured dynamic image data to be written is ensured to be continuously written to the SD memory card, the "CMD25" 800-3 and 800-5 are issued in the middle to Figure 2 as well as Figure 3 The file system 108 of the host device shown writes the FAT (File Allocation Table) which has been appropriately updated based on the data written to the file into the SD memory card.

[0203] The “speed grade recording period” ends by issuing another write command ( 800 - 6 ).

[0204] The inventors believe that, in the above series of speed guarantee recording sequences, at least before the speed guarantee recording is indicated, that is, before the signal is issued, Fig.19 Before "CMD25" 800-2 (Write RU) of the SD memory card, information indicating the transition to the best performance operation mode is notified to the SD memory card, so that the SD memory card operates at the minimum performance required to ensure the execution speed of recording, and the power consumption of the memory card can be suppressed to a low level.

[0205] Regarding the means by which the host device notifies the SD memory card of information indicating the transition to the best performance operation mode, various specific means are considered, such as a method of utilizing an unused (reserved) independent variable of an existing command (CMD) specified in the SD memory card standard, or a method of newly defining a command not specified in the SD memory card standard.

[0206] In the embodiment of the present invention, a method of utilizing an unused code (value) of an argument of the existing “CMD20” defined in the SD memory card standard is disclosed as an example.

[0207] Fig.18The following example is shown: to the unused code (value) of the original "CMD20" independent variable "Speed ​​Class Control (SCC)" specified in the SD memory card standard, that is, "SCC" = 1011b, the host device is assigned the information "OMPREQ" (Optimal Minimum Performance Request) to instruct the SD memory card to transition to the optimal performance operation mode.

[0208] Next, refer to Fig.21 An example in which speed guarantee recording is performed after the host device notifies the SD memory card of information indicating a transition to the best performance operation mode will be described.

[0209] Fig.21 An example of a command sequence is shown in which speed guarantee recording is performed after the host device notifies (prompts) the SD memory card of information instructing a transition to the best performance operation mode.

[0210] exist Fig.21 In the example shown, a command is described as "CMD" and is sent from the host device to the SD memory card.

[0211] "CMD20" is a control command issued when speed-guaranteed recording is performed in the SD memory card.

[0212] Fig.18 The data structure 600 of "CMD20" is shown. The speed guarantee record is implemented by parameters designated by "Speed ​​Class Control (SCC)", "CNT / ID" and "ADDR" in "CMD20".

[0213] Refer again Fig.21 For example, the first "CMD20" 700-1 notifies the SD memory card of the location of the directory entry of the data stream to be written thereafter from the host device ( Fig.18 The directory entry records the file name, attributes, etc. of the data stream to be written thereafter. Then, "CMD24" 800-1 is issued to write to the directory entry.

[0214] Furthermore, "CMD24" in the SD memory card standard is a command for writing data of a single block (1 block = 512 bytes).

[0215] Next, the host device specifies the location of the allocation unit (AU) for speed-guaranteed recording to the SD memory card through "CMD20" 700-2. Fig.18 "SCC" = 0111b).

[0216] The SD memory card standard stipulates that when recording at a guaranteed speed, the data stream is written in each free allocation unit (free AU). Fig.18 ) specifies the number of free allocation units (free AUs) that can be continuously secured. The maximum number that can be specified is 8, and the "CNT / ID" field is 3 bits long.

[0217] After that, the host device instructs the SD memory card to start speed guaranteed recording via "CMD20" 700-3 ( Fig.18 of the RAID controller card (“SCC”=0000b).

[0218] Next, the SD memory card is notified of a transition instruction to the best performance operation mode through "CMD20" 700-6.

[0219] When "CMD20" 700-6 is received and the SD memory card recognizes the instruction to transfer to the best performance operation mode, the SD memory card operates at the execution speed to ensure the minimum performance required for recording, and transfers to the operation mode represented as "best performance operation range" that suppresses the power consumption of the memory card to a lower level.

[0220] Here, in a nonvolatile storage device including an SD memory card equipped with a NAND flash memory, generally speaking, Figure 2 as well as Figure 3 Compared with the power consumption of the PCIe interface 214a, PCIe interface 214b, PCIe interface 314a or PCIe interface 314b of the host device, Figure 2 as well as Figure 3 The total power consumption of the CPU 212, the buffer memory 216, and the NAND control unit 218 in the controller 210 shown, and the power consumption of the NAND flash memory 220 are much larger.

[0221] For example, in Figure 3 In a circuit implementation example of the UHS-II interface 314a, there is a semiconductor power simulation result report with a power consumption of 60mW. Fig.14 As shown, the maximum power consumption of the SD memory card with the UHS-II interface is 1.80 W, which is about 30 times the power consumption of the UHS-II interface 314a.

[0222] These circuit blocks within the controller 210 and the NAND flash memory are usually based on Figure 2 as well as Figure 3 The oscillator 219 shown operates based on a clock that is multiplied and / or divided.

[0223] The controller 210 generally has the following mechanism: when no instructions are issued from the host device for a certain period of time, in order to suppress power consumption as low as possible, the clock frequency is reduced by dividing the clock supplied to the circuit blocks inside the controller 210, thereby switching to the power saving mode.

[0224] Therefore, the following power saving control is considered: before receiving "CMD20" 700-6 (OMPREQ), the clock supplied to the circuit block inside the controller 210 is set to the maximum clock frequency to enable it to operate, and in the "optimal performance operation interval" after receiving "CMD20" 700-6, it is set to the minimum clock frequency required for execution speed guarantee recording to enable it to operate.

[0225] Later, proceed in Fig.21 In the speed grade recording section, "CMD25" 800-2 and 800-4, which are data writing commands, are sent from the host device to the SD memory card to transfer speed guarantee data such as captured moving image data to be written.

[0226] Furthermore, "CMD25" in the SD memory card standard is a command for writing data of a plurality of blocks (a plurality of blocks: n blocks=512×n bytes).

[0227] In addition, when the speed of writing the captured dynamic image data to be written is ensured to be written continuously to the SD memory card, the "CMD25" 800-3 and 800-5 are issued in the middle of the process. Figure 2 as well as Figure 3 The file system 108 of the host device shown writes the FAT (File Allocation Table) which has been appropriately updated based on the data written to the file into the SD memory card.

[0228] The “speed grade recording period” ends when another write command ( 800 - 6 ) is issued.

[0229] As described above, the host device predetermines the specifications for the memory card so as to notify the SD memory card of the information indicating the host device's transition to the best performance operation mode, thereby allowing the SD memory card to operate at an execution speed that ensures the minimum performance required for recording, thereby suppressing the power consumption of the memory card. As a result, the heat generation of the host device and the SD memory card can be suppressed.

[0230] In addition, in the embodiment of the present invention, as an example of a means for notifying the memory card of information indicating that the host device has shifted to the best performance operation mode, a method using "CMD20" of the SD memory card standard is shown, but for a memory card that complies with the NVMe standard, such as Fig.23 as well as Fig.24 As shown, the inventors have also studied and designed a mechanism for implementing the function of "CMD20" in the SD memory card standard by following the instructions of the NVMe standard, thereby being able to notify the memory card of information indicating that the host device is transitioning to the optimal performance operation mode.

[0231] Specifically, Fig.18 The SCC, CNT / ID, and ADDR in the "CMD20" of the SD memory card standard shown in the figure are directly assigned to the Fig.23 The NVMe standard NVM command set (NVM Command Set) shown in the Write command (data write command) includes bits "31" to "28" of Dword "13" (a 4-bit area), bits "26" to "24" of Dword "13" (a 3-bit area), bits "5" to "0" of Dword "10", and bits "31" to "10" of Dword "11" (a total of 28-bit area).

[0232] In addition, the NVMe standard specifies two types of command sets: the Admin Command Set and the NVM Command Set. The Admin Command Set is a control command group that mainly reads information related to the functions / performance / specifications of the non-volatile storage device from the recording device, or performs various settings of the non-volatile storage device, while the NVM Command Set is a command group associated with data, such as writing data to the non-volatile memory (Non-volatile memory) of the non-volatile storage device or reading data from the non-volatile memory.

[0233] In this way, by directly assigning the function of "CMD20" in the SD memory card standard to the command that complies with the NVMe standard, it is possible to Fig.19 and Fig.21 The speed shown in the SD memory card guarantees the command sequence when recording, such as Fig. 20 and Fig. 22 As shown, speed-guaranteed recording control is performed based on sequential NVMe standard instructions.

[0234] In addition, since SCC, CNT / ID, and ADDR in the SD memory card standard "CMD20" are directly assigned to Fig.23 The NVMe standard Write command (data write instruction) shown in the figure, Fig. 20 as well as Fig. 22All NVMe CMDs (NVMe instructions) are NVMe standard Write commands (data write instructions).

[0235] In addition, as another mechanism to implement the function of "CMD20" in the SD memory card standard by following the instructions of the NVMe standard, a method has been studied and designed to set the eight functions of SCC in "CMD20", namely, Fig.18 The method of assigning Start REC, Update DIR, Update CI, Suspend AU, Resume AU, Set FreeAU, Release DIR, and OMPREQ to NVMe instructions is shown in the figure. (In addition, Fig.25 , Fig.26 The method and Fig.23 , Fig.24 The function of "CMD20" in the SD memory card standard shown is directly assigned to any of the methods of instructions that comply with the NVMe standard).

[0236] Specifically, the following mechanism: Fig.25 The NVMe standard NVM command set (NVM Command Set) of the Dataset Management command (hereinafter referred to as "DSM command") is shown in Figure 1, and the setting values ​​of Number of Ranges (bits "7" to "0") in Dword "10", AD (Attribute-Deallocate) (bit "2"), IDW (Attribute-Integral Dataset for Write) (bit "1"), and IDR (Attribute-Integral Dataset for Read) (bit "0") in Dword "11", and the attribute information of the Range set in the list of Ranges stored in the Data Pointer (storage address of the main storage of the recording device 10, etc.) in Dword "6" to Dword "9" are used to uniquely identify the Range.

[0237] Fig.26 This is a table showing the correspondence between the Dword "10" and Dword "11" of the DSM instruction of the NVMe standard, the values ​​set in the Range list, and the attribute information of the Range set in the Range list and the eight functions of the SCC in "CMD20".

[0238] Here, the so-called Range attribute information refers to Fig.26The table at the bottom left is labeled "Range: Context Attributes" to show the 32-bit information.

[0239] according to Fig.26 The combination of Dword “10” and Dword “11” of the DSM instruction recorded in the table and the value set in the attribute information of Range (Range: Context Attributes) uniquely defines the eight functions of the SCC in “CMD20”.

[0240] In addition, Update DIR is a function for notifying the host to the card of the location of directory entries, and Update CI is a function for notifying the host to write CI (Continuous Information) to the card. However, both are functions for notifying the card to write smaller data than continuous stream recording data such as directory entries and FAT (File Allocation Table) represented by dynamic image shooting, so Fig.26 In the function correspondence table shown, Update DIR and Update CI are combined into one function, Update DIR / CI.

[0241] In addition, the instruction to transfer to the optimal performance operation mode is performed by setting the bit "03" of the Dword "11" of the DSM instruction to "1". That is, the bit "03" of the Dword "11" of the DSM instruction is assigned to the information "OMPREQ" (Optimal Minimum Performance Request) indicating the transfer to the optimal performance operation mode. (In addition, the bits "31" to "03" of the Dword "11" of the DSM instruction become unused (Reserved) bits in the NVM Express Base Specification Revision1.4).

[0242] Thus, in the embodiment of the present disclosure, as an example of a means of notifying the memory card of information indicating the host device to shift to the best performance operation mode, a method using "CMD20" of the SD memory card standard is shown, but for a memory card that complies with the NVMe standard, such as Fig.25 as well as Fig.26 As shown, the inventors have also studied and designed a mechanism for implementing the function of "CMD20" in the SD memory card standard by following the instructions of the NVMe standard, thereby being able to notify the memory card of information indicating that the host device is transitioning to the optimal performance operation mode.

[0243] Thus, it is possible not to change Fig.19 and Fig.21 The speed shown in the SD memory card guarantees the command sequence when recording, such as Fig. 20 and Fig. 22 Speed-guaranteed recording control is performed based on instructions that comply with the NVMe standard as shown.

[0244] In addition, since SCC, CNT / ID, and ADDR in the SD memory card standard "CMD20" are assigned to Fig.25 , Fig.26 The NVMe standard DSM instructions shown are therefore Fig. 20 as well as Fig. 22 In the NVMe CMD (NVMe command), 700-1, 700-2, 700-3, and 700-6 are DSM commands, and 800-1, 800-2, 800-3, 800-4, and 800-5 are NVMe standard Write commands (data write commands).

[0245] In addition, it is also possible that a memory card that complies with the SD memory card standard and / or a memory card that complies with the NVMe standard utilizes control instructions other than "CMD20" in the SD memory card standard and instructions for writing to a control register or NAND flash memory in the memory card to notify the memory card of information indicating that the host device is transitioning to the optimal performance operation mode.

[0246] For example, consider using control instructions for setting power consumption limits according to the SD memory card standard and control instructions for performing power consumption management according to the NVMe standard.

[0247] Here, as an example, a method using "CMD6" of the SD memory card standard is briefly described.

[0248] “CMD6” is a control command issued when limiting the power consumption of the SD memory card or switching the interface mode (Switch) by the Switch Function Command in the conventional SD memory card. Fig. 27 The data structure of the command argument (argument: Arg. Slice) in "CMD6" is shown. For example, by Fig. 27 The bits "3" to "0" of the command argument (argument) of CMD6 shown in the figure indicate Fig.14The bus speed modes of UHS-I shown are switching of SDR25, DDR50, SDR50, and SDR104. That is, when 1h is set in bit "3" to bit "0", it becomes a switching instruction to SDR25. Similarly, when 2h is set in bit "3" to bit "0", it becomes a switching instruction to SDR50. When 3h is set in bit "3" to bit "0", it becomes a switching instruction to SDR104. When 4h is set in bit "3" to bit "0", it becomes a switching instruction to DDR50.

[0249] in addition, Fig. 27 The bits "15" to "12" of the command argument (argument) of CMD6 shown are bits for switching the power consumption limit. When 0h is set in bits "15" to "12", it indicates the operation in the mode of suppressing the maximum power consumption of the SD memory card to less than 0.72W. Similarly, when 1h is set in bits "15" to "12", it becomes an operation instruction in the mode of suppressing to less than 1.44W. When 2h is set in bits "15" to "12", it becomes an operation instruction in the mode of suppressing to less than 2.16W. When 3h is set in bits "15" to "12", it becomes an operation instruction in the mode of suppressing to less than 2.88W. When 4h is set in bits "15" to "12", it becomes an operation instruction in the mode of suppressing to less than 1.80W.

[0250] Therefore, as a means for the host device to instruct the transition to the best performance operation mode, it is considered to use "CMD6" of the SD memory card standard to set the power commensurate with the guaranteed speed. Fig.21 The 700-6 "OMPREQ" is replaced from "CMD20" to "CMD6" to execute.

[0251] Next, as another example of a method of notifying a memory card of information indicating that the host device has instructed the memory card to transition to the best performance operation mode, a method of using control instructions for performing power consumption management in accordance with the NVMe standard will be briefly described.

[0252] Fig.28 This is a diagram showing the data structure of a Set Features command belonging to the Admin Command Set of the NVMe standard.

[0253] Bits “7” to “0” of Dword “10” in the feature setting command are feature identifiers (FeatureIdentifier), which are fields that specify the ID (Identifier) ​​of the function set by the feature setting command.

[0254] in addition, Fig.29 A list of various functions set by setting feature commands and their IDs (FeatureIdentifiers) is shown.

[0255] Bits "31" to "0" of Dword "11" in the feature instruction are set as parameters. The parameters are specified for each function specified by the feature identifier (bits "7" to "0" of Dword "10").

[0256] For example, Fig.29 The characteristic identifier "02h" shown is Power Management (power consumption management function), and the parameters of the above Power Management (power consumption management function) are shown in Fig.30 .

[0257] Fig.30 Bits "7" to "5" of the Dword "11" shown are WH (Workload Hint), which is a parameter used to notify the non-volatile storage device of reference information related to the processing volume, such as how much writing to the non-volatile memory has been generated, and bits "4" to "0" of Dword "11" are Power State (power consumption state), which is used to specify one of the multiple power consumption states supported by the non-volatile storage device and enable it to operate.

[0258] Therefore, as a means for the host device to instruct the transition to the best performance operation mode, it is considered to use the Power Management (power consumption management function) of the NVMe standard to set the power consumption state commensurate with the guaranteed speed. Fig. 22 The 700-6 "OMPREQ".

[0259] Here, use Fig.31 A plurality of power consumption states supported by the nonvolatile storage device will be described.

[0260] Fig.31 (a) shows the power consumption status of the SD Express card type that the card must have according to the SD standard.

[0261] There are four types of SD Express cards: a card with a PCIe interface of Gen3 (Generation 3) × 1 channel (marked as "PCIe G3x1" in the figure), a card with a PCIe interface of Gen3 (Generation 3) × 2 channels (marked as "PCIe G3x2" in the figure), a card with a PCIe interface of Gen4 (Generation 4) × 1 channel (marked as "PCIe G4x1" in the figure), and a card with a PCIe interface of Gen4 (Generation 4) × 2 channels (marked as "PCIe G4x2" in the figure).

[0262] PCIe G3x1 card and PCIe G4x1 card corresponding to 1 lane of PCIe interface have Figure 6 The terminals shown above correspond to the two lanes of the PCIe interface on the PCIe G3x2 card and PCIe G4x2 card. Figure 7 Terminals shown.

[0263] Here, since the data transmission path of the PCIe standard Gen4 achieves twice the speed of the data transmission path of Gen3, the PCIe G3x2 (a card with 2 channels of Gen3) and PCIe G4x1 (a card with 1 channel of Gen4) among the SD Express card types have the same interface speed as cards (non-volatile storage devices).

[0264] Therefore, if Fig.31 As shown in (a), the SD standard stipulates that the card type PCIe G3x2 and the card type PCIe G4x1 have the same five required power consumption states.

[0265] As mentioned above, Fig.31 (a) shows the power consumption status of the SD Express card type that the card must have according to the SD standard, but in Fig.31 (b) shows an example of the power consumption state of an actual SD Express card.

[0266] Regarding the specifications related to the power consumption states, in the NVMe standard that the SD standard refers to and complies with, a card (non-volatile storage device) can have a maximum of 32 power consumption states.

[0267] Therefore, in the SD standard, in addition to Fig.31 In addition to the SD standard required power consumption states for each card type shown in (a), the optional power consumption states and the required power consumption states can be combined to provide a maximum of 32 states.

[0268] In addition, in the NVMe standard, such as Fig.32As shown, in the identification command issued by the host device to the card, the specification indicating the power consumption status of the card is defined in bytes 2048 to 3071 of the 4,096-byte identification controller data structure read from the card.

[0269] In addition, according to the NVMe standard, a card can have a maximum of 32 power consumption states (Power State 0 to 31), but it is sufficient to have at least one power consumption state.

[0270] That is, the power consumption state must be 1, and if Fig.32 As shown, power consumption state 0 (Power State 0) is M (Mandatory) = mandatory, and power consumption states 1 to 31 (Power State 1 to 31) are O (Optional).

[0271] Here, we return to the description of the SD standard. Fig.31 (b) shows an example in which a PCIe G3x1 card has a selectable power consumption state of 1.6 W in addition to the required power states of 1.8 W, 1.44 W, and 0.72 W specified in the SD standard.

[0272] In addition, the figure (table) shows that the power consumption states shown with shading are not set as mandatory in the SD standard, that is, the card (non-volatile storage device) has this power consumption state as a single installation (single design), indicating that it is positioned as an optional power consumption state in the SD standard, and the power consumption states without shading are set as mandatory power consumption states for each card type in the SD standard.

[0273] The same is true below. Fig.31 (b) shows that in the example of a PCIe G3x2 card, in addition to 2.8 W, 2.5 W, 1.8 W, 1.44 W, and 0.72 W, which are required power consumption states specified in the SD standard, there are also selectable power consumption states of 2.0 W and 1.6 W. In the example of a PCIe G4x1 card, there are selectable power consumption states of 2.3 W, 2.1 W, and 1.6 W. In the example of a PCIe G4x2 card, there are selectable power consumption states of 2.2 W and 1.6 W.

[0274] As described above, the number of power consumption states and power values ​​that a card (nonvolatile storage device) has vary for each individual manufacturer and each individual product.

[0275] Therefore, the host device needs to know in advance the number of power consumption states that the card mounted in the host device has and the power value of each power consumption state in a stage called initialization immediately after the card is powered on.

[0276] The host device can read the number of power consumption states that the card has and the power consumption values ​​of each state from the card using an identification command (Identify command) that belongs to the Admin Command Set of the NVMe standard.

[0277] like Fig.32 As shown in the figure on the left, regarding the number of power consumption states that the card has, 263 bytes of the 4,096-byte identification controller data structure (Identify Controller Data Structure) read from the card by the host device through the identification command are shown as the number of supported power consumption states (Number of Power States Support, NPSS) in the range of 1 to 32.

[0278] In addition, Fig.32 In the byte allocation table on the right side, the Number of Power States Support (NPSS) of the 263rd Byte is omitted, but the detailed specifications can be confirmed by referring to the NVMe standard.

[0279] In addition, the power consumption values ​​of each power consumption state of the card are as follows: Fig.32 As shown, 2,048 to 3,071 bytes are shown in the 4,096-byte identification controller data structure read from the card by the identification command.

[0280] Specifically, for a power consumption state (Power State), 32Bytes (byte, 256Bits) of information is shown. In the 32Bytes, the power value is stored as Maximum Power (MP) in the lower 2 bits (Bits15~0), and in Bit24, the scale of the above-mentioned minimum power consumption (Maximum Power, MP) is shown as the maximum power consumption scale (Max Power Scale, MXPS). Therefore, the power in watts can be calculated by multiplying the MP value by the scale shown by MXPS.

[0281] Furthermore, when MXPS is 0, the scale of MP is 0.01 Watt, and when MXPS is 1, the scale of MP is 0.0001 Watt unit.

[0282] The detailed specifications regarding the above-mentioned identification instructions, the identification controller data structure read by the identification instructions, and the number of power consumption states (NPSS) and the power consumption value (MXPS×MP) contained therein are recorded in the NVMe standard book, so the detailed description in this manual is omitted.

[0283] As described above, the host device reads the number of power consumption states that the card has and information on the power consumption value from the card, and then specifies (sets) a desired power consumption state for the card.

[0284] Specifically, in Fig.30 The Power State value is set in bits "4" to "0" of Dword "11" in the set feature command shown, and a command is issued to the card.

[0285] For example, in Fig.31 (b) When the PCIe G4x1 card is set to the power consumption state 1.8W (Power State 4), Fig.30 In the illustrated setting feature command, the PowerState value "4" is set in bits "4" to "0" of Dword "11", and a command is issued to the card.

[0286] In addition, if Fig.31 (a) and Fig.31 As shown in (b), the power consumption states are assigned consecutive numbers starting from 0 (Power State values) so that each subsequent power consumption state is equal to or less than the power of the previous state. Therefore, Power State 0 (PS 0) indicates the maximum power consumption that the SD Express card can consume.

[0287] Here, the problem of when the host device instructs transition to the best performance operation mode is described.

[0288] As described above, a card can have a plurality of power consumption states, and the number of power consumption states that a card has and the power consumption value of each power consumption state vary among manufacturers and cards.

[0289] The host device can know the number of power consumption states that the card has and the power consumption value of each power consumption state by issuing the identification command.

[0290] On the other hand, since the host device is unaware of the method of power consumption required by the card when recording data such as dynamic images on the card (non-volatile storage device) at the desired guaranteed speed, when the host device issues a setting feature instruction and specifies the power consumption state for the card, there is insufficient power to record on the card (non-volatile storage device) at the desired guaranteed speed, and the speed guaranteed recording cannot be performed correctly. Or, conversely, the card consumes more power than is required to record on the card at the desired guaranteed speed. As a result, the temperature of the card rises, and there is a problem that the speed guaranteed recording cannot be continued.

[0291] Therefore, the present inventors have studied a new mechanism for notifying the host device from the card of a power consumption state for operating to reduce the power (performance) required and sufficient for recording data such as moving images on the card at a desired guaranteed speed.

[0292] As described above, in the NVMe standard, the number of power consumption states that a card has is shown in the range of 1 to 32 as Number of Power States Support (NPSS) in 263 bytes of the 4,096-byte Identify Controller Data Structure read from the card by the Identify command. In addition, the power consumption value of each power consumption state that the card has is shown as follows: Fig.32 As shown, 2,048 to 3,071 bytes of the identification controller data structure of 4,096 bytes are read from the card through the identification command.

[0293] In addition, the mechanism shown by the host device was studied by newly allocating information for notifying the host device from the card (non-volatile storage device) of the power consumption status for causing it to operate with the efficiency (performance) required and sufficient to record data such as dynamic images in the card at the desired guaranteed speed to the Vendor Specific area ensured in the 3072-byte to 4095-byte area of ​​the Identify Controller Data Structure.

[0294] Fig.32 Shows the Vendor Specific area of ​​the Identify Controller Data Structure.

[0295] like Fig.32 As shown, the Vendor Specific area is allocated to 3072 to 4096 bytes.

[0296] Fig.33 : is a diagram showing an example of information newly allocated to the above area. In the present embodiment, first, the value of the speed guarantee level (SDExpress speed level) supported by the card is shown in bytes 3072 to 3073 of the above Vendor Specific area.

[0297] For example, in Fig.16 The Gen3x1 card shown corresponds to speed guarantee level 150 (150MB / s), level 300 (300MB / s), and level 450 (450MB / s), but not to level 600 (600MB / s). In this case, 01C2h (=450 (decimal number)) is displayed at bytes 3072 to 3073 of the above-mentioned VendorSpecific area.

[0298] In addition, the value shown here is set to the speed value itself of the fastest speed guarantee level supported by the card.

[0299] Furthermore, in the SD standard, in order to ensure backward compatibility, cards must also cope with speed guarantee levels lower than the speed guarantee levels shown here.

[0300] That is, when the card notifies 01C2h (=450 (decimal number)), it means that the card also supports class 450 (450 MB / s), class 300 (300 MB / s) which is lower than class 450, and class 150 (150 MB / s).

[0301] Next, in bytes 3088 to 3103 of the Vendor Specific area, a combination of a speed guarantee level and a bus mode, and a sufficient and minimum power consumption state required by the card in the combination are defined as an area indicated by the host device.

[0302] In Bit [7] (MSB: most significant bit) in each byte from 3088 to 3103, it is shown which bus mode and speed guarantee level the card (non-volatile storage device) corresponds to. "0" means invalid, indicating non-correspondence, and "1" means valid, indicating correspondence.

[0303] The following description takes the Gen4x1 card as an example.

[0304] Gen4x1 cards have Gen4x1 and Gen3x1 as bus modes.

[0305] In the SD standard, in order to ensure backward compatibility, a card having a bus mode with a faster speed needs to correspond to a bus mode with a speed lower than the faster speed.

[0306] However, if Figure 6 As shown, the Gen4x1 card only has one row of PCIe terminal groups, so it does not support Gen3x2.

[0307] On the other hand, Figure 7 As shown, the Gen4x2 card has two rows of terminal groups for PCIe, and therefore supports all four bus modes of Gen4x2, Gen4x1, Gen3x2, and Gen3x1 as bus modes.

[0308] Therefore, for the Gen4x1 card, the following is displayed: Figure 7 In the Power State of the bus mode of the PCIe terminal group shown, Bit [7] (MSB: most significant bit) in each byte 3092 to 3095 (the area for the combination of Gen3x2 and each SC (speed guarantee level)) and 3100 to 3103 (the area for the combination of Gen4x2 and each SC (speed guarantee level)) displays "0", that is, "invalid (non-corresponding)".

[0309] Below, use Fig.34 and Fig.35 The example for the Gen4x1 card is explained in further detail.

[0310] Fig.34 (b) is Fig.31 Reproduction of (b).

[0311] In Gen4x1 cards such as Fig.34 In the example shown in (b) of FIG. 1 , there are five required power consumption states (2.8 W, 2.5 W, 1.8 W, 1.44 W, and 0.71 W) and three optional power consumption states (2.3 W, 2.1 W, and 1.6 W) specified in the SD standard. When the card corresponds to all four speed guarantee classes (SD Express speed classes), namely, "Class 150" of 150 MB / s, "Class 300" of 300 MB / s, "Class 450" of 450 MB / s, and "Class 600" of 600 MB / s, an example of sufficient and minimum power consumption required to perform moving image recording at each SC (speed guarantee class) using the bus modes of Gen3x1 and Gen4x1 is shown. Fig.34 (a).

[0312] like Fig.34 As shown in (a) of FIG. 1 , for each card type and bus mode, a sufficient and minimum power consumption state required for performing speed guarantee recording of each speed guarantee level (speed level) is defined as a “speed class power consumption state (Speed ​​Class Power State)”.

[0313] For example, in bus mode Gen4x1, the speed level power consumption state when executing the speed guarantee record of level 600 is PS2. Fig.34 As can be seen from (b), 2.3 W is the sufficient and minimum power required.

[0314] Similarly, the speed level power consumption state when executing the speed guarantee recording of level 450 is PS3. Fig.34 From (b), it can be seen that 2.1 W is the sufficient and minimum power required.

[0315] Hereinafter, the speed level power consumption state when executing the speed guaranteed recording of level 300 becomes 1.8W for PS4, and the speed level power consumption state when executing the speed guaranteed recording of level 150 becomes 1.6W for PS5.

[0316] In addition, the present embodiment also shows the following situation: when performing "Class 600" speed guaranteed recording at 600MB / s with the same Gen4x1 card, 2.3W of PS2 is required in the Gen4x1 bus mode with a faster interface speed (bus speed). In contrast, in the Gen3x1 bus mode, even when performing "Class 600" recording with the same 2.1W of PS3, the operation can be performed more power-saving.

[0317] Next, an example of notifying the host device of the speed grade power consumption state of the above-mentioned Gen4x1 card through the Vendor Specific area 3088 bytes to 3103 bytes of the Identify Controller Data Structure (ICDS) is shown. Fig.35 (b).

[0318] In addition, for ease of understanding Fig.35 The corresponding (b) is Fig.35 (a) reproduces Fig.34 (a).

[0319] As described above, since the Gen4x1 card cannot handle the bus modes of Gen4x2 and Gen3x2, the value "0" indicating "invalid" is stored in Bit [7] of bytes 3092 to 3095 and bytes 3100 to 3103 for notification.

[0320] On the other hand, the above-mentioned Gen4x1 card is an example that supports all four speed levels in the two bus modes of Gen4x1 and Gen3x1, so Bit [7] of bytes 3088 to 3091 and bytes 3096 to 3099 stores a value "1" indicating "valid" for notification.

[0321] In addition, in Bits "4:0" from 3088 bytes to 3091 bytes and from 3096 bytes to 3099 bytes, the Fig.34 (a) and Fig.35 The speed level shown in (a) is notified by the status value of the power consumption status itself.

[0322] As described above, in the present disclosure, a mechanism for notifying a host device of a sufficient and minimum power consumption state required for a card to perform speed-guaranteed recording is newly designed and specified.

[0323] Next, use Fig.36 The following describes a procedure (sequence) in which the host device obtains the speed grade power consumption status of the card from the card and sets the power consumption status corresponding to the desired guaranteed speed before starting speed guaranteed recording.

[0324] Fig.36 An example of a command sequence for speed-guaranteed recording in an SD Express card is shown. Fig.36 The horizontal axis of represents time, and the recording device 100 issues instructions to the memory card 200 in sequence from the left side to the right side of the figure.

[0325] exist Fig.36 In the example shown, the quadrilateral symbols (sequential graphic elements) shown by 700 - 1 to 700 - 6 , 800 - 1 to 800 - 6 , and 900 - 1 to 900 - 2 represent the functions of commands sent from the host device to the SD Express card.

[0326] In addition, the actual instruction name is marked in the oval symbol (sequence graphic element) recorded below the quadrilateral symbol. Fig.36 In the example, all instructions are MVMe standard instructions.

[0327] In addition, regarding the basic sequence for speed guarantee recording, use Fig. 22 The description has been given, so the description is omitted here.

[0328] In addition, regarding the method of implementing the functions of each instruction through the NVMe DSM (Dataset Management) instruction, follow the use of Fig.26 And the specifications described.

[0329] Fig.36 exist Fig. 22 The following processing is added to the basic sequence for performing speed-guaranteed recording as shown.

[0330] In 900 - 1 (Power On), the host device turns on power (supplies power) to the SD Express card mounted in the host device.

[0331] In 900 - 2 , the host device executes initialization processing of the SD Express card.

[0332] Here, the so-called initialization processing refers to the host device reading the card's corresponding functions, performance, manufacturer ID and other card-specific information from the card, and then the host device performs processing such as settings related to the functions and performance used by the host device on the card.

[0333] 700 - 4 is the issuance of an identification command executed as part of the aforementioned initialization process. By issuing this command, the host device reads an identification controller data structure (ICDS: Identify Controller Data Structure) consisting of 4,096 bytes from the card.

[0334] Through the ICDS, the number of power consumption states that the card has as specified in the NVMe standard and the power consumption value of each of the power consumption states are notified from the card to the host device.

[0335] In addition, SC (Speed ​​Class = Speed ​​Guaranteed Class) and SCPS (Speed ​​Class Power Consumption Status) established by the present inventor are notified from the card to the host device.

[0336] In 700-5, the host device issues the identification command of 700-4, and sets the maximum power consumption state of the Gen4x1 card by setting the characteristic command based on the number of power consumption states in the ICDS acquired from the Gen4x1 card and the power consumption value of each of the power consumption states.

[0337] By setting the maximum power consumption state, when simultaneously shooting very high-pixel still image RAW data (unprocessed data) and still image JPEG data (compressed data) at high speeds such as 20 frames per second using a digital single-lens reflex camera, etc., it is possible to record using the highest speed performance of the memory card.

[0338] Here, RAW data refers to unprocessed image data output from an image sensor, and is raw data of the image sensor that cannot be observed as a photographed photo unless color restoration processing or the like is performed.

[0339] In order to visually observe and confirm the photos taken by the user of the digital camera, the following operations are generally performed: color restoration processing is performed based on the RAW data, and JPEG data that has been compressed by thinning out the information on light intensity is also recorded simultaneously with the RAW data.

[0340] Therefore, for example, in high-speed continuous shooting at 20 frames / second, RAW data of 20 images and JPEG data of the corresponding 20 images need to be recorded per second, requiring very high-speed recording to the memory card.

[0341] On the other hand, with regard to movie shooting, codecs such as MPEG that use algorithms that are more suitable for movie data and have higher compression rates are widely used. For example, by recording difference information between a benchmark movie frame (1 movie frame) and subsequent movie frames, the recording rate to the memory card is suppressed to a lower level compared to high-speed continuous shooting of still images.

[0342] In addition, the default power consumption state (initial power state after power is turned on) of the SD Express card is specified as 1.8W in the SD standard.

[0343] Therefore, through the set feature instruction of 700-5, the PS (power consumption state) of the Gen4x1 card is switched from PS4 (1.8W) to PS0 (2.8W).

[0344] 700-1, 800-1, 700-2, 700-3 are Fig.19 , Fig. 20 , Fig.21 , Fig. 22 Symbols with the same numbers (graphic elements of a sequence) are shown with the same processing, and therefore description thereof is omitted.

[0345] 700-6 is Fig. 22 The illustrated example shows issuance of a command to notify information “OMPREQ” (Optimal Minimum Performance Request) instructing transition to the optimal performance operating mode.

[0346] In the present disclosure, the host device issues a feature setting command to the Gen4x1 card, and then, in order to perform a class 150 speed guarantee recording, notifies the card to operate in the power consumption state of the PS5 (1.8 W).

[0347] As a result, the Gen4x1 card shifts to a state of sufficient and minimum power consumption required for recording at a guaranteed speed of 150 MB / s, that is, an optimal performance operation mode.

[0348] As described above, the host device can use the number of power consumption states that the card has and the power consumption value of each of the power consumption states to newly design and define the power consumption state according to the present disclosure. Fig.33 The information on the speed level and the speed level power consumption state shown in the above is used to set the sufficient and optimal (lowest) power consumption state required by the card in order to perform recording at the speed (desired speed level) expected by the host device.

[0349] Finally, a specific example of a nonvolatile storage device operating in a power consumption state commensurate with the guaranteed speed is briefly described. In a nonvolatile storage device including an SD memory card equipped with a NAND flash memory (nonvolatile memory), generally speaking, Figure 2 as well as Figure 3 Compared with the power consumption of the PCIe interface 214a, SD interface 214b, UHS-II interface 314a or SD interface 314b of the host device (recording device 100), Figure 2 as well as Figure 3 The total power consumption of the CPU 212, the buffer memory 216, and the NAND control unit 218 in the controller 210 shown, and the power consumption of the NAND flash memory 220 are much larger.

[0350] For example, in Figure 2 In the circuit implementation example of the PCIe interface 214a, there is a semiconductor power simulation result report with a power consumption of 61mW. Fig.14 As shown, the maximum power consumption of the SD Express card having the PCIe interface is 4.00 W, which is approximately 65 times the power consumption of the PCIe interface 214a.

[0351] These circuit blocks inside the controller 210 and the NAND flash memory are usually Figure 2 as well as Figure 3 The oscillator 219 shown operates based on a clock generated (transmitted) by the oscillator 219 and based on the clock after multiplication and / or frequency division.

[0352] The controller 210 generally has the following mechanism: when no instructions are issued from the host device (recording device 100) for a certain period of time, in order to suppress power consumption as low as possible, the clock frequency supplied to the circuit block inside the controller 210 is divided, etc., thereby gradually reducing the clock frequency and switching to multiple power saving modes.

[0353] Therefore, the following installation is considered: before receiving the Power Management setting 700-6 (OMPREQ) setting for setting the feature instruction, the clock supplied to the circuit block inside the controller 210 is set to the maximum clock frequency and is operated, and in the "optimal performance operation interval" after receiving the Power Management setting 700-6 (OMPREQ) setting for setting the feature instruction, the clock frequency is reduced so as to satisfy the set value of the power consumption state commensurate with the guaranteed speed, that is, the clock frequency is reduced to the minimum clock frequency required for executing speed guaranteed recording and operated.

[0354] In addition, as a means for the host device to instruct the transition to the optimal performance operation mode, an example of using an SD interface or a UHS-II interface and utilizing instructions that comply with the SD protocol, and an example of using a PCIe interface and utilizing instructions that comply with the NVMe protocol are described. However, the PCIe interface is faster than the SD interface and the UHS-II interface, and as a result, the example of using the PCIe interface consumes more power.

[0355] For example, Fig.14 As shown in the figure, in the bus speed mode "UHS-II HD312", the maximum bus speed is 312 Mbytes / second, while in "SD Express PCIe Gen4x2", the maximum bus speed is 3,938 Mbytes / second, which is more than 12 times the speed (bus speed). Fig.14 As shown, in the bus speed mode "UHS-II HD312", the maximum power consumption is 1.80 W, whereas in "SD Express PCIe Gen4x2", the maximum power consumption is 4.00 W, which is more than twice the power consumption.

[0356] Based on this, it can also be considered that the best performance operation mode is only effective when using the more effective PCIe interface and following the NVMe standard protocol for data recording.

[0357] (Overview of Implementation Methods)

[0358] (1) The recording device of the present disclosure is a recording device that records data in a nonvolatile storage device in a recording mode that ensures a minimum recording speed.

[0359] The non-volatile storage device has: a memory that can be loaded and unloaded relative to a recording device, and records data in compliance with the NVMe standard and / or the SD memory card standard.

[0360] The memory guarantees the recording speed for continuous stream recording.

[0361] The recording device includes an interface unit that is physically connected to the nonvolatile storage device and can send at least a data write command and a control command to the nonvolatile storage device.

[0362] The interface unit can send control commands including a data write command for performing data recording, a command for instructing to perform speed-guaranteed recording, and / or a command for reading and writing from a register in the nonvolatile storage device.

[0363] The control command includes information for instructing a transition to the best performance operation mode during continuous stream recording.

[0364] The interface unit sends a control command to the nonvolatile storage device, notifies information indicating speed-guaranteed recording and transition to the best performance operation mode, and sends data for continuous stream recording by a data write command.

[0365] (2) The nonvolatile storage device of the present disclosure is a nonvolatile storage device capable of recording data in a recording mode that ensures a minimum recording speed.

[0366] The nonvolatile storage device is attachable to and detachable from the recording device.

[0367] The non-volatile storage device comprises: a memory; an interface unit for communicating with a recording device; and a memory control unit for recording data in the memory in accordance with the NVMe standard and / or the SD memory card standard.

[0368] The memory guarantees the recording speed for continuous stream recording.

[0369] The nonvolatile storage device includes an interface unit that is physically connected to the recording device and can receive at least a data write command and a control command from the recording device.

[0370] The interface unit can receive control commands including a data write command for performing data recording, a command for instructing to perform speed-guaranteed recording, and / or a command for reading and writing registers in the nonvolatile storage device from the recording device.

[0371] The control command includes information for instructing a transition to the best performance operation mode during continuous stream recording.

[0372] The interface unit receives the control command, and then receives a data write command and data for data recording.

[0373] The memory control unit shifts to an operation mode sufficient to ensure speed based on information instructing shift to the best performance operation mode included in the control command, and performs continuous data recording based on the data write command.

[0374] (3) The recording method of the present disclosure is a recording method performed in a recording device that records data in a nonvolatile storage device in a recording mode that ensures a minimum recording speed.

[0375] The non-volatile storage device includes: a memory that can be loaded and unloaded relative to the above-mentioned recording device, and records data in accordance with the NVMe standard and / or the SD memory card standard.

[0376] The memory guarantees the recording speed for continuous stream recording.

[0377] The recording device includes an interface unit that is physically connected to the nonvolatile storage device and can send at least a data write command and a control command to the nonvolatile storage device.

[0378] The interface unit can send control commands including a data write command for performing data recording, a command for instructing speed-guaranteed recording, and / or a command for reading and writing registers in the nonvolatile storage device.

[0379] The control command includes information for instructing a transition to the best performance operation mode during continuous stream recording.

[0380] The recording method includes: the interface unit sends a control instruction to the non-volatile storage device to indicate speed-guaranteed recording and to notify information indicating a transition to an optimal performance operation mode; and after sending the above-mentioned control instruction, sending a data write instruction and data for continuous data recording.

[0381] In addition, the above-mentioned embodiments are for illustrating the technology in the present disclosure, and therefore various changes, substitutions, additions, omissions, etc. can be made within the scope of the claims or their equivalents.

[0382] For example, in the above-mentioned embodiment, if Fig.21 , Fig. 22 As shown, "OMPREQ" is set as a new instruction, but it can also be unified into "StartREC".

[0383] Industrial Applicability

[0384] The present disclosure can be suitably used in a storage system using a recording device as a host device and the nonvolatile storage device 20 .

[0385] -Explanation of symbols-

[0386] 1, 2, 3 Save System

[0387] 10 Recording Device

[0388] 20 Non-volatile storage device

[0389] 16, 26, 102, 302 interface

[0390] 30 Non-volatile memory

[0391] 100 Recording Device

[0392] 200 memory cards.

Claims

1. A recording device for recording data into a non-volatile storage device at a guaranteed minimum recording speed, The recording device comprises: an interface unit, which is physically connected to the nonvolatile storage device and has a transmission speed faster than the minimum recording speed; The interface unit performs the following operations: A data write command for data recording, a control command including a command for instructing speed-guaranteed recording and a command for instructing transition to a best performance operation mode can be sent to the nonvolatile storage device. After the command instructing to perform the speed-guaranteed recording and the command instructing to shift to the best performance operation mode are transmitted, a data write command for performing the data recording is transmitted.

2. The recording device according to claim 1, wherein The recording speed of the best performance operation mode is faster than the minimum recording speed and slower than the maximum transfer speed of the interface unit.

3. The recording device according to claim 1, wherein: The interface portion corresponds to the NVMe standard, The instruction for indicating the optimal performance operation mode is the data set management instruction of the NVMe standard.

4. The recording device according to claim 1, wherein The interface portion corresponds to the NVMe standard, The instruction for indicating the optimal performance operation mode is a setting feature instruction of the NVMe standard.

5. The recording device according to claim 1, wherein The interface portion corresponds to the SD memory card standard and the NVMe standard, The optimal performance operation mode is only valid when data recording is performed in accordance with the protocol of the NVMe standard.

6. A non-volatile storage device capable of recording data at a minimum recording speed guaranteed by using a recording device, The nonvolatile storage device comprises: an interface unit, which is physically connected to the recording device and has a transmission speed faster than the minimum recording speed; The interface unit performs the following operations: capable of receiving from the recording device a data write command for performing data recording, a control command including a command for instructing to perform speed-guaranteed recording, and a command for instructing to shift to a best performance operation mode, After receiving a command instructing to perform the speed-guaranteed recording and a command instructing to shift to the best performance operation mode, a data write command for performing the data recording is received.

7. The nonvolatile memory device according to claim 6, wherein: The recording speed of the best performance operation mode is faster than the minimum recording speed and slower than the maximum transfer speed of the interface unit.

8. The nonvolatile memory device according to claim 6, wherein: The interface portion corresponds to the NVMe standard, The instruction for indicating the optimal performance operation mode is the data set management instruction of the NVMe standard.

9. The nonvolatile memory device according to claim 6, wherein: The interface portion corresponds to the NVMe standard, The instruction for indicating the optimal performance operation mode is a setting feature instruction of the NVMe standard.

10. The nonvolatile memory device according to claim 6, wherein: The interface portion corresponds to the SD memory card standard and the NVMe standard, The optimal performance operation mode is only valid when data recording is performed in accordance with the protocol of the NVMe standard.

11. A recording method, executed in a recording device for recording data in a nonvolatile storage device at a guaranteed minimum recording speed via an interface unit having a transfer speed faster than the guaranteed minimum recording speed, In the recording method, Sending a command to instruct to perform speed guarantee recording and a command to instruct to shift to the best performance operation mode, A data write command for performing the data recording is sent to the nonvolatile storage device.

12. The recording method according to claim 11, wherein: The recording speed of the best performance operation mode is faster than the minimum recording speed and slower than the maximum transfer speed of the interface unit.

13. The recording method according to claim 11, wherein: The recording device corresponds to the NVMe standard, The instruction for indicating the optimal performance operation mode is the data set management instruction of the NVMe standard.

14. The recording method according to claim 11, wherein: The recording device corresponds to the NVMe standard, The instruction for indicating the optimal performance operation mode is a setting feature instruction of the NVMe standard.

15. The recording method according to claim 11, wherein: The recording device corresponds to the NVMe standard, The optimal performance operation mode is only valid when data recording is performed in accordance with the protocol of the NVMe standard.

Images