Page cleaning scheme for keeping directory pages in exclusive state in single complex

Abstract

In one embodiment, a method includes storing an entry in a cache directory that associates a memory region with an exclusive coherency state, and in response to a memory access to the memory region, sending a degraded super probe to transition at least one cache line of the memory region from the exclusive coherency state to a shared coherency state.

Description

Background Art

[0001] Modern computing systems have multiple central processing units (CPUs) that typically include and rely on multiple caches in a cache hierarchy to improve processor and memory performance. A cache is a smaller, faster memory device that stores frequently accessed data compared to the main memory so that the data can be accessed with low latency. Such cache devices are typically implemented in static random access memory (SRAM) and are typically located between the processing unit that issues the memory request and the main memory device. A memory-side cache is a dedicated cache attached to a specific memory device or partition of memory that caches data written to the memory device and read from the memory device by other devices.

[0002] In multi-node computer systems, special precautions must be taken to maintain the consistency of data used by different processing nodes. For example, if a processor attempts to access data at a certain memory address, it must first determine whether the memory is stored in another cache and has been modified. In order to implement such a cache consistency protocol, the cache typically contains multiple status bits to indicate the state of the cache line to maintain data consistency throughout the system. A common consistency protocol is, for example, the "MOESI" protocol, where each letter represents the state of the cache line. These states are as follows: the cache line has been modified (M), the cache line is exclusive (E) or shared (S), or the cache line is invalid (I). The owned (O) state indicates that the line has been modified in one cache, there may be shared copies in other caches, and the data in the memory is stale. Each cache line includes a status bit in the cache directory (which tracks the cache lines currently used by the system) to indicate which MOESI state the line is in.

[0003] Based on various types of processing requirements and the increase in cache size and main memory size, it becomes very difficult to manage cache directory schemes in multiprocessor systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The implementations illustrated in the figures of the accompanying drawings herein are by way of example and not by way of limitation.

[0005] Figure 1 is a block diagram of a specific implementation of a computing system.

[0006] Figure 2 is a block diagram of a specific implementation of the kernel complex.

[0007] Figure 3 It is a block diagram of a specific implementation of a multi-CPU processor system.

[0008] Figure 4 is a block diagram of a specific implementation of a portion of a processor system.

[0009] Figure 5 is a flow chart of a data extraction process in a processor system without demote superprobe enabled according to a specific implementation.

[0010] Figure 6 is a flow chart of a data extraction process in a processor system with degraded hyper-detection enabled according to a particular implementation. DETAILED DESCRIPTION

[0011] The following description sets forth numerous specific details such as examples of specific systems, components, methods, etc., in order to provide a good understanding of specific implementations. However, it will be apparent to those skilled in the art that at least some specific implementations may be practiced without these specific details. In other cases, well-known components or methods are not described in detail, or are presented in a simple block diagram format in order to avoid unnecessary confusion of specific implementations. Therefore, the specific details set forth are merely exemplary. Specific specific implementations may vary due to these exemplary details, and are still contemplated to be within the scope of specific implementations.

[0012] Computer systems use main memory that is typically formed from inexpensive and high-density dynamic random access memory (DRAM) chips. However, the access time of DRAM chips is relatively long. To improve performance, data processors typically include at least one local high-speed memory called a cache. In a multi-core data processor, each data processor core may have its own dedicated upper-level cache, while lower-level caches are shared by the data processor cores. For example, a typical configuration includes two data processor cores, each with their own dedicated L1 cache, but sharing L2 and L3 caches.

[0013] In more advanced computing systems, each multi-core processor itself can be interconnected with one or more other multi-core processors using high-speed data links to form a data processing fabric. Within the data processing fabric, the various multi-core processors are connected to each other and to their own local memories. All local memories together form a storage space available to any processor in the processor. However, since the memory is physically distributed, the memory access time seen by each processor depends on whether the memory is local or remote. Therefore, this architecture is called a non-uniform memory access (NUMA) architecture.

[0014] In computer systems using a NUMA architecture, special precautions must be taken to maintain the consistency of data that can be used by different processing nodes. For example, if a processor attempts to access data at a certain memory address, it must first determine whether the memory is stored in another cache and has been modified. In order to implement this cache consistency protocol, the cache typically contains multiple status bits to indicate the state of the cache line to maintain data consistency throughout the system. According to the MOESI protocol, each cache line includes a status bit indicating which MOESI state the line is in, including a bit indicating that the cache line has been modified (M), whether the cache line is exclusive (E) or shared (S), or that the cache line is invalid (I). The owned (O) state indicates that the line has been modified in one cache, there may be a shared copy in other caches, and the data in the memory is stale.

[0015] To maintain coherence, these systems use "probes" to communicate between the various caches within a computer system. A "probe" is a message passed from a coherence point in a computer system (e.g., a coherence master or slave) to one or more caches in the computer system to determine whether the cache has a copy of a data block and optionally indicate the state the cache should place the data block into. After a processing node receives a probe, it responds to the probe by taking appropriate action.

[0016] In one implementation, memory access requests for memory are forwarded to a cache directory where a lookup of the requested address is performed to determine which caches are caching the data. Probes may then be sent to those caches to perform appropriate actions to maintain consistency. For example, the cache directory may contain information indicating that various subsystems contain shared copies of a block of data. In response to a command to exclusively access the block, invalidation probes may be transmitted to other shared subsystems so that they may invalidate their respective copies of the block.

[0017] The bandwidth associated with the network interconnecting processing nodes can quickly become a limiting factor for performance, particularly for systems employing a large number of processors or when a large number of probes are sent during a short period of time. In such systems, cache directories are used as probe filters to reduce bandwidth requirements by filtering out unnecessary probes. For example, if a cache line is designated as read-only, the memory controller associated with the requesting processor core does not need to send a probe to determine whether another processing node with a copy of the cache line has modified the data. However, while probe filters can reduce system traffic and access latency, they consume a large amount of storage space to maintain the state of all cache lines in the system. In addition, if the size of the memory that needs to be searched is too large, the probe filter can add a clock cycle delay between the access request and the determination that a probe does not need to be issued.

[0018] Some implementations employ a region-based snoop filter design as a tradeoff between area (and its associated issues, such as power consumption, timing, throughput, etc.) and accuracy. As the number of CPUs increases, and the corresponding caches and cache sizes become larger, the cache directory also scales up proportionally to track the larger number of entries. One implementation accesses the cache directory on a per-cache-line basis to determine where the line has been cached in the system and the current state of the line in order to properly filter out snoops when a memory request is received. In contrast, a region-based snoop filter reduces the amount of chip area consumed by the cache directory by tracking memory regions corresponding to multiple groups of cache lines in the system rather than a single cache line. In this way, decisions can be made collectively for the entire cache line group. In one implementation, each region in a region-based snoop filter is associated with one of the following coherency states:

[0019] Exclusive: Each row in the region is owned by a single kernel complex.

[0020] Shared: Multiple core complexes have rows in the region. The same row can be shared between multiple core complexes (true sharing), or multiple core complexes can each own different rows in the same region (false sharing).

[0021] Clean: cannot be exclusive (e.g., "clean shared" (CS)), and is unmodified with respect to the backing data in memory.

[0022] Dirty: Can be exclusive or shared (e.g., "dirty exclusive" (DE) or "dirty shared" (DS)). Dirty rows have been modified and are known to be dirty or considered dirty because they may have changed without the detection filter's knowledge.

[0023] However, when clean data is widely shared among multiple core complexes, the region-based probe filter design can lead to performance issues due to the lack of per-row accuracy in the coherence state tracking. The core complex brings data blocks into its cache subsystem by issuing data fetch opcodes (e.g., RdBlkL) that attempt to return exclusive lines whenever possible. However, exclusive lines can be silently modified (upgrading their coherence state to M) without the probe filter's knowledge.

[0024] When the region is subsequently accessed from another core cache complex, the region-based probe filter cannot determine whether the data block is clean or dirty due to the lack of row-by-row fidelity. Therefore, probes are issued to maintain correctness unless a supporting row-based probe filter entry is available. Although the system can include row-based probe filters, these filters are typically sized for communication variables and will be violated by workloads with a large memory footprint. Once the region transitions to the "dirty shared" (DS) state, the unavailability of row-based probe filters results in the generation of multicast probes. These probes and probe responses can cause bottlenecks on cross-die or socket links, limiting performance as the design scales. In many applications, many of the probes are unnecessary because the requested rows are already kept clean. Widely shared clean workloads may result in a large number of multicast probes because at least one row in the region is considered dirty.

[0025] In one specific implementation, a computing system implements a degraded super probe to mitigate this problem, where a super probe is a probe for multiple destinations (e.g., each row of a region). In such a system, certain trigger conditions prior to the above may cause a degraded super probe to be transmitted to any cache containing rows in the entire region where the trigger condition is detected. The degraded super probe changes any "exclusive" (E) cache line of the region to a "shared" (S) cache line without changing any other consistency state. The degraded super probe also determines whether any row in the region is "dirty" (D), and updates the consistency state of the region accordingly in the region-based detection filter. If the degraded super probe finds any dirty rows in the region, the consistency state of the region is corrected to a "modified shared" (MS) state. If no dirty rows are found, the region state is corrected to a "clean shared" (CS) state. Therefore, for a "clean shared" (CS) region, the generation of excessive multicast probes is avoided, while for a "modified shared" (MS) region known to have modified rows, probes are still appropriately generated.

[0026] Figure 11 is a block diagram of one implementation of a computing system 100 that implements a region-based probing filter with a degraded superprobing. The computing system 100 includes a plurality of core complexes 105A-N and a plurality of home nodes 130A-N. The computing system 100 also includes an input / output (I / O) interface 120, a data fabric / bus 125, and a network interface 135. In other implementations, the computing system 100 may include other components and / or be arranged in other configurations.

[0027] In one implementation, each core complex 105A-N includes a processing element, such as one or more processor cores or other dedicated processing elements. Each processor core within a core complex 105A-105N includes a cache subsystem having one or more levels of cache. In one implementation, the cache subsystem includes a shared cache (e.g., Figure 2 In some implementations, one or more core complexes 105A-N may include a data parallel processor with a highly parallel architecture, such as one or more of a graphics processing unit (GPU), a digital signal processor (DSP), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc. As used herein, a "core complex" may also be referred to as a "processing node" or a "CPU" or a "CPU complex."

[0028] In one specific implementation, the home node 130 may include one or more of a coherent slave, a cache directory, and a memory controller coupled to any number and type of memory devices (not shown). For example, the memory devices coupled to the home node 130 may include dynamic random access memory (DRAM), static random access memory (SRAM), NAND flash memory, NOR flash memory, ferroelectric random access memory (FeRAM), etc.

[0029] The I / O (input / output) interface 120 represents any number and type of I / O interfaces, such as, but not limited to, various types of peripheral component interconnect (PCI) buses, gigabit Ethernet (GBE) buses, universal serial buses (USB), dedicated processors (e.g., platform security processors, graphics processors), and system management logic. Various types of peripheral devices may be coupled to the I / O interface 120. Such peripheral devices include, but are not limited to, displays, keyboards, mice, printers, scanners, joysticks or other types of game controllers, media recording devices, external storage devices, network interface cards, and the like.

[0030] In various implementations, computing system 100 may be any of a server, a desktop computer, a laptop computer, a mobile device, a gaming console, a streaming device, a wearable device, or various other types of computing systems or devices. The number, orientation, and type of components shown in computing system 100 are by way of example only and may vary between different implementations based on the application and system architecture.

[0031] Figure 2 is the core complex 200 (e.g. Figure 1 20A-N). In one implementation, the core complex 200 may include four processor cores 210A-D and a cache subsystem including a level 1 (L1) cache 215A-D, a level 2 (L2) cache 220A-D, and a level 3 (L3) cache 230. The cache subsystem may include a high-speed cache memory (e.g., L1 cache 215A-215D, L2 cache 220A-220D, and L3 cache 230) configured to store blocks of data (not shown). As used herein, a "block" is a group of bytes stored in contiguous memory locations within a cache memory that is treated as a unit for consistency purposes. Additionally, each of the terms "cache block," "block," "cache line," and "line" are interchangeable herein. In some implementations, a block may also be a unit of allocation and release in a cache. Blocks may be allocated from other caches within the system, such as from other core complexes (e.g., Figure 1 of the core complex 105A-105N), or retrieved from main memory, for example by Figure 1 The home node 130A is retrieved.

[0032] Additionally, in one implementation, the L3 cache 230 is shared by each of the processor cores 210A-D. The L3 cache 230 is coupled to a cache memory for accessing data structures (e.g., Figure 1 10A). In other implementations, the core complex 200 may include fewer or more processor cores (e.g., processor core 210A) and corresponding L2 caches (e.g., L2 cache 220A). In still other implementations, the core complex 200 may include other types of addressable cache subsystems that may include different numbers, types, and levels of cache memory without departing from the scope of the present disclosure.

[0033] Figure 3308A-N). In various implementations, the number of CPUs (e.g., CPU 305A) and the number of cores (e.g., cores 308A-N) per CPU may vary according to design choice. Each CPU 305A-N also includes a corresponding one of cache subsystems 310A-N. In various implementations, cache subsystems 310A-N may vary in size and structure, as described above with reference to FIG. Figure 2 described.

[0034] In one specific implementation, each CPU 305A-N is connected to a corresponding coherence master 315A-N, which is further connected to data fabric / bus 318. As used herein, "coherence master" is defined as an agent that includes circuit components that handle traffic flowing on an interconnect (e.g., data fabric / bus 318) and manage cache coherence, including each coherence master (e.g., coherence master 315A-N), each of which works in concert to generate, receive, and process coherence-related messages and probes to synchronize copies of shared cache data within processor system 300.

[0035] In various implementations, each CPU 305A-N may be connected to one or more coherence slaves through a corresponding coherence master 315A-N and data texture / bus 318. For example, CPU 305A may be connected to multiple coherence slaves, such as coherence slaves (CS) 320A-320D and coherence slaves 321A-321D, each connected through coherence master 315A and data texture / bus 318, that may access each other's cache directories. Coherence slave 320A is connected to memory controller (MC) 330A and cache directory (CD) 325A, while coherence slave 321A is coupled to memory controller 331A and cache directory 326A. Each memory controller 330A-N and 331A-N is connected to a respective one of memory devices 340. One of the functions of each memory controller, such as memory controller 330A, is to provide access to memory devices 340 to elements of processor system 300. In various implementations, although shown as one block, the memory device 340 may be comprised of one or more physical memories and may be of any type suitable for storing data, such as dynamic random access memory (DRAM), static random access memory (SRAM), etc.

[0036] In one implementation, each cache directory (e.g., cache directory 325A) includes one or more entries, and each entry corresponds to a region in memory 340. Each entry includes information to track data cached within processor system 300 that corresponds to data within a region in memory 340. Region sizes (sometimes referred to as page sizes) may be defined by blocks of addresses in memory 340, and this address may vary between implementations depending on how the memory is organized (e.g., whether the memory is interleaved across channels) and the memory address mapping basis. In one implementation, one or more fields of an entry may be configured to change the page size of the region in memory 340 being tracked by the cache directory.

[0037] In one implementation, the memory in device 340 is equally divided in each of memory controllers 330A-N and 331A-N, and each coherent slave device (e.g., coherent slave devices 320A-N and 321A-N) and their corresponding cache directories (e.g., cache directories 325A-N and 326A-N) manage corresponding equal and contiguous portions of the memory. Alternatively, some or all of the memory devices in memory device 340 have different storage capacities. In various implementations, a coherent slave device may access the cache directories of one or more other coherent slave devices. For example, coherent slave device 320A may access multiple other cache directories within processor system 300, such as 326A-326N and 325B-325N.

[0038] In one specific implementation, the coherence slaves 320A-N and 321A-N are each coupled to a corresponding cache directory 325A-N and 326A-N that functions as a probe filter. When the coherence slave 320A receives a memory request targeted to its corresponding memory controller 330A, the coherence slave 320A performs a lookup in its corresponding cache directory 325A to determine whether the request targets data in a memory location within a region of memory 340 tracked by an entry in the cache directory 325A, and whether the memory request results in a cache hit, meaning that the requested data can be found in a cache line stored in a cache subsystem 310A-N associated with the region. In one specific implementation, if the lookup results in a hit, the coherence slave 320A sends a probe to the CPU (e.g., CPU 305A-N) identified in the hit entry in the cache directory. The type of probe generated by the coherence slave 320A depends on the coherence state specified by the hit entry.

[0039] Despite Figure 3318 to other components not shown in the figure, but in other implementations, there may be other connections from the data fabric / bus 318 to other components not shown to avoid obscuring the figure. For example, in another implementation, the data fabric / bus 318 includes connections to one or more I / O interfaces and one or more I / O devices, such as Figure 1 shown.

[0040] Figure 4 A portion of a processor system 300 according to a specific implementation is illustrated. The cache directory 325A includes a row detection filter directory 410 and a region detection filter directory 420. The row detection filter directory 410 includes a set of entries, each entry identifying a cache line 411 (e.g., with an address or other identifier) ​​and associating it with a consistency state 412. The region detection filter directory 420 includes a set of entries, each entry identifying a memory region 421 in the memory device 340A and associating the region 421 with a consistency state 422. In one specific implementation, the region is a memory page. The row 411 and region 421 fields identify the cache line and region by their address (e.g., base address) or address range. The consistency state fields 412 and 422 store values ​​indicating the consistency state of the associated row or region, such as clean, dirty or modified, and exclusive or shared. Each entry in the row snoop filter directory 410 and the region snoop filter directory 420 may also include additional metadata for the identified row or region, such as a valid bit, a reference count of the number of cache lines of the region that is cached somewhere in the processor system, and the like.

[0041] A controller device such as a coherent slave 320A includes a probe filter logic 431 that, in conjunction with a cache directory 325A, performs a coherent action by sending a probe in response to a memory access request based on whether the requested line is cached and based on the coherence state and cache location of the requested line as indicated by the cache directory 325A. The coherent slave 320A also includes throttling logic and registers 430 for performing throttling of degraded super probes. The registers are used to record metrics related to degraded super probes (e.g., the number of incomplete degraded super probe recommendations, the number of failed degraded super probes, etc.) and the throttling logic compares the recorded metrics to one or more thresholds to determine whether to allow for the recommendation of further degraded super probes.

[0042] Figure 5 is a flow chart illustrating the operation of the processor system 300 when the degraded super detection function is disabled or unavailable according to a specific implementation. In this specific implementation, widely shared clean data may cause congestion in the data fabric interconnect due to lack of row-by-row accuracy in coherency state tracking.

[0043] At box 501, a data fetch operation allocates an "exclusive" (E) region. The data fetch opcode (e.g., RdBlkL) attempts to return "exclusive" (E) lines whenever possible and points to a memory region in memory 340A when the data fetch is executed. In response to the data fetch, the probe filter implemented by the coherent slave device 320A and the cache directory 325A returns the "exclusive" (E) lines to the requesting kernel complex, which installs the lines in its cache subsystem. The coherence state of the region is recorded as "dirty exclusive" (DE) in the region probe filter directory 420 because the returned lines can be silently upgraded to the "modified" (M) state without the knowledge of the probe filter. That is, if or when the line is modified by the kernel complex system, the probe filter does not receive any indication because the line is "exclusive" (E).

[0044] At block 503, data fetches from different core complexes target the same region, so the coherency state of the region is changed from "dirty exclusive" (DE) to "dirty shared" (DS) in the region snoop filter directory 420. To properly maintain cache coherency, the snoop filter assumes that the region is "dirty" (D) if an "exclusive" (E) line is modified without the snoop filter's knowledge.

[0045] When a subsequent data fetch is received from any core complex for a region in the "Dirty Shared" (DS) state, as provided at block 505, the row probe filter directory 410 is checked for the requested row.

[0046] At block 507 , if row probe filter 410 contains an entry for the requested row, the consistency state of the row may be determined from the entry, and the process continues at block 511 .

[0047] At block 511, the row probe filter recommends directed probing, multicast probing, or no probing for a particular row, depending on the row's coherency state. The row is then installed in the cache subsystem of the requesting core in the appropriate coherency state, which depends on the coherency state associated with the row in the row probe filter directory 410.

[0048] The requested row will not be found in the row probe filter directory 410, especially when a workload with a large memory footprint is being processed. The row probe filter directory 410 may be undersized (e.g., it may be sized for communication variables) and will be repeatedly checked and unable to provide consistency status for most of the requested rows. Therefore, due to the lack of row-by-row fidelity in the design, when the row probe filter cannot provide consistency status for a row, a probe is issued to ensure correctness. Therefore, process 500 continues from block 507 to block 509.

[0049] Once the region is transitioned to the "dirty shared" (DS) state and subsequently hit by a data fetch operation, this will result in the generation of a multicast probe. At block 509, the region probe filter recommends a multicast probe for each row in the region. Multicast probes and probe responses may cause bottlenecks on cross-die and / or socket links, thereby limiting performance when the design is scaled. At block 509, the probe filter allows the installation of an "exclusive" (E) row in the cache of the requesting core complex.

[0050] The coherency state of the cache lines for the region is updated at block 513 via the probe generated at block 509 or 511 , as appropriate.

[0051] Figure 6 is a flow chart illustrating the operation of the processor system 300 with the degraded super detection function enabled according to a specific implementation. Figure 6 The operations shown are performed by components of the processor system 300, including cache directory 325A, coherence slave 320A, memory controller 330A, etc. Typically, a data fetch opcode is issued by the core complex (e.g., CPU 305A) to fetch a row of data from memory. The data fetch is received by a coherence slave (e.g., coherence slave 320A) associated with the memory device storing the row. The coherence slave obtains the requested row from the memory device via the memory controller and provides the row to the core complex for installation in the cache subsystem of the core complex. The coherence slave also performs actions for maintaining the coherence of rows stored in different caches, such as sending coherence probes.

[0052] A kernel complex (e.g., kernel complex 305A) extracts data from one of the memory devices 340 by sending a data extraction opcode (e.g., RdBlkL) via data texture 318. At block 601, the data extraction opcode is received by the coherent slave device 320A. At block 603, if the memory region is accessed by only one kernel complex (e.g., the kernel complex that issues the data extraction is the first kernel complex to access the region, and no other kernel complex has accessed the region), the process 600 continues at block 605. At block 605, the requested line from the memory region is installed in the cache subsystem of the kernel complex. When possible, a data extraction opcode such as RdBlkL returns an "exclusive" (E) line, so the cache line is installed with an "exclusive" (E) coherency state. At this point, there is no need to track the line separately in the line detection filter directory. According to block 605, the process 600 returns to block 601 to process subsequent data extraction. Subsequent data fetches from the same core complex for the same region are also installed in the cache in the "exclusive" (E) state, via blocks 603 and 605.

[0053] At box 603, if more than one core complex is accessing the region (e.g., the data fetch is accessing the region from a second core complex), process 600 continues at box 607. At box 607, coherency slave 320A determines whether the region has a "clean exclusive" (CE) or "clean shared" (CS) coherency state by looking up the region in the region probe filter directory 420. If the region is in the "clean exclusive" (CE) or "clean shared" (CS) state, at box 609, the cache line is installed in the cache subsystem of the requesting core complex with a "shared" (S) coherency state. Because the region is "clean", the coherency slave 320A does not generate a probe. According to box 609, process 600 returns to box 601 to continue processing subsequent data fetches.

[0054] At block 607, if the region is not in a "clean exclusive" (CE) or "clean shared" (CS) coherency state, process 600 continues at block 611. At block 611, the coherency slave device 320A determines whether any of several trigger conditions have occurred. Trigger conditions may include, but are not limited to:

[0055] A first new kernel access occurs when a first data fetch is performed from the second kernel complex to access the region, the first data fetch causing the region to transition from a Dirty Exclusive (DE) state to a Dirty Shared (DS) state.

[0056] A data fetch that hits a region in the "Dirty Shared" (DS) state and increments the Aggregate Reference Count (ARC) above a programmable threshold. The ARC tracks the number of lines in the region that have a copy cached in one of the caches.

[0057] The first data fetch hits a region from a remote socket that is in a "dirty shared" DS state.

[0058] In one specific implementation, the coherent slave records information about which core complexes have sent data fetches to a particular region to identify when a trigger condition has occurred. When no trigger condition is detected, the requested line is installed in the cache subsystem of the core complex that issued the request, as provided in block 605.

[0059] At box 611, if one or more of the trigger conditions are detected, the consistency slave device recommends a downgrade super probe, as provided in box 613. In one specific implementation, the downgrade super probe recommendation is recorded by asserting a register bit or flag. In one specific implementation, the consistency slave device includes a throttling function that adjusts the rate at which downgrade super probe recommendations are generated based on one or more result indicators of the downgrade operation during the monitored time period. Such a specific implementation may include static and dynamic throttling mechanisms for downgrade super probes. For example, a static upper limit can be set on the number of incomplete downgrade super probe recommendations at any point in time. Dynamic throttling options include counters that count the number of qualified, recommended, and failed downgrade operations within a runtime window, and provide programmable thresholds to increase or decrease the rate of downgrade recommendations to allow the design to be dynamically adjusted according to the nature of the workload, thereby minimizing the number of wasted downgrade super probes. "Eligible" means the trigger conditions for downgrading the super probe have been met, "Recommended" means eligibility is defined by dynamic throttling conditions, and "Failed" means the region is transitioned from "Clean Share" back to "Modified Share", "Modified Share" means the cleaning action of the failed super probe is not warranted or is short-sighted.

[0060] In one implementation, the counter and comparison logic for performing throttling are included in the coherence slaves 320A-N and 321A-N, or alternatively in the cache directories 325A-N and 326A-N. If throttling is enabled for the number of outstanding downgrade super probe recommendations, a downgrade super probe is recommended when the number of outstanding downgrade super probes is less than a threshold limit. Then, when a downgrade super probe is recommended, the throttling logic 430 increments the number of outstanding downgrade super probes.

[0061] At block 614, if throttling is enabled and the number of downgraded super probe recommendations is not less than the throttling threshold limit, then at block 616, the recommendation is discarded and the number of outstanding downgraded super probe recommendations is decremented. As provided at block 605, the cache line is installed and process 600 returns to block 601 to continue processing the next data fetch operation.

[0062] At box 614, if the number of downgraded super probe recommendations is less than the threshold limit, the process 600 continues at box 615. At box 615, conventional consistency actions and concurrent operations on addresses in the same region are allowed to complete. These may include, for example, data extraction operations for other rows in the same region occurring in the same cycle, and their associated consistency actions (such as detection). If at box 617, the region has any dirty rows resulting from the operation of box 615, then at box 619, the downgraded super probe recommendation is discarded. For example, a bit or flag indicating the recommendation may be deasserted. If throttling is enabled, the number of incomplete downgraded super probes is decremented. The region is transitioned to a "modified shared" (MS) consistency state, which explicitly indicates that at least one of the rows in the region has been changed and is different from the data in the backing store 340. According to box 619, the process 600 returns to box 601 to continue processing data extraction operations.

[0063] If, at block 617, the region does not have any dirty lines, then process 600 continues at block 621. If the region has an ambiguous "dirty shared" (DS) coherency state indicated in the region probe filter directory, this indicates that it is not known whether any of the lines in the region have actually been modified, as it is possible that at least one of the lines has been silently modified without any updates to cache directory 325A. If the region is not in an ambiguous "dirty shared" (DS) state, then process 600 installs the requested cache line, as provided in block 605. The coherency state of individual lines is tracked in row probe filter directory 410, as appropriate.

[0064] At block 621, if the region is associated with an ambiguous "dirty shared" DS state in the region probe filter 420, the coherency slave device 320A sends a demote super probe, as provided in block 623. The demote super probe is a multicast coherency probe that targets all cache lines in the cache lines associated with the memory region and demotes (i.e., converts) cache lines with an "exclusive" (E) coherency state to a "shared" (S) coherency state without changing other coherency states. The converted cache lines may include cache lines installed in response to data fetch opcodes issued from multiple respective core complexes; thus, the cache lines may be distributed among multiple different cache subsystems in different core complexes.

[0065] In response to the downgraded super probe, the coherence master associated with the hit cache line returns a probe response indicating whether the cache line is dirty. At box 625, if the downgraded super probe finds that any of the lines in the region are dirty, the coherence state of the region is corrected to "modified shared" (MS) in the region probe filter directory 420. When the region is in the MS coherence state, in response to data extraction, the cache line is installed in the "exclusive" (E) coherence state, and an entry in the line probe filter 410 can be allocated to track the coherence state of the dirty cache line, as provided in box 605. At box 625, if the downgraded super probe does not find any dirty lines in the region, the coherence state of the region is corrected to "clean shared" (CS) in the region probe filter directory 420. According to box 627 or 629, the process 600 returns to box 601 to continue processing data extraction. In the case where the region is in the "clean shared" CS state, subsequent data extraction will not cause a probe to be issued, and the cache line is installed in the "shared" (S) coherence state, as provided in box 609.

[0066] A method includes storing an entry in a cache directory associating a memory region with an exclusive coherence state, and in response to a memory access to the memory region, sending a destage superprobe to convert at least one cache line of the memory region from the exclusive coherence state to a shared coherence state.

[0067] The method further includes, in response to the memory access, determining whether the memory region is associated with one or more dirty cache lines, and in response to determining that the region is not associated with the one or more dirty cache lines, changing a coherency state of the memory region to a clean shared coherency state.

[0068] The method further includes, in response to a data fetch opcode for the memory region, installing one or more cache lines having a shared coherence state when the coherence state of the memory region is a clean shared coherence state.

[0069] In the method, storing of an entry associating a memory region with an exclusive coherency state is responsive to a first data fetch opcode received from a first core complex for the memory region.The memory access is a second data fetch opcode received from a second core complex.

[0070] In the method, the at least one cache line includes a plurality of cache lines, each cache line being installed in response to a data fetch opcode issued by a different corresponding core complex.

[0071] The method further includes, in response to the memory access, determining whether the memory region is associated with one or more dirty cache lines, and in response to determining that the memory region is associated with the one or more dirty cache lines, adding one or more entries in a line probe filter to track a coherency state of each of the one or more dirty cache lines.

[0072] The method further includes, after determining that the memory region is associated with one or more dirty cache lines, installing the cache line with an exclusive coherency state in response to receiving a subsequent data fetch opcode for the memory region.

[0073] In the method, sending of the degraded super probe is further performed in response to determining that the number of outstanding degraded super probe recommendations is less than a threshold limit.

[0074] The method further includes adjusting a rate at which degrade super detection recommendations are generated based on one or more outcome indicators of degraded operation during the monitored time period.

[0075] A computing device includes: a cache directory for storing entries associating a memory region with an exclusive coherence state; and a controller device coupled to the cache directory and, in response to a memory access to the memory region, sending a degraded super probe to convert at least one cache line associated with the memory region from an exclusive coherence state to a shared coherence state.

[0076] In the computing device, the controller device further determines, in response to the memory access, whether the memory region is associated with one or more dirty cache lines, and in response to determining that the region is not associated with the one or more dirty cache lines, changes the coherence state of the memory region to a clean shared coherence state.

[0077] In the computing device, the controller device further installs one or more cache lines having a shared coherence state in response to a data fetch opcode for the memory region when the coherence state of the memory region is a clean shared coherence state.

[0078] In a computing device, in response to a first data fetch opcode received from a first core complex for a memory region, a cache directory stores an entry associating the memory region with an exclusive coherency state, and a memory access includes a second data fetch opcode received by a controller device from a second core complex.

[0079] In the computing device, the controller device further determines, in response to the memory access, whether the memory region is associated with one or more dirty cache lines. The cache directory further includes a line snoop filter directory, the line snoop filter directory being used to store one or more entries to track a coherence state of each of the one or more dirty cache lines when the memory region is associated with the one or more dirty cache lines.

[0080] In the computing device, the controller device further installs the cache line with an exclusive coherency state in response to receiving a subsequent data fetch opcode for the memory region after determining that the memory region is associated with one or more dirty cache lines.

[0081] In the computing device, the controller device performs sending of the degraded super probe in response to determining that a number of outstanding degraded super probe recommendations is less than a threshold limit.

[0082] In the computing device, a controller device adjusts a rate at which degraded super detection recommendations are generated based on one or more result indicators of degraded operation during a monitored time period.

[0083] A system includes: a set of processor core complexes; a cache directory coupled to the set of processor core complexes to store entries associating a memory region with an exclusive coherence state; and a controller device coupled to the cache directory to send a degrade super probe in response to a memory access to the memory region to convert at least one cache line associated with the memory region from an exclusive coherence state to a shared coherence state.

[0084] In the system, the cache directory further includes: a region detection filter directory, which is used to store a first set of entries for tracking the consistency status associated with multiple memory regions of the memory device; and a line detection filter directory, which is used to store a second set of entries for tracking the consistency status of multiple cache lines associated with the memory device.

[0085] In the system, each processor core complex in the set of processor core complexes includes a cache device for storing one or more cache lines that are associated with a memory region and are installed in the cache device in response to one or more data fetch opcodes issued by the processor core complex.

[0086] As used herein, the term "coupled to" may mean directly coupled or indirectly coupled through one or more intervening components. Any signal provided on the various buses described herein may be time-division multiplexed with other signals and provided on one or more common buses. In addition, the interconnections between circuit components or blocks may be shown as buses or single signal lines. Each of the buses may alternatively be one or more single signal lines, and each of the single signal lines may alternatively be a bus.

[0087] Certain specific implementations may be implemented as a computer program product, which may include instructions stored on a non-transitory computer-readable medium. These instructions can be used to program a general-purpose or special-purpose processor to perform the described operations. Computer-readable media include any mechanism for storing or transmitting information in a form (e.g., software, processing application) readable by a machine (e.g., a computer). Non-transitory computer-readable storage media may include, but are not limited to: magnetic storage media (e.g., floppy disks); optical storage media (e.g., CD-ROMs); magneto-optical storage media; read-only memory (ROM); random access memory (RAM); erasable programmable memory (e.g., EPROM and EEPROM); flash memory or another type of medium suitable for storing electronic instructions.

[0088] In addition, some embodiments may be practiced in a distributed computing environment in which the computer-readable medium is stored on more than one computer system and / or executed by more than one computer system. In addition, information transmitted between computer systems may be pushed or pulled across the transmission medium connecting the computer systems.

[0089] In general, the data structure representing the computing system 100 and / or its parts carried on the computer-readable storage medium can be a database or other data structure that can be read by a program and used directly or indirectly to manufacture the hardware including the computing system 100. For example, the data structure can be a behavioral level description of the hardware functions in a high-level design language (HDL) such as Verilog or VHDL or a register transfer level (RTL) description. The description can be read by a synthesis tool, which can synthesize the description to produce a netlist including a list of gates from a synthesis library. The netlist includes a set of gates, which also represents the functions of the hardware including the computing system 100. The netlist can then be placed and routed to produce a data set describing the geometry to be applied to the mask. The mask can then be used in various semiconductor manufacturing steps to produce a semiconductor circuit or circuit corresponding to the computing system 100. Alternatively, the database on the computer-readable storage medium can be a netlist (with or without a synthesis library) or a data set (as needed) or a graphic data system (GDS) II data.

[0090] Although the operations of the methods herein are shown and described in a particular order, the order of the operations of each method may be changed so that certain operations may be performed in reverse order, or certain operations may be performed at least partially simultaneously with other operations. In another specific implementation, instructions or sub-operations of different operations may be performed in an intermittent and / or alternating manner.

[0091] In the foregoing description, the implementations have been described with reference to specific exemplary embodiments thereof. However, it will be apparent that various modifications and changes may be made to these implementations without departing from the broader scope of the implementations as set forth in the appended claims. Therefore, the description and drawings should be regarded as illustrative rather than restrictive.

Claims

1. A method, comprising: storing an entry associating a memory region with an exclusive coherence state; as well as In response to a memory access to the memory region, a destage superprobe is sent to transition at least one cache line of the memory region from an exclusive coherence state to a shared coherence state.

2. The method according to claim 1, further comprising: The coherence state of the memory region is changed to a clean shared coherence state based on the memory region not being associated with one or more dirty cache lines.

3. The method according to claim 2, further comprising: When the coherence state of the memory region is the clean shared coherence state, in response to a data fetch opcode for the memory region, one or more cache lines having a shared coherence state are installed.

4. The method according to claim 1, wherein: The storing of the entry associating the memory region with the exclusive coherency state is responsive to a first data fetch opcode received from a first core complex for the memory region; and The memory access is a second data fetch opcode received from a second core complex.

5. The method according to claim 1, wherein: The at least one cache line includes a plurality of cache lines, each cache line being installed in response to a data fetch opcode issued by a different corresponding core complex.

6. The method according to claim 1, further comprising: Based on the memory region being associated with one or more dirty cache lines, one or more entries are added in a line snoop filter to track a coherency state of each of the one or more dirty cache lines.

7. The method of claim 6, further comprising, after determining that the memory region is associated with the one or more dirty cache lines: In response to receiving a subsequent data fetch opcode for the memory region, the cache line having the exclusive coherency state is installed.

8. The method of claim 1, wherein: In response to determining that the number of outstanding degraded super probe recommendations is less than a threshold limit, the sending of the degraded super probe is further performed.

9. The method according to claim 1, further comprising: A rate at which degrade super detection recommendations are generated is adjusted based on one or more outcome metrics of the degrade operation over a monitored time period.

10. A computing device, comprising: a cache directory configured to store entries associating a memory region with an exclusive coherence state; as well as A controller device is coupled to the cache directory and is configured to send a degraded super probe in response to a memory access to the memory region to transition at least one cache line associated with the memory region from an exclusive coherence state to a shared coherence state.

11. The computing device of claim 10, wherein: The controller device is further configured to: responsive to the memory access, determining whether the memory region is associated with one or more dirty cache lines; as well as In response to determining that the region is not associated with the one or more dirty cache lines, the coherence state of the memory region is changed to a clean shared coherence state.

12. The computing device of claim 11, wherein: The controller device is further configured to: When the coherence state of the memory region is the clean shared coherence state, in response to a data fetch opcode for the memory region, one or more cache lines having a shared coherence state are installed.

13. The computing device of claim 10, wherein: The cache directory is configured to, in response to a first data fetch opcode received from a first core complex for the memory region, store the entry associating the memory region with the exclusive coherency state; and The memory access includes a second data fetch opcode received by the controller device from a second core complex.

14. The computing device of claim 10, wherein: The controller device is further configured to, in response to the memory access, determine whether the memory region is associated with one or more dirty cache lines; and The cache directory further includes a line snoop filter directory configured to store one or more entries to track a coherency state of each of the one or more dirty cache lines when the memory region is associated with the one or more dirty cache lines.

15. The computing device of claim 14, wherein: The controller device is further configured to, after determining that the memory region is associated with the one or more dirty cache lines, install the cache line having the exclusive coherency state in response to receiving a subsequent data fetch opcode for the memory region.

16. The computing device of claim 10, wherein: The controller device is configured to perform the sending of the degraded super probe in response to determining that a number of outstanding degraded super probe recommendations is less than a threshold limit.

17. The computing device of claim 10, wherein: The controller device is configured to adjust a rate at which degraded super detection recommendations are generated based on one or more outcome indicators of degraded operation during a monitored time period.

18. A system, comprising: a set of processor core complexes; a cache directory coupled to the set of processor core complexes and configured to store entries associating a memory region with an exclusive coherency state; as well as A controller device is coupled to the cache directory and is configured to send a degraded super probe in response to a memory access to the memory region to transition at least one cache line associated with the memory region from an exclusive coherence state to a shared coherence state.

19. The system of claim 18, wherein: The cache directory further includes: a region probe filter directory configured to store a first set of entries for tracking coherency states associated with a plurality of memory regions of a memory device; and A line snoop filter directory is configured to store a second set of entries for tracking a coherency state of a plurality of cache lines associated with the memory device.

20. The system of claim 18, wherein: Each processor core complex in the set of processor core complexes includes a cache device configured to store one or more cache lines, The one or more cache lines are associated with the memory region and are installed in the cache device in response to one or more data fetch opcodes issued by the processor core complex.

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