Display substrate, driving method and preparation method thereof and display device

Abstract

The invention discloses a display substrate, a driving method and a preparation method thereof, and a display device. The display substrate comprises a plurality of circuit units, each circuit unit at least comprises a pixel driving circuit, the pixel driving circuit at least comprises a data write-in transistor (T4), and the data write-in transistor (T4) is connected with a data signal line (62); the plurality of circuit units at least comprise a first circuit unit (Q1) and a second circuit unit (Q2), the first circuit unit (Q1) comprises a first pixel driving circuit, the second circuit unit (Q2) comprises a second pixel driving circuit, and the first pixel driving circuit and the second pixel driving circuit share the same data write-in transistor (T4) and are connected with the same data signal line (62). The data signal line (62) sequentially provides a first data signal to the first pixel driving circuit and a second data signal to the second pixel driving circuit through the data writing transistor (T4).

Description

Display substrate, driving method and manufacturing method thereof, and display device Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, and specifically to a display substrate, a driving method and a preparation method thereof, and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] On the one hand, the present disclosure provides a display substrate, including multiple circuit units constituting multiple unit rows and multiple unit columns, at least one circuit unit at least including a pixel driving circuit, at least one pixel driving circuit at least including a data writing transistor, and the data writing transistor is connected to a data signal line; the multiple circuit units at least include a first circuit unit and a second circuit unit adjacent to each other in the unit row direction, the first circuit unit includes a first pixel driving circuit, the second circuit unit includes a second pixel driving circuit, the first pixel driving circuit and the second pixel driving circuit share the same data writing transistor and are connected to the same data signal line, and the data signal line provides a first data signal to the first pixel driving circuit and a second data signal to the second pixel driving circuit in sequence through the data writing transistor.

[0006] In an exemplary embodiment, the orthographic projection of the data write transistor on the display substrate plane at least partially overlaps with the orthographic projection of the unit boundary line on the display substrate plane, and the orthographic projection of the data signal line on the display substrate plane at least partially overlaps with the orthographic projection of the unit boundary line on the display substrate plane, and the unit boundary line is a straight line located between the first circuit unit and the second circuit unit and extending along the unit column direction.

[0007] In an exemplary embodiment, the data write transistor includes at least a data write active layer, the data signal line is connected to the first region of the data write active layer through a data connection electrode, the orthographic projection of the data write active layer on the display substrate plane at least partially overlaps with the orthographic projection of the unit dividing line on the display substrate plane, and the orthographic projection of the data connection electrode on the display substrate plane at least partially overlaps with the orthographic projection of the unit dividing line on the display substrate plane.

[0008] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate includes a plurality of conductive layers sequentially arranged on a base, the data signal line and the data connection electrode are arranged in different conductive layers, the data signal line is connected to the data connection electrode through a first connection via, and the orthographic projection of the first connection via on the plane of the display substrate at least partially overlaps with the orthographic projection of the unit dividing line on the plane of the display substrate.

[0009] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate further includes a first semiconductor layer, the data writing active layer is arranged in the first semiconductor layer, the data connection electrode is connected to the first area of ​​the data writing active layer through a second connection via, and the orthographic projection of the second connection via on the plane of the display substrate at least partially overlaps with the orthographic projection of the unit dividing line on the plane of the display substrate.

[0010] In an exemplary embodiment, the display substrate further includes a first control signal line and a second control signal line; the first control signal line is connected to the first pixel driving circuit, and the first control signal line is configured to cause the data signal line to provide a first data signal to the first pixel driving circuit; the second control signal line is connected to the second pixel driving circuit, and the second control signal line is configured to cause the data signal line to provide a second data signal to the second pixel driving circuit.

[0011] In an exemplary embodiment, the first pixel driving circuit further includes a first compensation transistor and a first driving transistor, the second pixel driving circuit further includes a second compensation transistor and a second driving transistor, the data writing transistor is connected to the first electrode of the first driving transistor and the first electrode of the second driving transistor, respectively; the gate electrode of the first compensation transistor is connected to the first control signal line, the first electrode of the first compensation transistor is connected to the gate electrode of the first driving transistor, and the second electrode of the first compensation transistor is connected to the second electrode of the first driving transistor; the gate electrode of the second compensation transistor is connected to the second control signal line, the first electrode of the second compensation transistor is connected to the gate electrode of the second driving transistor, and the second electrode of the second compensation transistor is connected to the second electrode of the second driving transistor.

[0012] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate includes a plurality of conductive layers sequentially disposed on a base, and the first control signal line and the second control signal line are disposed in the same conductive layer.

[0013] In an exemplary embodiment, the data write transistor, the first drive transistor, and the second drive transistor are polysilicon transistors, and the first compensation transistor and the second compensation transistor are oxide transistors.

[0014] In an exemplary embodiment, the pixel driving circuit further includes a light emitting control transistor, the first pixel driving circuit and the second pixel driving circuit share the same light emitting control transistor, a first electrode of the light emitting control transistor is connected to a first power line, and a second electrode of the light emitting control transistor is connected to a second electrode of the data writing transistor.

[0015] In an exemplary embodiment, the light-emitting control transistor includes at least a light-emitting control active layer, the first power line is connected to the first region of the light-emitting control active layer through a power connection electrode, the orthographic projection of the light-emitting control active layer on the display substrate plane at least partially overlaps with the orthographic projection of the unit dividing line on the display substrate plane, and the orthographic projection of the power connection electrode on the display substrate plane at least partially overlaps with the orthographic projection of the unit dividing line on the display substrate plane.

[0016] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate includes a plurality of conductive layers sequentially arranged on a base, the first power line and the power connection electrode are arranged in different conductive layers, the first power line is connected to the power connection electrode through a third connection via, and the third connection via is respectively arranged in the first circuit unit and the second circuit unit.

[0017] In an exemplary embodiment, the pixel driving circuit further includes an initialization transistor, the first pixel driving circuit and the second pixel driving circuit share the same initialization transistor, a first electrode of the initialization transistor is connected to an initial signal line, and a second electrode of the initialization transistor is connected to a second electrode of the data writing transistor.

[0018] In an exemplary embodiment, the initialization transistor includes at least an initialization active layer, a first region of the initialization active layer is connected to the initial signal line, a second electrode of the initialization transistor is connected to the second electrode of the data writing transistor via an initial connection electrode, and an orthographic projection of the initial connection electrode on the plane of the display substrate at least partially overlaps with an orthographic projection of the cell boundary line on the plane of the display substrate.

[0019] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate further includes a first semiconductor layer, the initialization active layer is arranged in the first semiconductor layer, the initial connection electrode is connected to the active layer of the data writing transistor through a fourth connection via, and the orthographic projection of the fourth connection via on the plane of the display substrate at least partially overlaps with the orthographic projection of the unit dividing line on the plane of the display substrate.

[0020] On the other hand, the present disclosure further provides a display device comprising the aforementioned display substrate.

[0021] In yet another aspect, the present disclosure further provides a method for driving a display substrate, the display substrate comprising a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, at least one circuit unit comprising at least a pixel driving circuit, at least one pixel driving circuit comprising at least a data writing transistor, the data writing transistor being connected to a data signal line; the plurality of circuit units comprising at least a first circuit unit and a second circuit unit adjacent to each other in a unit row direction, the first circuit unit comprising a first pixel driving circuit, the second circuit unit comprising a second pixel driving circuit, the first pixel driving circuit and the second pixel driving circuit sharing a same data writing transistor and a same data signal line; the driving method comprising:

[0022] The data signal line sequentially provides a first data signal to the first pixel driving circuit and a second data signal to the second pixel driving circuit through the data writing transistor.

[0023] In an exemplary embodiment, the display substrate further includes a first control signal line and a second control signal line; the first pixel driving circuit further includes a first compensation transistor, a first driving transistor and a first storage capacitor, the gate electrode of the first compensation transistor is connected to the first control signal line, the first electrode of the first compensation transistor is respectively connected to the gate electrode of the first driving transistor and the first storage capacitor, the second electrode of the first compensation transistor is connected to the second electrode of the first driving transistor, and the first electrode of the first driving transistor is connected to the data writing transistor; the second pixel driving circuit further includes a second compensation transistor, a second driving transistor and a second storage capacitor, the gate electrode of the second compensation transistor is connected to the second control signal line, the first electrode of the second compensation transistor is respectively connected to the gate electrode of the second driving transistor and the second storage capacitor, the second electrode of the second compensation transistor is connected to the second electrode of the second driving transistor, and the first electrode of the second driving transistor is connected to the data writing transistor.

[0024] In an exemplary embodiment, the data signal line sequentially provides a first data signal to the first pixel driving circuit and a second data signal to the second pixel driving circuit through the data writing transistor, including:

[0025] The first control signal line provides a turn-on signal, and the second control signal line provides a turn-off signal, so that the first compensation transistor is turned on to initialize the first storage capacitor;

[0026] The first control signal line provides a disconnection signal, the second control signal line provides a conduction signal, the second compensation transistor is turned on, and the second storage capacitor is initialized;

[0027] The first control signal line provides a turn-on signal, the second control signal line provides a turn-off signal, the first compensation transistor is turned on, and the data signal line provides a first data signal to the first storage capacitor through the data writing transistor, the first driving transistor, and the first compensation transistor;

[0028] The first control signal line provides a disconnect signal, the second control signal line provides a turn-on signal, the second compensation transistor is turned on, and the data signal line provides a second data signal to the second storage capacitor through the data writing transistor, the second driving transistor and the second compensation transistor.

[0029] In an exemplary embodiment, the data signal line sequentially provides a first data signal to the first pixel driving circuit and a second data signal to the second pixel driving circuit through the data writing transistor, including:

[0030] The first control signal line provides a turn-on signal, and the second control signal line provides a turn-off signal, so that the first compensation transistor is turned on to initialize the first storage capacitor;

[0031] The first control signal line provides a turn-on signal, the second control signal line provides a turn-off signal, the first compensation transistor is turned on, and the data signal line provides a first data signal to the first storage capacitor through the data writing transistor, the first driving transistor, and the first compensation transistor;

[0032] The first control signal line provides a disconnect signal, the second control signal line provides a turn-on signal, the second compensation transistor is turned on, and the second storage capacitor is initialized;

[0033] The first control signal line provides a disconnect signal, the second control signal line provides a turn-on signal, the second compensation transistor is turned on, and the data signal line provides a second data signal to the second storage capacitor through the data writing transistor, the second driving transistor and the second compensation transistor.

[0034] In an exemplary embodiment, the data signal line sequentially provides a first data signal to the first pixel driving circuit and a second data signal to the second pixel driving circuit through the data writing transistor, including:

[0035] The first control signal line provides a turn-on signal, and the second control signal line provides a turn-off signal, so that the first compensation transistor is turned on to initialize the first storage capacitor;

[0036] The first control signal line provides a conduction signal, the second control signal line provides a conduction signal, the first compensation transistor is turned on to initialize the first storage capacitor, and the second compensation transistor is turned on to initialize the second storage capacitor;

[0037] The first control signal line provides a turn-on signal, the second control signal line provides a turn-on signal, the first compensation transistor is turned on, the data signal line provides a first data signal to the first storage capacitor through the data write transistor, the first drive transistor and the first compensation transistor, the second compensation transistor is turned on, and the data signal line provides the first data signal to the second storage capacitor through the data write transistor, the second drive transistor and the second compensation transistor;

[0038] The first control signal line provides a disconnect signal, the second control signal line provides a turn-on signal, the second compensation transistor is turned on, and the data signal line provides a second data signal to the second storage capacitor through the data writing transistor, the second driving transistor and the second compensation transistor.

[0039] In yet another aspect, the present disclosure further provides a method for manufacturing a display substrate, the display substrate comprising a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, at least one circuit unit comprising at least a pixel driving circuit, at least one pixel driving circuit comprising at least a data writing transistor, the data writing transistor being connected to a data signal line, the plurality of circuit units comprising at least a first circuit unit and a second circuit unit adjacent to each other in a unit row direction; the manufacturing method comprising:

[0040] A first pixel driving circuit is formed in the first circuit unit, and a second pixel driving circuit is formed in the second circuit unit. The first pixel driving circuit and the second pixel driving circuit share the same data writing transistor and the same data signal line. The data signal line provides a first data signal to the first pixel driving circuit and a second data signal to the second pixel driving circuit in sequence through the data writing transistor.

[0041] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0043] FIG1 is a schematic structural diagram of a display device;

[0044] FIG2 is a schematic diagram of a planar structure of a display substrate;

[0045] FIG3 is a schematic diagram of a cross-sectional structure of a display substrate;

[0046] FIG4 is a schematic diagram of an equivalent circuit of a pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0047] FIG5 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0048] FIG6 is a schematic diagram of a connection between a pixel driving circuit and signal lines according to an exemplary embodiment of the present disclosure;

[0049] FIG7 is a schematic diagram showing a substrate after forming a first semiconductor layer pattern according to the present disclosure;

[0050] 8A and 8B are schematic diagrams showing a substrate after forming a first conductive layer pattern according to the present disclosure;

[0051] 9A and 9B are schematic diagrams showing a substrate after forming a second conductive layer pattern according to the present disclosure;

[0052] 10A and 10B are schematic diagrams showing a substrate after forming a second semiconductor layer pattern according to the present disclosure;

[0053] 11A and 11B are schematic diagrams showing a substrate after a third conductive layer pattern is formed thereon according to the present disclosure;

[0054] FIG12 is a schematic diagram showing a substrate after a sixth insulating layer pattern is formed according to the present disclosure;

[0055] 13A and 13B are schematic diagrams showing a substrate after a fourth conductive layer pattern is formed in the present disclosure;

[0056] FIG14 is a schematic diagram showing a substrate after forming a first planar layer pattern according to the present disclosure;

[0057] 15A and 15B are schematic diagrams showing a substrate after a fifth conductive layer pattern is formed thereon according to the present disclosure;

[0058] FIG16 is a schematic diagram showing a substrate after forming a second planar layer pattern according to the present disclosure;

[0059] FIG17 is a schematic diagram showing a substrate after forming an anode conductive layer pattern according to the present disclosure;

[0060] FIG18 is a driving timing diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0061] FIG19 is another driving timing diagram of the pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0062] FIG. 20 is another driving timing diagram of the pixel driving circuit according to an exemplary embodiment of the present disclosure.

[0063] Explanation of Reference Numerals: 11—first active layer; 12—second active layer; 13—third active layer; 14—fourth active layer; 15—fifth active layer; 16—sixth active layer; 17—seventh active layer; 18—eighth active layer; 21—first scanning signal line; 22—second scanning signal line; 23—third scanning signal line; 24—light-emitting signal line; 31—first shielding line; 32—second shielding line; 41—first initial signal line; 42—second initial signal line; 43—third initial signal line; 51—first connecting electrode; 52—second connecting electrode; 53—third connecting electrode; 54—fourth connecting electrode; 55—fifth connecting electrode; 56—sixth connecting electrode; 57—seventh connecting electrode; 58—eighth connecting electrode; 59—ninth connecting electrode; 61—first power line; 62—data signal line; 63—anode connecting electrode; 71—first electrode plate; 72—second electrode plate; 73—opening; 74—electrode plate connecting strip; 81—first control line; 82—second control line; 101—substrate; 102—driving circuit layer; 103—light-emitting structure layer; 104—encapsulation structure layer. DETAILED DESCRIPTION

[0064] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0065] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0066] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0067] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0068] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0069] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0070] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" can be interchanged, and "source terminal" and "drain terminal" can be interchanged.

[0071] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0072] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0073] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0074] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0075] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0076] FIG1 is a schematic diagram of the structure of a display device. As shown in FIG1 , the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is respectively connected to the data driver, the scan driver, and the light-emitting driver. The data driver is respectively connected to a plurality of data signal lines (D1 to Dn). The scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm). The light-emitting driver is respectively connected to a plurality of light-emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is respectively connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. The light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, may provide clock signals, scan start signals, etc. suitable for the specifications of the scan driver to the scan driver, and may provide clock signals, emission stop signals, etc. suitable for the specifications of the light-emitting driver to the light-emitting driver. The data driver can generate data voltages to be supplied to data signal lines D1, D2, D3, ..., and Dn using grayscale values ​​and control signals received from a timing controller. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a per-pixel basis, where n can be a natural number. The scan driver can generate scan signals to be supplied to scan signal lines S1, S2, S3, ..., and Sm by receiving clock signals, scan start signals, and the like from the timing controller. For example, the scan driver can sequentially supply scan signals having on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can sequentially transmit scan start signals provided in the form of on-level pulses to the next-stage circuit under the control of a clock signal, where m can be a natural number. The light driver can generate emission signals to be supplied to light signal lines E1, E2, E3, ..., and Eo by receiving clock signals, emission stop signals, and the like from the timing controller. For example, the light emitting driver may sequentially provide emission signals having off-level pulses to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be configured as a shift register and may generate emission signals by sequentially transmitting emission stop signals provided in the form of off-level pulses to the next stage circuit under the control of a clock signal. o may be a natural number. In an exemplary embodiment, the pixel array may be provided on a display substrate.

[0077] FIG2 is a schematic diagram of a planar structure of a display substrate. As shown in FIG2 , the display substrate may include a plurality of pixel units P arranged in a matrix, and at least one pixel unit P may include a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit is respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting unit. The light-emitting unit may include a light-emitting device. The light-emitting device is connected to the pixel driving circuit of the sub-pixel in which it is located. The light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which it is located.

[0078] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) that emits red light, the second subpixel P2 and the fourth subpixel P4 may be green subpixels (G) that emit green light, and the third subpixel P3 may be a blue subpixel (B) that emits blue light. In an exemplary embodiment, the subpixels may be rectangular, rhombus, pentagonal, or hexagonal, and the four subpixels may be arranged in a diamond shape to form an RGBG pixel arrangement. In other exemplary embodiments, the four subpixels may be arranged horizontally, vertically, or in a square, etc., which is not limited in this disclosure.

[0079] In an exemplary embodiment, a pixel unit may include three sub-pixels, and the three sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a triangular arrangement, which is not limited in the present disclosure.

[0080] Figure 3 is a schematic cross-sectional view of a display substrate, illustrating the structure of four sub-pixels in the display area. As shown in Figure 3, in a plane perpendicular to the display substrate, the display substrate may include a drive circuit layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on the side of the drive circuit layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which is not limited in this disclosure.

[0081] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. The driving circuit layer 102 may include a plurality of circuit units, each of which may include at least a pixel driving circuit composed of a plurality of transistors and a storage capacitor. The light-emitting structure layer 103 may include a plurality of light-emitting units, each of which may include a light-emitting device, which may include at least an anode, an organic light-emitting layer, and a cathode. The anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of a corresponding color under the drive of the anode and the cathode. The encapsulation structure layer 104 may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0082] The exemplary embodiments of the present disclosure provide a display substrate. In an exemplary embodiment, on a plane perpendicular to the display substrate, the display substrate may include a driving structure layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving structure layer away from the substrate. On a plane parallel to the display substrate, the driving structure layer may include a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, at least one of the circuit units may include a pixel driving circuit, and the pixel driving circuit is configured to output a corresponding current to the connected light-emitting device. The light-emitting structure layer may include a plurality of light-emitting units, at least one of the light-emitting units may include a light-emitting device, the light-emitting device being connected to the pixel driving circuit of the corresponding circuit unit, and the light-emitting device being configured to emit light of corresponding brightness in response to the current output by the connected pixel driving circuit.

[0083] In exemplary embodiments, the circuit unit referred to in this disclosure refers to a region divided according to the pixel driving circuit, and the light-emitting unit referred to in this disclosure refers to a region divided according to the light-emitting device. In exemplary embodiments, the position and shape of the orthographic projection of the light-emitting unit on the substrate may correspond to the position and shape of the orthographic projection of the circuit unit on the substrate, or the position and shape of the orthographic projection of the light-emitting unit on the substrate may not correspond to the position and shape of the orthographic projection of the circuit unit on the substrate.

[0084] In an exemplary embodiment, the display substrate of the present disclosure may include multiple circuit units constituting multiple unit rows and multiple unit columns, at least one circuit unit includes at least a pixel driving circuit, and at least one pixel driving circuit includes at least a data writing transistor, and the data writing transistor is connected to a data signal line; the multiple circuit units include at least a first circuit unit and a second circuit unit adjacent to each other in the unit row direction, the first circuit unit includes a first pixel driving circuit, and the second circuit unit includes a second pixel driving circuit, the first pixel driving circuit and the second pixel driving circuit share the same data writing transistor and are connected to the same data signal line, and the data signal line provides a first data signal to the first pixel driving circuit and a second data signal to the second pixel driving circuit in sequence through the data writing transistor.

[0085] In an exemplary embodiment, the display substrate further includes a first control signal line and a second control signal line; the first control signal line is connected to the first pixel driving circuit, and the first control signal line is configured to cause the data signal line to provide a first data signal to the first pixel driving circuit; the second control signal line is connected to the second pixel driving circuit, and the second control signal line is configured to cause the data signal line to provide a second data signal to the second pixel driving circuit.

[0086] In an exemplary embodiment, the pixel driving circuit further includes a light emitting control transistor, the first pixel driving circuit and the second pixel driving circuit share the same light emitting control transistor, a first electrode of the light emitting control transistor is connected to a first power line, and a second electrode of the light emitting control transistor is connected to a second electrode of the data writing transistor.

[0087] In an exemplary embodiment, the pixel driving circuit further includes an initialization transistor, the first pixel driving circuit and the second pixel driving circuit share the same initialization transistor, a first electrode of the initialization transistor is connected to an initial signal line, and a second electrode of the initialization transistor is connected to a second electrode of the data writing transistor.

[0088] The display substrate of the exemplary embodiments of the present disclosure will be described below with reference to some examples.

[0089] Figure 4 is a schematic diagram of an equivalent circuit of a pixel driving circuit according to an exemplary embodiment of the present disclosure, illustrating the structures of a first pixel driving circuit (left side) in a first circuit unit and a second pixel driving circuit (right side) in a second circuit unit. As shown in Figure 4, the pixel driving circuit in each circuit unit may include eight transistors (first transistor T1 to eighth transistor T8) and one storage capacitor C. Each pixel driving circuit is connected to ten signal lines (a first scanning signal line S1, a second scanning signal line S2, a third scanning signal line S3, a control signal line KS, an emission signal line EM, a first initial signal line INIT1, a second initial signal line INIT2, a third initial signal line INIT3, a data signal line DATA, and a first power line VDD).

[0090] In an exemplary embodiment, each pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is respectively connected to the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first end of the storage capacitor C, the second node N2 is respectively connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8, the third node N3 is respectively connected to the second electrode of the first transistor T1, the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, the fourth node N4 is respectively connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, and the fourth node N4 is also connected to the anode of the light emitting device EL.

[0091] In an exemplary embodiment, a first terminal of the storage capacitor C in each pixel driving circuit is connected to the first node N1 , and a second terminal of the storage capacitor C is connected to the first power line VDD.

[0092] In an exemplary embodiment, the first transistor T1 in the first pixel driving circuit and the second pixel driving circuit may be referred to as a first initialization transistor, a gate electrode of the first transistor T1 is connected to the third scan signal line S3, a first electrode of the first transistor T1 is connected to the first initial signal line INIT1, and a second electrode of the first transistor T1 is connected to the third node N3. In an exemplary embodiment, the gate electrodes of the first transistors T1 in the first pixel driving circuit and the second pixel driving circuit may be connected to each other, and the first electrodes of the first transistors T1 in the first pixel driving circuit and the second pixel driving circuit may be connected to each other.

[0093] In an exemplary embodiment, the second transistor T2 in each pixel driving circuit may be referred to as a compensation transistor. A first electrode of the second transistor T2 is connected to the first node N1, and a second electrode of the second transistor T2 is connected to the third node N3. A gate electrode of the second transistor T2 in the first pixel driving circuit is connected to the first control signal line KS1, and a gate electrode of the second transistor T2 in the second pixel driving circuit is connected to the second control signal line KS2.

[0094] In an exemplary embodiment, the third transistor T3 in the first pixel driving circuit and the second pixel driving circuit may be referred to as a driving transistor. The gate electrode of the third transistor T3 is connected to the first node N1, that is, the gate electrode of the third transistor T3 is connected to the first end of the storage capacitor C. The first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3. In an exemplary embodiment, the second electrodes of the third transistors T3 in the first pixel driving circuit and the second pixel driving circuit may be connected to each other.

[0095] In an exemplary embodiment, the fourth transistor T4 in the first pixel driving circuit and the second pixel driving circuit can be referred to as a data writing transistor. The gate electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line DATA, and the second electrode of the fourth transistor T4 is connected to the second node N2. In an exemplary embodiment, the fourth transistor T4 in the first pixel driving circuit can serve as the fourth transistor T4 in the second pixel driving circuit, or the fourth transistor T4 in the second pixel driving circuit can serve as the fourth transistor T4 in the first pixel driving circuit, that is, the first pixel driving circuit and the second pixel driving circuit share the same fourth transistor T4.

[0096] In an exemplary embodiment, the fifth transistor T5 in the first pixel driving circuit and the second pixel driving circuit can be referred to as a first light emission control transistor. A gate electrode of the fifth transistor T5 is connected to the light emission signal line EM, a first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and a second electrode of the fifth transistor T5 is connected to the second node N2. In an exemplary embodiment, the fifth transistor T5 in the first pixel driving circuit can serve as the fifth transistor T5 in the second pixel driving circuit, or the fifth transistor T5 in the second pixel driving circuit can serve as the fifth transistor T5 in the first pixel driving circuit. That is, the first pixel driving circuit and the second pixel driving circuit share the same fifth transistor T5.

[0097] In an exemplary embodiment, the sixth transistor T6 in each pixel driving circuit can be referred to as a second light emitting control transistor, a gate electrode of the sixth transistor T6 is connected to the light emitting signal line EM, a first electrode of the sixth transistor T6 is connected to the third node N3, and a second electrode of the sixth transistor T6 is connected to the fourth node N4.

[0098] In an exemplary embodiment, the seventh transistor T7 in the first pixel driving circuit and the second pixel driving circuit may be referred to as a second initialization transistor, a gate electrode of the seventh transistor T7 is connected to the second scan signal line S2, a first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and a second electrode of the seventh transistor T7 is connected to the fourth node N4. In an exemplary embodiment, the gate electrodes of the seventh transistors T7 in the first pixel driving circuit and the second pixel driving circuit may be connected to each other, and the first electrodes of the seventh transistors T7 in the first pixel driving circuit and the second pixel driving circuit may be connected to each other.

[0099] In an exemplary embodiment, the eighth transistor T8 in the first pixel driving circuit and the second pixel driving circuit can be referred to as a third initialization transistor. The gate electrode of the eighth transistor T8 is connected to the second scan signal line S2, the first electrode of the eighth transistor T8 is connected to the third initialization signal line INIT3, and the second electrode of the eighth transistor T8 is connected to the second node N2. In an exemplary embodiment, the eighth transistor T8 in the first pixel driving circuit can serve as the eighth transistor T8 in the second pixel driving circuit, or the eighth transistor T8 in the second pixel driving circuit can serve as the eighth transistor T8 in the first pixel driving circuit, that is, the first pixel driving circuit and the second pixel driving circuit share the same eighth transistor T8.

[0100] In an exemplary embodiment, the light-emitting device EL in each circuit unit can be an OLED, including a stacked anode (first pole), an organic light-emitting layer and a cathode (second pole), or can be a QLED, including a stacked anode (first pole), a quantum dot light-emitting layer and a cathode (second pole).

[0101] In an exemplary embodiment, a first electrode of the light emitting device EL in each circuit unit is connected to the fourth node N4 , and a second electrode of the light emitting device EL is connected to the second power line VSS.

[0102] In an exemplary embodiment, the signal of the first power line VDD is a continuously provided high level signal, and the signal of the second power line VSS is a continuously provided low level signal.

[0103] In some possible exemplary embodiments, the first transistor T1 to the eighth transistor T8 in each pixel driving circuit may be a P-type transistor, or may be an N-type transistor. In other possible exemplary embodiments, the first transistor T1 to the eighth transistor T8 in each pixel driving circuit may include a P-type transistor and an N-type transistor.

[0104] In an exemplary embodiment, the first transistor T1 to the eighth transistor T8 in each pixel driving circuit may be low-temperature polysilicon transistors, or oxide transistors, or both low-temperature polysilicon transistors and metal oxide transistors. The active layer of the low-temperature polysilicon transistor is made of low-temperature polysilicon (LTPS), while the active layer of the metal oxide transistor is made of metal oxide semiconductor (Oxide). Low-temperature polysilicon transistors have advantages such as high mobility and fast charging, while oxide transistors have advantages such as low leakage current. Integrating low-temperature polysilicon transistors and metal oxide transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate can leverage the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0105] In an exemplary embodiment, the second transistor T2 in the first pixel driving circuit and the second pixel driving circuit may be a metal oxide transistor (N-type transistor), and the first transistor T1 and the third transistor T3 to the eighth transistor T8 may be a low-temperature polysilicon transistor (P-type transistor).

[0106] Figure 5 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of a first circuit unit Q1 and a second circuit unit Q2 adjacent to each other in a first direction X (unit row direction). In an exemplary embodiment, the display substrate may include a plurality of circuit units, which may form a plurality of unit rows and a plurality of unit columns. The plurality of circuit units in each unit row are sequentially arranged along the first direction X, and the plurality of unit rows are sequentially arranged along the second direction Y, forming an array of circuit units arranged in an array, with the first direction X intersecting the second direction Y.

[0107] As shown in FIG5 , the first circuit unit Q1 may include a first pixel driving circuit, and the second circuit unit Q2 may include a second pixel driving circuit. Each pixel driving circuit may include at least a storage capacitor and multiple transistors. The storage capacitor may include a stacked first electrode plate and a second electrode plate. The multiple transistors may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8. The second transistor T2 is an oxide transistor, and the first transistor T1, the third transistor T3, the third transistor T4, the fourth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8. The second transistor T2 is an oxide transistor, and the first transistor T1, the third transistor T3, the third transistor T8, and the eighth transistor T8 are low-temperature polysilicon transistors.

[0108] In an exemplary embodiment, the fourth transistor T4 in the first pixel driving circuit can serve as the fourth transistor T4 in the second pixel driving circuit, or the fourth transistor T4 in the second pixel driving circuit can serve as the fourth transistor T4 in the first pixel driving circuit. The first pixel driving circuit and the second pixel driving circuit share the same fourth transistor T4, and the fourth transistor T4 can serve as the data writing transistor of the present disclosure.

[0109] In an exemplary embodiment, the fifth transistor T5 in the first pixel driving circuit can serve as the fifth transistor T5 in the second pixel driving circuit, or the fifth transistor T5 in the second pixel driving circuit can serve as the fifth transistor T5 in the first pixel driving circuit. The first pixel driving circuit and the second pixel driving circuit share the same fifth transistor T5, and the fifth transistor T5 can serve as the light-emitting control transistor of the present disclosure.

[0110] In an exemplary embodiment, the eighth transistor T8 in the first pixel driving circuit can serve as the eighth transistor T8 in the second pixel driving circuit, or the eighth transistor T8 in the second pixel driving circuit can serve as the eighth transistor T8 in the first pixel driving circuit. The first pixel driving circuit and the second pixel driving circuit share the same eighth transistor T8, and the eighth transistor T8 can serve as the initialization transistor of the present disclosure.

[0111] In an exemplary embodiment, in each pixel driving circuit, the gate electrode of the first transistor T1 is connected to the third scanning signal line 23 , the first electrode of the first transistor T1 is connected to the first initial signal line 41 , and the second electrode of the first transistor T1 is connected to the second electrode of the third transistor T3 .

[0112] In an exemplary embodiment, the second transistor T2 in the first pixel driving circuit may serve as a first compensation transistor, and the third transistor T3 in the first pixel driving circuit may serve as a first driving transistor. In the first pixel driving circuit, the second transistor T2 is connected to the first control signal line 81, a first electrode of the second transistor T2 is connected to a gate electrode of the third transistor T3, and a second electrode of the second transistor T2 is connected to a second electrode of the third transistor T3.

[0113] In an exemplary embodiment, the second transistor T2 in the second pixel driving circuit may serve as a second compensation transistor, and the third transistor T3 in the second pixel driving circuit may serve as a second driving transistor. In the second pixel driving circuit, the second transistor T2 is connected to the second control signal line 82, a first electrode of the second transistor T2 is connected to a gate electrode of the third transistor T3, and a second electrode of the second transistor T2 is connected to a second electrode of the third transistor T3.

[0114] In an exemplary embodiment, the fourth transistor T4 shared by the first pixel driving circuit and the second pixel driving circuit can be used as a data writing transistor, the gate electrode of the fourth transistor T4 is connected to the first scanning signal line 21, the first electrode of the fourth transistor T4 is connected to the data signal line 62, and the second electrode of the fourth transistor T4 is connected to the first electrode of the third transistor T3 in the two pixel driving circuits.

[0115] In an exemplary embodiment, the fifth transistor T5 shared by the first pixel driving circuit and the second pixel driving circuit can serve as a first light-emitting control transistor, the gate electrode of the fifth transistor T5 is connected to the light-emitting signal line 24, the first electrode of the fifth transistor T5 is connected to the first power line 61, and the second electrode of the fifth transistor T5 is simultaneously connected to the first electrode of the third transistor T3 in the two pixel driving circuits and the second electrode of the fourth transistor T4 shared by the two pixel driving circuits.

[0116] In an exemplary embodiment, in each pixel driving circuit, the gate electrode of the sixth transistor T6 is connected to the light emitting signal line 24 , the first electrode of the sixth transistor T6 is connected to the second electrode of the third transistor T3 , and the second electrode of the sixth transistor T6 is connected to the second electrode of the seventh transistor T7 .

[0117] In an exemplary embodiment, in each pixel driving circuit, the gate electrode of the seventh transistor T7 is connected to the second scanning signal line 22 , the first electrode of the seventh transistor T7 is connected to the second initial signal line 42 , and the second electrode of the seventh transistor T7 is connected to the second electrode of the sixth transistor T6 .

[0118] In an exemplary embodiment, the eighth transistor T8 shared by the first pixel driving circuit and the second pixel driving circuit can serve as an initialization transistor, the gate electrode of the eighth transistor T8 is connected to the second scanning signal line 22, the first electrode of the eighth transistor T8 is connected to the third initial signal line 43, and the second electrode of the eighth transistor T8 is simultaneously connected to the first electrode of the third transistor T3 in the two pixel driving circuits, the second electrode of the fourth transistor T4 shared by the two pixel driving circuits, and the second electrode of the fifth transistor T5 shared by the two pixel driving circuits.

[0119] In an exemplary embodiment, the shapes of the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, the light-emitting signal line 24, the first initial signal line 41, the second initial signal line 42, the third initial signal line 43, the first control signal line 81 and the second control signal line 82 can be straight lines or broken lines with the main parts extending along the first direction X, and the shapes of the first power line 61 and the data signal line 62 can be straight lines or broken lines with the main parts extending along the second direction Y.

[0120] In this disclosure, "A extends along direction B" means that A can include a main portion and a secondary portion connected to the main portion, the main portion being a line, line segment, or strip, extending along direction B, and the length of the main portion extending along direction B being greater than the length of the secondary portion extending along other directions. In the following description, "A extends along direction B" means "the main portion of A extends along direction B."

[0121] In an exemplary embodiment, the data signal line 62 connected to the first pixel driving circuit can serve as the data signal line 62 connected to the second pixel driving circuit, or the data signal line 62 connected to the second pixel driving circuit can serve as the data signal line 62 connected to the first pixel driving circuit. The first pixel driving circuit and the second pixel driving circuit are connected to the same data signal line 62, that is, the first pixel driving circuit and the second pixel driving circuit share the same data signal line 62.

[0122] In an exemplary embodiment, the data signal line 62 can sequentially provide a first data signal to the first pixel driving circuit and a second data signal to the second pixel driving circuit through the fourth transistor T4, that is, in one time period, the data signal line 62 provides the first data signal required by the first pixel driving circuit to the first pixel driving circuit, and in another time period, the data signal line 62 provides the second data signal required by the second pixel driving circuit to the second pixel driving circuit.

[0123] In an exemplary embodiment, the data signal line 62 shared by the first pixel driving circuit and the second pixel driving circuit can be set at a position between the first circuit unit Q1 and the second circuit unit Q2, and the orthographic projection of the data signal line 62 on the display substrate plane at least partially overlaps with the orthographic projection of the unit dividing line A on the display substrate plane, and the unit dividing line A is a straight line located between the first circuit unit Q1 and the second circuit unit Q2 and extending along the second direction Y.

[0124] In an exemplary embodiment, the fourth transistor T4 shared by the first pixel driving circuit and the second pixel driving circuit can be set at a position between the first circuit unit Q1 and the second circuit unit Q2, and the orthographic projection of the fourth transistor T4 on the display substrate plane at least partially overlaps with the orthographic projection of the unit dividing line A on the display substrate plane.

[0125] In an exemplary embodiment, the fourth transistor T4 may include at least a fourth active layer. The data signal line 62 may be connected to the first region of the fourth active layer via the third connection electrode 53. The orthographic projection of the fourth active layer on the display substrate plane at least partially overlaps with the orthographic projection of the cell boundary line A on the display substrate plane. The orthographic projection of the third connection electrode 53 on the display substrate plane at least partially overlaps with the orthographic projection of the cell boundary line A on the display substrate plane. The fourth active layer may serve as the data writing active layer of the present disclosure, and the third connection electrode 53 may serve as the data connection electrode of the present disclosure.

[0126] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include a plurality of conductive layers sequentially arranged on a base, the data signal line 62 and the third connection electrode 53 may be arranged in different conductive layers, the data signal line 62 is connected to the third connection electrode 53 through a first connection via K1, and the orthographic projection of the first connection via K1 on the plane of the display substrate at least partially overlaps with the orthographic projection of the unit dividing line A on the plane of the display substrate.

[0127] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may further include a first semiconductor layer, a fourth active layer may be arranged in the first semiconductor layer, the third connection electrode 53 is connected to the first region of the fourth active layer through a second connection via K2, and the orthographic projection of the second connection via K2 on the plane of the display substrate at least partially overlaps with the orthographic projection of the unit dividing line A on the plane of the display substrate.

[0128] In an exemplary embodiment, the fifth transistor T5 shared by the first pixel driving circuit and the second pixel driving circuit can be set in the area between the first circuit unit Q1 and the second circuit unit Q2, and the orthographic projection of the fifth transistor T5 on the display substrate plane at least partially overlaps with the orthographic projection of the unit dividing line A on the display substrate plane.

[0129] In an exemplary embodiment, the fifth transistor T5 may include at least a fifth active layer. The first power line 61 may be connected to the first region of the fifth active layer via the fourth connection electrode 54. The orthographic projection of the fifth active layer on the display substrate plane at least partially overlaps with the orthographic projection of the cell boundary line A on the display substrate plane. The orthographic projection of the fourth connection electrode 54 on the display substrate plane at least partially overlaps with the orthographic projection of the cell boundary line A on the display substrate plane. The fifth active layer may serve as the light emission control active layer of the present disclosure, and the fourth connection electrode 54 may serve as the power connection electrode of the present disclosure.

[0130] In an exemplary embodiment, the first power line 61 and the fourth connection electrode 54 may be provided in different conductive layers, the first power line 61 is connected to the fourth connection electrode 54 through the third connection via K3, and the third connection via K3 may be provided in the first circuit unit Q1 and the second circuit unit Q2, respectively.

[0131] In an exemplary embodiment, the eighth transistor T8 shared by the first pixel driving circuit and the second pixel driving circuit may be provided in the first circuit unit Q1 or may be provided in the second circuit unit Q2 .

[0132] In an exemplary embodiment, the eighth transistor T8 may include at least an eighth active layer, a first region of the eighth active layer being connected to the third initial signal line 43, and a second region of the eighth active layer being connected to the second region of the fourth active layer via a fifth connection electrode 55. The orthographic projection of the eighth active layer on the display substrate plane does not overlap with the orthographic projection of the cell boundary line A on the display substrate plane, and the orthographic projection of the fifth connection electrode 55 on the display substrate plane at least partially overlaps with the orthographic projection of the cell boundary line A on the display substrate plane. The eighth active layer may serve as the initialization active layer of the present disclosure, and the fifth connection electrode 55 may serve as the initial connection electrode of the present disclosure.

[0133] In an exemplary embodiment, the eighth active layer can be arranged in the first semiconductor layer, the fifth connection electrode 55 is connected to the second region of the fourth active layer through the fourth connection via K4, and the orthographic projection of the fourth connection via K4 on the display substrate plane at least partially overlaps with the orthographic projection of the unit dividing line A on the display substrate plane.

[0134] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include a plurality of conductive layers sequentially arranged on a base, the first initial signal line 41, the second initial signal line 42, and the third initial signal line 43 may be arranged in the same conductive layer, the first power line 61 and the data signal line 62 may be arranged in the same conductive layer, and the first control signal line 81 and the second control signal line 82 may be arranged in the same conductive layer.

[0135] Figure 6 is a schematic diagram of a pixel driver circuit and signal line connection according to an exemplary embodiment of the present disclosure. As shown in Figure 6, a display substrate includes multiple unit rows and multiple unit columns. In each unit row, first circuit units Q1 and second circuit units Q2 are alternately arranged along a first direction X. Multiple unit rows are arranged sequentially along a second direction Y. Each unit column includes multiple first circuit units Q1 or multiple second circuit units Q2. The first circuit unit Q1 includes a first pixel driver circuit, and the second circuit unit Q2 includes a second pixel driver circuit.

[0136] In an exemplary embodiment, each unit row further includes a first control signal line 81 and a second control signal line 82, the first control signal line 81 in each unit row is connected to multiple first pixel driving circuits in the unit row, and the second control signal line 82 in each unit row is connected to multiple second pixel driving circuits in the unit row.

[0137] In an exemplary embodiment, every two unit columns further include a data signal line 62 , and the data signal line 62 is respectively connected to the plurality of first pixel driving circuits and the plurality of second pixel driving circuits in the two unit columns.

[0138] In an exemplary embodiment, the first control signal line 81 is configured to cause the data signal line 62 to provide a first data signal to the first pixel driving circuit, and the second control signal line 82 is configured to cause the data signal line 62 to provide a second data signal to the second pixel driving circuit.

[0139] In an exemplary embodiment, in one unit row, the first control signal line 81 is connected to the gate electrodes of the second transistors T2 in the first pixel driving circuits, and the second control signal line 82 is connected to the gate electrodes of the second transistors T2 in the second pixel driving circuits.

[0140] The following is an illustrative explanation of the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes the deposition of film layers, coating of photoresist on the film layers, mask exposure, development, etching, stripping of photoresist and other processes for metal materials, inorganic materials or transparent conductive materials, and includes the coating of organic materials, mask exposure and development and other processes for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a thin film made by deposition, coating or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0141] In an exemplary embodiment, taking two circuit units (a first circuit unit Q1 and a second circuit unit Q2 ) as an example, the preparation process of the display substrate of this embodiment may include the following operations.

[0142] (1) Forming a first semiconductor layer pattern. In an exemplary embodiment, forming the first semiconductor layer pattern may include: sequentially depositing a first insulating film and a first semiconductor film on a substrate, patterning the first semiconductor film through a patterning process to form a first insulating layer covering the substrate, and a first semiconductor layer pattern disposed on the first insulating layer, as shown in FIG. 7 .

[0143] In an exemplary embodiment, the first semiconductor layer pattern of each circuit unit may include at least the first active layer 11 of the first transistor T1, the third active layer 13 of the third transistor T3 to the eighth active layer 18 of the eighth transistor T8, and the third active layer 13 to the seventh active layer 17 of each circuit unit are an integrated structure connected to each other, and the first active layer 11 and the eighth active layer 18 are separately provided.

[0144] In an exemplary embodiment, in the first direction X, the first active layer 11, the sixth active layer 16, and the seventh active layer 17 of each circuit unit may be located on a side of the third active layer 13 in the circuit unit away from the unit dividing line A, and the fourth active layer 14 and the fifth active layer 15 may be located between the first circuit unit Q1 and the second circuit unit Q2, and the orthographic projection of the fourth active layer 14 on the substrate at least partially overlaps with the orthographic projection of the unit dividing line A on the substrate, and the orthographic projection of the fifth active layer 15 on the substrate at least partially overlaps with the orthographic projection of the unit dividing line A on the substrate.

[0145] In an exemplary embodiment, in the second direction Y, the first active layer 11 and the fourth active layer 14 of each circuit unit can be located on the side opposite to the second direction Y of the third active layer 13 in the present circuit unit, and the fifth active layer 15, the sixth active layer 16, the seventh active layer 17 and the eighth active layer 18 can be located on the side of the second direction Y of the third active layer 13 in the present circuit unit.

[0146] In an exemplary embodiment, the third active layer 13 of each circuit unit may have an inverted "Ω" shape, the first active layer 11, the fourth active layer 14, the sixth active layer 16, the seventh active layer 17, and the eighth active layer 18 may have an "I" shape, and the fifth active layer 15 may have an "L" shape.

[0147] In an exemplary embodiment, the first active layer 11 and the third active layers 13 to 18 of each circuit unit may each include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, the first region 13-1 of the third active layer may simultaneously serve as the second region 14-2 of the fourth active layer and the second region 15-2 of the fifth active layer, the second region 13-2 of the third active layer may serve as the first region 16-1 of the sixth active layer, and the second region 16-2 of the sixth active layer may serve as the second region 17-2 of the seventh active layer. The first region 11-1 of the first active layer, the second region 11-2 of the first active layer, the first region 14-1 of the fourth active layer, the first region 15-1 of the fifth active layer, the first region 17-1 of the seventh active layer, the first region 18-1 of the eighth active layer, and the second region 18-2 of the eighth active layer may be provided separately.

[0148] In an exemplary embodiment, the first region 14-1 of the fourth active layer, the second region 14-2 of the fourth active layer, and the second region 15-2 of the fifth active layer may be located between the first circuit unit Q1 and the second circuit unit Q2, and the orthographic projections of the first region 14-1 of the fourth active layer, the second region 14-2 of the fourth active layer, and the second region 15-2 of the fifth active layer on the substrate at least partially overlap with the orthographic projection of the cell boundary line A on the substrate. The first region 15-1 of the fifth active layer may be located near the cell boundary line A in the second circuit unit Q2, and the first region 18-1 and the second region 18-2 of the eighth active layer may be located near the cell boundary line A in the first circuit unit Q1.

[0149] In an exemplary embodiment, the fourth active layer 14 can simultaneously serve as the fourth active layer of the first circuit unit and the second circuit unit, the fifth active layer 15 can simultaneously serve as the fifth active layer of the first circuit unit and the second circuit unit, and the eighth active layer 18 can simultaneously serve as the eighth active layer of the first circuit unit and the second circuit unit, that is, the first circuit unit Q1 and the second circuit unit Q2 can share one fourth active layer 14, the first circuit unit Q1 and the second circuit unit Q2 can share one fifth active layer 15, and the first circuit unit Q1 and the second circuit unit Q2 can share one eighth active layer 18.

[0150] In an exemplary embodiment, the first region 13 - 1 of the third active layer in the first circuit unit Q1 and the first region 13 - 1 of the third active layer in the second circuit unit Q2 may be connected to each other.

[0151] In an exemplary embodiment, the third active layer 13 in the first circuit unit Q1 and the third active layer 13 in the second circuit unit may be an integrated structure connected to each other. Since the third active layer 13 to the seventh active layer 17 of each circuit unit are an integrated structure connected to each other, the third active layer 13 to the seventh active layer 17 in the first circuit unit Q1 and the second circuit unit Q2 are an integrated structure connected to each other.

[0152] In an exemplary embodiment, the first semiconductor layer may be made of polycrystalline silicon (p-Si), meaning that the first transistor, the third transistor, the fourth transistor, the fifth transistor, and the eighth transistor are LTPS transistors. In an exemplary embodiment, patterning the first semiconductor film through a patterning process may include: first forming an amorphous silicon (a-Si) film on the first insulating film, performing a dehydrogenation treatment on the amorphous silicon film, and then crystallizing the dehydrogenated amorphous silicon film to form a polycrystalline silicon film. Subsequently, patterning the polycrystalline silicon film to form a first semiconductor layer pattern.

[0153] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on the substrate having the aforementioned pattern formed thereon, patterning the first conductive film through a patterning process to form a second insulating layer covering the first semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, as shown in FIG8A and FIG8B , where FIG8B is a plan view schematic diagram of the first conductive layer in FIG8A . In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0154] In an exemplary embodiment, the first conductive layer pattern of each circuit unit includes at least a first scan signal line 21 , a second scan signal line 22 , a third scan signal line 23 , a light emitting signal line 24 and a first plate 71 of a storage capacitor.

[0155] In an exemplary embodiment, the first electrode plate 71 in each circuit unit may be rectangular, with chamfered corners. The orthographic projection of the first electrode plate 71 on the substrate at least partially overlaps the orthographic projection of the third active layer of the third transistor T3 on the substrate. In an exemplary embodiment, the first electrode plate 71 may serve as both a plate of the storage capacitor and a gate electrode of the third transistor T3.

[0156] In an exemplary embodiment, the shape of the first scanning signal line 21 can be a zigzag shape with the main portion extending along the first direction X. The first scanning signal line 21 can be located on the side of the first electrode 71 in the opposite direction of the second direction Y. The area where the first scanning signal line 21 overlaps with the fourth active layer can serve as the gate electrode of the fourth transistor T4.

[0157] In an exemplary embodiment, the shape of the second scan signal line 22 can be a straight line or a broken line with the main portion extending along the first direction X. The second scan signal line 22 can be located on one side of the first electrode 71 in the second direction Y. The area where the second scan signal line 22 overlaps with the seventh active layer in each circuit unit can serve as the gate electrode of the seventh transistor T7, and the area where the second scan signal line 22 overlaps with the eighth active layer can serve as the gate electrode of the eighth transistor T8.

[0158] In an exemplary embodiment, the shape of the third scan signal line 23 can be a straight line or a broken line with the main portion extending along the first direction X. The third scan signal line 23 can be located on a side of the first scan signal line 21 away from the first electrode plate 71. The area where the third scan signal line 23 overlaps with the first active layer in each circuit unit can serve as the gate electrode of the first transistor T1.

[0159] In an exemplary embodiment, the shape of the light-emitting signal line 24 can be a straight line or a broken line with the main portion extending along the first direction X. The light-emitting signal line 24 can be located between the second scanning signal line 22 and the first electrode 71. The area where the light-emitting signal line 24 overlaps with the fifth active layer can serve as the gate electrode of the fifth transistor T5, and the area where the light-emitting signal line 24 overlaps with the sixth active layer in each circuit unit can serve as the gate electrode of the sixth transistor T6.

[0160] In an exemplary embodiment, the first scan signal line 21, the second scan signal line 22, the third scan signal line 23 and the light-emitting signal line 24 may include an overlapping area with the first semiconductor layer and an area not overlapping with the first semiconductor layer. The width of at least one signal line in the area overlapping with the first semiconductor layer may be greater than the width of at least one signal line in the area not overlapping with the first semiconductor layer, and the width is the dimension in the second direction Y.

[0161] In an exemplary embodiment, after forming the first conductive layer pattern, the first conductive layer can be used as a shield to perform conductorization on the first semiconductor layer. The first semiconductor layer in the area shielded by the first conductive layer forms the channel region of the first transistor T1 and the third transistor T3 to the eighth transistor T8, and the first semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first area and the second area of ​​the first transistor T1 and the third transistor T3 to the eighth transistor T8 are all conductorized.

[0162] (3) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on the substrate having the aforementioned pattern formed thereon, patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer, as shown in FIG9A and FIG9B , where FIG9B is a plan view schematic diagram of the second conductive layer in FIG9A . In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0163] In an exemplary embodiment, the second conductive layer pattern of each circuit unit includes at least a first shielding line 31 , a second shielding line 32 , and a second plate 72 of the storage capacitor.

[0164] In an exemplary embodiment, the first shielding line 31 and the second shielding line 32 may be in the shape of a straight line or a broken line, with the main portion extending along the first direction X. The first shielding line 31 and the second shielding line 32 may be located between the first scan signal line 21 and the third scan signal line 23. Specifically, the first shielding line 31 may be located on a side of the second shielding line 32 closer to the first scan signal line 21, and the second shielding line 32 may be located on a side of the first shielding line 31 closer to the third scan signal line 23.

[0165] In an exemplary embodiment, in the first circuit unit Q1, a first shielding block 31-1 is provided on a side of the first shielding line 31 away from the first scan signal line 21. The first shielding block 31-1 may be in a block shape (e.g., a rectangle), with a first end of the first shielding block 31-1 connected to the first shielding line 31 and a second end of the first shielding block 31-1 extending in a direction away from the first scan signal line 21. The first shielding block 31-1 is configured to serve as a shielding layer for the second transistor T2 in the first circuit unit Q1, shielding the channel region of the second transistor T2 to ensure the electrical performance of the oxide second transistor T2. The first shielding block 31-1 is also configured to serve as the bottom gate electrode of the second transistor T2 in the first circuit unit Q1.

[0166] In an exemplary embodiment, the first shielding line 31 and the first shielding block 31 - 1 may be an integral structure connected to each other.

[0167] In an exemplary embodiment, in the second circuit unit Q2, a second shielding block 32-1 is provided on a side of the second shielding line 32 close to the first scan signal line 21. The second shielding block 32-1 may be in a block shape (e.g., a rectangle), with a first end of the second shielding block 32-1 connected to the second shielding line 32, and a second end of the second shielding block 32-1 extending in a direction close to the first scan signal line 21. The second shielding block 32-1 is configured to serve as a shielding layer for the second transistor T2 in the second circuit unit Q2, shielding the channel region of the second transistor T2 to ensure the electrical performance of the oxide second transistor T2, and is also configured to serve as the bottom gate electrode of the second transistor T2 in the second circuit unit Q2.

[0168] In an exemplary embodiment, the second shielding line 32 and the second shielding block 32 - 1 may be an integral structure connected to each other.

[0169] In an exemplary embodiment, the outline of the second electrode plate 72 can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the second electrode plate 72 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 71 on the substrate. The second electrode plate 72 can serve as another electrode plate of the storage capacitor, and the first electrode plate 71 and the second electrode plate 72 constitute the storage capacitor of the pixel driving circuit.

[0170] In an exemplary embodiment, an opening 73 is provided on the second electrode plate 72. Opening 73 can be rectangular and located in the central region of the second electrode plate 72, forming an annular structure. Opening 73 exposes the third insulating layer covering the first electrode plate 71, and the orthographic projection of the first electrode plate 71 on the substrate includes the orthographic projection of the opening 73 on the substrate. In an exemplary embodiment, opening 73 is configured to accommodate a thirteenth via hole to be formed later. The thirteenth via hole is located within opening 73 and exposes the first electrode plate 71, allowing a first connecting electrode to be formed later to connect to the first electrode plate 71.

[0171] In an exemplary embodiment, the second conductive layer of each circuit unit may further include a plate connecting bar 74. The plate connecting bar 74 may be in the shape of a bar extending along the first direction X. The plate connecting bar 74 may be disposed on one side of the second plate 72 in the first direction X or on a side opposite to the first direction X. The first end of the plate connecting bar 74 is connected to the second plate 72 in the circuit unit in question, and the second end of the plate connecting bar 74 is connected to the second plate 72 in the adjacent circuit unit in the first direction X. This allows the second plates 72 in adjacent circuit units in a row of units to form an interconnected, integrated structure. Because the second plate 72 in each circuit unit is connected to a subsequently formed first power line, by forming the second plates 72 of adjacent circuit units into an interconnected, integrated structure, the second plates of the integrated structure can be reused as power signal lines. This ensures that multiple second plates in a row of units have the same potential, which helps improve panel uniformity, prevent display defects on the display substrate, and ensure the display quality of the display substrate.

[0172] (4) Forming a second semiconductor layer pattern. In an exemplary embodiment, forming the second semiconductor layer pattern may include: sequentially depositing a fourth insulating film and a second semiconductor film on the substrate having the aforementioned pattern formed thereon, patterning the second semiconductor film through a patterning process to form a fourth insulating layer covering the substrate, and a second semiconductor layer pattern disposed on the fourth insulating layer, as shown in FIG10A and FIG10B , where FIG10B is a plan view schematic diagram of the second semiconductor layer in FIG10A .

[0173] In an exemplary embodiment, the second semiconductor layer pattern of each circuit unit includes at least a second active layer 12 of a second transistor T2 .

[0174] In an exemplary embodiment, the second active layer 12 may be shaped like a strip extending along the first direction X, and may be located between the first shielding line 31 and the second shielding line 32. The orthographic projection of the second active layer 12 in the first circuit unit Q1 on the substrate at least partially overlaps with the orthographic projection of the first shielding block 31-1 on the substrate, and the orthographic projection of the second active layer 12 in the second circuit unit Q2 on the substrate at least partially overlaps with the orthographic projection of the second shielding block 32-1 on the substrate.

[0175] In an exemplary embodiment, the second active layer 12 of each circuit unit may include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, in the first circuit unit Q1, the first region 12-1 of the second active layer may be located on a side of the first blocking block 31-1 close to the fourth active layer, and the second region 12-2 of the second active layer may be located on a side of the first blocking block 31-1 away from the fourth active layer. In an exemplary embodiment, in the second circuit unit Q2, the first region 12-1 of the second active layer may be located on a side of the second blocking block 32-1 close to the fourth active layer, and the second region 12-2 of the second active layer may be located on a side of the second blocking block 32-1 away from the fourth active layer.

[0176] In an exemplary embodiment, the second semiconductor layer may be made of oxide, that is, the eighth transistor T8 is an oxide transistor. In an exemplary embodiment, the second semiconductor thin film may be made of indium gallium zinc oxide (IGZO), which has higher electron mobility than amorphous silicon.

[0177] (5) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern may include: sequentially depositing a fifth insulating film and a third conductive film on the substrate having the aforementioned pattern formed thereon, patterning the third conductive film using a patterning process to form a fifth insulating layer covering the second semiconductor layer, and a third conductive layer pattern disposed on the fifth insulating layer, as shown in FIG11A and FIG11B , where FIG11B is a plan view schematic diagram of the third conductive layer in FIG11A . In an exemplary embodiment, the second conductive layer may be referred to as a third gate metal (GATE3) layer.

[0178] In an exemplary embodiment, the third conductive layer pattern of each circuit unit includes at least a first preliminary signal line 41 , a second preliminary signal line 42 , a third preliminary signal line 43 , a first control signal line 81 , and a second control signal line 82 .

[0179] In an exemplary embodiment, the shape of the first initial signal line 41 can be a straight line or a broken line with the main part extending along the first direction X. The first initial signal line 41 can be located on the side of the second shielding line 32 away from the second electrode plate 72. A first initial connection block 41-1 is provided on the side of the first initial signal line 41 of each circuit unit away from the second electrode plate 72. The first end of the first initial connection block 41-1 is connected to the first initial signal line 41, and the second end of the first initial connection block 41-1 extends in a direction away from the second electrode plate 72. The first initial connection block 41-1 is configured to be connected to the first region of the first active layer through a seventh connection electrode formed subsequently.

[0180] In an exemplary embodiment, the orthographic projection of the first initial signal line 41 on the substrate at least partially overlaps with the orthographic projection of the third scanning signal line 23 on the substrate, and the first initial signal line 41 with a constant voltage can act as a shield to reduce the influence of the third scanning signal line 23 on the pixel driving circuit.

[0181] In an exemplary embodiment, the shape of the second initial signal line 42 can be a straight line or a broken line with the main part extending along the first direction X. The second initial signal line 42 can be located on the side of the second scanning signal line 22 away from the second electrode plate 72. A second initial connection block 42-1 is provided on the side of the second initial signal line 42 of each circuit unit close to the second electrode plate 72. The first end of the second initial connection block 42-1 is connected to the second initial signal line 42, and the second end of the second initial connection block 42-1 extends in a direction close to the second electrode plate 72. The second initial connection block 42-1 is configured to be connected to the first area of ​​the seventh active layer through the subsequently formed eighth connection electrode.

[0182] In an exemplary embodiment, the shape of the third initial signal line 43 can be a straight line or a broken line with the main portion extending along the first direction X. The third initial signal line 43 can be located between the light-emitting signal line 24 and the second initial signal line 42. A third initial connection block 43-1 is provided on the side of the third initial signal line 43 of the first circuit unit Q1 away from the second electrode plate 72. The first end of the third initial connection block 43-1 is connected to the third initial signal line 43, and the second end of the third initial connection block 43-1 extends in a direction away from the second electrode plate 72. The third initial connection block 43-1 is configured to be connected to the first region of the eighth active layer through a ninth connection electrode formed subsequently.

[0183] In an exemplary embodiment, the orthographic projection of the third initial signal line 43 on the substrate at least partially overlaps with the orthographic projection of the second scanning signal line 22 on the substrate. The third initial signal line 43 with a constant voltage can play a shielding role, reducing the impact of the second scanning signal line 22 on the pixel driving circuit.

[0184] In an exemplary embodiment, the first control signal line 81 and the second control signal line 82 may be in the shape of a straight line or a zigzag line, with the main portion extending along the first direction X. The first control signal line 81 and the second control signal line 82 may be located between the first scan signal line 21 and the third scan signal line 23. Specifically, the first control signal line 81 may be located on a side of the second control signal line 82 closer to the first scan signal line 21, and the second control signal line 82 may be located on a side of the first control signal line 81 closer to the third scan signal line 23.

[0185] In an exemplary embodiment, in the first circuit unit Q1, a first gate block 81-1 is provided on a side of the first control signal line 81 away from the first scan signal line 21. The first gate block 81-1 may be in a block shape (e.g., a rectangular shape), with a first end of the first gate block 81-1 connected to the first control signal line 81, and a second end of the first gate block 81-1 extending in a direction away from the first scan signal line 21. The region where the first gate block 81-1 overlaps with the second active layer in the first circuit unit Q1 may serve as the gate electrode of the second transistor T2.

[0186] In an exemplary embodiment, the first control signal line 81 and the first gate block 81 - 1 may be an integral structure connected to each other.

[0187] In an exemplary embodiment, the orthographic projection of the first control signal line 81 on the substrate at least partially overlaps with the orthographic projection of the first shielding line 31 on the substrate, and the orthographic projection of the first gate block 81-1 on the substrate at least partially overlaps with the orthographic projection of the first shielding block 31-1 on the substrate. The first control signal line 81 and the first shielding line 31 can be connected to the same signal source, so that the first shielding block 31-1 of the first shielding line 31 serves as the bottom gate electrode of the second transistor T2, and the first gate block 81-1 of the first control signal line 81 can serve as the top gate electrode of the second transistor T2, forming the second transistor T2 with a top-gate and bottom-gate structure in the first circuit unit Q1.

[0188] In an exemplary embodiment, in the second circuit unit Q2, a second gate block 82-1 is provided on a side of the second control signal line 82 close to the first scan signal line 21. The second gate block 82-1 may be in a block shape (e.g., a rectangular shape), with a first end of the second gate block 82-1 connected to the second control signal line 82, and a second end of the second gate block 82-1 extending in a direction close to the first scan signal line 21. The region where the second gate block 82-1 overlaps with the second active layer in the second circuit unit Q2 may serve as the gate electrode of the second transistor T2.

[0189] In an exemplary embodiment, the second control signal line 82 and the second gate block 82 - 1 may be an integral structure connected to each other.

[0190] In an exemplary embodiment, the orthographic projection of the second control signal line 82 on the substrate at least partially overlaps with the orthographic projection of the second shielding line 32 on the substrate, and the orthographic projection of the second gate block 82-1 on the substrate at least partially overlaps with the orthographic projection of the second shielding block 32-1 on the substrate. The second control signal line 82 and the second shielding line 32 can be connected to the same signal source, so that the second shielding block 32-1 of the second shielding line 32 serves as the bottom gate electrode of the second transistor T2, and the second gate block 82-1 of the second control signal line 82 can serve as the top gate electrode of the second transistor T2, forming the second transistor T2 with a top gate and bottom gate structure in the second circuit unit Q2.

[0191] In example embodiments, the first region of the fourth active layer (the first electrode of the fourth transistor T4 ) may be located between the first control signal line 81 and the second control signal line 82 .

[0192] (6) Forming a sixth insulating layer pattern. In an exemplary embodiment, forming the sixth insulating layer pattern may include: depositing a sixth insulating film on the substrate having the aforementioned pattern formed thereon, patterning the fifth insulating film using a patterning process to form a sixth insulating layer covering the third conductive layer, wherein the sixth insulating layer is provided with a plurality of vias, as shown in FIG. 12 .

[0193] In an exemplary embodiment, the plurality of vias include at least a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16, and a seventeenth via V17.

[0194] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the first region of the first active layer on the substrate. The sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer within the first via hole V1 are etched away, exposing the surface of the first region of the first active layer. The first via hole V1 is configured to connect a subsequently formed seventh connection electrode to the first region of the first active layer through the via hole. In an exemplary embodiment, the first via hole V1 can be provided in each circuit unit.

[0195] In an exemplary embodiment, the orthographic projection of the second via hole V2 on the substrate is located within the orthographic projection of the second region of the first active layer on the substrate. The sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer within the second via hole V2 are etched away, exposing the surface of the second region of the first active layer. The second via hole V2 is configured to connect a subsequently formed second connection electrode to the second region of the first active layer through the via hole. In an exemplary embodiment, the second via hole V2 can be provided in each circuit unit.

[0196] In an exemplary embodiment, the orthographic projection of the third via hole V3 on the substrate is located within the orthographic projection of the first region of the second active layer on the substrate. The sixth insulating layer and the fifth insulating layer within the third via hole V3 are etched away, exposing the surface of the first region of the second active layer. The third via hole V3 is configured to connect a subsequently formed first connection electrode to the first region of the second active layer through the via hole. In an exemplary embodiment, the third via hole V3 may be provided in each circuit unit.

[0197] In an exemplary embodiment, the orthographic projection of the fourth via hole V4 on the substrate is located within the orthographic projection of the second region of the second active layer on the substrate. The sixth insulating layer and the fifth insulating layer within the fourth via hole V4 are etched away, exposing the surface of the second region of the second active layer. The fourth via hole V4 is configured to connect a subsequently formed second connection electrode to the second region of the second active layer through the via hole. In an exemplary embodiment, the fourth via hole V4 may be provided in each circuit unit.

[0198] In an exemplary embodiment, the orthographic projection of the fifth via V5 on the substrate is located within the range of the orthographic projection of the second region of the third active layer (also the first region of the sixth active layer) on the substrate. The sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer within the fifth via V5 are etched away, exposing the surface of the second region of the third active layer (also the first region of the sixth active layer). The fifth via V5 is configured to connect a subsequently formed second connection electrode to the second region of the third active layer (also the first region of the sixth active layer) through the via. In an exemplary embodiment, the fifth via V5 can be provided in each circuit unit.

[0199] In an exemplary embodiment, the orthographic projection of the sixth via hole V6 on the substrate is located within the range of the orthographic projection of the first area of ​​the fourth active layer on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the sixth via hole V6 are etched away to expose the surface of the first area of ​​the fourth active layer. The sixth via hole V6 is configured to connect a subsequently formed third connecting electrode to the first area of ​​the fourth active layer through the via hole.

[0200] In an exemplary embodiment, since the first circuit unit Q1 and the second circuit unit Q2 share the fourth active layer, the first circuit unit Q1 and the second circuit unit Q2 share the sixth via V6, and the orthographic projection of the sixth via V6 on the substrate at least partially overlaps with the orthographic projection of the unit dividing line A on the substrate. The sixth via V6 can serve as the second connecting via of the present disclosure.

[0201] In an exemplary embodiment, the orthographic projection of the seventh via hole V7 on the substrate is located within the range of the orthographic projection of the first area of ​​the fifth active layer on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the seventh via hole V7 are etched away to expose the surface of the first area of ​​the fifth active layer, and the seventh via hole V7 is configured to connect a subsequently formed fourth connecting electrode to the first area of ​​the fifth active layer through the via hole.

[0202] In an exemplary embodiment, the orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projection of the second area of ​​the fifth active layer (also the first area of ​​the third active layer and the second area of ​​the fourth active layer) on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the eighth via V8 are etched away to expose the surface of the second area of ​​the fifth active layer, and the eighth via V8 is configured to connect the subsequently formed fifth connecting electrode to the second area of ​​the fifth active layer (also the first area of ​​the third active layer and the second area of ​​the fourth active layer) through the via hole.

[0203] In an exemplary embodiment, since the first circuit unit Q1 and the second circuit unit Q2 share the fifth active layer, the first circuit unit Q1 and the second circuit unit Q2 share the seventh via V7 and the eighth via V8, the seventh via V7 can be set in the second circuit unit Q2, and the orthographic projection of the eighth via V8 on the substrate at least partially overlaps with the orthographic projection of the unit dividing line A on the substrate, and the eighth via V8 can serve as the fourth connecting via of the present disclosure.

[0204] In an exemplary embodiment, the orthographic projection of the ninth via V9 on the substrate is located within the range of the orthographic projection of the second region of the sixth active layer (also the second region of the seventh active layer) on the substrate. The sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer within the ninth via V9 are etched away, exposing the surface of the second region of the sixth active layer (also the second region of the seventh active layer). The ninth via V9 is configured to connect a subsequently formed sixth connection electrode to the second region of the sixth active layer (also the second region of the seventh active layer) through the via. In an exemplary embodiment, the ninth via V9 can be provided in each circuit unit.

[0205] In an exemplary embodiment, the orthographic projection of the tenth via hole V10 on the substrate is located within the range of the orthographic projection of the first region of the seventh active layer on the substrate. The sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer within the tenth via hole V10 are etched away, exposing the surface of the first region of the seventh active layer. The tenth via hole V10 is configured to connect a subsequently formed eighth connection electrode to the first region of the seventh active layer through the via hole. In an exemplary embodiment, the tenth via hole V10 can be provided in each circuit unit.

[0206] In an exemplary embodiment, the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the first region of the eighth active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the eleventh via hole V11 are etched away to expose the surface of the first region of the eighth active layer, and the eleventh via hole V11 is configured to connect a subsequently formed ninth connecting electrode to the first region of the eighth active layer through the via hole.

[0207] In an exemplary embodiment, the orthographic projection of the twelfth via hole V12 on the substrate is located within the range of the orthographic projection of the second region of the eighth active layer on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the twelfth via hole V12 are etched away to expose the surface of the second region of the eighth active layer. The twelfth via hole V12 is configured to connect the subsequently formed fifth connecting electrode to the second region of the eighth active layer through the via hole.

[0208] In an exemplary embodiment, since the first circuit unit Q1 and the second circuit unit Q2 share the eighth active layer, the first circuit unit Q1 and the second circuit unit Q2 share the eleventh via V11 and the twelfth via V12, and the eleventh via V11 and the twelfth via V12 may be provided in the first circuit unit Q1.

[0209] In an exemplary embodiment, the orthographic projection of the thirteenth via hole V13 on the substrate is within the range of the orthographic projection of the opening 73 on the substrate. The sixth insulating layer, the fifth insulating layer, the fourth insulating layer, and the third insulating layer within the thirteenth via hole V13 are etched away, exposing the surface of the first electrode plate 71. The thirteenth via hole V13 is configured to connect a subsequently formed first connection electrode to the first electrode plate 71 through the via hole. In an exemplary embodiment, the thirteenth via hole V13 can be provided in each circuit unit.

[0210] In an exemplary embodiment, the orthographic projection of the fourteenth via hole V14 on the substrate is located within the range of the orthographic projection of the plate connecting bar 74 of the second plate 72 on the substrate, the sixth insulating layer, the fifth insulating layer and the fourth insulating layer in the fourteenth via hole V14 are etched away to expose the surface of the plate connecting bar 74, and the fourteenth via hole V14 is configured to connect the subsequently formed fourth connecting electrode to the plate connecting bar 74 through the via hole.

[0211] In an exemplary embodiment, the fourteenth via V14 may be located on the unit boundary line A, an orthographic projection of the fourteenth via V14 on the substrate at least partially overlaps with an orthographic projection of the unit boundary line A on the substrate, and the first circuit unit Q1 and the second circuit unit Q2 share one fourteenth via V14.

[0212] In an exemplary embodiment, the orthographic projection of the fifteenth via hole V15 on the substrate is located within the range of the orthographic projection of the first preliminary connection block 41-1 of the first preliminary signal line 41 on the substrate. The sixth insulating layer within the fifteenth via hole V15 is etched away, exposing the surface of the first preliminary connection block 41-1. The fifteenth via hole V15 is configured to connect a subsequently formed seventh connection electrode to the first preliminary connection block 41-1 through the via hole. In an exemplary embodiment, the fifteenth via hole V15 can be provided in each circuit unit.

[0213] In an exemplary embodiment, the orthographic projection of the sixteenth via hole V16 on the substrate is located within the range of the orthographic projection of the second initial connection block 42-1 of the second initial signal line 42 on the substrate. The sixth insulating layer within the sixteenth via hole V16 is etched away, exposing the surface of the second initial connection block 42-1. The sixteenth via hole V16 is configured to connect the subsequently formed eighth connection electrode to the second initial connection block 42-1 through the via hole. In an exemplary embodiment, the sixteenth via hole V16 can be provided in each circuit unit.

[0214] In an exemplary embodiment, the orthographic projection of the seventeenth via V17 on the substrate is located within the range of the orthographic projection of the third initial connection block 43-1 of the third initial signal line 43 on the substrate, the sixth insulating layer in the seventeenth via V17 is etched away, exposing the surface of the third initial connection block 43-1, and the seventeenth via V17 is configured to connect the subsequently formed ninth connection electrode to the third initial connection block 43-1 through the via.

[0215] In an exemplary embodiment, since the first and second circuit units Q1 and Q2 share the eighth active layer, the first and second circuit units Q1 and Q2 share the seventeenth via hole V17 , and the seventeenth via hole V17 may be provided in the first circuit unit Q1 .

[0216] (7) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on the sixth insulating layer, as shown in FIG13A and FIG13B , where FIG13B is a plan view schematic diagram of the fourth conductive layer in FIG13A . In an exemplary embodiment, the fourth conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0217] In an exemplary embodiment, the fourth conductive layer may include at least a first connection electrode 51 , a second connection electrode 52 , a third connection electrode 53 , a fourth connection electrode 54 , a fifth connection electrode 55 , a sixth connection electrode 56 , a seventh connection electrode 57 , an eighth connection electrode 58 and a ninth connection electrode 59 .

[0218] In an exemplary embodiment, the first connection electrode 51 may be shaped like a zigzag line with a main portion extending along the second direction Y. A first end of the first connection electrode 51 is connected to the first region of the second active layer through a third via hole V3. A second end of the first connection electrode 51 extends along the second direction Y and is connected to the first electrode plate 71 through a thirteenth via hole V13. In an exemplary embodiment, the first connection electrode 51 may be provided in each circuit unit.

[0219] In an exemplary embodiment, since the first electrode 71 also serves as the gate electrode of the third transistor T3, the first connecting electrode 51 enables the first electrode of the second transistor T2, the gate electrode of the third transistor T3 and the first electrode 71 to have the same potential, forming the first node N1 of the pixel driving circuit.

[0220] In an exemplary embodiment, the second connection electrode 52 may be in an "L" shape. A first end of the second connection electrode 52 is connected to the second region of the first active layer via a second via hole V2. A second end of the second connection electrode 52 is connected to the second region of the third active layer (also the first region of the sixth active layer) via a fifth via hole V5. The area between the first and second ends of the second connection electrode 52 is connected to the second region of the second active layer via a fourth via hole V4. In an exemplary embodiment, the second connection electrode 52 may be provided in each circuit unit.

[0221] In an exemplary embodiment, the second connection electrode 52 allows the second electrodes of the first transistor T1 , the second transistor T2 , the third transistor T3 , and the first electrode of the sixth transistor T6 to have the same potential, forming a third node N3 of the pixel driving circuit.

[0222] In an exemplary embodiment, the third connection electrode 53 may be in a block shape (e.g., a rectangular shape) and is connected to the first region of the fourth active layer through a sixth via hole V6. In an exemplary embodiment, the third connection electrode 53 may serve as a first electrode of the fourth transistor T4 and is configured to be connected to a subsequently formed data signal line.

[0223] In an exemplary embodiment, since the first circuit unit Q1 and the second circuit unit Q2 share the sixth via V6, the first circuit unit Q1 and the second circuit unit Q2 share the third connection electrode 53, and the orthographic projection of the third connection electrode 53 on the substrate at least partially overlaps with the orthographic projection of the unit dividing line A on the substrate. The third connection electrode 53 can serve as the data connection electrode of the present disclosure.

[0224] In an exemplary embodiment, the fourth connection electrode 54 may include a first sub-electrode 54-1 and a second sub-electrode 54-2. The first sub-electrode 54-1 may be in the shape of a strip, with its main portion extending along the second direction Y. The first end of the first sub-electrode 54-1 is connected to the first region of the fifth active layer via a seventh via hole V7. The second end of the fourth connection electrode 54 extends toward the second electrode plate 72 and is connected to the second sub-electrode 54-2. The second sub-electrode 54-2 may be in a "U" shape, with its central portion in the first direction X connected to a plate connection bar 74 via a fourteenth via hole V14. Since the plate connection bar 74 is connected to the second electrode plates 72 in the first circuit unit Q1 and the second circuit unit Q2, respectively, the first electrode of the fifth transistor T5 and the second electrode plate 72 of the storage capacitor in each circuit unit are at the same potential.

[0225] In an exemplary embodiment, the first sub-electrode 54 - 1 and the second sub-electrode 54 - 2 may be an integral structure connected to each other.

[0226] In an exemplary embodiment, since the first circuit unit Q1 and the second circuit unit Q2 share the seventh via V7 and the fourteenth via V14, the first circuit unit Q1 and the second circuit unit Q2 share the fourth connection electrode 54. The fourth connection electrode 54 can serve as the power connection electrode of the present disclosure. The orthographic projection of the fourth connection electrode 54 on the substrate at least partially overlaps with the orthographic projection of the cell boundary line A on the substrate. In an exemplary embodiment, the first sub-electrode 54-1 can be disposed in the second circuit unit Q2, and the orthographic projection of the second sub-electrode 54-2 on the substrate at least partially overlaps with the orthographic projection of the cell boundary line A on the substrate. The two ends of the second sub-electrode 54-2 in the first direction X are respectively disposed in the first circuit unit Q1 and the second circuit unit Q2.

[0227] In an exemplary embodiment, the fifth connection electrode 55 may be shaped like a zigzag line. A first end of the fifth connection electrode 55 is connected to the second region of the fifth active layer via an eighth via hole V8, and a second end of the fifth connection electrode 55 is connected to the second region of the eighth active layer via a twelfth via hole V12. In an exemplary embodiment, because the second region of the fifth active layer serves as both the first region of the third active layer and the second region of the fourth active layer, the fifth connection electrode 55 causes the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8 to have the same potential, forming a second node N2 of the pixel driving circuit.

[0228] In an exemplary embodiment, since the first circuit unit Q1 and the second circuit unit Q2 share the eighth via V8 and the twelfth via V12, the first circuit unit Q1 and the second circuit unit Q2 share the fifth connection electrode 55. The fifth connection electrode 55 can be set in the first circuit unit Q1. The fifth connection electrode 55 can serve as the initial connection electrode of the present disclosure, and the orthographic projection of the fifth connection electrode 55 on the substrate at least partially overlaps with the orthographic projection of the unit dividing line A on the substrate.

[0229] In an exemplary embodiment, the sixth connection electrode 56 may be in a block shape (e.g., a rectangle) and is connected to the second region of the sixth active layer (also the second region of the seventh active layer) via a ninth via hole V9. In an exemplary embodiment, the sixth connection electrode 56 may simultaneously serve as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7. The sixth connection electrode 56 is configured to be connected to a subsequently formed anode connection electrode. In an exemplary embodiment, the sixth connection electrode 56 may be provided in each circuit unit.

[0230] In an exemplary embodiment, the seventh connection electrode 57 may be in a block shape (e.g., a rectangle). A first end of the seventh connection electrode 57 is connected to the first region of the first active layer via a first via hole V1, and a second end of the seventh connection electrode 57 is connected to the first initial connection block 41-1 via a fifteenth via hole V15. In an exemplary embodiment, the seventh connection electrode 57 may serve as the first electrode of the first transistor T1. Because the first initial connection block 41-1 is connected to the first initial signal line 41, the seventh connection electrode 57 allows the first initial signal transmitted by the first initial signal line 41 to be written to the first electrode of the first transistor T1. In an exemplary embodiment, the seventh connection electrode 57 may be provided in each circuit unit.

[0231] In an exemplary embodiment, the eighth connection electrode 58 may be in a block shape (e.g., a rectangle). A first end of the eighth connection electrode 58 is connected to the first region of the seventh active layer via a tenth via hole V10, and a second end of the eighth connection electrode 58 is connected to the second initial connection block 42-1 via a sixteenth via hole V16. In an exemplary embodiment, the eighth connection electrode 58 may serve as the first electrode of the seventh transistor T7. Since the second initial connection block 42-1 is connected to the second initial signal line 42, the eighth connection electrode 58 writes the second initial signal transmitted by the second initial signal line 42 to the first electrode of the seventh transistor T7. In an exemplary embodiment, the eighth connection electrode 58 may be provided in each circuit unit.

[0232] In an exemplary embodiment, the ninth connection electrode 59 may be L-shaped. A first end of the ninth connection electrode 59 is connected to the first region of the eighth active layer via an eleventh via hole V11, and a second end of the ninth connection electrode 59 is connected to the third initial connection block 43-1 via a seventeenth via hole V17. The ninth connection electrode 59 may serve as the first electrode of the eighth transistor T8. Because the third initial connection block 43-1 is connected to the third initial signal line 43, the ninth connection electrode 59 writes the third initial signal transmitted by the third initial signal line 43 into the first electrode of the eighth transistor T8. In an exemplary embodiment, the ninth connection electrode 59 may be provided in each circuit unit.

[0233] (8) Forming a first planar layer pattern. In an exemplary embodiment, forming the first planar layer pattern may include: coating a first planar film on the substrate on which the aforementioned pattern is formed, patterning the first planar film using a patterning process to form a first planar layer covering the fourth conductive layer pattern, wherein a plurality of vias are provided on the first planar layer, as shown in FIG. 14 .

[0234] In an exemplary embodiment, the plurality of via holes include at least a twenty-first via hole V21 , a twenty-second via hole V22 , and a twenty-third via hole V23 .

[0235] In an exemplary embodiment, the orthographic projection of the twenty-first via hole V21 on the substrate is within the range of the orthographic projection of the third connection electrode 53 on the substrate. The first planar layer within the twenty-first via hole V21 is etched away, exposing the surface of the third connection electrode 53. The twenty-first via hole V21 is configured to allow a subsequently formed data signal line to be connected to the third connection electrode 53 through the via hole. In an exemplary embodiment, since the first circuit unit Q1 and the second circuit unit Q2 share the third connection electrode 53, the first circuit unit Q1 and the second circuit unit Q2 share the twenty-first via hole V21. The twenty-first via hole V21 can serve as the first connection via hole of the present disclosure. The orthographic projection of the twenty-first via hole V21 on the substrate at least partially overlaps with the orthographic projection of the unit boundary line A on the substrate.

[0236] In an exemplary embodiment, the orthographic projection of the twenty-second via V22 on the substrate is located within the orthographic projection of the second sub-electrode 54-2 in the fourth connecting electrode 54. The first planar layer within the twenty-second via V22 is etched away, exposing the surface of the second sub-electrode 54-2. The twenty-second via V22 is configured to connect a subsequently formed first power line to the second sub-electrode 54-2 through the via. In an exemplary embodiment, although the first circuit unit Q1 and the second circuit unit Q2 share the fourth connecting electrode 54, the twenty-second via V22 can be provided in each circuit unit. One twenty-second via V22 can be provided at the end of the second sub-electrode 54-2 in the opposite direction of the first direction X in the first circuit unit Q1, and the other twenty-second via V22 can be provided at the end of the second sub-electrode 54-2 in the first direction X in the second circuit unit Q2. The twenty-second via V22 can serve as the third connecting via of the present disclosure, and its orthographic projection on the substrate does not overlap with the orthographic projection of the unit boundary line A on the substrate.

[0237] In an exemplary embodiment, the orthographic projection of the twenty-third via hole V23 on the substrate is located within the range of the orthographic projection of the sixth connection electrode 56 on the substrate. The first flat layer within the twenty-third via hole V23 is etched away, exposing the surface of the sixth connection electrode 56. The twenty-third via hole V23 is configured to connect a subsequently formed anode connection electrode to the sixth connection electrode 56 through the via hole. In an exemplary embodiment, the twenty-third via hole V23 may be provided in each circuit unit.

[0238] (9) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer may include: depositing a fifth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fifth conductive film using a patterning process to form a fifth conductive layer disposed on the first planar layer, as shown in FIG15A and FIG15B , where FIG15B is a planar schematic diagram of the fifth conductive layer in FIG15A . In an exemplary embodiment, the fifth conductive layer may be referred to as a second source / drain metal (SD2) layer.

[0239] In an exemplary embodiment, the fifth conductive layer includes at least a first power supply line 61 , a data signal line 62 , and an anode connection electrode 63 .

[0240] In an exemplary embodiment, the first power line 61 may be in the shape of a straight line or a zigzag line, with its main portion extending along the second direction Y. The first power line 61 is connected to the fourth connection electrode 54 via the twenty-second via hole V22. Because the fourth connection electrode 54 is respectively connected to the first region of the fifth active layer and the second plate 72 of the storage capacitor, the first power line 61 writes the first power signal to the fifth transistor T5 and the second plate 72 of the storage capacitor. In an exemplary embodiment, the first power line 61 may be provided in each circuit unit.

[0241] In an exemplary embodiment, the first power line 61 may be a zigzag line with unequal width, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the first power line and the data signal line.

[0242] In an exemplary embodiment, a power connection block 61-1 is connected to the first power line 61. The power connection block 61-1 may be in a block shape (e.g., rectangular). The power connection block 61-1 is connected to the second sub-electrode 54-2 in each circuit unit via a twenty-second via hole V22. Since the second sub-electrodes 54-2 in the first circuit unit Q1 and the second circuit unit Q2 are both connected to the first sub-electrode 54-1, and the first sub-electrode 54-1 is connected to the first electrode of the fifth transistor T5 shared by the first circuit unit Q1 and the second circuit unit Q2, the fourth connection electrode 54 interconnects the first power line 61 in the first circuit unit Q1 and the first power line 61 in the second circuit unit Q2. This ensures that the multiple first power lines 61 in a unit row have the same potential, which helps improve the uniformity of the panel, avoid display defects on the display substrate, and ensure the display quality of the display substrate.

[0243] In an exemplary embodiment, a shielding block 61-2 is connected to the first power line 61. The shape of the shielding block 61-2 can be a block shape (such as a rectangle). The orthographic projection of the shielding block 61-2 on the substrate at least partially overlaps with the orthographic projection of the second active layer on the substrate, so that the shielding block 61-2 can block the second active layer, thereby blocking the light emission of the light-emitting device and the light reflected by the film layer from irradiating the second transistor T2 of the oxide, preventing the characteristics of the oxide transistor from drifting due to light, and improving the electrical characteristics of the oxide transistor.

[0244] In an exemplary embodiment, the orthographic projections of the first power line 61 and the shielding block 61-2 on the substrate at least partially overlap with the orthographic projection of the first connection electrode 51 on the substrate. The first power line 61 and the shielding block 61-2 having a constant potential can effectively shield the influence of data voltage jumps and other signals on the first node N1 in the pixel driving circuit, thereby preventing the data voltage jumps and other signals from affecting the potential of the first node N1, thereby improving the driving performance of the pixel driving circuit.

[0245] In an exemplary embodiment, the orthographic projections of the first power line 61 and the shielding block 61-2 on the substrate at least partially overlap with the orthographic projection of the second connection electrode 52 on the substrate. The first power line 61 and the shielding block 61-2 having a constant potential can effectively shield the influence of data voltage jumps and other signals on the third node N3 in the pixel driving circuit, thereby preventing the data voltage jumps and other signals from affecting the potential of the third node N3, thereby improving the driving performance of the pixel driving circuit.

[0246] In an exemplary embodiment, the data signal line 62 may be in the shape of a straight line or a zigzag line, with the main portion extending along the second direction Y. The data signal line 62 is connected to the third connection electrode 53 through the twenty-first via hole V21. Since the third connection electrode 53 is connected to the first region of the fourth active layer through the via hole, the data signal line 62 is connected to the first electrode of the fourth transistor T4. The data signal line 62 can write a data signal to the first electrode of the fourth transistor T4.

[0247] In an exemplary embodiment, since the first circuit unit Q1 and the second circuit unit Q2 share the twenty-first via V21, the first circuit unit Q1 and the second circuit unit Q2 share the data signal line 62, and the orthographic projection of the data signal line 62 on the substrate at least partially overlaps with the orthographic projection of the unit boundary line A on the substrate.

[0248] In an exemplary embodiment, the anode connection electrode 63 may be in a block shape (e.g., a rectangular shape). The anode connection electrode 63 is connected to the sixth connection electrode 56 via a twenty-third via hole V23. The anode connection electrode 63 is configured to be connected to a subsequently formed anode. Since the sixth connection electrode 56 is connected to the second region of the sixth active layer and the second region of the seventh active layer via the via hole, the subsequently formed anode can be connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, and the pixel driving circuit can drive the light-emitting device to emit light. In an exemplary embodiment, the anode connection electrode 63 may be provided in each circuit unit.

[0249] (10) Forming a second planar layer pattern. In an exemplary embodiment, forming the second planar layer pattern may include: coating a second planar film on the substrate on which the aforementioned pattern is formed, patterning the first planar film using a patterning process to form a second planar layer covering the fifth conductive layer pattern, wherein a plurality of vias are provided on the second planar layer, as shown in FIG. 16 .

[0250] In an exemplary embodiment, the plurality of vias includes at least an anode connection via V30. The orthographic projection of the anode connection via V30 on the substrate is within the orthographic projection of the anode connection electrode 63 on the substrate. The second flat layer within the anode connection via V30 is etched away, exposing the surface of the anode connection electrode 63. The anode connection via V30 is configured to connect a subsequently formed anode to the anode connection electrode 63 through the via. In an exemplary embodiment, the anode connection via V30 may be provided in each circuit unit.

[0251] At this point, the driving circuit layer is prepared on the substrate. In a plane parallel to the display substrate, the driving circuit layer may include a plurality of circuit units, each of which may include a pixel driving circuit, and a first scanning signal line, a second scanning signal line, a third scanning signal line, a control signal line, a light-emitting signal line, a data signal line, a first power line, a first initial signal line, a second initial signal line, and a third initial signal line connected to the pixel driving circuit. In a plane perpendicular to the display substrate, the driving circuit layer may include a first insulating layer, a first semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a second semiconductor layer, a fifth insulating layer, a third conductive layer, a sixth insulating layer, a fourth conductive layer, a first planar layer, a fifth conductive layer, and a second planar layer, which are sequentially arranged on the substrate. The first semiconductor layer may include at least the active layers of the first transistor and the third to eighth transistors, the first conductive layer may include at least the first scanning signal line, the second scanning signal line, the third scanning signal line, the light-emitting signal line and the first plate of the storage capacitor, the second conductive layer may include at least the first shielding line, the second shielding line and the second plate of the storage capacitor, the second semiconductor layer may include at least the active layer of the second transistor, the third conductive layer may include at least the first initial signal line, the second initial signal line, the third initial signal line, the first control signal line and the second control signal line, the fourth conductive layer may include at least a plurality of connecting electrodes, and the fifth conductive layer may include at least the first power line, the data signal line and the anode connecting electrode.

[0252] In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may include, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked. The materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the water and oxygen resistance of the substrate. The first and second inorganic material layers are also referred to as barrier layers, and the material of the semiconductor layer may be amorphous silicon (a-Si).

[0253] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single layer structure or a multilayer composite structure, such as Mo / Cu / Mo. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, and the sixth insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, a multilayer, or a composite layer. The first planarizing layer and the second planarizing layer can be made of an organic material, such as a resin.

[0254] In an exemplary embodiment, after the driving circuit layer is prepared, the light emitting structure layer may be prepared. In an exemplary embodiment, preparing the light emitting structure layer may include:

[0255] (11) Forming an anode conductive layer pattern. In an exemplary embodiment, forming the anode conductive layer pattern may include: depositing an anode conductive film on the substrate on which the aforementioned pattern is formed, and patterning the anode conductive film using a patterning process to form an anode conductive layer disposed on the second flat layer, as shown in FIG. 17 .

[0256] In an exemplary embodiment, the anode conductive layer includes at least a plurality of anodes 90. The anodes 90 may include an anode main body 90-1 and an anode connecting portion 90-2 connected to each other. The anode main body 90-1 may be circular or elliptical, and the anode connecting portion 90-2 may be strip-shaped. A first end of the anode connecting portion 90-2 is connected to the anode main body 90-1, and a second end of the anode connecting portion 90-2 extends away from the anode main body 90-1 and is connected to the anode connecting electrode 63 through an anode connecting via V30.

[0257] In an exemplary embodiment, the anode conductive layer has a single-layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or may have a multi-layer composite structure, such as ITO / Ag / ITO.

[0258] In an exemplary embodiment, the subsequent preparation process may include: first forming a pixel definition layer pattern, then forming an organic light emitting layer by evaporation or inkjet printing, and then forming a cathode on the organic light emitting layer.

[0259] In an exemplary embodiment, after the light-emitting structure layer is prepared, an encapsulation structure layer can be prepared. The encapsulation structure layer can include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. The first encapsulation layer and the third encapsulation layer can be made of inorganic materials, and the second encapsulation layer can be made of organic materials. The second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to ensure that external water vapor cannot enter the light-emitting structure layer.

[0260] In a display substrate, because each circuit unit's pixel driver circuit includes eight transistors and one storage capacitor, reducing the circuit unit size is difficult, making it difficult to improve the display device's resolution (Pixels Per Inch, PPI). Furthermore, increasing resolution requires reducing the circuit unit size. As the circuit unit size decreases, the distances between nodes within the pixel driver circuit and between each node and signal lines decrease, increasing signal capacitance and causing crosstalk, which can even degrade the display quality.

[0261] The display substrate provided by the disclosed embodiments effectively reduces the size of the circuit units and improves the resolution of the display device by arranging two circuit units to share a data signal line, a fourth transistor T4, a fifth transistor T5, and an eighth transistor T8. By arranging the data signal line, the fourth transistor T4, and the fifth transistor T5 between the two circuit units and positioning the eighth transistor T8 near the unit boundary A, the disclosed display substrate enables a single data signal line to provide data signals to the pixel driving circuits of two unit columns, respectively, via a single fourth transistor T4. The two circuit units comprise only 13 transistors, two storage capacitors, and a single data signal line. Compared with the existing structure in which two circuit units include 16 transistors, 2 storage capacitors and two data signal lines, the present disclosure effectively reduces the number of transistors and the number of data signal lines in the circuit unit, reduces the occupied area of ​​the pixel driving circuit, and simplifies the structure of the pixel driving circuit. Therefore, it can not only effectively reduce the size of each circuit unit and effectively improve the resolution of the display device, but also ensure the distance between each node inside the pixel driving circuit and the distance between each node and the signal line, effectively avoid crosstalk, effectively improve the display quality of the display device, effectively improve the product yield, and reduce production costs.

[0262] The display substrate of the disclosed embodiment can also reduce the number of data channels in the data driver chip by setting two circuit units to share one data signal line, which can effectively reduce the cost of the data driver chip and lower the product cost.

[0263] The present disclosure sets a first power line to cover the first connection electrode, which can effectively shield the influence of data voltage jumps and other signals on the first node in the pixel driving circuit, avoid the influence of data voltage jumps and other signals on the potential of the first node, and effectively avoid the deterioration of crosstalk. The present disclosure sets a first power line to cover the second active layer, which can effectively block the light emission of the light-emitting device and the light reflected by the film layer from irradiating the oxide transistor, prevent the oxide transistor from drifting due to light, and improve the electrical characteristics of the oxide transistor. The preparation process of the present disclosure is well compatible with existing preparation processes, and the process is simple to implement, easy to implement, high in production efficiency, low in production cost, and high in yield.

[0264] The structure and preparation process shown above in the present disclosure are merely exemplary. In exemplary embodiments, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs, and the present disclosure does not limit this.

[0265] In an exemplary embodiment, the display substrate of the present disclosure can be applied to a display device having a pixel driving circuit, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., which is not limited in the present disclosure.

[0266] The exemplary embodiments of the present disclosure also provide a method for driving a display substrate to drive the aforementioned display substrate. In an exemplary embodiment, the display substrate includes a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, at least one circuit unit includes at least a pixel driving circuit, at least one pixel driving circuit includes at least a data writing transistor, and the data writing transistor is connected to a data signal line; the plurality of circuit units include at least a first circuit unit and a second circuit unit adjacent to each other in the unit row direction, the first circuit unit includes a first pixel driving circuit, the second circuit unit includes a second pixel driving circuit, and the first pixel driving circuit and the second pixel driving circuit share the same data writing transistor and the same data signal line; the driving method may include:

[0267] The data signal line sequentially provides a first data signal to the first pixel driving circuit and a second data signal to the second pixel driving circuit through the data writing transistor.

[0268] In an exemplary embodiment, the display substrate further includes a first control signal line and a second control signal line; the first pixel driving circuit further includes a first compensation transistor, a first driving transistor and a first storage capacitor, the gate electrode of the first compensation transistor is connected to the first control signal line, the first electrode of the first compensation transistor is respectively connected to the gate electrode of the first driving transistor and the first storage capacitor, the second electrode of the first compensation transistor is connected to the second electrode of the first driving transistor, and the first electrode of the first driving transistor is connected to the data writing transistor; the second pixel driving circuit further includes a second compensation transistor, a second driving transistor and a second storage capacitor, the gate electrode of the second compensation transistor is connected to the second control signal line, the first electrode of the second compensation transistor is respectively connected to the gate electrode of the second driving transistor and the second storage capacitor, the second electrode of the second compensation transistor is connected to the second electrode of the second driving transistor, and the first electrode of the second driving transistor is connected to the data writing transistor.

[0269] In an exemplary embodiment, the driving method may include:

[0270] B11. The first control signal line provides a turn-on signal, and the second control signal line provides a turn-off signal. The first compensation transistor is turned on to initialize the first storage capacitor.

[0271] B12: The first control signal line provides a disconnect signal, the second control signal line provides a turn-on signal, the second compensation transistor is turned on, and the second storage capacitor is initialized;

[0272] B13. The first control signal line provides a turn-on signal, the second control signal line provides a turn-off signal, the first compensation transistor is turned on, and the data signal line provides a first data signal to the first storage capacitor through the data write transistor, the first drive transistor, and the first compensation transistor;

[0273] B14. The first control signal line provides a disconnect signal, the second control signal line provides a turn-on signal, the second compensation transistor is turned on, and the data signal line provides a second data signal to the second storage capacitor through the data write transistor, the second drive transistor and the second compensation transistor.

[0274] FIG18 is a driving timing diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure. As shown in FIG18 , the operation process of the pixel driving circuit shown in FIG4 may include:

[0275] The first phase A1 can be referred to as a reset phase for the second node N2 and the fourth node N4. The signals on the first control signal line KS1, the second control signal line KS2, and the second scan signal line S2 are low-level signals, while the signals on the first scan signal line S1, the third scan signal line S3, and the light-emitting signal line EM are high-level signals. This turns on the seventh transistor T7 of each pixel driving circuit, turns on the eighth transistor T8 shared by both pixel driving circuits, and turns off the other transistors.

[0276] The seventh transistor T7 of each pixel driving circuit is turned on so that the signal of the second initialization signal line INIT2 is supplied to the fourth node N4, thereby initializing (resetting) the first electrode of the light-emitting device EL and clearing the original charge in the first electrode of the light-emitting device EL, so that the potential of the fourth node N4 is Vinit2. The eighth transistor T8 shared by the two pixel driving circuits is turned on so that the signal of the third initialization signal line INIT3 is supplied to the second node N2, thereby initializing (resetting) the second node N2 and clearing the original charge in the second node N2, so that the potential of the second node N2 is Vinit3.

[0277] The second phase A2 can be referred to as a phase in which the first node N1 of the first pixel driving circuit is reset. The signals on the second control signal line KS2 and the third scan signal line S3 are low-level signals, while the signals on the first control signal line KS1, the first scan signal line S1, the second scan signal line S2, and the light-emitting signal line EM are high-level signals. This turns on the first transistor T1 and the second transistor T2 of each pixel driving circuit, while turning off the other transistors.

[0278] The first transistor T1 of each pixel driving circuit is turned on, so that the signal of the first initial signal line INIT1 is provided to the third node N3, initializing (resetting) the third node N3, clearing the original charge in the third node N3, and setting the potential of the third node N3 to Vinit1. The second transistor T2 of the first pixel driving circuit is turned on, so that the first node N1 and the third node N3 are connected, initializing (resetting) the first node N1 of the first pixel driving circuit, clearing the original charge in the first node N1, and setting the potential of the first node N1 to Vinit1. In this stage, the third transistor T3 of the first pixel driving circuit is turned on, and the signal of the second node N2 can be provided to the first node N1 and the third node N3.

[0279] The third phase A3 can be referred to as a phase in which the first node N1 of the second pixel driving circuit is reset. The signals on the first control signal line KS1 and the third scan signal line S3 are low-level signals, while the signals on the second control signal line KS2, the first scan signal line S1, the second scan signal line S2, and the light-emitting signal line EM are high-level signals. This turns on the first transistor T1 and the second transistor T2 of each pixel driving circuit, while turning off the other transistors.

[0280] The first transistor T1 of each pixel driving circuit is turned on, so that the signal of the first initial signal line INIT1 is provided to the third node N3, initializing (resetting) the third node N3, clearing the original charge in the third node N3, and setting the potential of the third node N3 to Vinit1. The second transistor T2 of the second pixel driving circuit is turned on, so that the first node N1 and the third node N3 are connected, initializing (resetting) the first node N1 of the second pixel driving circuit, clearing the original charge in the first node N1, and setting the potential of the first node N1 to Vinit1. In this stage, the third transistor T3 of the second pixel driving circuit is turned on, and the signal of the second node N2 can be provided to the first node N1 and the third node N3.

[0281] In an exemplary embodiment, the first phase A1 , the second phase A2 , and the third phase A3 may be collectively referred to as an initialization phase.

[0282] The fourth phase A4 can be referred to as the first pixel driver circuit data writing phase. The signals on the second control signal line KS2 and the first scan signal line S1 are low-level signals, while the signals on the first control signal line KS1, the second scan signal line S2, the third scan signal line S3, and the light-emitting signal line EM are high-level signals. This turns on the second transistor T2 of the first pixel driver circuit, turns on the fourth transistor T4 shared by both pixel driver circuits, and turns off the other transistors.

[0283] Since the third transistor T3 is continuously turned on during this stage, the second transistor T2 of the first pixel driving circuit is turned on, and therefore the fourth transistor T4 is turned on, so that the first data signal output by the data signal line DATA is provided to the first node N1 through the second node N2 of the first pixel driving circuit, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2, and the difference between the first data voltage output by the data signal line DATA and the threshold voltage of the third transistor T3 is charged into the storage capacitor C of the first pixel driving circuit. The voltage of the first node N1 of the first pixel driving circuit is Vd1-|Vth1|, where Vd1 is the first data voltage output by the data signal line DATA and Vth1 is the threshold voltage of the third transistor T3 of the first pixel driving circuit.

[0284] The fifth phase A5 can be referred to as the data writing phase for the second pixel driving circuit. The signals on the first control signal line KS1 and the first scan signal line S1 are low-level signals, while the signals on the second control signal line KS2, the second scan signal line S2, the third scan signal line S3, and the light-emitting signal line EM are high-level signals. This turns on the second transistor T2 of the second pixel driving circuit, turns on the fourth transistor T4 shared by both pixel driving circuits, and turns off the other transistors.

[0285] Since the third transistor T3 is continuously turned on during this stage, the second transistor T2 of the second pixel driving circuit is turned on, and therefore the fourth transistor T4 is turned on, so that the second data signal output by the data signal line DATA is provided to the first node N1 through the second node N2 of the second pixel driving circuit, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2, and the difference between the second data voltage output by the data signal line DATA and the threshold voltage of the third transistor T3 is charged into the storage capacitor C of the second pixel driving circuit. The voltage of the first node N1 of the second pixel driving circuit is Vd2-|Vth2|, where Vd2 is the second data voltage output by the data signal line DATA, and Vth2 is the threshold voltage of the third transistor T3 of the second pixel driving circuit.

[0286] In an exemplary embodiment, the fourth phase A4 and the fifth phase A5 together may be referred to as a charging phase.

[0287] The sixth phase A6 can be referred to as a phase in which the second node N2, the third node N3, and the fourth node N4 are reset. The signals on the first control signal line KS1, the second control signal line KS2, and the second scan signal line S2 are low-level signals, while the signals on the first scan signal line S1, the third scan signal line S3, and the light-emitting signal line EM are high-level signals. This turns on the seventh transistor T7 of each pixel driving circuit, turns on the eighth transistor T8 shared by both pixel driving circuits, and turns off the other transistors.

[0288] During this phase, the third transistor T3 is continuously turned on, the seventh transistor T7 is turned on, and the signal of the second initial signal line INIT2 is supplied to the fourth node N4. The eighth transistor T8 is turned on, and the signal of the third initial signal line INIT3 is supplied to the second node N2 and the third node N3. This resets the second node N2, the third node N3, and the fourth node N4, respectively. The potentials of the second node N2 and the third node N3 are Vinit3, and the potential of the fourth node N4 is Vinit2. Resetting the second node N2, the third node N3, and the fourth node N4 in this phase can eliminate and reduce hysteresis deviation caused by grayscale differences between adjacent pixels. It can also periodically reset the OLED anode to improve low-frequency flicker.

[0289] The seventh stage A7 can be called the light-emitting stage. The signals on the first control signal line KS1, the second control signal line KS2, and the light-emitting signal line EM are low-level signals, and the signals on the first scan signal line S1, the second scan signal line S2, and the third scan signal line S3 are high-level signals, turning on the fifth transistor T5 and the sixth transistor T6 of each pixel driving circuit, and turning off the other transistors.

[0290] The fifth transistor T5 and the sixth transistor T6 are turned on so that the power voltage output from the first power line VDD provides a driving voltage to the first electrode of the light emitting device EL through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, driving the light emitting device EL to emit light.

[0291] During the pixel driving circuit driving process, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the first node N1 is Vd-|Vth|, the driving current of the third transistor T3 is: I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd] 2

[0292] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light-emitting device EL, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal line DATA, and Vdd is the power supply voltage output by the first power supply line VDD.

[0293] It can be seen from the derivation results of the above current formula that in the light-emitting stage, the driving current of the third transistor T3 of each pixel driving circuit is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring uniform display brightness of the display product and improving the display effect of the entire display product.

[0294] The driving method of the display substrate provided in this embodiment first initializes the first pixel driving circuit and the second pixel driving circuit in sequence, and then charges the first pixel driving circuit and the second pixel driving circuit in sequence, thereby achieving normal operation of each pixel driving circuit. Specifically, the first control signal line KS1 outputs a conduction signal in the second phase A2 and the fourth phase A4, the third scan signal line S3 outputs a conduction signal in the second phase A2 to initialize the third node N3 of the first pixel driving circuit, and the first scan signal line S1 outputs a conduction signal in the fourth phase A4 to charge and maintain the storage capacitor C of the first pixel driving circuit. The second control signal line KS2 outputs a conduction signal in the third phase A3 and the fifth phase A5, the third scan signal line S3 outputs a conduction signal in the third phase A3 to initialize the third node N3 of the second pixel driving circuit, and the first scan signal line S1 outputs a conduction signal in the fifth phase A5 to charge and maintain the storage capacitor C of the second pixel driving circuit.

[0295] The driving method of the display substrate provided in this embodiment is as follows: the first control signal line KS1 alternately outputs an on signal and an off signal twice, the second control signal line KS2 alternately outputs an on signal and an off signal twice, the third scan signal line S3 and the first scan signal line S1 sequentially output an on signal, the first pixel drive circuit is initialized when the first control signal line KS1 and the third scan signal line S3 output the on signal, the second pixel drive circuit is initialized when the second control signal line KS2 and the third scan signal line S3 output the on signal, the first pixel drive circuit is charged when the first control signal line KS1 and the first scan signal line S1 output the on signal, and the second pixel drive circuit is charged when the second control signal line KS2 and the first scan signal line S1 output the on signal, and the data signal line sequentially outputs the data voltages of the two pixel drive circuits, so that the data signal line shared by the two pixel drive circuits and the fourth transistor T4 respectively provide the data voltage to the storage capacitor C of each pixel drive circuit, thereby ensuring the normal operation of each pixel drive circuit.

[0296] In another exemplary embodiment, the driving method may include:

[0297] B21: The first control signal line provides a turn-on signal, and the second control signal line provides a turn-off signal, so that the first compensation transistor is turned on to initialize the first storage capacitor.

[0298] B22: The first control signal line provides a turn-on signal, the second control signal line provides a turn-off signal, the first compensation transistor is turned on, and the data signal line provides a first data signal to the first storage capacitor through the data write transistor, the first drive transistor, and the first compensation transistor;

[0299] B23: The first control signal line provides a disconnect signal, the second control signal line provides a turn-on signal, the second compensation transistor is turned on, and the second storage capacitor is initialized;

[0300] B24. The first control signal line provides a disconnect signal, the second control signal line provides a turn-on signal, the second compensation transistor is turned on, and the data signal line provides a second data signal to the second storage capacitor through the data write transistor, the second drive transistor and the second compensation transistor.

[0301] FIG19 is another driving timing diagram of the pixel driving circuit of the exemplary embodiment of the present disclosure. As shown in FIG19 , the operation process of the pixel driving circuit shown in FIG4 may include:

[0302] The first phase A1 is substantially the same as the first phase A1 of the embodiment shown in FIG18 , wherein the seventh transistor T7 of each pixel driving circuit is turned on, the eighth transistor T8 shared by the two pixel driving circuits is turned on, and the other transistors are turned off.

[0303] The second stage A2 is substantially the same as the second stage A2 of the embodiment shown in FIG18 , wherein the first transistor T1 of each pixel driving circuit and the second transistor T2 of the first pixel driving circuit are turned on, and the other transistors are turned off.

[0304] The third stage A3 is basically the same as the fourth stage A4 of the embodiment shown in Figure 18. The second transistor T2 of the first pixel driving circuit is turned on, the fourth transistor T4 shared by the two pixel driving circuits is turned on, the other transistors are turned off, and the data signal line DATA outputs the first data signal to the first pixel driving circuit.

[0305] The fourth stage A4 is substantially the same as the third stage A3 of the embodiment shown in FIG18 , wherein the first transistor T1 of each pixel driving circuit and the second transistor T2 of the second pixel driving circuit are turned on, and the other transistors are turned off.

[0306] The fifth stage A5 is basically the same as the fifth stage A5 of the embodiment shown in Figure 18. The second transistor T2 of the second pixel driving circuit is turned on, the fourth transistor T4 shared by the two pixel driving circuits is turned on, the other transistors are turned off, and the data signal line DATA outputs the second data signal to the second pixel driving circuit.

[0307] The sixth stage A6 is substantially the same as the sixth stage A6 of the embodiment shown in FIG18 , wherein the seventh transistor T7 of each pixel driving circuit is turned on, the eighth transistor T8 shared by the two pixel driving circuits is turned on, and the other transistors are turned off.

[0308] The seventh stage A7 is substantially the same as the seventh stage A7 of the embodiment shown in FIG18 , wherein the fifth transistor T5 and the sixth transistor T6 of each pixel driving circuit are turned on, and the other transistors are turned off.

[0309] The driving method of the display substrate provided in this embodiment first initializes and charges the first pixel driving circuit, and then initializes and charges the second pixel driving circuit, thereby achieving normal operation of each pixel driving circuit. Specifically, the first control signal line KS1 outputs a conduction signal in the second phase A2 and the third phase A3, the third scan signal line S3 outputs a conduction signal in the second phase A2 to initialize the third node N3 of the first pixel driving circuit, and the first scan signal line S1 outputs a conduction signal in the third phase A3 to charge and maintain the storage capacitor C of the first pixel driving circuit. The second control signal line KS2 outputs a conduction signal in the fourth phase A4 and the fifth phase A5, the third scan signal line S3 outputs a conduction signal in the fourth phase A4 to initialize the third node N3 of the second pixel driving circuit, and the first scan signal line S1 outputs a conduction signal in the fifth phase A5 to charge and maintain the storage capacitor C of the second pixel driving circuit.

[0310] The driving method of the display substrate provided in this embodiment sequentially outputs a conduction signal through the first control signal line KS1 and the second control signal line KS2, the third scan signal line S3 alternately outputs a conduction signal and an off signal twice, and the first scan signal line S1 alternately outputs a conduction signal and an off signal twice. The first pixel driving circuit is initialized when the first control signal line KS1 and the third scan signal line S3 output the conduction signal, and the first pixel driving circuit is charged when the first control signal line KS1 and the first scan signal line S1 output the conduction signal. The second pixel driving circuit is initialized when the second control signal line KS2 and the third scan signal line S3 output the conduction signal, and the second pixel driving circuit is charged when the second control signal line KS2 and the first scan signal line S1 output the conduction signal. The data signal line sequentially outputs the data voltages of the two pixel driving circuits, thereby realizing that the data signal line shared by the two pixel driving circuits and the fourth transistor T4 respectively provide the data voltage to the storage capacitor C of each pixel driving circuit, thereby ensuring the normal operation of each pixel driving circuit.

[0311] In yet another exemplary embodiment, the driving method may include:

[0312] B31: The first control signal line provides a turn-on signal, and the second control signal line provides a turn-off signal, so that the first compensation transistor is turned on to initialize the first storage capacitor.

[0313] B32. The first control signal line provides a turn-on signal, the second control signal line provides a turn-on signal, the first compensation transistor is turned on to initialize the first storage capacitor, and the second compensation transistor is turned on to initialize the second storage capacitor;

[0314] B33: The first control signal line provides a turn-on signal, the second control signal line provides a turn-on signal, the first compensation transistor is turned on, the data signal line provides a first data signal to the first storage capacitor through the data write transistor, the first drive transistor, and the first compensation transistor, the second compensation transistor is turned on, and the data signal line provides a first data signal to the second storage capacitor through the data write transistor, the second drive transistor, and the second compensation transistor;

[0315] B34. The first control signal line provides a disconnect signal, the second control signal line provides a turn-on signal, the second compensation transistor is turned on, and the data signal line provides a second data signal to the second storage capacitor through the data write transistor, the second drive transistor and the second compensation transistor.

[0316] FIG20 is another driving timing diagram of the pixel driving circuit of the exemplary embodiment of the present disclosure. As shown in FIG20 , the operation process of the pixel driving circuit shown in FIG4 may include:

[0317] The first phase A1 is substantially the same as the first phase A1 of the embodiment shown in FIG18 , wherein the seventh transistor T7 of each pixel driving circuit is turned on, the eighth transistor T8 shared by the two pixel driving circuits is turned on, and the other transistors are turned off.

[0318] The second stage A2 is substantially the same as the second stage A2 of the embodiment shown in FIG18 , wherein the first transistor T1 of each pixel driving circuit and the second transistor T2 of the first pixel driving circuit are turned on, and the other transistors are turned off.

[0319] The third phase A3 can be referred to as a phase in which the first nodes N1 of the two pixel driving circuits are reset. The signal on the third scan signal line S3 is a low-level signal, and the signals on the first control signal line KS1, the second control signal line KS2, the first scan signal line S1, the second scan signal line S2, and the light-emitting signal line EM are high-level signals, turning on the first transistor T1 and the second transistor T2 of each pixel driving circuit, while turning off the other transistors.

[0320] The first transistor T1 of each pixel driving circuit is turned on, so that the signal of the first initial signal line INIT1 is provided to the third node N3, initializing (resetting) the third node N3 and clearing the original charge in the third node N3, so that the potential of the third node N3 is Vinit1. The second transistor T2 of each pixel driving circuit is turned on, so that the first node N1 and the third node N3 are connected, initializing (resetting) the first node N1, clearing the original charge in the first node N1, and the potential of the first node N1 is Vinit1. In this stage, the third transistors T3 of the two pixel driving circuits are turned on, and the signal of the second node N2 can be provided to the first node N1 and the third node N3.

[0321] The fourth phase A4 can be referred to as a data writing phase for the first pixel driving circuit and the second pixel driving circuit. The signal on the first scanning signal line S1 is a low-level signal, and the signals on the first control signal line KS1, the second control signal line KS2, the second scanning signal line S2, the third scanning signal line S3, and the light-emitting signal line EM are high-level signals. This turns on the second transistors T2 of the two pixel driving circuits, turns on the fourth transistor T4 shared by the two pixel driving circuits, and turns off the other transistors.

[0322] Since the third transistor T3 is continuously turned on during this stage, the second transistors T2 of the two pixel driving circuits are turned on, and therefore the fourth transistor T4 is turned on, so that the first data signal output by the data signal line DATA is provided to the first node N1 through the second node N2 of each pixel driving circuit, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2, and the difference between the first data voltage output by the data signal line DATA and the threshold voltage of the third transistor T3 is respectively charged into the storage capacitors C of the two pixel driving circuits.

[0323] The fifth stage A5 can be referred to as the data rewriting stage for the second pixel driving circuit. The signals on the first control signal line KS1 and the first scanning signal line S1 are low-level signals, while the signals on the second control signal line KS2, the second scanning signal line S2, the third scanning signal line S3, and the light-emitting signal line EM are high-level signals. This turns on the second transistor T2 of the second pixel driving circuit, turns on the fourth transistor T4 shared by both pixel driving circuits, and turns off the other transistors.

[0324] Since the third transistor T3 is continuously turned on during this phase, and the second transistor T2 of the second pixel driving circuit is turned on, the fourth transistor T4 is turned on, causing the second data signal output by the data signal line DATA to be provided to the first node N1 through the second node N2 of the second pixel driving circuit, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the second data voltage output by the data signal line DATA and the threshold voltage of the third transistor T3 is charged into the storage capacitor C of the second pixel driving circuit. Although the first data voltage is written to both pixel driving circuits simultaneously in the fourth phase A4, since the second transistor T2 of the first pixel driving circuit is turned off during this phase, the storage capacitor C of the first pixel driving circuit maintains the first data voltage written in the fourth phase A4. The second transistor T2 of the second pixel driving circuit is turned on, and the storage capacitor C of the second pixel driving circuit is recharged and maintains the second data voltage written in the fifth phase A5.

[0325] The sixth stage A6 is substantially the same as the sixth stage A6 of the embodiment shown in FIG18 , wherein the seventh transistor T7 of each pixel driving circuit is turned on, the eighth transistor T8 shared by the two pixel driving circuits is turned on, and the other transistors are turned off.

[0326] The seventh stage A7 is substantially the same as the seventh stage A7 of the embodiment shown in FIG18 , wherein the fifth transistor T5 and the sixth transistor T6 of each pixel driving circuit are turned on, and the other transistors are turned off.

[0327] The display substrate provided in this embodiment outputs on signals and off signals through the staggered arrangement of the first control signal line KS1 and the second control signal line KS2. The third scanning signal line S3 and the first scanning signal line S1 output on signals in sequence. When the first control signal line KS1 and the third scanning signal line S3 output on signals, the first pixel driving circuit is initialized. When the second control signal line KS2 and the third scanning signal line S3 output on signals, the second pixel driving circuit is initialized. When the first control signal line KS1 and the first scanning signal line S1 output on signals, the first pixel driving circuit and the second pixel driving circuit are charged. When the second control signal line KS2 and the first scanning signal line S1 output on signals, the second pixel driving circuit is charged again. The data signal line outputs data voltages of the two pixel driving circuits in sequence, thereby realizing that the data signal line shared by the two pixel driving circuits and the fourth transistor T4 respectively provide data voltages to the capacitor C of each pixel driving circuit, thereby ensuring the normal operation of each pixel driving circuit.

[0328] The present disclosure also provides a method for manufacturing a display substrate, for producing the display substrate provided in the above embodiment. In an exemplary embodiment, the display substrate includes a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, at least one circuit unit including at least a pixel driving circuit, at least one pixel driving circuit including at least a data writing transistor connected to a data signal line, and the plurality of circuit units including at least a first circuit unit and a second circuit unit adjacent to each other in the unit row direction; the manufacturing method includes:

[0329] A first pixel driving circuit is formed in the first circuit unit, and a second pixel driving circuit is formed in the second circuit unit. The first pixel driving circuit and the second pixel driving circuit share the same data writing transistor and the same data signal line. The data signal line provides a first data signal to the first pixel driving circuit and a second data signal to the second pixel driving circuit in sequence through the data writing transistor.

[0330] The present disclosure further provides a display device including the aforementioned display substrate. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system, but the embodiments of the present invention are not limited thereto.

[0331] While the embodiments disclosed herein are as described above, it should be noted that the embodiments described above are merely illustrative and not restrictive. Therefore, the present disclosure is not limited to what is specifically shown and described herein. Various modifications, substitutions, or omissions may be made to the forms and details of the embodiments without departing from the scope of the present disclosure.

Claims

1. A display substrate, comprising a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, wherein at least one circuit unit comprises at least a pixel driving circuit, and at least one pixel driving circuit comprises at least a data writing transistor, wherein the data writing transistor is connected to a data signal line; the plurality of circuit units comprises at least a first circuit unit and a second circuit unit adjacent to each other in a unit row direction, wherein the first circuit unit comprises a first pixel driving circuit, and the second circuit unit comprises a second pixel driving circuit, wherein the first pixel driving circuit and the second pixel driving circuit share the same data writing transistor and are connected to the same data signal line, wherein the data signal line sequentially provides a first data signal to the first pixel driving circuit and provides a second data signal to the second pixel driving circuit through the data writing transistor.

2. The display substrate according to claim 1, wherein: The orthographic projection of the data write transistor on the display substrate plane at least partially overlaps with the orthographic projection of the unit boundary line on the display substrate plane, and the orthographic projection of the data signal line on the display substrate plane at least partially overlaps with the orthographic projection of the unit boundary line on the display substrate plane. The unit boundary line is a straight line located between the first circuit unit and the second circuit unit and extending along the unit column direction.

3. The display substrate according to claim 2, wherein: The data writing transistor at least includes a data writing active layer, the data signal line is connected to the first area of ​​the data writing active layer through a data connection electrode, the orthographic projection of the data writing active layer on the display substrate plane at least partially overlaps with the orthographic projection of the unit boundary line on the display substrate plane, and the orthographic projection of the data connection electrode on the display substrate plane at least partially overlaps with the orthographic projection of the unit boundary line on the display substrate plane.

4. The display substrate according to claim 3, wherein: In a direction perpendicular to the display substrate, the display substrate includes a plurality of conductive layers arranged in sequence on a base, the data signal line and the data connection electrode are arranged in different conductive layers, the data signal line is connected to the data connection electrode through a first connection via, and the orthographic projection of the first connection via on the plane of the display substrate at least partially overlaps with the orthographic projection of the unit boundary line on the plane of the display substrate.

5. The display substrate according to claim 4, wherein: In a direction perpendicular to the display substrate, the display substrate also includes a first semiconductor layer, the data writing active layer is arranged in the first semiconductor layer, the data connection electrode is connected to the first area of ​​the data writing active layer through a second connection via, and the orthographic projection of the second connection via on the plane of the display substrate at least partially overlaps with the orthographic projection of the unit boundary line on the plane of the display substrate.

6. The display substrate according to any one of claims 1 to 5, wherein: The display substrate further includes a first control signal line and a second control signal line; the first control signal line is connected to the first pixel driving circuit, and the first control signal line is configured to enable the data signal line to provide a first data signal to the first pixel driving circuit; The second control signal line is connected to the second pixel driving circuit, and the second control signal line is configured to cause the data signal line to provide a second data signal to the second pixel driving circuit.

7. The display substrate according to claim 6, wherein: The first pixel driving circuit further includes a first compensation transistor and a first driving transistor, the second pixel driving circuit further includes a second compensation transistor and a second driving transistor, the data writing transistor is connected to a first electrode of the first driving transistor and a first electrode of the second driving transistor respectively; a gate electrode of the first compensation transistor is connected to the first control signal line, a first electrode of the first compensation transistor is connected to the gate electrode of the first driving transistor, and a second electrode of the first compensation transistor is connected to a second electrode of the first driving transistor; A gate electrode of the second compensation transistor is connected to the second control signal line, a first electrode of the second compensation transistor is connected to the gate electrode of the second driving transistor, and a second electrode of the second compensation transistor is connected to the second electrode of the second driving transistor.

8. The display substrate according to claim 6, wherein: In a direction perpendicular to the display substrate, the display substrate includes a plurality of conductive layers sequentially arranged on a base, and the first control signal line and the second control signal line are arranged in the same conductive layer.

9. The display substrate according to claim 6, wherein: The data writing transistor, the first driving transistor, and the second driving transistor are polysilicon transistors, and the first compensation transistor and the second compensation transistor are oxide transistors.

10. The display substrate according to any one of claims 1 to 5, wherein: The pixel driving circuit also includes a light emitting control transistor. The first pixel driving circuit and the second pixel driving circuit share the same light emitting control transistor. The first electrode of the light emitting control transistor is connected to the first power line, and the second electrode of the light emitting control transistor is connected to the second electrode of the data writing transistor.

11. The display substrate according to claim 10, wherein: The light-emitting control transistor at least includes a light-emitting control active layer, the first power line is connected to the first area of ​​the light-emitting control active layer through a power connection electrode, the orthographic projection of the light-emitting control active layer on the display substrate plane at least partially overlaps with the orthographic projection of the unit boundary line on the display substrate plane, and the orthographic projection of the power connection electrode on the display substrate plane at least partially overlaps with the orthographic projection of the unit boundary line on the display substrate plane.

12. The display substrate according to claim 11, wherein: In a direction perpendicular to the display substrate, the display substrate includes a plurality of conductive layers arranged in sequence on a base, the first power line and the power connection electrode are arranged in different conductive layers, the first power line is connected to the power connection electrode through a third connection via, and the third connection via is respectively arranged in the first circuit unit and the second circuit unit.

13. The display substrate according to any one of claims 1 to 5, wherein: The pixel driving circuit also includes an initialization transistor. The first pixel driving circuit and the second pixel driving circuit share the same initialization transistor. The first electrode of the initialization transistor is connected to the initial signal line, and the second electrode of the initialization transistor is connected to the second electrode of the data writing transistor.

14. The display substrate according to claim 13, wherein: The initialization transistor at least includes an initialization active layer, a first region of the initialization active layer is connected to the initial signal line, a second electrode of the initialization transistor is connected to the second electrode of the data writing transistor via an initial connection electrode, and an orthographic projection of the initial connection electrode on a display substrate plane at least partially overlaps with an orthographic projection of a unit boundary line on a display substrate plane.

15. The display substrate according to claim 14, wherein: In a direction perpendicular to the display substrate, the display substrate also includes a first semiconductor layer, the initialization active layer is arranged in the first semiconductor layer, the initial connection electrode is connected to the active layer of the data writing transistor through a fourth connection via, and the orthographic projection of the fourth connection via on the plane of the display substrate at least partially overlaps with the orthographic projection of the unit boundary line on the plane of the display substrate.

16. A display device comprising the display substrate according to any one of claims 1 to 15.

17. A method for driving a display substrate, the display substrate comprising a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, at least one circuit unit comprising at least a pixel driving circuit, at least one pixel driving circuit comprising at least a data writing transistor, the data writing transistor being connected to a data signal line; the plurality of circuit units comprising at least a first circuit unit and a second circuit unit adjacent to each other in a unit row direction, the first circuit unit comprising a first pixel driving circuit, the second circuit unit comprising a second pixel driving circuit, the first pixel driving circuit and the second pixel driving circuit sharing the same data writing transistor and the same data signal line; the driving method comprising: The data signal line sequentially provides a first data signal to the first pixel driving circuit and a second data signal to the second pixel driving circuit through the data writing transistor.

18. The driving method according to claim 17, wherein: The display substrate further includes a first control signal line and a second control signal line; the first pixel driving circuit further includes a first compensation transistor, a first driving transistor and a first storage capacitor, the gate electrode of the first compensation transistor is connected to the first control signal line, the first electrode of the first compensation transistor is respectively connected to the gate electrode of the first driving transistor and the first storage capacitor, the second electrode of the first compensation transistor is connected to the second electrode of the first driving transistor, and the first electrode of the first driving transistor is connected to the data writing transistor; The second pixel driving circuit further includes a second compensation transistor, a second driving transistor and a second storage capacitor, the gate electrode of the second compensation transistor is connected to the second control signal line, the first electrode of the second compensation transistor is respectively connected to the gate electrode of the second driving transistor and the second storage capacitor, the second electrode of the second compensation transistor is connected to the second electrode of the second driving transistor, and the first electrode of the second driving transistor is connected to the data writing transistor; The data signal line sequentially provides a first data signal to the first pixel driving circuit and a second data signal to the second pixel driving circuit through the data writing transistor, including: The first control signal line provides a turn-on signal, the second control signal line provides a turn-off signal, the first compensation transistor is turned on, and the first storage capacitor is initialized; The first control signal line provides a disconnection signal, the second control signal line provides a conduction signal, the second compensation transistor is turned on, and the second storage capacitor is initialized; The first control signal line provides a turn-on signal, the second control signal line provides a turn-off signal, the first compensation transistor is turned on, and the data signal line provides a first data signal to the first storage capacitor through the data writing transistor, the first driving transistor and the first compensation transistor; The first control signal line provides a disconnection signal, the second control signal line provides a conduction signal, the second compensation transistor is turned on, and the data signal line provides a second data signal to the second storage capacitor through the data writing transistor, the second driving transistor and the second compensation transistor.

19. The driving method according to claim 17, wherein: The display substrate further includes a first control signal line and a second control signal line; the first pixel driving circuit further includes a first compensation transistor, a first driving transistor and a first storage capacitor, the gate electrode of the first compensation transistor is connected to the first control signal line, the first electrode of the first compensation transistor is respectively connected to the gate electrode of the first driving transistor and the first storage capacitor, the second electrode of the first compensation transistor is connected to the second electrode of the first driving transistor, and the first electrode of the first driving transistor is connected to the data writing transistor; The second pixel driving circuit further includes a second compensation transistor, a second driving transistor and a second storage capacitor, the gate electrode of the second compensation transistor is connected to the second control signal line, the first electrode of the second compensation transistor is respectively connected to the gate electrode of the second driving transistor and the second storage capacitor, the second electrode of the second compensation transistor is connected to the second electrode of the second driving transistor, and the first electrode of the second driving transistor is connected to the data writing transistor; The data signal line sequentially provides a first data signal to the first pixel driving circuit and a second data signal to the second pixel driving circuit through the data writing transistor, including: The first control signal line provides a turn-on signal, the second control signal line provides a turn-off signal, the first compensation transistor is turned on, and the first storage capacitor is initialized; The first control signal line provides a turn-on signal, the second control signal line provides a turn-off signal, the first compensation transistor is turned on, and the data signal line provides a first data signal to the first storage capacitor through the data writing transistor, the first driving transistor and the first compensation transistor; The first control signal line provides a disconnection signal, the second control signal line provides a conduction signal, the second compensation transistor is turned on, and the second storage capacitor is initialized; The first control signal line provides a disconnection signal, the second control signal line provides a conduction signal, the second compensation transistor is turned on, and the data signal line provides a second data signal to the second storage capacitor through the data writing transistor, the second driving transistor and the second compensation transistor.

20. The driving method according to claim 17, wherein: The display substrate further includes a first control signal line and a second control signal line; the first pixel driving circuit further includes a first compensation transistor, a first driving transistor and a first storage capacitor, the gate electrode of the first compensation transistor is connected to the first control signal line, the first electrode of the first compensation transistor is respectively connected to the gate electrode of the first driving transistor and the first storage capacitor, the second electrode of the first compensation transistor is connected to the second electrode of the first driving transistor, and the first electrode of the first driving transistor is connected to the data writing transistor; The second pixel driving circuit further includes a second compensation transistor, a second driving transistor and a second storage capacitor, the gate electrode of the second compensation transistor is connected to the second control signal line, the first electrode of the second compensation transistor is respectively connected to the gate electrode of the second driving transistor and the second storage capacitor, the second electrode of the second compensation transistor is connected to the second electrode of the second driving transistor, and the first electrode of the second driving transistor is connected to the data writing transistor; The data signal line sequentially provides a first data signal to the first pixel driving circuit and a second data signal to the second pixel driving circuit through the data writing transistor, including: The first control signal line provides a turn-on signal, the second control signal line provides a turn-off signal, the first compensation transistor is turned on, and the first storage capacitor is initialized; The first control signal line provides a conduction signal, the second control signal line provides a conduction signal, the first compensation transistor is turned on to initialize the first storage capacitor, and the second compensation transistor is turned on to initialize the second storage capacitor; The first control signal line provides a turn-on signal, the second control signal line provides a turn-on signal, the first compensation transistor is turned on, the data signal line provides a first data signal to the first storage capacitor through the data write transistor, the first drive transistor and the first compensation transistor, the second compensation transistor is turned on, and the data signal line provides a first data signal to the second storage capacitor through the data write transistor, the second drive transistor and the second compensation transistor; The first control signal line provides a disconnection signal, the second control signal line provides a conduction signal, the second compensation transistor is turned on, and the data signal line provides a second data signal to the second storage capacitor through the data writing transistor, the second driving transistor and the second compensation transistor.

21. A method for preparing a display substrate, the display substrate comprising a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, at least one circuit unit comprising at least a pixel driving circuit, at least one pixel driving circuit comprising at least a data writing transistor, the data writing transistor being connected to a data signal line, the plurality of circuit units comprising at least a first circuit unit and a second circuit unit adjacent to each other in a unit row direction; the preparation method comprising: A first pixel driving circuit is formed in the first circuit unit, and a second pixel driving circuit is formed in the second circuit unit. The first pixel driving circuit and the second pixel driving circuit share the same data writing transistor and the same data signal line. The data signal line provides a first data signal to the first pixel driving circuit and a second data signal to the second pixel driving circuit in sequence through the data writing transistor.

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