Storage device

Abstract

Provided is a memory device that can be miniaturized or highly integrated. The memory device includes a plurality of memory cells, a first insulator, and a second insulator on the first insulator. The memory cell includes a capacitor and a transistor on the capacitor. At least a portion of the capacitor is disposed in a first opening in the first insulator. At least a portion of the transistor is disposed in a second opening in the second insulator. The first opening has a region overlapping the second opening. The diameter of the first opening portion is larger than that of the second opening portion. In addition, in adjacent memory cells, the interval between the disposed capacitors and the interval between the disposed transistors coincide.

Description

Technical Field

[0001] One embodiment of the present invention relates to a transistor, a semiconductor device, a storage device, and an electronic device. Another embodiment of the present invention relates to a method for manufacturing a storage device or a semiconductor device. Another embodiment of the present invention relates to a semiconductor wafer and a module.

[0002] Note that in this specification, etc., semiconductor devices refer to all devices that can work by utilizing semiconductor characteristics. In addition to semiconductor elements such as transistors, semiconductor circuits, computing devices, and storage devices are also a form of semiconductor devices. Display devices (liquid crystal display devices, light-emitting display devices, etc.), projection devices, lighting devices, electro-optical devices, power storage devices, storage devices, semiconductor circuits, camera devices, electronic devices, etc. sometimes include semiconductor devices.

[0003] Note that one embodiment of the present invention is not limited to the above-mentioned technical field. One embodiment of the invention disclosed in this specification, etc., relates to an object, method, or manufacturing method. In addition, one embodiment of the present invention relates to a process, machine, product, or composition of matter. Background Art

[0004] In recent years, semiconductor devices have been developed, and LSI (Large Scale Integration), CPU (Central Processing Unit), memory, etc. are mainly used for semiconductor devices. CPU is a collection of semiconductor elements including a semiconductor integrated circuit (at least a transistor and a capacitor) formed by processing a semiconductor wafer to form a chip and having electrodes formed as connection terminals.

[0005] Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as one of the components of various electronic devices.

[0006] In addition, a technology for forming a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. The transistor is widely used in electronic devices such as integrated circuits (ICs) and image display devices (simply described as display devices). As a semiconductor material that can be applied to transistors, silicon-based semiconductor materials are widely known. As other materials, oxide semiconductors have attracted attention.

[0007] In addition, it is known that the leakage current of a transistor using an oxide semiconductor is extremely small in a non-conducting state. For example, Patent Document 1 discloses a low-power CPU that utilizes the small leakage current characteristic of a transistor using an oxide semiconductor. In addition, for example, Patent Document 2 discloses a storage device that utilizes the small leakage current characteristic of a transistor using an oxide semiconductor to achieve long-term retention of stored content.

[0008] In addition, in recent years, as electronic devices have become smaller and lighter, there has been an increased demand for further high density of integrated circuits. In addition, there is a demand for improving the productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technology in which a plurality of memory cells are arranged in an overlapping manner by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film, thereby increasing the density of the integrated circuit.

[0009] Furthermore, if a vertical transistor can be realized, the density of integrated circuits can be increased. For example, Patent Document 4 discloses a vertical transistor in which the side surface of an oxide semiconductor is covered with a gate electrode via a gate insulator. [Prior technical literature] [Patent Document]

[0010] [Patent Document 1] Japanese Patent Application Publication No. 2012-257187 [Patent Document 2] Japanese Patent Application Publication No. 2011-151383 [Patent Document 3] International Patent Application Publication No. 2021 / 053473 [Patent Document 4] Japanese Patent Application Publication No. 2013-211537 [Non-patent literature]

[0011] [Non-patent document 1] M. Oota et al., “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig., 2019, pp. 50-53 Summary of the invention Technical problem to be solved by the invention

[0012] One of the purposes of one embodiment of the present invention is to provide a storage device that can achieve miniaturization or high integration. Another purpose of one embodiment of the present invention is to provide a storage device with a high operating speed. Another purpose of one embodiment of the present invention is to provide a storage device with good electrical characteristics. Another purpose of one embodiment of the present invention is to provide a storage device with small unevenness in the electrical characteristics of transistors. Another purpose of one embodiment of the present invention is to provide a storage device with high reliability. Another purpose of one embodiment of the present invention is to provide a storage device with a large on-state current. Another purpose of one embodiment of the present invention is to provide a storage device with low power consumption. Another purpose of one embodiment of the present invention is to provide a novel storage device. Another purpose of one embodiment of the present invention is to provide a method for manufacturing a novel storage device.

[0013] Note that the description of these purposes does not prevent the existence of other purposes. Note that one embodiment of the present invention does not necessarily achieve all of the above purposes. Note that purposes other than the above can be known and extracted from the description of the specification, drawings, claims, etc. Solutions to technical problems

[0014] One embodiment of the present invention is a storage device including a first storage unit, a second storage unit, a first insulator, and a second insulator on the first insulator. The first storage unit includes a first capacitor and a first transistor on the first capacitor. The second storage unit includes a second capacitor and a second transistor on the second capacitor. The interval between the first capacitor and the second capacitor is consistent with the interval between the first transistor and the second transistor. The first insulator includes a first opening and a second opening. At least a portion of the first capacitor is arranged in the first opening. At least a portion of the second capacitor is arranged in the second opening. The second insulator includes a third opening and a fourth opening. At least a portion of the first transistor is arranged in the third opening. At least a portion of the second transistor is arranged in the fourth opening. The first opening has an area overlapping with the third opening. The second opening has an area overlapping with the fourth opening. The maximum width of the first opening is different from the maximum width of the third opening. The maximum width of the second opening is different from the maximum width of the fourth opening.

[0015] In the above storage device, preferably, the maximum width of the first opening is larger than the maximum width of the third opening, and the maximum width of the second opening is larger than the maximum width of the fourth opening.

[0016] In the above-mentioned memory device, preferably, a channel length of the first transistor is smaller than a channel width of the first transistor, and a channel length of the second transistor is smaller than a channel width of the second transistor.

[0017] In the above memory device, preferably, the first transistor and the second transistor include an oxide semiconductor in each semiconductor layer, and the oxide semiconductor includes one or more selected from In, Ga, and Zn.

[0018] In the above storage device, preferably, the first capacitor and the second capacitor respectively include a first conductor, a third insulator on the first conductor and a second conductor on the third insulator, and the third insulator includes a first zirconium oxide, aluminum oxide on the first zirconium oxide and a second zirconium oxide on the aluminum oxide.

[0019] Preferably, the storage device comprises a plurality of layers having the first storage unit and the second storage unit, and the plurality of layers are stacked.

[0020] One embodiment of the present invention is a memory device including a first conductor, a memory cell on the first conductor, a first insulator on the first conductor, and a second insulator. The memory cell includes a capacitor and a transistor on the capacitor. The capacitor includes a second conductor, a third insulator on the second conductor, and a third conductor on the third insulator. A first opening portion reaching the first conductor is provided in the first insulator. At least a portion of the second conductor, at least a portion of the third insulator, and at least a portion of the third conductor are arranged in the first opening portion. The second conductor, the third insulator, and the second insulator are arranged on the third conductor. The transistor includes a third conductor, a fourth conductor on the second insulator, an oxide semiconductor, a fourth insulator, and a fifth conductor. A second opening portion reaching the third conductor is provided in the second insulator and the fourth conductor. At least a portion of the oxide semiconductor is arranged in the second opening portion. The oxide semiconductor has a region in the second opening portion that contacts the top surface of the third conductor, a region in the second opening portion that contacts the side surface of the fourth conductor, and a region that contacts at least a portion of the top surface of the fourth conductor. The fourth insulator is arranged on the oxide semiconductor in such a way that at least a portion of it is located in the second opening portion. The fifth conductor is disposed on the fourth insulator so that at least a portion thereof is located in the second opening. The maximum width of the first opening is different from the maximum width of the second opening.

[0021] In the above storage device, the maximum width of the first opening is preferably larger than the maximum width of the second opening.

[0022] In the above storage device, the second opening preferably has a region overlapping with the first opening.

[0023] In the above-mentioned memory device, the channel length of the transistor is preferably smaller than the channel width of the transistor.

[0024] In the above-mentioned memory device, the third insulator preferably includes a material having ferroelectricity.

[0025] In the above-mentioned memory device, the third insulator preferably includes a first zirconium oxide, aluminum oxide on the first zirconium oxide, and a second zirconium oxide on the aluminum oxide.

[0026] In the above memory device, the oxide semiconductor preferably includes any one or more selected from In, Ga, and Zn.

[0027] In the above-mentioned memory device, preferably, the first insulator includes a stacked body including a first layer and a second layer on the first layer, the first layer includes silicon and nitrogen, and the second layer includes silicon and oxygen.

[0028] In the above-mentioned memory device, preferably, a fifth insulator is provided between a side surface of the first insulator in the first opening and the second conductor, and the fifth insulator contains silicon and nitrogen.

[0029] In the above storage device, preferably, the fifth electrical conductor extends in a first direction, the fourth electrical conductor extends in a second direction, and the first direction is orthogonal to the second direction.

[0030] Preferably, the storage device comprises a plurality of layers having storage units, and the plurality of layers are stacked. Effects of the Invention

[0031] According to one embodiment of the present invention, a storage device capable of miniaturization or high integration can be provided. In addition, a storage device with a high operating speed can be provided. In addition, a storage device with high reliability can be provided. In addition, a storage device with small unevenness in the electrical characteristics of transistors can be provided. In addition, a storage device with good electrical characteristics can be provided. In addition, a storage device with a large on-state current can be provided. In addition, a storage device with low power consumption can be provided. In addition, a novel storage device can be provided. In addition, a method for manufacturing a novel storage device can be provided.

[0032] Note that the description of these effects does not prevent the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of the above effects. Note that effects other than the above can be known and extracted from the description of the specification, drawings, claims, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1A is a plan view showing an example of a storage device. Figure 1B and Figure 1C is a cross-sectional view showing an example of a storage device. Figure 1D is a circuit diagram illustrating an example of the structure of a storage device. Figure 2A is a plan view showing an example of a storage device. Figure 2B and Figure 2Cis a cross-sectional view showing an example of a storage device. Figure 3A is a plan view showing an example of a storage device. Figure 3B and Figure 3C is a cross-sectional view showing an example of a storage device. Figure 4A and Figure 4B is a plan view showing an example of a storage device. Figure 5A is a plan view showing an example of a storage device. Figure 5B and Figure 5C is a cross-sectional view showing an example of a storage device. FIG. 6A to FIG. 6D is a cross-sectional view showing an example of a storage device. Fig. 7A is a plan view showing an example of a storage device. Figure 7B and Figure 7C is a cross-sectional view showing an example of a storage device. Fig. 8A is a plan view showing an example of a storage device. Figure 8B and Figure 8C is a cross-sectional view showing an example of a storage device. Fig.9A is a plan view showing an example of a storage device. Fig. 9B and Fig. 9C is a cross-sectional view showing an example of a storage device. Fig. 10A is a plan view showing an example of a storage device. Fig. 10B and Fig. 10C is a cross-sectional view showing an example of a storage device. Fig.11A is a plan view showing an example of a storage device. Fig. 11B and Fig. 11C is a cross-sectional view showing an example of a storage device. FIG. 12A to FIG. 12D is a cross-sectional view showing an example of a storage device. Fig.13A is a cross-sectional view showing an example of a storage device. Fig. 13B is a cross-sectional view showing an example of a storage device. FIG. 14A to FIG. 14D is a cross-sectional view showing an example of a storage device. Fig.15A is a plan view showing an example of a storage device. Fig. 15B and Fig. 15C is a cross-sectional view showing an example of a storage device. Fig.16A and Fig. 16B is a cross-sectional view showing an example of a storage device. 17A to 17D is a cross-sectional view showing an example of a storage device. Fig.18A and Fig.18B is a cross-sectional view showing an example of a storage device. Fig.19A is a plan view showing an example of a storage device. Fig.19B and Fig.19C is a cross-sectional view showing an example of a storage device. Fig. 20A is a plan view showing an example of a storage device. Fig. 20B and Fig. 20C is a cross-sectional view showing an example of a storage device. Fig.21A is a plan view showing an example of a storage device. Fig. 21B and Fig. 21C is a cross-sectional view showing an example of a storage device. Fig.22A This is a plan view showing an example of a method for manufacturing a storage device. Fig. 22B and Fig. 22C is a cross-sectional view showing an example of a method for manufacturing a storage device. Fig.23A This is a plan view showing an example of a method for manufacturing a storage device. Fig. 23B and Fig.23C is a cross-sectional view showing an example of a method for manufacturing a storage device. Fig.24A This is a plan view showing an example of a method for manufacturing a storage device. Fig. 24B and Fig.24C is a cross-sectional view showing an example of a method for manufacturing a storage device. Fig.25A This is a plan view showing an example of a method for manufacturing a storage device. Fig.25B and Fig.25C is a cross-sectional view showing an example of a method for manufacturing a storage device. Fig.26A This is a plan view showing an example of a method for manufacturing a storage device. Fig.26B and Fig.26C is a cross-sectional view showing an example of a method for manufacturing a storage device. Fig.27A This is a plan view showing an example of a method for manufacturing a storage device. Fig.27B and Fig.27C is a cross-sectional view showing an example of a method for manufacturing a storage device. Fig.28AThis is a plan view showing an example of a method for manufacturing a storage device. Fig.28B and Fig.28C is a cross-sectional view showing an example of a method for manufacturing a storage device. Fig.29A This is a plan view showing an example of a method for manufacturing a storage device. Fig.29B and Fig.29C is a cross-sectional view showing an example of a method for manufacturing a storage device. Fig. 30A This is a plan view showing an example of a method for manufacturing a storage device. Fig. 30B and Fig. 30C is a cross-sectional view showing an example of a method for manufacturing a storage device. Fig.31A This is a plan view showing an example of a method for manufacturing a storage device. Fig.31B and Fig. 31C is a cross-sectional view showing an example of a method for manufacturing a storage device. Fig.32A This is a plan view showing an example of a method for manufacturing a storage device. Fig.32B and Fig.32C is a cross-sectional view showing an example of a method for manufacturing a storage device. Fig.33A This is a plan view showing an example of a method for manufacturing a storage device. Fig.33B and Fig.33C is a cross-sectional view showing an example of a method for manufacturing a storage device. Fig.34A This is a plan view showing an example of a method for manufacturing a storage device. Fig.34B and Fig.34C is a cross-sectional view showing an example of a method for manufacturing a storage device. Fig.35A This is a plan view showing an example of a method for manufacturing a storage device. Fig.35B and Fig.35C is a cross-sectional view showing an example of a method for manufacturing a storage device. Fig.36A This is a plan view showing an example of a method for manufacturing a storage device. Fig.36B and Fig.36C is a cross-sectional view showing an example of a method for manufacturing a storage device. Fig.37A This is a plan view showing an example of a method for manufacturing a storage device. Fig.37B and Fig.37C is a cross-sectional view showing an example of a method for manufacturing a storage device. Fig.38A This is a plan view showing an example of a method for manufacturing a storage device. Fig.38B and Fig.38C is a cross-sectional view showing an example of a method for manufacturing a storage device. Fig.39A is a plan view showing an example of a storage device. Fig.39B is a cross-sectional view showing an example of a storage device. Fig.40A is a plan view showing an example of a storage device. Fig.40B is a cross-sectional view showing an example of a storage device. Fig.41A is a plan view showing an example of a storage device. Fig.41B is a cross-sectional view showing an example of a storage device. FIG. 42A to FIG. 42C FIG. 1 is a planar layout showing an example of a storage device. FIG. 43A to FIG. 43C FIG. 1 is a planar layout showing an example of a storage device. Fig.44 is a cross-sectional view showing an example of a storage device. Fig.45 is a block diagram showing an example of a storage device. Fig.46A and Fig.46B is a schematic diagram showing an example of a storage device. FIG. 47A to FIG. 47D is a circuit diagram showing an example of a storage device. Fig.48 is a circuit diagram showing an example of a storage device. Fig.49A and Fig.49B This is a diagram showing an example of an electronic component. Fig.50A and Fig.50B is a diagram showing an example of an electronic device. FIG. 50C to FIG. 50E This is a diagram showing an example of a large computer. Fig.51 is a diagram showing an example of space equipment. Fig.52 This is a diagram showing an example of a storage system that can be applied to a data center. Modes for Carrying Out the Invention

[0034] The following describes the embodiments with reference to the accompanying drawings. It should be noted that a person skilled in the art can easily understand that the embodiments can be implemented in a variety of different forms, and the methods and details can be transformed into various forms without departing from the purpose and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the embodiments shown below.

[0035] In addition, in the drawings, the size, thickness of the layer or the area are sometimes exaggerated for obvious reasons. Therefore, the present invention is not limited to the dimensions in the drawings. In addition, in the drawings, ideal examples are schematically shown, and therefore the shapes or numerical values ​​shown in the drawings are not limited. For example, in the actual manufacturing process, layers or resist masks are sometimes unintentionally thinned due to treatments such as etching, but this is sometimes not reflected in the drawings for ease of understanding. In addition, in the drawings, the same symbols are sometimes used in common between different drawings to represent the same parts or parts with the same function, and their repeated descriptions are omitted. In addition, when representing parts with the same function, the same hatching is sometimes used without special additional symbols.

[0036] In addition, in particular, in a plan view (also referred to as a “top view”) or a perspective view, some components may be omitted to facilitate understanding of the invention. In addition, some hidden lines may be omitted.

[0037] In addition, in this specification, for the sake of convenience, ordinal numbers such as first and second are added, but they do not indicate the order of processes or the order of stacking. Therefore, for example, "first" can be appropriately replaced with "second" or "third" for description. In addition, the ordinal numbers recorded in this specification and the like are sometimes inconsistent with the ordinal numbers used to specify one embodiment of the present invention.

[0038] In addition, in this specification, for the sake of convenience, words and phrases indicating configuration such as "upper" and "lower" are used to explain the positional relationship of the components with reference to the drawings. In addition, the positional relationship of the components is appropriately changed according to the direction in which each component is described. Therefore, the words and phrases described in the specification are not limited, and the words and phrases can be appropriately changed according to the situation.

[0039] For example, in this specification, etc., X and Y are connected, which means that X and Y are electrically connected. Here, X and Y are electrically connected, which means that an electric signal can be transmitted between X and Y when an object (element such as a switch, transistor element or diode, or a circuit including the element and wiring, etc.) exists between X and Y. Note that the case where X and Y are electrically connected includes the case where X and Y are directly connected. Here, X and Y are directly connected, which means that X and Y can transmit an electric signal between X and Y through wiring (or electrodes) without passing through the above-mentioned object. In other words, direct connection means a connection that can be regarded as the same circuit diagram when expressed using an equivalent circuit.

[0040] In addition, in this specification, etc., a transistor refers to an element including at least three terminals: a gate, a drain, and a source. Furthermore, a transistor has a region (hereinafter also referred to as a channel formation region) where a channel is formed between a drain (drain terminal, a drain region, or a drain electrode) and a source (source terminal, a source region, or a source electrode), and current can flow between the source and the drain through the channel formation region. Note that in this specification, etc., a channel formation region refers to a region where current mainly flows.

[0041] In addition, when transistors with different polarities are used or when the direction of current changes during circuit operation, the functions of the source and drain may be interchanged. Therefore, in this specification, the source and drain may be interchanged.

[0042] Note that the impurities of a semiconductor refer to, for example, elements other than the main components that constitute the semiconductor. For example, an element with a concentration lower than 0.1 atomic % can be said to be an impurity. When impurities are contained, for example, the defect state density of the semiconductor may increase, the crystallinity may decrease, etc. may occur. When the semiconductor is an oxide semiconductor, the impurities that change the properties of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor. For example, there are hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc. In addition, water sometimes acts as an impurity. In addition, for example, sometimes the mixing of impurities leads to oxygen vacancies (also called V O : The formation of oxygenvacancy).

[0043] Note that in this specification, etc., oxynitride refers to a substance containing more oxygen than nitrogen in its composition. Examples of oxynitride include silicon oxynitride, aluminum oxynitride, and hafnium oxynitride. In addition, oxynitride refers to a substance containing more nitrogen than oxygen in its composition. Examples of oxynitride include silicon oxynitride, aluminum oxynitride, and hafnium oxynitride.

[0044] In this specification, the term "insulator" may be referred to as an insulating film or insulating layer, the term "conductor" may be referred to as a conductive film or conductive layer, and the term "semiconductor" may be referred to as a semiconductor film or semiconductor layer.

[0045] In addition, in this specification, etc., "parallel" refers to a state where the angle formed by two straight lines is greater than -10 degrees and less than 10 degrees. Therefore, a state where the angle is greater than -5 degrees and less than 5 degrees is also included. In addition, "approximately parallel" refers to a state where the angle formed by two straight lines is greater than -30 degrees and less than 30 degrees. In addition, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80 degrees and less than 100 degrees. Therefore, a state where the angle is greater than 85 degrees and less than 95 degrees is also included. In addition, "approximately perpendicular" refers to a state where the angle formed by two straight lines is greater than 60 degrees and less than 120 degrees.

[0046] In addition, in this specification, "voltage" and "potential" can be appropriately interchanged. "Voltage" refers to the potential difference from the reference potential. For example, when the reference potential is the ground potential (ground potential), "voltage" can also be replaced with "potential". Note that the ground potential does not necessarily mean 0V. In addition, potential is relative, and the potential supplied to the wiring, the potential applied to the circuit, the potential output from the circuit, etc., etc., also changes according to the change of the reference potential.

[0047] In this specification and the like, when the same symbol is used for a plurality of components and it is necessary to distinguish them, a symbol for identification such as “_1”, “[n]”, or “[m, n]” may be added to the symbol.

[0048] Note that in this specification, etc., "high consistency" refers to a structure in which the height from the reference surface (for example, a flat surface such as a substrate surface) in a cross section is equal. For example, in the manufacturing process of a storage device, a flattening process (typically a CMP (Chemical Mechanical Polishing) process) is sometimes performed to expose the surface of a single layer or multiple layers. In this case, the height of the processed surface treated by CMP is equal to the height of the reference surface. Note that depending on the processing device, processing method or material of the processed surface during the CMP process, the height of multiple layers is sometimes different. In this specification, etc., "high consistency" also includes the above situation. For example, in the case of a layer having two heights relative to the reference surface (referred to as the first layer and the second layer here), when the difference between the height of the top surface of the first layer and the height of the top surface of the second layer is less than 20nm, it is also referred to as "high consistency".

[0049] Note that in this specification, etc., "ends are consistent" refers to a situation where at least a portion of the contours of the stacked layers overlap when viewed from a plane. For example, this includes a situation where the upper layer and the lower layer are processed by using the same mask pattern or a portion of them is processed by using the same mask pattern. However, strictly speaking, sometimes the contours do not overlap and the contour of the upper layer is located inside the contour of the lower layer or the contour of the upper layer is located outside the contour of the lower layer. These situations can also be said to be "ends consistent".

[0050] Note that, in general, it is difficult to clearly distinguish between “completely consistent” and “substantially consistent.” Therefore, in this specification and the like, “consistent” includes both completely consistent and substantially consistent.

[0051] Note that in this specification, etc., the normally-on characteristic refers to a state in which a channel exists and current flows through a transistor even when no potential is applied to the gate. Also, the normally-off characteristic refers to a state in which current does not flow through a transistor when no voltage is applied to the gate or when a ground potential is supplied to the gate.

[0052] In addition, in this specification, off-state current may be referred to as leakage current. In addition, in this specification, off-state current may refer to current flowing between a source and a drain when a transistor is in an off state, for example.

[0053] (Implementation Method 1) In this embodiment, referring to FIGS. 1 to Fig.44 An example of a memory device according to one embodiment of the present invention and a method for manufacturing the same will be described. A memory device according to one embodiment of the present invention includes one or more memory cells. The memory cell includes a transistor and a capacitor.

[0054] <Configuration Example of Storage Device> The structure of a storage device according to one embodiment of the present invention will be described with reference to FIG. 1 . Figures 1A to 1C 1 and 2 are a plan view and a cross-sectional view of a memory device including a memory cell 150 . Figure 1A is a plan view of the storage device. In addition, Figure 1B and Figure 1C is a cross-sectional view of the storage device. Figure 1B It is along Figure 1A A cross-sectional view of the portion along the dot-dash line A1-A2 in FIG. Figure 1C It is along Figure 1A The cross-sectional view of the portion along the dashed line A3-A4 in FIG. Figure 1A In the plan view, some components are omitted for clarity.

[0055] Note that arrows indicating the X direction, Y direction, and Z direction are sometimes attached in the drawings of this specification. Note that in this specification, "X direction" refers to the direction along the X axis, and sometimes the forward and reverse directions are not distinguished except for the cases clearly stated. The same applies to "Y direction" and "Z direction". In addition, the X direction, Y direction, and Z direction are directions that intersect each other. For example, the X direction, Y direction, and Z direction are directions that are orthogonal to each other. In this specification, the X direction, Y direction, or Z direction is sometimes referred to as the "first direction". In addition, the other one is sometimes referred to as the "second direction". In addition, the remaining one is sometimes referred to as the "third direction".

[0056] Figures 1A to 1C The memory device shown includes: an insulator 140 on a substrate (not shown); a conductor 110 on the insulator 140; a memory cell 150 on the conductor 110; an insulator 180 on the conductor 110; an insulator 280 on the insulator 180; and an insulator 283 on the memory cell 150. The insulator 140, the insulator 180, the insulator 280, and the insulator 283 are used as interlayer films. The conductor 110 is used as wiring.

[0057] The memory cell 150 includes a capacitor 100 on a conductor 110 and a transistor 200 on the capacitor 100 .

[0058] The capacitor 100 includes a conductor 115 on a conductor 110, an insulator 130 on the conductor 115, and a conductor 120 on the insulator 130. The conductor 120 is used as one of a pair of electrodes (sometimes referred to as an upper electrode), the conductor 115 is used as the other of the pair of electrodes (sometimes referred to as a lower electrode), and the insulator 130 is used as a dielectric. That is, the capacitor 100 constitutes a MIM (Metal-Insulator-Metal) capacitor.

[0059] like Figure 1B and Figure 1C As shown, the insulator 180 is provided with an opening 190 that reaches the conductor 110. At least a portion of the capacitor 100 is disposed in the opening 190. Specifically, at least a portion of the conductor 115, at least a portion of the insulator 130, and at least a portion of the conductor 120 are disposed in the opening 190. Note that the conductor 115 has a region that contacts the top surface of the conductor 110 in the opening 190, a region that contacts the side surface of the insulator 180 in the opening 190, and a region that contacts at least a portion of the top surface of the insulator 180. In addition, as shown in FIG. Figure 1B and Figure 1C As shown, the conductor 120 is preferably provided in a manner embedded in the opening 190 .

[0060] The capacitor 100 has a structure in which the upper electrode and the lower electrode are opposed to each other through a dielectric body in the opening 190 not only on the bottom surface but also on the side surface, so that the electrostatic capacitance per unit area can be increased. Thus, the deeper the depth of the opening 190, the greater the electrostatic capacitance of the capacitor 100 can be. In this way, by increasing the electrostatic capacitance per unit area of ​​the capacitor 100, the read operation of the storage device can be stabilized. In addition, the miniaturization or high integration of the storage device can be promoted.

[0061] The side wall of the opening 190 is preferably perpendicular to the top surface of the conductor 110. In this case, the opening 190 has a cylindrical shape. By adopting such a structure, miniaturization or high integration of the storage device can be achieved.

[0062] Note that this embodiment shows an example in which the shape of the opening 190 when viewed from a plane is circular, but the present invention is not limited to this. For example, the shape of the opening 190 when viewed from a plane may be a substantially circular shape such as an ellipse, a polygonal shape such as a quadrangle, or a shape in which the corners of a polygon such as a quadrangle are curved. In this case, the maximum width of the opening 190 may be appropriately calculated based on the shape of the uppermost portion of the opening 190. For example, when the shape of the opening when viewed from a plane is a quadrangle, the maximum width of the opening 190 is preferably the length of the diagonal line of the uppermost portion of the opening 190.

[0063] The portions of the conductor 115, the insulator 130, and the conductor 120 disposed in the opening 190 reflect the shape of the opening 190. Therefore, the conductor 115 is disposed so as to cover the bottom and side walls of the opening 190, the insulator 130 is disposed so as to cover the conductor 115, and the conductor 120 is disposed so as to fit into the recess of the insulator 130 reflecting the shape of the opening 190.

[0064] Conductor 115 and insulator 130 are stacked along the sidewalls of opening 190 and the top surface of conductor 110. Conductor 120 is provided on insulator 130 so as to be embedded in opening 190. Capacitor 100 having such a structure may be referred to as a trench capacitor or trench capacitor.

[0065] The insulator 280 is disposed on the capacitor 100 . That is, the insulator 280 is disposed on the conductor 115 , the insulator 130 , and the conductor 120 . In other words, the conductor 120 is disposed under the insulator 280 .

[0066] The transistor 200 includes a conductor 120, a conductor 240 on an insulator 280, an oxide semiconductor 230, an insulator 250 on the oxide semiconductor 230, and a conductor 260 on the insulator 250. The oxide semiconductor 230 is used as a semiconductor layer, the conductor 260 is used as a gate electrode, the insulator 250 is used as a gate insulator, the conductor 120 is used as one of a source electrode and a drain electrode, and the conductor 240 is used as the other of the source electrode and the drain electrode.

[0067] like Figure 1B and Figure 1C As shown, an opening 290 that reaches the conductor 120 is provided in the insulator 280 and the conductor 240. That is, the opening 290 is composed of an opening provided in the insulator 280 and an opening provided in the conductor 240. At this time, the side end of the opening provided in the insulator 280 and the side end of the opening provided in the conductor 240 are preferably consistent.

[0068] At least a portion of the oxide semiconductor 230 is disposed in the opening 290. In addition, the oxide semiconductor 230 has a region in contact with the top surface of the conductor 120 in the opening 290, a region in contact with the side surface of the conductor 240 in the opening 290, and a region in contact with at least a portion of the top surface of the conductor 240. The insulator 250 is disposed so that at least a portion thereof is located in the opening 290. The conductor 260 is disposed so that at least a portion thereof is located in the opening 290. In addition, as Figure 1B and Figure 1C As shown, the conductor 260 is preferably provided in a manner embedded in the opening 290 .

[0069] The oxide semiconductor 230 has a region in contact with the side surface of the conductor 240 and a region in contact with a portion of the top surface of the conductor 240 in the opening 290. In this way, since the oxide semiconductor 230 is in contact with the top surface of the conductor 240 in addition to the side surface, the contact area between the oxide semiconductor 230 and the conductor 240 can be increased.

[0070] like Figures 1A to 1CAs shown, the transistor 200 overlaps with the capacitor 100. In addition, the opening 290 in which a part of the structure of the transistor 200 is provided has an area overlapping with the opening 190 in which a part of the structure of the capacitor 100 is provided. In addition, the conductor 120 is used as one of the source electrode and the drain electrode of the transistor 200 and is used as the upper electrode of the capacitor 100, so the transistor 200 and the capacitor 100 share part of the structure. By adopting this structure, the transistor 200 and the capacitor 100 can be arranged in a manner that does not significantly increase the occupied area when viewed from a plane. As a result, the occupied area of ​​the memory cell 150 can be reduced, so the memory cell 150 can be arranged at a high density to increase the storage capacity of the storage device. In other words, high integration of the storage device can be achieved.

[0071] Figure 1D 2 is a circuit diagram of a storage device shown in this embodiment. Figure 1D As shown, Figures 1A to 1C The structure shown is used as a memory cell of a memory device. The memory cell includes a transistor Tr and a capacitor C. Here, the transistor Tr corresponds to the transistor 200, and the capacitor C corresponds to the capacitor 100.

[0072] One of the source and drain of the transistor Tr is connected to one of the pair of electrodes of the capacitor C. The other of the source and drain of the transistor Tr is connected to the wiring BL. The gate of the transistor Tr is connected to the wiring WL. The other of the pair of electrodes of the capacitor C is connected to the wiring PL.

[0073] Here, the wiring BL corresponds to the conductor 240, the wiring WL corresponds to the conductor 260, and the wiring PL corresponds to the conductor 110. Figures 1A to 1C As shown in FIG. 1 , it is preferred that the conductor 260 extends in the Y direction and the conductor 240 extends in the X direction. By adopting this structure, the wiring BL and the wiring WL intersect each other. By the wiring BL and the wiring WL intersecting each other, the area of ​​the wiring BL and the wiring WL overlapping each other becomes smaller, and the parasitic capacitance generated between the wiring BL and the wiring WL can be reduced. In addition, Figure 1A The wiring PL (conductor 110) is provided in a planar shape, but the present invention is not limited thereto. For example, the wiring PL may be parallel to the wiring WL (conductor 260) or the wiring BL (conductor 240).

[0074] FIG. 2A to FIG. 2C The structure in which the conductor 110 extends in the Y direction is shown. At this time, the conductor 110 is parallel to the conductor 260. In addition, the conductor 110 and the conductor 240 are perpendicular to each other.

[0075] FIG. 3A to FIG. 3CThe structure in which the conductor 110 extends in the X direction is shown. At this time, the conductor 110 is parallel to the conductor 240. In addition, the conductor 110 and the conductor 260 are perpendicular to each other.

[0076] Figure 1B The structure in which the conductor 115 is separated in the X direction is shown, but the present invention is not limited thereto. Figure 3A and Figure 3B As shown, the conductor 115 may extend in the X direction. In addition, in a structure in which the conductor 110 is provided in a planar shape, the conductor 115 may extend in the X direction and the Y direction.

[0077] Note that the storage unit will be described in detail in a later embodiment.

[0078] In addition, the storage device of one embodiment of the present invention preferably includes a plurality of storage cells 150 arranged in a matrix. As an example, Figure 4A and Figure 4B An example of a storage device is shown in which 2×2 memory cells 150 are arranged in a matrix in the X direction and the Y direction.

[0079] Figure 4A is a plan view of a region including four transistors (transistor 200p to transistor 200s). Figure 4A The conductor 120, the oxide semiconductor 230, the conductor 240, the conductor 260, and the opening 290 included in each transistor are summarized. Note that the opening 290 provided in the insulator 280 and the conductor 240 is indicated by a dotted line. Figure 4A The insulator 280 is not shown in the figure.

[0080] exist Figure 4A , the conductor 240 and the insulator 280 include an opening 290p, an opening 290q, an opening 290r, and an opening 290s. At least a portion of the transistor 200p is disposed in the opening 290p, at least a portion of the transistor 200q is disposed in the opening 290q, at least a portion of the transistor 200r is disposed in the opening 290r, and at least a portion of the transistor 200s is disposed in the opening 290s.

[0081] Figure 4B is a plan view of a region including four capacitors (capacitor 100p to capacitor 100s). Figure 4B The conductor 110, the conductor 115, the conductor 120 and the opening 190 included in each capacitor are summarized. Note that the opening 190 provided in the insulator 180 is shown by a dotted line. Figure 4B The insulator 180 is not shown in the figure.

[0082] exist Figure 4B In the embodiment, the insulator 180 includes an opening 190p, an opening 190q, an opening 190r, and an opening 190s. At least a portion of the capacitor 100p is disposed in the opening 190p, at least a portion of the capacitor 100q is disposed in the opening 190q, at least a portion of the capacitor 100r is disposed in the opening 190r, and at least a portion of the capacitor 100s is disposed in the opening 190s.

[0083] The transistor 200p and the capacitor 100p form one memory cell, the transistor 200q and the capacitor 100q form one memory cell, the transistor 200r and the capacitor 100r form one memory cell, and the transistor 200s and the capacitor 100s form one memory cell. In addition, the opening 190p has a region overlapping with the opening 290p, the opening 190q has a region overlapping with the opening 290q, the opening 190r has a region overlapping with the opening 290r, and the opening 190s has a region overlapping with the opening 290s.

[0084] The structures of transistors 200p to 200s can refer to the description of transistor 200. The structures of capacitors 100p to 100s can refer to the description of capacitor 100. In addition, the opening 190 is sometimes referred to as the opening 190p to 190s to describe the common contents between the openings 190p to 190s. In addition, the opening 290 is sometimes referred to as the opening 290p to 290s to describe the common contents between the openings 290p to 290s.

[0085] exist Figure 4A In FIG. 2 , the double solid arrow indicates the maximum width Dt of the opening 290. Note that when the opening is circular when viewed from a plane, the maximum width of the opening can also be referred to as the maximum diameter of the opening. Figure 4B In FIG. 1 , the maximum width Dc of the opening 190 is indicated by a solid double arrow.

[0086] In addition, Figure 4A In the figure, the double arrow with a double dotted line indicates the distance GPt between transistors adjacent in the X direction. For example, the distance GPt is the distance between the transistors 200 arranged in the X direction. In addition, the distance GPt is the distance between the transistors 200p and 200q. Here, the distance GPt can be said to be the distance between the centers of the openings 290 adjacent in the X direction. In addition, the distance GPt can be said to be the distance between the conductors 260 arranged as the wiring WL. Therefore, the distance GPt can be replaced by the gate pitch. In addition, in Figure 4BThe double arrows with double dotted lines in the figure represent the distance GPc between the capacitors adjacent in the X direction. For example, the distance GPc is the interval between the capacitors 100 arranged in the X direction. In addition, the distance GPc is the interval between the capacitors 100p and 100q. Here, the distance GPc can be said to be the distance between the centers of the openings 190 adjacent in the X direction.

[0087] In addition, Figure 4A In the figure, the distance MPt between transistors adjacent to each other in the Y direction is represented by a double-dash arrow. For example, the distance MPt is the spacing between transistors 200 configured in the Y direction. In addition, the distance MPt is the spacing between transistors 200p and 200r. Here, the distance MPt can be said to be the distance between the centers of openings 290 adjacent to each other in the Y direction. In addition, the distance MPt can be said to be the spacing between conductors 240 configured as wiring BL. Therefore, the distance MPt can be replaced by the metal pitch. In addition, in Figure 4B The double-pointed arrow in the figure indicates the distance MPc between the capacitors adjacent in the Y direction. For example, the distance MPc is the interval between the capacitors 100 arranged in the Y direction. In addition, the distance MPc is the interval between the capacitors 100p and 100r. Here, the distance MPc can be said to be the distance between the centers of the openings 190 adjacent in the Y direction.

[0088] like Figure 4A As shown in FIG. 1 , the opening 290 is provided so as to overlap with the conductor 120. Figure 4B As shown, the opening 190 is provided so as to overlap with the conductor 110 .

[0089] The maximum widths of the opening 190 and the opening 290 are preferably different. Specifically, the maximum width Dc of the opening 190 is preferably different from the maximum width Dt of the opening 290. In particular, the maximum width Dc of the opening 190 is preferably larger than the maximum width Dt of the opening 290. By adopting this structure, the electrostatic capacitance of the capacitor 100 can be increased. In addition, by increasing the maximum width Dc of the opening 190, the conductor 115, the insulator 130 and the conductor 120 can be reliably embedded in the opening 190, thereby providing a storage device with good reliability. In addition, the area of ​​the conductor 120 when viewed from a plane can be increased, so that the position alignment accuracy of the opening 290 is relaxed. Therefore, the difficulty in manufacturing the micro storage unit can be reduced.

[0090] In addition to the above, the distance GPc is preferably consistent with the distance GPt. In addition, the distance MPc is preferably consistent with the distance MPt. By adopting this structure, the electrostatic capacitance can be increased without increasing the occupied area of ​​the storage unit. Therefore, the read operation of the storage device can be stabilized. In addition, a storage device that can achieve miniaturization or high integration can be provided.

[0091] In this specification, etc., the distance A and the distance B are equal to each other when the absolute value of the difference between the distance A and the distance B is divided by the distance A and is less than 0.1. Alternatively, the distance A and the distance B are equal to each other when the absolute value of the difference between the distance A and the distance B is divided by the distance B and is less than 0.1.

[0092] Note that the distance GPc and the distance GPt may be consistent and the distance MPc and the distance MPt may be consistent, but the distance GPc and the distance MPc may not be consistent. Similarly, the distance GPt and the distance MPt may not be consistent.

[0093] As an example, the conductor 260 is a continuous film provided in common to the transistors 200 arranged in the Y direction. Also, as an example, the conductor 240 is a continuous film provided in common to the transistors 200 arranged in the X direction.

[0094] The above shows an example in which the maximum width of opening 190 is larger than the maximum width of opening 290. In one embodiment of the present invention, the maximum width of opening 190 is preferably different from the maximum width of opening 290, so the maximum width of opening 190 may be smaller than the maximum width of opening 290. In other words, the maximum width of opening 290 may be larger than the maximum width of opening 190. FIG. 5A to FIG. 5C The example in which the maximum width of the opening 290 is larger than the maximum width of the opening 190 is shown. By increasing the maximum width of the opening 290, the channel width per unit area can be increased and the on-state current can be increased. As a result, the read speed and write speed of the memory cell 150 can be increased, so a memory device with a high operating speed can be provided.

[0095] [Capacitor 100] The capacitor 100 includes a conductor 115, an insulator 130, and a conductor 120. The conductor 110 is provided below the conductor 115. The conductor 115 has a region in contact with the conductor 110.

[0096] The conductor 110 is provided on the insulator 140. The conductor 110 is used as the wiring PL, and can be provided in a planar shape, for example. As the conductor 110, a single layer or a stack of conductors described in [Conductor] to be described later can be used. As the conductor 110, for example, a highly conductive conductive material such as tungsten can be used. By using a highly conductive conductive material in this way, the conductivity of the conductor 110 can be improved, so that the conductor 110 can fully function as the wiring PL.

[0097] As the conductor 115, it is preferred to use a conductive material that is not easily oxidized or a conductive material that has a function of inhibiting oxygen diffusion in a single layer or a stacked layer. For example, titanium nitride or indium tin oxide with silicon added thereto may be used. Alternatively, for example, a structure may be provided in which titanium nitride is stacked on tungsten. Alternatively, for example, a structure may be provided in which tungsten is stacked on a first titanium nitride and a second titanium nitride is stacked on the tungsten. By adopting such a structure, when an oxide insulator is used as the insulator 130, oxidation of the conductor 110 due to the insulator 130 can be suppressed. In addition, when an oxide insulator is used as the insulator 180, oxidation of the conductor 110 due to the insulator 180 can be suppressed.

[0098] The insulator 130 is provided on the conductor 115. The insulator 130 is provided in contact with the top surface and the side surface of the conductor 115. That is, the insulator 130 preferably covers the side end portion of the conductor 115. Thus, the conductor 110 and the conductor 120 can be prevented from being short-circuited.

[0099] It is preferable to use a material having a high relative dielectric constant, i.e., a so-called high-k material, as described in [Insulator] described later as the insulator 130. By using the high-k material as the insulator 130, the thickness of the insulator 130 can be increased to a level that can suppress leakage current and the electrostatic capacitance of the capacitor 100 can be sufficiently ensured.

[0100] In addition, as the insulator 130, it is preferred to stack an insulating layer composed of a high-k material, and it is preferred to use a stacked structure of a material with a high relative dielectric constant (high-k) and a material with a dielectric strength greater than that of the high-k material. For example, as the insulator 130, an insulating film in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked in sequence can be used. In addition, for example, an insulating film in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are stacked in sequence can be used. In addition, for example, an insulating film in which hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide are stacked in sequence can be used. By stacking an insulator with a relatively large dielectric strength such as aluminum oxide, the dielectric strength can be increased and the electrostatic destruction of the capacitor 100 can be suppressed.

[0101] In addition, a material having ferroelectricity may be used as the insulator 130. Examples of the material having ferroelectricity include hafnium oxide, zirconium oxide, HfZrO X (X is a real number greater than 0) and other metal oxides. In addition, as a material that can have ferroelectricity, a material in which an element J1 (herein, the element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to hafnium oxide can be cited. Here, the ratio of the number of atoms of hafnium to the number of atoms of element J1 can be appropriately set. For example, the ratio of the number of atoms of hafnium to the number of atoms of element J1 can be set to 1:1 or thereabouts. In addition, as a material that can have ferroelectricity, a material in which an element J2 (herein, the element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to zirconium oxide can be cited. In addition, the ratio of the number of atoms of zirconium to the number of atoms of element J2 can be appropriately set. For example, the ratio of the number of atoms of zirconium to the number of atoms of element J2 can be set to 1:1 or thereabouts. In addition, as a material that can have ferroelectricity, lead titanate (PbTiO X ), barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), barium titanate and other piezoelectric ceramics with perovskite structure.

[0102] In addition, as a material that can have ferroelectricity, a metal nitride containing an element M1, an element M2 and nitrogen can be cited. Here, the element M1 is one or more selected from aluminum, gallium, indium, etc. In addition, the element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. In addition, the atomic number ratio of the element M1 to the element M2 can be appropriately set. In addition, a metal oxide containing the element M1 and nitrogen sometimes has ferroelectricity even if it does not contain the element M2. In addition, as a material that can have ferroelectricity, a material in which the element M3 is added to the above-mentioned metal nitride can be cited. Note that the element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, etc. In addition, the atomic number ratio of the element M1, the element M2 and the element M3 can be appropriately set.

[0103] In addition, as materials that can have ferroelectricity, there can be mentioned perovskite-type oxynitrides such as SrTaO2N and BaTaO2N, and GaFeO3 of κ-type alumina.

[0104] Note that although the above description shows examples of metal oxides and metal nitrides, the present invention is not limited thereto and, for example, metal oxynitrides obtained by adding nitrogen to the above metal oxides or metal nitride oxides obtained by adding oxygen to the above metal nitrides may also be used.

[0105] In addition, as a material that can have ferroelectricity, for example, a mixture or compound composed of a plurality of materials selected from the above materials can be used. In addition, the insulator 130 can have a stacked structure composed of a plurality of materials selected from the above materials. Note that the crystal structure (properties) of the materials listed above may change not only depending on the deposition conditions but also depending on various processes, and thus in this specification, etc., a material that exhibits ferroelectricity is referred to not only as a ferroelectric but also as a material that can have ferroelectricity.

[0106] Metal oxides containing one or both of hafnium and zirconium are preferred because they can have ferroelectricity even if they are processed into a thin film of a few nm. Here, the thickness of the insulator 130 can be less than 100 nm, preferably less than 50 nm, more preferably less than 20 nm, and further preferably less than 10 nm (typically, more than 2 nm and less than 9 nm). For example, the thickness is preferably more than 8 nm and less than 12 nm. By using a ferroelectric layer that can be thin-filmed, the capacitor 100 can be combined with semiconductor elements such as miniaturized transistors to form a semiconductor device. Note that in this specification, etc., a material that can have ferroelectricity and is formed in a layered state is sometimes referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. In addition, in this specification, etc., a device including a ferroelectric layer, a metal oxide film, or a metal nitride film is sometimes referred to as a ferroelectric device.

[0107] In addition, a metal oxide containing one or both of hafnium and zirconium is preferred because it has ferroelectricity even when its area is small. For example, even if the area (occupied area) of the ferroelectric layer when viewed from a plane is 100 μm 2 Below, 10μm 2 Below, 1μm 2 Below or 0.1μm 2 The following may also have ferroelectric properties. In addition, sometimes the ferroelectric layer has an area (occupied area) of 10000nm when viewed from a plane. 2 Below or 1000nm 2 The area occupied by the capacitor 100 can be reduced by reducing the area of ​​the ferroelectric layer.

[0108] Ferroelectrics are insulators that are polarized internally when exposed to an external electric field and that maintain polarization even when the electric field is zero. Therefore, a nonvolatile memory element can be formed by using a capacitor (hereinafter sometimes referred to as a ferroelectric capacitor) that uses the material as a dielectric. Nonvolatile memory elements using ferroelectric capacitors are sometimes referred to as FeRAM (Ferroelectric Random Access Memory), ferroelectric memories, and the like. For example, a ferroelectric memory includes a transistor and a ferroelectric capacitor, and one of the source and drain of the transistor is electrically connected to a terminal of the ferroelectric capacitor. Thus, in the case where a ferroelectric capacitor is used as the capacitor 100, the storage device shown in this embodiment is used as a ferroelectric memory.

[0109] In addition, ferroelectricity is considered to be exhibited because oxygen or nitrogen of the crystal contained in the ferroelectric layer is displaced by the action of an external electric field. In addition, the exhibiting of ferroelectricity is presumed to depend on the crystal structure of the crystal contained in the ferroelectric layer. Therefore, in order for the insulator 130 to exhibit ferroelectricity, the insulator 130 needs to contain crystals. In particular, the insulator 130 preferably contains crystals having an orthorhombic crystal structure, thereby exhibiting ferroelectricity. In addition, the crystal structure of the crystal contained in the insulator 130 is any one or more selected from the group consisting of cubic system, tetragonal system, orthorhombic system, monoclinic system and hexagonal system. In addition, the insulator 130 may also have an amorphous structure. At this time, the insulator 130 may also have a composite structure of an amorphous structure and a crystal structure.

[0110] The conductor 120 is provided in a manner of contacting a portion of the top surface of the insulator 130. Figure 4B As shown, the side end of the conductor 120 is preferably located inside the side end of the conductor 115 in both the X direction and the Y direction. Note that in the structure where the insulator 130 covers the side end of the conductor 115, the side end of the conductor 120 may also be located outside the side end of the conductor 115.

[0111] As the conductor 120, a single layer or a stack of conductors described in [Conductor] to be described later can be used. As the conductor 120, it is preferable to use a conductive material that is not easily oxidized or a conductive material that has a function of inhibiting oxygen diffusion. For example, titanium nitride or tantalum nitride can be used. In addition, for example, there can also be a structure in which tantalum nitride is stacked on titanium nitride. In this case, titanium nitride is in contact with the insulator 130 and tantalum nitride is in contact with the oxide semiconductor 230. By adopting such a structure, excessive oxidation of the conductor 120 due to the oxide semiconductor 230 can be suppressed. In addition, when an oxide insulator is used for the insulator 130, excessive oxidation of the conductor 120 due to the insulator 130 can be suppressed. Alternatively, as the conductor 120, for example, there can be a structure in which tungsten is stacked on titanium nitride.

[0112] In addition, the conductor 120 has a region in contact with the oxide semiconductor 230, so it is preferable to use a conductive material containing oxygen in the [conductor] described later. By using a conductive material containing oxygen as the conductor 120, the conductor 120 can maintain conductivity even if it absorbs oxygen. In addition, even if an insulator containing oxygen such as zirconium oxide is used as the insulator 130, the conductor 120 can maintain conductivity, so it is preferred. As the conductor 120, for example, indium tin oxide (also called ITO), indium tin oxide with silicon added (also called ITSO), indium zinc oxide (also called IZO (registered trademark)), etc. can be used in a single layer or a stacked layer.

[0113] Since the insulator 180 is used as an interlayer film, its relative dielectric constant is preferably low. By using a material with a low relative dielectric constant for the interlayer film, the parasitic capacitance generated between the wirings can be reduced. As the insulator 180, a single layer or a stack of insulators containing a material with a low relative dielectric constant described in [Insulator] described later can be used. Silicon oxide and silicon oxynitride are preferred because they have thermal stability. In this case, the insulator 180b contains at least silicon and oxygen.

[0114] Note that Figure 1B and Figure 1C The insulator 180 is shown as a single-layer structure, but the present invention is not limited thereto. The insulator 180 may also have a stacked-layer structure.

[0115] For example, Fig. 6A and Figure 6B As shown, the insulator 180 may also have a stacked structure of an insulator 180a and an insulator 180b on the insulator 180a.

[0116] As the insulator 180 b , the insulating material described above that can be used as the insulator 180 can be used.

[0117] As insulator 180a, an insulator having oxygen barrier properties described below is preferably used. In addition, due to oxygen in insulator 180b, conductor 110 is oxidized, and the resistance sometimes increases. By providing insulator 180a between insulator 180b and conductor 110, it is possible to prevent conductor 110 from being oxidized and the resistance from increasing.

[0118] When impurities such as hydrogen are mixed into the insulator 130, leakage current generated between the upper electrode and the lower electrode may increase. In addition, when a material having ferroelectricity is used as the insulator 130, the crystallinity of the material having ferroelectricity may be reduced due to the mixing of impurities such as hydrogen into the material having ferroelectricity. In view of this, it is preferable to suppress the mixing of impurities such as hydrogen into the insulator 130.

[0119] Therefore, as the insulator 180a, it is preferable to use an insulator having hydrogen barrier properties in the [insulator] described later. Thus, it is possible to suppress the diffusion of hydrogen from the bottom of the capacitor 100 through the insulator 180b and the conductor 115 to the insulator 130. Since silicon nitride and silicon oxynitride each have the characteristics of less release of impurities (e.g., water and hydrogen) from themselves and less penetration of oxygen and hydrogen, they can be applied to the insulator 180a. In this case, the insulator 180a contains at least silicon and nitrogen.

[0120] In addition, as the insulator 180a, it is preferable to use an insulator having a function of capturing or fixing hydrogen in the [insulator] described later. By adopting such a structure, hydrogen of the insulator 130 can be captured or fixed to reduce the hydrogen concentration of the insulator 130. As the insulator 180a, magnesium oxide, aluminum oxide, or hafnium oxide can be used. For example, as the insulator 180a, a laminated film of aluminum oxide and silicon nitride on the aluminum oxide can also be used.

[0121] Note that Fig. 6A and Figure 6B The middle insulator 180 has a two-layer stacked structure, but one embodiment of the present invention is not limited thereto. The insulator 180 may have a three-layer or more stacked structure.

[0122] For example, when the insulator 180 has a three-layer stacked structure, in addition to the insulators 180a and 180b, an insulator may be provided between the insulator 180b and the conductor 115 and the insulator 130. As the insulator, an insulator that can be used as the insulator 180a may be used. Thus, diffusion of hydrogen into the insulator 130 through the insulator 180b can be suppressed.

[0123] In addition, if Fig. 6A and Figure 6BAs shown, the insulator 185 is preferably provided between the conductor 115 and the insulator 180. In addition, the insulator 185 is preferably provided in a manner of contacting the side surface of the insulator 180 in the opening 190. That is, the insulator 185 is preferably provided between the side surface of the insulator 180 in the opening 190 and the conductor 115.

[0124] As insulator 185, an insulator having hydrogen barrier properties in [insulator] described later is preferably used. Thus, diffusion of hydrogen from the outside of capacitor 100 through insulator 180 to insulator 130 can be suppressed. For example, silicon nitride or silicon nitride oxide can be used as insulator 185. In this case, insulator 185 contains at least silicon and nitrogen.

[0125] In addition, it is preferable to use an insulator having a function of capturing or fixing hydrogen in the [insulator] described later as the insulator 185. By adopting such a structure, hydrogen in the insulator 130 can be captured or fixed to reduce the hydrogen concentration of the insulator 130. Magnesium oxide, aluminum oxide, hafnium oxide, etc. can be used as the insulator 185. For example, a stacked film of aluminum oxide and silicon nitride on the aluminum oxide can also be used as the insulator 185.

[0126] Note that Fig. 6A and Figure 6B In the embodiment, the insulator 185 is provided in a manner of contacting the side surface of the insulator 180a in the opening 190 and the side surface of the insulator 180b in the opening 190, but the present invention is not limited thereto. Figure 6C and Fig.6D As shown, the insulator 185 may be provided in a manner that contacts a portion of the top surface of the insulator 180 a and the side surface of the insulator 180 b in the opening 190 .

[0127] Note that although Figure 1B and Figure 1C The structure in which the conductor 115 has a region in contact with the top surface of the insulator 180 is shown, but the present invention is not limited thereto. Figure 7B and Figure 7C As shown in FIG. 1 , the height of the top surface of the conductor 115 may be consistent with the height of the top surface of the insulator 180. 7A to 7C As shown, the side end of the conductor 120 may be located outside the side end of the conductor 115. The side end of the conductor 120 may be consistent with the side end of the conductor 115, or may be located inside the side end of the conductor 115.

[0128] Notice, 7A to 7CThe top surface of the conductor 120 is higher than the top surface of the insulator 130 , but the present invention is not limited thereto. For example, the top surface of the conductor 120 may be the same as or lower than the top surface of the insulator 130 .

[0129] FIG. 8A to FIG. 8C Shown with 7A to 7C An example of a storage device with a different structure is shown. Fig. 8A is a plan view showing an example of a storage device. Figure 8B and Figure 8C is a cross-sectional view of the storage device. Figure 8B It is along Fig. 8A A cross-sectional view of the portion along the dot-dash line A1-A2 in FIG. Figure 8C It is along Fig. 8A The cross-sectional view of the portion along the dashed line A3-A4 in FIG. Fig. 8A In the plan view, some components are omitted for clarity.

[0130] FIG. 8A to FIG. 8C The storage device shown is 7A to 7C The memory devices shown differ primarily in the shape of the electrical conductor 120 .

[0131] exist 7A to 7C In the memory device shown, the larger the maximum width of the opening 190, the smaller the distance between the side surfaces of the adjacent conductors 120. The smaller the distance, the more difficult it is to separate the adjacent conductors 120. When the adjacent conductors 120 are not separated but provided between the adjacent capacitors 100, leakage current flows between the capacitors 100.

[0132] So, if Figure 8B and Figure 8C As shown, the height of the top surface of the conductor 120 is lower than the height of the top surface of the insulator 130. Thus, the adjacent conductors 120 can be reliably separated. Therefore, even when the maximum width of the opening 190 is increased, the leakage current between the capacitors 100 can be suppressed.

[0133] The top surface of conductor 120 is preferably lower than the top surface of insulator 130 and close to or equal to the top surface of conductor 115. With this structure, reduction in capacitance of capacitor 100 can be suppressed.

[0134] Note that although FIG. 8A to FIG. 8C Although the conductor 120 has a region in contact with the bottom surface of the oxide semiconductor 230 , the present invention is not limited thereto. For example, a conductor may be provided between the conductor 120 and the oxide semiconductor 230 .

[0135] 9A to 9C 1 shows a structure in which a conductor 122 is provided between the conductor 120 and the oxide semiconductor 230. That is, 9A to 9C The storage device shown is FIG. 8A to FIG. 8C The main difference of the memory device shown is the inclusion of an electrical conductor 122 .

[0136] The conductor 122 is disposed on the conductor 120, and the oxide semiconductor 230 is disposed on the conductor 122. The conductor 122 has a region that contacts at least a portion of the top surface of the conductor 120 and a region that contacts at least a portion of the bottom surface of the oxide semiconductor 230. Fig. 9B and Fig. 9C As shown, the conductor 122 is preferably provided in a manner of being embedded in the insulator 182. At this time, the height of the top surface of the conductor 122 is consistent with the height of the top surface of the insulator 182.

[0137] like Fig. 9B and Fig. 9C As shown, the width of the conductor 122 when viewed in cross section is preferably smaller than the maximum width of the opening 190. By adopting such a structure, the distance between adjacent conductors 122 can be increased, and the parasitic capacitance between adjacent conductors 122 can be suppressed.

[0138] Furthermore, the width of the conductor 122 when viewed from the cross section is preferably the same as or larger than the maximum width of the opening 290. For example, when the width of the conductor 122 when viewed from the cross section is set to be the same as the maximum width of the opening 290, the same mask can be used in the anisotropic etching performed when forming the opening for providing the conductor 122 and the opening 290. Thus, the number of masks can be reduced, and the cost of the storage device can be reduced. In addition, for example, when the width of the conductor 122 when viewed from the cross section is larger than the maximum width of the opening 290, the position alignment accuracy of the opening 290 is relaxed. Therefore, the difficulty in manufacturing the micro storage unit can be reduced.

[0139] The conductor 122 has a region which is electrically connected to the capacitor 100 and the transistor 200 and functions as a plug. In addition, the conductor 122 has a region which functions as one of a source electrode and a drain electrode of the transistor 200 .

[0140] By adopting the above structure, even if the top surface of the conductor 120 is not sufficiently flattened, the transistor 200 can be appropriately formed on the capacitor 100 .

[0141] As the conductor 122, a single layer or a stack of conductors described in [Conductor] to be described later can be used. As the conductor 122, it is preferable to use a conductive material that is not easily oxidized or a conductive material that has a function of inhibiting oxygen diffusion. For example, titanium nitride or tantalum nitride can be used. In addition, for example, there can also be a structure in which tantalum nitride is stacked on titanium nitride. In this case, titanium nitride is in contact with the conductor 120 and the insulator 182 and tantalum nitride is in contact with the oxide semiconductor 230. By adopting such a structure, excessive oxidation of the conductor 122 due to the oxide semiconductor 230 can be suppressed. In addition, excessive oxidation of the conductor 122 due to the insulator 182 can be suppressed. Alternatively, as the conductor 122, for example, there can be a structure in which tungsten is stacked on titanium nitride.

[0142] Since the insulator 182 is used as an interlayer film, its relative dielectric constant is preferably low. By using a material with a low relative dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced. As the insulator 182, an insulator that can be used as the insulator 180 can be used.

[0143] exist Fig. 9B and Fig. 9C In the embodiment, the conductor 120 and the conductor 122 both have a single-layer structure, but the conductor 120 and the conductor 122 may also have a stacked-layer structure. FIG. 10A to FIG. 10C As shown, the conductor 120 may also have a two-layer stacked structure, and the conductor 122 may also have a two-layer stacked structure.

[0144] As described above, the conductors 120 and 122 may have a structure in which, for example, tantalum nitride is stacked on titanium nitride. Alternatively, the conductors 120 and 122 may have a structure in which, for example, tungsten is stacked on titanium nitride.

[0145] In addition, if FIG. 10A to FIG. 10C As shown in FIG. 1 , a conductor 121 may be provided on the conductor 120. The conductor 121 has a region that contacts a portion of the top surface of the conductor 120 and a region that contacts a portion of the side surface of the insulator 130. Furthermore, the conductor 121 has a region that faces the conductor 115 across the insulator 130. In this case, the conductor 120 and the conductor 121 are used as one of a pair of electrodes of the capacitor 100. That is, in FIG. 10A to FIG. 10C In the structure shown, the capacitor 100 includes a conductor 121 in addition to the conductor 115 , the insulator 130 , and the conductor 120 .

[0146] By adopting the above structure, even if the height of the top surface of the conductor 120 is lower than the height of the top surface of the conductor 115 , the electrostatic capacitance of the capacitor 100 can be sufficiently ensured.

[0147] Although 9A to 9CAlthough the structure in which the conductor 122 is provided between the conductor 120 and the oxide semiconductor 230 is shown, the present invention is not limited thereto. For example, a further conductor may be provided between the conductor 122 and the oxide semiconductor 230 .

[0148] FIG. 11A to FIG. 11C 1 shows a structure in which the conductor 125 is provided between the conductor 122 and the oxide semiconductor 230. That is, FIG. 11A to FIG. 11C The storage device shown is 9A to 9C The main difference of the memory device shown is the inclusion of the conductor 125. FIG. 8A to FIG. 8C The main difference of the memory device shown is the inclusion of electrical conductors 122 and 125 .

[0149] The conductor 125 is provided on the conductor 122 , and the oxide semiconductor 230 is provided on the conductor 125 . The conductor 125 has a region in contact with the top surface of the conductor 122 and a region in contact with at least a portion of the bottom surface of the oxide semiconductor 230 .

[0150] The conductor 122 has a region which is electrically connected to the capacitor 100 and the transistor 200 and functions as a plug. The conductor 125 has a region which functions as one of a source electrode and a drain electrode of the transistor 200. Materials and the like which can be used for the conductor 125 will be described later.

[0151] In addition, if Fig. 11B and Fig. 11C As shown in FIG. 1 , the width of the conductor 125 when viewed in cross section is preferably larger than the width of the conductor 122. In addition, the width of the conductor 125 when viewed in cross section is preferably larger than the maximum width of the opening 290. By adopting such a structure, the position alignment accuracy of the opening 290 is relaxed. Therefore, the difficulty in manufacturing the micro memory cell can be reduced.

[0152] Note that Figure 1B and Figure 1C In the embodiment, the conductor 120 is located inside the conductor 115 via the insulator 130, but the present invention is not limited thereto. For example, the conductor 120 may also be located outside the conductor 115 via the insulator 130.

[0153] For example, Fig. 12A and Fig. 12B As shown, the insulator 130 has a region on the side surface of the outer side of the conductor 115 in addition to a region in contact with the inner side of the recess of the conductor 115 and a region in contact with the top surface of the conductor 115 .

[0154] The conductor 120 is provided so as to be embedded in the recess of the conductor 115 via the insulator 130. The conductor 120 has a region facing a part of the outer side surface of the conductor 115 via the insulator 130.

[0155] By adopting the above structure, the electrostatic capacitance per unit area can be further increased.

[0156] Note that Fig. 12A and Fig. 12B As shown, an insulator 135 may be provided between the outer side surface of the conductor 115 and the insulator 130 and the insulator 180 .

[0157] Alternatively, an insulator 182 may be provided on the conductor 120 and the insulator 130. Preferably, the insulator 182 is planarized so that the top surface of the conductor 120 is exposed. By planarizing the insulator 182, the transistor 200 can be appropriately formed on the capacitor 100.

[0158] Since the insulator 182 is used as an interlayer film, its relative dielectric constant is preferably low. By using a material with a low relative dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced. As the insulator 182, an insulator that can be used as the insulator 180 can be used.

[0159] Note that in Fig. 12A and Fig. 12B In the case where the conductor 120 is provided so as to face the inner side and the outer side of the conductor 115 as shown and a sufficient electrostatic capacitance as a memory cell can be ensured, the insulator 180 b may not be provided.

[0160] Fig. 12C and Fig.12D The storage device shown is Fig. 12A and Fig. 12B The difference between the memory device shown is that the former is not provided with the insulator 180b. By not providing the insulator 180b, the manufacturing process of the memory device can be simplified.

[0161] [Transistor 200] like Figures 1A to 1C As shown, the transistor 200 may include a conductor 120, a conductor 240 on an insulator 280, an oxide semiconductor 230 arranged in contact with a top surface of the conductor 120 exposed in an opening 290, a side surface of the insulator 280 in the opening 290, a side surface of the conductor 240 in the opening 290, and at least a portion of a top surface of the conductor 240, an insulator 250 arranged in contact with the top surface of the oxide semiconductor 230, and a conductor 260 arranged in contact with the top surface of the insulator 250.

[0162] At least a part of the components of the transistor 200 is disposed in the opening 290 . Here, the bottom of the opening 290 is the top surface of the conductor 120 , and the side walls of the opening 290 are the side surfaces of the insulator 280 and the conductor 240 .

[0163] The side wall of the opening 290 is preferably perpendicular to the top surface of the conductor 120. In this case, the opening 290 has a cylindrical shape. By adopting such a structure, miniaturization or high integration of the storage device can be achieved.

[0164] Note that this embodiment shows an example in which the shape of the opening 290 when viewed from a plane is circular, but the present invention is not limited to this. For example, the shape of the opening 290 when viewed from a plane may be a substantially circular shape such as an ellipse, a polygonal shape such as a quadrangle, or a shape in which the corners of a polygon such as a quadrangle are curved. In this case, the maximum width of the opening 290 may be appropriately calculated according to the shape of the uppermost portion of the opening 290. For example, when the shape of the opening when viewed from a plane is a quadrangle, the maximum width of the opening 290 is preferably the length of the diagonal line of the uppermost portion of the opening 290.

[0165] The portions of the oxide semiconductor 230, the insulator 250, and the conductor 260 arranged in the opening 290 reflect the shape of the opening 290. Therefore, the oxide semiconductor 230 is provided so as to cover the bottom and sidewalls of the opening 290, the insulator 250 is provided so as to cover the oxide semiconductor 230, and the conductor 260 is provided so as to fit into the recess of the insulator 250 reflecting the shape of the opening 290.

[0166] here, Fig.13A yes Figure 1B An enlarged view of the oxide semiconductor 230 and its vicinity in FIG. Fig. 13B It is along Fig.13A 2 is a cross-sectional view of a portion along a dashed line B1 - B2 in FIG. 2 , which corresponds to a cross-sectional view taken along an XY plane including the conductor 240 .

[0167] like Fig.13A As shown, the oxide semiconductor 230 includes a region 230i, a region 230na, and a region 230nb.

[0168] The region 230na is a region in the oxide semiconductor 230 that is in contact with the conductor 120. At least a portion of the region 230na is used as one of the source region and the drain region of the transistor 200. The region 230nb is a region in the oxide semiconductor 230 that is in contact with the conductor 240. At least a portion of the region 230nb is used as the other of the source region and the drain region of the transistor 200. Fig. 13BAs shown, the conductor 240 is in contact with the entire periphery of the oxide semiconductor 230. Therefore, the other of the source region and the drain region of the transistor 200 may be formed on the entire periphery of the portion of the oxide semiconductor 230 formed in the same layer as the conductor 240.

[0169] At least a portion of the region 230i is located in a region between the region 230na and the region 230nb in the oxide semiconductor 230. At least a portion of the region 230i is used as a channel formation region of the transistor 200. That is, the channel formation region of the transistor 200 is located in a region between the conductor 120 and the conductor 240 of the oxide semiconductor 230. In addition, it can also be said that the channel formation region of the transistor 200 is located in a region of the oxide semiconductor 230 that contacts the insulator 280 or a region near the insulator 280.

[0170] In the channel formation region of a transistor using an oxide semiconductor for a semiconductor layer, it is preferred that the number of oxygen vacancies is small or the concentration of impurities such as hydrogen, nitrogen, and metal elements is low compared to the source region and the drain region. In addition, hydrogen near an oxygen vacancy sometimes forms a defect in which hydrogen enters the oxygen vacancy (hereinafter, sometimes referred to as V O H) and generate electrons that become carriers, so in the channel formation region V O H is also preferably reduced. Thus, the channel formation region of the transistor is a high resistance region with a low carrier concentration. Therefore, the channel formation region of the transistor can be said to be i-type (intrinsic) or substantially i-type.

[0171] In addition, the source region and the drain region of a transistor using an oxide semiconductor for a semiconductor layer are regions where there are more oxygen vacancies than in a channel formation region, and V O The resistance is reduced by increasing the carrier concentration when there is more H or a high concentration of impurities such as hydrogen, nitrogen, or metal elements. That is, the source and drain regions of the transistor are n-type regions with higher carrier concentration and lower resistance than the channel formation region.

[0172] The details will be described later. When an insulator containing oxygen that is released by heating (hereinafter, sometimes referred to as excess oxygen) is used as the insulator 280, oxygen can be supplied from the insulator 280 to the region of the oxide semiconductor 230 that is in contact with the insulator 280 by performing heat treatment, thereby reducing oxygen vacancies in the region and V O H. In addition, oxygen contained in the insulator 280 is supplied to a region of the oxide semiconductor 230 in contact with the insulator 250 through the insulator 250, thereby reducing oxygen vacancies in the region and V O H. Therefore, if Fig.13A and Fig. 13BAs shown, the region 230 i having fewer oxygen vacancies than the region 230 na and the region 230 nb is located near the insulator 280 and the insulator 250 .

[0173] When the oxide semiconductor 230 is in contact with the conductor 120, a metal compound or oxygen vacancy is formed, and the region 230na of the oxide semiconductor 230 is reduced in resistance. By reducing the resistance of the oxide semiconductor 230 in contact with the conductor 120, the contact resistance between the oxide semiconductor 230 and the conductor 120 can be reduced. Similarly, when the oxide semiconductor 230 is in contact with the conductor 240, the region 230nb of the oxide semiconductor 230 is reduced in resistance. Thus, the contact resistance between the oxide semiconductor 230 and the conductor 240 can be reduced.

[0174] Note that the ranges of the regions 230na and 230nb vary depending on the degree of resistance reduction of the regions 230na and 230nb and the amount of oxygen supplied from the insulator 280 through the insulator 250. For example, when the degree of resistance reduction of the regions 230na and 230nb is large or the amount of oxygen supplied from the insulator 280 through the insulator 250 is small, the regions 230na and 230nb may extend to the interface with the insulator 250.

[0175] The channel length of the transistor 200 is the distance between the source and the drain. In other words, it can be said that the channel length of the transistor 200 is determined by the thickness of the insulator 280 on the conductor 120. Fig.13A , the dotted double arrow indicates the channel length L of the transistor 200. When viewed from a cross section, the channel length L is the distance between the end of the region where the oxide semiconductor 230 and the conductor 120 are in contact and the end of the region where the oxide semiconductor 230 and the conductor 240 are in contact. That is, the channel length L is equivalent to the length of the side surface of the opening 290 side of the insulator 280 when viewed from a cross section.

[0176] In a planar transistor, the channel length is set according to the exposure limit of the photolithography method, but in the present invention, the channel length can be set according to the thickness of the insulator 280. Therefore, the channel length of the transistor 200 can be set to a very fine structure below the exposure limit of the photolithography method (for example, below 60nm, below 50nm, below 40nm, below 30nm, below 20nm, or below 10nm and above 1nm or above 5nm). Therefore, the on-state current of the transistor 200 becomes larger, thereby improving the frequency characteristics. Thus, the read speed and write speed of the memory cell 150 can be improved, so a memory device with a high operating speed can be provided.

[0177] Furthermore, as described above, a channel formation region, a source region, and a drain region can be formed on the oxide semiconductor 230 in the opening 290. Therefore, compared with a planar transistor in which a channel formation region, a source region, and a drain region are provided separately on the XY plane, the occupied area of ​​the transistor 200 can be reduced. Thus, the memory device can be highly integrated, so that the memory capacity per unit area can be increased.

[0178] In addition, Fig. 13B Similarly, on the XY plane including the channel formation region of the oxide semiconductor 230, the oxide semiconductor 230, the insulator 250, and the conductor 260 are arranged in concentric circles. Therefore, the side surface of the conductor 260 arranged in the center is opposite to the side surface of the oxide semiconductor 230 via the insulator 250. In other words, the entire circle of the oxide semiconductor 230 becomes the channel formation region when viewed from a plane. At this time, for example, the channel width of the transistor 200 is determined by the length of the outer circumference of the oxide semiconductor 230. That is, it can be said that the channel width of the transistor 200 is determined by the maximum width of the opening 290 (the maximum diameter when the shape of the opening 290 when viewed from a plane is circular). Fig.13A and Fig. 13B In FIG. 1 , the double-pointed arrow indicates the maximum width Dt of the opening 290. Fig. 13B In FIG. 1 , a double-pointed arrow indicates a channel width W of the transistor 200 . By increasing the maximum width Dt of the opening 290 , the channel width per unit area can be increased, thereby increasing the on-state current.

[0179] When the opening 290 is formed by photolithography, the maximum width Dt of the opening 290 is set according to the exposure limit of the photolithography. In addition, the maximum width Dt of the opening 290 is set according to the thickness of the oxide semiconductor 230, the insulator 250, and the conductor 260 provided in the opening 290. The maximum width Dt of the opening 290 is preferably, for example, not less than 1 nm, not less than 5 nm, or not less than 10 nm and not more than 100 nm, not more than 60 nm, not more than 50 nm, not more than 40 nm, not more than 30 nm, or not more than 20 nm. Note that in the case where the shape of the opening 290 when viewed from a plane is circular, the maximum width Dt of the opening 290 is equivalent to the diameter of the opening 290, and the channel width W can be calculated as "D×π".

[0180] In addition, in a memory device according to one embodiment of the present invention, the channel length L of the transistor 200 is preferably at least smaller than the channel width W of the transistor 200. The channel length L of the transistor 200 according to one embodiment of the present invention is greater than or equal to 0.1 times and less than or equal to 0.99 times, and preferably greater than or equal to 0.5 times and less than or equal to 0.8 times, the channel width W of the transistor 200. By adopting such a structure, a transistor having good electrical characteristics and high reliability can be realized.

[0181] In addition, the opening 290 is formed to have a circular shape when viewed from a plane, so that the oxide semiconductor 230, the insulator 250, and the conductor 260 are arranged in concentric circles. As a result, the distance between the conductor 260 and the oxide semiconductor 230 is substantially uniform, so that the gate electric field can be applied to the oxide semiconductor 230 substantially uniformly.

[0182] The distance from the interface between the conductor 240 and the oxide semiconductor 230 in the opening 290 to the side end of the conductor 240 in the Y direction is preferably small. The distance is preferably 1 nm or more, 1.5 nm or more, or 2 nm or more, and 20 nm or less, 10 nm or less, 5 nm or less, or 3 nm or less. By adopting such a structure, the width of the conductor 240 in the Y direction can be reduced, thereby reducing the interval at which the conductor 240 is arranged. Thus, miniaturization or high integration of the storage device can be achieved.

[0183] Note that Figure 1B and Figure 1C In the embodiment, the opening 290 is provided in such a manner that the side wall of the opening 290 is perpendicular to the top surface of the conductor 110, but the present invention is not limited thereto. For example, the side wall of the opening 290 may also have a tapered shape.

[0184] exist Fig.14A and Fig. 14B In the storage device shown, the side wall of the opening 290 has an inverse tapered shape. Fig.14A and Fig. 14B The plan view of the storage device shown can be referred to Figure 1A .

[0185] By making the sidewall of the opening 290 have a tapered shape, the coverage of the oxide semiconductor 230 or the insulator 250 can be improved, thereby reducing defects such as voids. For example, the angle formed by the side surface of the insulator 280 in the opening 290 and the top surface of the conductor 120 ( Fig.14A The angle θ1) shown is preferably greater than or equal to 45 degrees and less than or equal to 90 degrees. Alternatively, it is preferably greater than or equal to 45 degrees and less than or equal to 75 degrees. Alternatively, it is preferably greater than or equal to 45 degrees and less than or equal to 65 degrees.

[0186] Note that in this specification, etc., a tapered shape refers to a shape in which at least a portion of the side surface of a component is inclined relative to a substrate surface or a formed surface. For example, a region having an angle (hereinafter sometimes referred to as a taper angle) formed by an inclined side surface and a substrate surface is less than 90°. Note that the side surface and the substrate surface of a component do not necessarily have to be completely flat, and may be a substantially planar shape with a slight curvature or a substantially planar shape with slight concavities and convexities.

[0187] Fig.14A and Fig. 14B The shape of the opening 290 shown is a truncated cone shape. In this case, the shape of the opening 290 when viewed from a plane is circular, and the shape of the opening 290 when viewed from a cross section is a trapezoid. In addition, the area of ​​the upper bottom surface of the truncated cone shape (for example, the opening provided in the conductor 240) is larger than the area of ​​the lower bottom surface of the truncated cone shape (the top surface of the conductor 120 exposed in the opening 290). In this case, the maximum diameter of the opening 290 can be calculated based on the upper bottom surface of the truncated cone shape.

[0188] When the side wall of the opening 290 has a tapered shape, the channel length can be set using the thickness of the insulator 280 and the angle θ1 formed by the side surface of the insulator 280 in the opening 290 and the top surface of the conductor 120. In addition, the length of the periphery of the oxide semiconductor 230 can be calculated, for example, based on the region opposite to the conductor 240 or the position of half the thickness of the insulator 280. Note that the perimeter of the opening 290 at any position (depth) can be set as the channel width of the transistor 200 as needed. For example, the perimeter of the lowermost portion of the opening 290 can be set as the channel width, or the perimeter of the uppermost portion of the opening 290 can be set as the channel width.

[0189] Although in Fig.14A and Fig. 14B , a structure in which the side surface of the conductor 240 in the opening 290 is aligned with the side surface of the insulator 280 in the opening 290 is shown, but the present invention is not limited to this. For example, the side surface of the conductor 240 in the opening 290 and the side surface of the insulator 280 in the opening 290 may also be discontinuous. In addition, the inclination of the side surface of the conductor 240 in the opening 290 and the inclination of the side surface of the insulator 280 in the opening 290 may also be different from each other. In addition, for example, the angle formed by the side surface of the conductor 240 in the opening 290 and the top surface of the conductor 120 is preferably smaller than the angle θ1. By adopting such a structure, the coverage of the side surface of the conductor 240 in the opening 290 by the oxide semiconductor 230 is improved, and defects such as voids can be reduced.

[0190] like Fig.14A and Fig. 14BAs shown in FIG. 1 , the bottom of the conductor 260 located in the opening 290 has a flat region. Note that depending on the maximum width of the opening 290 (the maximum diameter when the opening 290 is circular when viewed from a plane), the thickness of the insulator 280 (equivalent to the depth of the opening 290), the thickness of the oxide semiconductor 230, and the thickness of the insulator 250, etc., the bottom of the conductor 260 located in the opening 290 may not have a flat region. For example, Fig. 14C and Fig.14D As shown, sometimes the bottom of the conductor 260 located in the opening 290 has a needle-like shape. Fig. 14C and Fig.14D The plan view of the storage device shown can be referred to Figure 1A .

[0191] Here, the needle-like shape refers to a shape that becomes thinner as it approaches the top (closer to the bottom of the conductor 260 located in the opening 290). In addition, the top of the needle-like shape may be an acute angle or a curved shape that bulges downward. In addition, the shape of the needle-like shape with an acute angle at the top may also be called a V-shape.

[0192] The region of the conductor 260 located in the opening 290 facing the oxide semiconductor 230 through the insulator 250 is used as a gate electrode. Therefore, the conductor 260 embedded in the opening 290 and having a needle-like bottom shape can also be called a needle-shaped gate. Fig.14A and Fig. 14B As shown, even if the bottom of the conductor 260 is in a shape having a flat region, the conductor 260 may sometimes be referred to as a needle-shaped gate.

[0193] Note that Figure 1B and Figure 1C The opening 190 is provided in such a manner that the side wall of the opening 190 is perpendicular to the top surface of the conductor 110, but the present invention is not limited thereto. For example, like the opening 290, the side wall of the opening 190 may have a tapered shape or an inverse tapered shape.

[0194] By making the side wall of the opening 190 have a tapered shape, the coverage of the conductor 115 or the insulator 130 can be improved, thereby reducing defects such as voids. For example, the angle formed by the side surface of the insulator 180 in the opening 190 and the top surface of the conductor 110 ( Fig.14A The angle θ2) shown is preferably greater than or equal to 45 degrees and less than or equal to 90 degrees. Alternatively, it is preferably greater than or equal to 45 degrees and less than or equal to 75 degrees. Alternatively, it is preferably greater than or equal to 45 degrees and less than or equal to 65 degrees.

[0195] like Fig.14A and Fig. 14BAs shown in FIG. 1 , the bottom of the conductor 120 located in the opening 190 has a flat region. Note that depending on the maximum width of the opening 190 (the maximum diameter when the opening 190 is circular when viewed from a plane), the thickness of the insulator 180 (equivalent to the depth of the opening 190), the thickness of the conductor 115, and the thickness of the insulator 130, etc., the bottom of the conductor 120 located in the opening 190 may not have a flat region. For example, Fig. 14C and Fig.14D As shown, sometimes the bottom of the conductor 120 located in the opening 190 has a needle-like shape. Fig. 14C and Fig.14D The plan view of the storage device shown can be referred to Figure 1A .

[0196] In addition, when the insulator 180 and the insulator 280 are made of the same material, the angle θ1 and the angle θ2 are consistent or approximately consistent. Note that the angle θ1 and the angle θ2 may be different depending on the material used for each of the insulators 180 and the insulators 280, the method for forming each of the openings 190 and the openings 290, etc. For example, the angle θ1 may be greater than or less than the angle θ2. In addition, one of the angles θ1 and θ2 may be 90 degrees or a value close thereto.

[0197] Alternatively, for example, one or both of the side wall of the opening 290 and the side wall of the opening 190 may have an inverse tapered shape.

[0198] Here, the inverse cone shape refers to a shape having a side or upper portion protruding more than the bottom in a direction parallel to the substrate. At this time, the shape of the opening 290 is a truncated cone shape. In this case, the opening 290 has a circular shape when viewed from a plane, and has a trapezoidal shape when viewed from a cross section. In addition, the area of ​​the upper bottom surface of the truncated cone shape (for example, the opening provided in the conductor 240) is larger than the area of ​​the lower bottom surface of the truncated cone shape (the top surface of the conductor 120 exposed in the opening 290). By adopting this structure, the area in which the oxide semiconductor 230 contacts the conductor 120 can be expanded.

[0199] like Figure 1B and Figure 1C As shown, a portion of the oxide semiconductor 230 is located outside the opening 290, that is, on the conductor 240. Figure 1B 2 shows a structure in which the oxide semiconductor 230 is separated in the X direction, but the present invention is not limited thereto. Fig.15A and Fig. 15B As shown in FIG. 1 , the oxide semiconductor 230 may also extend in the X direction. Fig.15A and Fig. 15BThe structure shown is also separated in the Y direction (refer to Fig. 15C ).

[0200] also, Figure 1C The structure in which the side end of the oxide semiconductor 230 is located inside the side end of the conductor 240 is shown. Note that the present invention is not limited to this. For example, a structure in which the side end of the oxide semiconductor 230 is consistent with the side end of the conductor 240 in the Y direction may be adopted. Alternatively, a structure in which the side end of the oxide semiconductor 230 is located outside the side end of the conductor 240 may be adopted.

[0201] The band gap of the metal oxide used as the oxide semiconductor 230 is preferably greater than 2 eV, and more preferably greater than 2.5 eV. By using a metal oxide with a large band gap as the oxide semiconductor 230, the off-state current of the transistor can be reduced. By using a transistor with a small off-state current for a memory cell, the storage content can be maintained for a long time. In other words, since no refresh operation is required or the frequency of the refresh operation is extremely low, the power consumption of the memory device can be substantially reduced. In addition, the frequency of the refresh operation required for a general DRAM is about 1 time / 60 msec, and the frequency of the refresh operation of a memory device of one embodiment of the present invention can be about 1 time / 10 sec, which can achieve a refresh line frequency of more than 10 times or more than 100 times. In addition, by using a memory device of one embodiment of the present invention, the frequency of the refresh operation can be set to more than 1 time / 1 sec and less than 1 time / 100 sec, preferably more than 1 time / 5 sec and less than 1 time / 50 sec.

[0202] Note that as the oxide semiconductor 230 , a single layer or a stacked layer of a metal oxide described in [Metal Oxide] below can be used.

[0203] As the oxide semiconductor 230, specifically, a metal oxide having the following composition can be used: In:M:Zn=1:3:2 [atomic ratio] or a composition close thereto, In:M:Zn=1:3:4 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:0.5 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:1 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:1.2 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:2 [atomic ratio] or a composition close thereto, or In:M:Zn=4:2:3 [atomic ratio] or a composition close thereto. Note that the nearby composition includes a range of ±30% of the desired atomic ratio. In addition, gallium is preferably used as the element M.

[0204] In addition, when the metal oxide is deposited by sputtering, the above-mentioned atomic number ratio is not limited to the atomic number ratio of the deposited metal oxide, but may also be the atomic number ratio of the sputtering target used for the deposition of the metal oxide.

[0205] As an analysis of the composition of the metal oxide used for the oxide semiconductor 230, for example, energy dispersive X-ray analysis (EDX: Energy Dispersive X-ray Spectrometry), X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectrometry), inductively coupled plasma mass spectrometry (ICP-MS: Inductively Coupled Plasma-Mass Spectrometry) or inductively coupled plasma atomic emission spectrometry (ICP-AES: Inductively Coupled Plasma-Atomic Emission Spectrometry) can be used. Alternatively, a combination of multiple of the above methods can be used for analysis. Note that elements with low contents are sometimes affected by the accuracy of analysis, and the actual contents are different from the contents obtained by analysis. For example, when the content of element M is low, the content of element M obtained by analysis is sometimes lower than the actual content.

[0206] The metal oxide can be formed by sputtering or atomic layer deposition (ALD) as appropriate. Note that when the metal oxide is formed by sputtering, the composition of the metal oxide after formation is sometimes different from the composition of the sputtering target. In particular, the zinc content in the metal oxide after formation is sometimes reduced to about 50% of the zinc content in the sputtering target.

[0207] The oxide semiconductor 230 preferably has crystallinity. Examples of crystalline oxide semiconductors include CAAC-OS (c-axis aligned crystalline oxide semiconductor), nc-OS (nanocrystalline oxide semiconductor), polycrystalline oxide semiconductors, and single crystal oxide semiconductors. CAAC-OS or nc-OS is preferably used as the oxide semiconductor 230, and CAAC-OS is particularly preferably used.

[0208] The CAAC-OS preferably has a plurality of layered crystal regions and the c-axis thereof is oriented in the normal direction of the formed surface. For example, the oxide semiconductor 230 preferably has layered crystals that are roughly parallel to the side walls of the opening 290, and in particular, layered crystals that are roughly parallel to the side surfaces of the insulator 280. By adopting such a structure, the layered crystals of the oxide semiconductor 230 are roughly parallel to the channel length direction of the transistor 200, so that the on-state current of the transistor can be increased.

[0209] CAAC-OS has a dense structure with high crystallinity and is a metal oxide with few impurities and defects (e.g., oxygen vacancies, etc.). In particular, by performing a heat treatment at a temperature at which the metal oxide is not polycrystallized (e.g., above 400°C and below 600°C) after forming the metal oxide, the CAAC-OS can have a dense structure with higher crystallinity. In this way, by further increasing the density of the CAAC-OS, the diffusion of impurities or oxygen in the CAAC-OS can be further reduced.

[0210] In addition, it is not easy to observe clear grain boundaries in CAAC-OS, so it is not easy to cause a decrease in electron mobility due to grain boundaries. Therefore, the physical properties of the metal oxide having CAAC-OS are stable. Therefore, the metal oxide having CAAC-OS has heat resistance and high reliability.

[0211] In addition, when a crystalline oxide such as CAAC-OS is used as the oxide semiconductor 230, oxygen can be suppressed from being extracted from the oxide semiconductor 230 by the source electrode or the drain electrode. Therefore, even when heat treatment is performed, oxygen can be suppressed from being extracted from the oxide semiconductor 230, so that the transistor 200 is stable to high temperatures (so-called thermal budget) in the manufacturing process.

[0212] The crystallinity of the oxide semiconductor 230 can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED), or a combination of a plurality of the above methods.

[0213] Note that Figure 1B and Figure 1C The oxide semiconductor 230 is shown as a single-layer structure, but the present invention is not limited thereto. The oxide semiconductor 230 may also have a stacked structure of multiple oxide layers with different chemical compositions. For example, a structure in which multiple types selected from the above-mentioned metal oxides are appropriately stacked may also be adopted.

[0214] For example, Fig.16A and Fig. 16B As shown, the oxide semiconductor 230 may have a stacked-layer structure of an oxide semiconductor 230 a and an oxide semiconductor 230 b on the oxide semiconductor 230 a .

[0215] The conductivity of the material used for the oxide semiconductor 230 a is preferably different from the conductivity of the material used for the oxide semiconductor 230 b .

[0216] For example, the oxide semiconductor 230a may use a material having a higher conductivity than the oxide semiconductor 230b. By using a material having a higher conductivity for the conductor 120 used as a source electrode or a drain electrode and the oxide semiconductor 230a in contact with the conductor 240, the contact resistance between the oxide semiconductor 230 and the conductor 120 and the contact resistance between the oxide semiconductor 230 and the conductor 240 can be reduced, thereby realizing a transistor having a large on-state current.

[0217] Here, when a material with high conductivity is used for an oxide semiconductor 230b disposed on one side of a conductor 260 used as a gate electrode, the threshold voltage of the transistor is sometimes caused to drift, so that the drain current (hereinafter also recorded as the cut-off current) flowing when the gate voltage is 0V becomes larger. Specifically, when the transistor 200 is an n-channel transistor, the threshold voltage is sometimes reduced. Therefore, the oxide semiconductor 230b preferably uses a material with a lower conductivity than the oxide semiconductor 230a. Thus, when the transistor 200 is an n-channel transistor, the threshold voltage can be increased, and a transistor with a small cut-off current can be realized. Note that sometimes the cut-off current is recorded as normally closed.

[0218] As described above, by making the oxide semiconductor 230 have a stacked structure and using a material having higher conductivity than the oxide semiconductor 230b for the oxide semiconductor 230a, a normally-off transistor with a large on-state current can be realized. Thus, a memory device having both low power consumption and high performance can be realized.

[0219] In addition, the carrier concentration of the oxide semiconductor 230a is preferably higher than the carrier concentration of the oxide semiconductor 230b. By increasing the carrier concentration of the oxide semiconductor 230a, the conductivity becomes higher, and the contact resistance between the oxide semiconductor 230 and the conductor 120 and the contact resistance between the oxide semiconductor 230 and the conductor 240 can be reduced, thereby realizing a transistor with a large on-state current. By reducing the carrier concentration of the oxide semiconductor 230b, the conductivity becomes lower, thereby realizing a normally-off transistor.

[0220] Here, although an example is shown in which a material having a higher conductivity than the oxide semiconductor 230b is used for the oxide semiconductor 230a, one embodiment of the present invention is not limited thereto. The oxide semiconductor 230a may also use a material having a lower conductivity than the oxide semiconductor 230b. The carrier concentration of the oxide semiconductor 230a may be lower than the carrier concentration of the oxide semiconductor 230b.

[0221] The band gap of the first metal oxide used for the oxide semiconductor 230a is preferably different from the band gap of the second metal oxide used for the oxide semiconductor 230b. For example, the difference between the band gaps of the first metal oxide and the second metal oxide is preferably 0.1 eV or more, more preferably 0.2 eV or more, and further preferably 0.3 eV or more.

[0222] The band gap of the first metal oxide used for the oxide semiconductor 230a can be smaller than the band gap of the second metal oxide used for the oxide semiconductor 230b. Thus, the contact resistance between the oxide semiconductor 230 and the conductor 120 and the contact resistance between the oxide semiconductor 230 and the conductor 240 can be reduced, thereby realizing a transistor with a large on-state current. In addition, in the case where the transistor 200 is an n-channel transistor, the threshold voltage can be increased, thereby realizing a normally closed transistor.

[0223] Here, although an example in which the band gap of the first metal oxide is smaller than the band gap of the second metal oxide is shown, one embodiment of the present invention is not limited thereto. The band gap of the first metal oxide may be larger than the band gap of the second metal oxide.

[0224] As described above, the band gap of the first metal oxide used for the oxide semiconductor 230a can be smaller than the band gap of the second metal oxide used for the oxide semiconductor 230b. The composition of the first metal oxide is preferably different from the composition of the second metal oxide. By making the composition of the first metal oxide different from the composition of the second metal oxide, the band gap can be controlled. For example, the content of element M of the first metal oxide is preferably lower than the content of element M of the second metal oxide. Specifically, in the case where the first metal oxide and the second metal oxide use In-M-Zn oxide, the composition of the first metal oxide can be set to In:M:Zn=1:1:1 [atomic number ratio] or thereabouts, and the composition of the second metal oxide can be set to In:M:Zn=1:3:2 [atomic number ratio] or thereabouts. As element M, it is particularly preferred to use one or more of gallium, aluminum and tin.

[0225] The first metal oxide may not contain the element M. For example, the first metal oxide used for the oxide semiconductor 230a may be an In-Zn oxide, and the second metal oxide used for the oxide semiconductor 230b may be an In-M-Zn oxide. Specifically, the first metal oxide may be an In-Zn oxide, and the second metal oxide may be an In-Ga-Zn oxide. More specifically, the composition of the first metal oxide may be set to In:Zn=1:1 [atomic ratio] or thereabouts or In:Zn=4:1 [atomic ratio] or thereabouts, and the composition of the second metal oxide may be set to In:Ga:Zn=1:1:1 [atomic ratio] or thereabouts.

[0226] Here, although an example is shown in which the content of the element M of the first metal oxide is lower than the content of the element M of the second metal oxide, one embodiment of the present invention is not limited thereto. The content of the element M of the first metal oxide may also be higher than the content of the element M of the second metal oxide. In addition, as long as the composition of the first metal oxide and the second metal oxide is different, the content of elements other than the element M of the first metal oxide and the second metal oxide may also be different.

[0227] The thickness of the oxide semiconductor 230 is preferably greater than or equal to 1 nm, greater than or equal to 3 nm, or greater than or equal to 5 nm, and less than or equal to 20 nm, less than or equal to 15 nm, less than or equal to 12 nm, or less than or equal to 10 nm.

[0228] The thickness of each layer constituting the oxide semiconductor 230 (here, the oxide semiconductor 230a and the oxide semiconductor 230b) may be determined so that the thickness of the oxide semiconductor 230 is within the above range. The thickness of the oxide semiconductor 230a may be determined so that the contact resistance between the oxide semiconductor 230a and the conductor 120 and the contact resistance between the oxide semiconductor 230a and the conductor 240 are within the required range. In addition, the thickness of the oxide semiconductor 230b may be determined so that the threshold voltage of the transistor is within the required range. Note that the thickness of the oxide semiconductor 230a may be the same as or different from the thickness of the oxide semiconductor 230b.

[0229] Fig.16A and Fig. 16B Although the oxide semiconductor 230 has an example of a stacked-layer structure of two layers, namely, the oxide semiconductor 230 a and the oxide semiconductor 230 b , the present invention is not limited thereto and may have a stacked-layer structure of three or more layers.

[0230] When the oxide semiconductor 230 has a three-layer stacked structure, for example, the following structure may be adopted: a metal oxide having a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition close thereto, a metal oxide having a composition of In:Zn=1:1 [atomic ratio] or a composition close thereto, or a metal oxide having a composition of In:Zn=4:1 [atomic ratio] or a composition close thereto, and a metal oxide having a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition close thereto may be provided in order from the conductor 120 side. By adopting such a structure, the on-state current of the transistor 200 can be increased, and a highly reliable transistor structure with less unevenness can be realized.

[0231] As the insulator 250, a single layer or a stack of insulators described in [Insulator] to be described later can be used. For example, as the insulator 250, it is preferable to use an insulator that is easily permeable to oxygen. By adopting this structure, the oxygen contained in the insulator 280 can be supplied to the region 230i through the insulator 250. In addition, as the insulator 250, an insulator containing excess oxygen can also be used. By adopting this structure, the oxygen contained in the insulator 250 can be supplied to the region 230i. For example, as the insulator 250, silicon oxide or silicon oxynitride can be used. Silicon oxide and silicon oxynitride are thermally stable and therefore are preferred.

[0232] In addition, a material having a high relative dielectric constant, that is, a so-called high-k material described in [Insulator] described later, may be used as the insulator 250. For example, hafnium oxide or aluminum oxide may be used.

[0233] The thickness of the insulator 250 is preferably 0.5 nm to 15 nm, more preferably 0.5 nm to 12 nm, and even more preferably 0.5 nm to 10 nm. At least a portion of the insulator 250 may be a region having the above thickness.

[0234] The concentration of impurities such as water and hydrogen in the insulator 250 is preferably reduced. This can prevent impurities such as water and hydrogen from entering the channel formation region of the oxide semiconductor 230 .

[0235] like Figure 1B and Figure 1C As shown, a portion of the insulator 250 is located outside the opening 290, that is, on the conductor 240 and the insulator 280. At this time, the insulator 250 preferably covers the side end of the oxide semiconductor 230. Thus, the conductor 260 and the oxide semiconductor 230 can be prevented from being short-circuited. In addition, the insulator 250 preferably covers the side end of the conductor 240. Thus, the conductor 260 and the conductor 240 can be prevented from being short-circuited.

[0236] Note that Figure 1B and Figure 1C The insulator 250 is shown as a single layer, but the present invention is not limited thereto. The insulator 250 may also have a stacked structure.

[0237] For example, Fig.16A and Fig. 16B As shown, the insulator 250 may also have a stacked structure of an insulator 250a, an insulator 250b on the insulator 250a, and an insulator 250c on the insulator 250b.

[0238] The insulator 250b preferably uses a material having a low relative dielectric constant as described in [Insulator] to be described later. In particular, silicon oxide and silicon oxynitride are preferred because they have thermal stability. In this case, the insulator 250b contains at least oxygen and silicon. By adopting this structure, the parasitic capacitance between the conductor 260 and the conductor 240 can be reduced. In addition, it is preferred that the impurity concentration of water, hydrogen, etc. in the insulator 250b is reduced.

[0239] The insulator 250a preferably uses an insulator having oxygen barrier properties as described in [Insulator] to be described later. The insulator 250a has a region in contact with the oxide semiconductor 230. When the insulator 250a has oxygen barrier properties, it is possible to suppress the detachment of oxygen from the oxide semiconductor 230 during heat treatment or the like. Therefore, the formation of oxygen vacancies in the oxide semiconductor 230 can be suppressed. As a result, the electrical characteristics of the transistor 200 can be improved, and the reliability can be improved. As the insulator 250a, for example, aluminum oxide is preferably used. In this case, the insulator 250a contains at least oxygen and aluminum.

[0240] The insulator 250c preferably uses an insulator having hydrogen barrier properties as described in [Insulator] described later. This can suppress the diffusion of impurities contained in the conductor 260 into the oxide semiconductor 230. Silicon nitride has high hydrogen barrier properties and is therefore preferably used for the insulator 250c. In this case, the insulator 250c contains at least nitrogen and silicon.

[0241] The insulator 250c may also have oxygen barrier properties. The insulator 250c is provided between the insulator 250b and the conductor 260. Thus, oxygen contained in the insulator 250b can be prevented from diffusing into the conductor 260 and oxidation of the conductor 260 can be suppressed. In addition, a reduction in the amount of oxygen supplied to the region 230i can be suppressed.

[0242] In addition, an insulator may be provided between the insulator 250b and the insulator 250c. The insulator preferably uses an insulator having a function of capturing or fixing hydrogen as described in [Insulator] to be described later. By providing the insulator, hydrogen contained in the oxide semiconductor 230 can be captured or fixed more efficiently. Therefore, the hydrogen concentration in the oxide semiconductor 230 can be reduced. As the insulator, for example, hafnium oxide is preferably used. In this case, the insulator contains at least oxygen and hafnium. In addition, the insulator may also have an amorphous structure.

[0243] In order to realize the miniaturization of transistor 200, the thickness of insulators 250a to 250c is preferably small, and it is preferable to set their thicknesses within the above range. Typically, the thicknesses of insulator 250a, insulator 250b, insulator having the function of capturing or fixing hydrogen, and insulator 250c are set to 1nm, 2nm, 2nm, and 1nm, respectively. By adopting such a structure, even if transistor 200 is miniaturized or highly integrated, it can have good electrical characteristics.

[0244] exist Fig.16A and Fig. 16B The insulator 250 has a three-layer laminated structure of insulators 250a to 250c, but the present invention is not limited thereto. The insulator 250 may also have a laminated structure of two or more layers. At this time, each layer included in the insulator 250 is preferably appropriately selected from the insulators 250a to 250c and an insulator having a function of capturing or fixing hydrogen.

[0245] A single layer or a stack of conductors described in [Conductor] described later can be used as the conductor 260. For example, a highly conductive material such as tungsten can be used as the conductor 260.

[0246] In addition, as the conductor 260, it is preferable to use a conductive material that is not easily oxidized or a conductive material that has a function of inhibiting oxygen diffusion. As the conductive material, a conductive material containing nitrogen (for example, titanium nitride or tantalum nitride, etc.) and a conductive material containing oxygen (for example, ruthenium oxide, etc.) can be cited. Thus, the decrease in the conductivity of the conductor 260 can be suppressed.

[0247] Note that Figure 1B and Figure 1C The conductor 260 is shown as a single layer, but the present invention is not limited thereto. The conductor 260 may also have a stacked structure. For example, Fig.16A and Fig. 16BAs shown in FIG. 1 , the conductor 260 may have a stacked structure of a conductor 260a and a conductor 260b on the conductor 260a. In this case, for example, titanium nitride may be used as the conductor 260a, and tungsten may be used as the conductor 260b. By stacking layers containing tungsten in this way, the conductivity of the conductor 260 can be improved, and the conductor 260 can fully function as the wiring WL.

[0248] exist Fig.16A and Fig. 16B The conductor 260 has a two-layer laminate structure of the conductor 260a and the conductor 260b, but the present invention is not limited thereto. The conductor 260 may also have a three-layer or more laminate structure.

[0249] exist Figure 1B and Figure 1C The conductor 260 is provided in a manner embedded in the opening 290, but the present invention is not limited thereto. For example, a concave portion reflecting the shape of the opening 290 may be formed in the center of the conductor 260, and a portion of the concave portion is located in the opening 290. In this case, the concave portion may be filled with an inorganic insulating material or the like.

[0250] In addition, if Figure 1B and Figure 1C As shown, a portion of the conductor 260 is preferably located outside the opening 290, that is, on the conductor 240 and the insulator 280. Figure 1B As shown, the side end of the conductor 260 is preferably located inside the side end of the oxide semiconductor 230. This can prevent the conductor 260 from being short-circuited with the oxide semiconductor 230. In addition, the side end of the conductor 260 may be consistent with the side end of the oxide semiconductor 230, or may be located outside the side end of the oxide semiconductor 230.

[0251] The conductor 120 may be provided in the manner described in [Capacitor 100 ].

[0252] in addition, Figure 1B and Figure 1C Although the top surface of the conductor 120 is flat, the present invention is not limited thereto. For example, a structure may be adopted in which a concave portion overlapping the opening 290 is formed on the top surface of the conductor 120. By adopting a structure in which at least a part of the oxide semiconductor 230, the insulator 250, and the conductor 260 is formed so as to be embedded in the concave portion, the gate electric field of the conductor 260 can be easily applied to the conductor 120 near the oxide semiconductor 230.

[0253] A single layer or a stack of conductors described in [Conductor] described later can be used as the conductor 240. For example, a highly conductive material such as tungsten can be used as the conductor 240.

[0254] As with the conductor 260, the conductor 240 is preferably made of a conductive material that is not easily oxidized or a conductive material that has a function of inhibiting oxygen diffusion. For example, titanium nitride or tantalum nitride can be used. By adopting such a structure, excessive oxidation of the conductor 240 due to the oxide semiconductor 230 can be suppressed.

[0255] Alternatively, for example, tungsten may be stacked on titanium nitride. By stacking layers containing tungsten in this manner, the conductivity of the conductor 240 can be improved, and the conductor 240 can fully function as the wiring BL.

[0256] Furthermore, when the conductor 240 has a stacked structure of a first conductor and a second conductor, for example, the first conductor may be formed of a highly conductive conductive material and the second conductor may be formed of a conductive material containing oxygen. By using a conductive material containing oxygen as the second conductor of the conductor 240 in contact with the insulator 250, it is possible to suppress diffusion of oxygen in the insulator 250 into the first conductor of the conductor 240. For example, tungsten may be used as the first conductor of the conductor 240 and indium tin oxide to which silicon is added may be used as the second conductor of the conductor 240.

[0257] Insulator 140 and insulator 280 are used as interlayer films, so their relative dielectric constant is preferably low. By using a material with a low relative dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced. As insulator 140 and insulator 280, a single layer or a stack of insulators containing a material with a low relative dielectric constant described in [Insulator] described later can be used. Silicon oxide and silicon oxynitride are preferred because they have thermal stability.

[0258] In addition, the concentration of impurities such as water and hydrogen in the insulator 140 and the insulator 280 is preferably reduced. This can prevent impurities such as water and hydrogen from entering the channel formation region of the oxide semiconductor 230 .

[0259] In addition, as the insulator 280 disposed near the channel formation region, an insulator containing excess oxygen is preferably used. By heat-treating the insulator 280 containing excess oxygen, oxygen can be supplied from the insulator 280 to the channel formation region of the oxide semiconductor 230, thereby reducing oxygen vacancies and V O H. Thus, the electrical characteristics of the transistor 200 can be stabilized and the reliability can be improved.

[0260] In addition, an insulator having a function of capturing or fixing hydrogen in the "insulator" described later may be used as the insulator 280. By adopting such a structure, hydrogen in the oxide semiconductor 230 can be captured or fixed to reduce the hydrogen concentration of the oxide semiconductor 230. Magnesium oxide, aluminum oxide, or the like can be used as the insulator 280.

[0261] Note that Figure 1B and Figure 1C The insulator 280 is shown as a single-layer structure, but the present invention is not limited thereto. The insulator 280 may also have a stacked-layer structure.

[0262] For example, Fig.17A and Fig. 17B As shown, the insulator 280 may also have a stacked structure of an insulator 280a, an insulator 280b on the insulator 280a, and an insulator 280c on the insulator 280b.

[0263] The insulator 280b preferably uses an insulator containing oxygen. The insulator 280b preferably has a region having a higher oxygen content than at least one of the insulator 280a and the insulator 280c. In particular, the insulator 280b preferably has a region having a higher oxygen content than the insulator 280a and the insulator 280c, respectively. When the oxygen content of the insulator 280b is high, an i-type region is easily formed in the region in contact with the insulator 280b in the oxide semiconductor 230 and in the vicinity thereof.

[0264] The insulator 280 b is preferably a film that releases oxygen by heating. Since the insulator 280 b releases oxygen due to heat applied in the manufacturing process of the transistor 200, oxygen can be supplied to the oxide semiconductor 230. By supplying oxygen from the insulator 280 b to the oxide semiconductor 230, especially to the channel formation region of the oxide semiconductor 230, oxygen vacancies in the oxide semiconductor 230 and V O H, a transistor with good electrical characteristics and high reliability can be realized.

[0265] For example, oxygen can be supplied to the insulator 280 b by performing heat treatment in an oxygen-containing atmosphere or plasma treatment in an oxygen-containing atmosphere. Alternatively, oxygen can be supplied by depositing an oxide film on the top surface of the insulator 280 b by sputtering in an oxygen atmosphere. The oxide film can then be removed.

[0266] The insulator 280b is preferably formed by a deposition method such as sputtering or plasma enhanced chemical vapor deposition (PECVD). In particular, when the sputtering method is used, a film containing very little hydrogen can be deposited by a deposition method that does not use hydrogen gas as a deposition gas. Therefore, the semiconductor 230 can be suppressed from being supplied with hydrogen, thereby stabilizing the electrical characteristics of the transistor 200.

[0267] When the channel length of the transistor 200 is short, oxygen vacancies in the channel formation region and V O The influence of H on the power supply characteristics and reliability is particularly great. By supplying oxygen from the insulator 280 b to the oxide semiconductor 230, oxygen vacancies and V can be suppressed at least in the region of the oxide semiconductor 230 that is in contact with the insulator 280 b. O H increases. Therefore, a transistor with a short channel length having good electrical characteristics and high reliability can be realized.

[0268] Insulator 280a and insulator 280c preferably use an insulator having oxygen barrier properties as described in [Insulator] to be described later. Thus, it is possible to suppress the diffusion of oxygen in insulator 280b to the substrate side through insulator 280a and to the insulator 250 side through insulator 280c due to heating. In other words, by clamping insulator 280b above and below using insulator 280a and insulator 280c, which are not easy to diffuse oxygen, oxygen in insulator 280b can be confined. Thus, oxygen can be effectively supplied to oxide semiconductor 230.

[0269] In addition, by using an insulator having a barrier property against oxygen as the insulator 280c, the amount of oxygen supplied from the insulator 280 through the insulator 250 to the region in contact with the insulator 250 in the oxide semiconductor 230 is reduced during heat treatment or the like. Fig.17A and Fig. 17B As shown, the region 230na and the region 230nb sometimes extend to one side of the insulator 250.

[0270] In addition, due to the oxygen in the insulator 280b, the conductor 120 and the conductor 240 are oxidized, and sometimes the resistance becomes higher. By providing the insulator 280a between the insulator 280b and the conductor 120, it is possible to suppress the conductor 120 from being oxidized and the resistance from becoming higher. In addition, by providing the insulator 280c between the insulator 280b and the conductor 240, it is possible to suppress the conductor 240 from being oxidized and the resistance from becoming higher. At the same time, the amount of oxygen supplied from the insulator 280b to the oxide semiconductor 230 increases, and the oxygen vacancies in the oxide semiconductor 230 can be reduced.

[0271] In addition, in the oxide semiconductor 230, the amount of oxygen supplied to the region in contact with the insulator 280a and the region in contact with the insulator 280c is smaller than that in contact with the insulator 280b. As a result, the region in contact with the insulator 280a and the region in contact with the insulator 280c of the oxide semiconductor 230 are sometimes reduced in resistance. That is, by adjusting the thickness of the insulator 280a, the range of the region 230na used as one of the source region and the drain region can be controlled. Similarly, by adjusting the thickness of the insulator 280c, the range of the region 230nb used as the other of the source region and the drain region can be controlled.

[0272] As described above, since the source region and the drain region can be controlled by the thickness of the insulator 280 a and the insulator 280 c , the thickness of the insulator 280 a and the insulator 280 c may be appropriately set according to the characteristics required for the transistor 200 .

[0273] For example, Fig.17A and Fig. 17B As shown, the thickness of the insulator 280a and the thickness of the insulator 280c may also be the same or substantially the same. Fig. 17C and Fig.17D As shown, the thickness of insulator 280a may also be greater than the thickness of insulator 280c. Fig. 17C and Fig.17D The structure shown can make the region 230na close to the bottom of the conductor 260 in the opening 290. In this case, it can be said that the range of the region 230i is reduced. As a result, the on-state current of the transistor 200 can be increased.

[0274] In addition, Fig. 17C and Fig.17D , a structure in which an insulator 280c is provided on a flattened insulator 280b is shown, but the present invention is not limited thereto. For example, the insulator 280c may be deposited without performing a flattening treatment on the insulator 280b. By not performing a flattening treatment, the yield rate can be improved while reducing the manufacturing cost. In addition, the insulator 280a, the insulator 280b, and the insulator 280c may be continuously deposited without being exposed to the atmospheric environment. By depositing without being exposed to the atmospheric environment, impurities or moisture from the atmospheric environment may be prevented from adhering to the insulators 280a to 280c, thereby keeping the vicinity of the interface between the insulator 280a and the insulator 280b and the vicinity of the interface between the insulator 280b and the insulator 280c clean.

[0275] Insulator 280a and insulator 280c preferably use an insulator having hydrogen barrier properties described in [Insulator] to be described later. Thus, it is possible to suppress the diffusion of hydrogen from the outside of the transistor through insulator 280a or insulator 280c to oxide semiconductor 230. Since silicon nitride film and silicon oxynitride film have the characteristics of less release of impurities (e.g., water and hydrogen) from themselves and less penetration of oxygen and hydrogen, respectively, they can be applied to insulator 280a and insulator 280c. Note that insulator 280a and insulator 280c can use the same material or different materials.

[0276] In addition, as the insulator 280a, it is preferable to use an insulator having the function of capturing or fixing hydrogen in the [insulator] described later. By adopting such a structure, it is possible to suppress the diffusion of hydrogen from the bottom of the insulator 280a to the oxide semiconductor 230, and to capture or fix the hydrogen in the oxide semiconductor 230, thereby reducing the hydrogen concentration of the oxide semiconductor 230. In addition, it is possible to suppress the diffusion of hydrogen from the top of the insulator 280a to the insulator 130, and to capture or fix the hydrogen in the insulator 130, thereby reducing the hydrogen concentration of the insulator 130. As the insulator 280a, magnesium oxide, aluminum oxide, hafnium oxide, etc. can be used. In addition, for example, as the insulator 280a, a stacked film of aluminum oxide and silicon nitride on the aluminum oxide can also be used.

[0277] The thickness of insulator 280a is preferably smaller than the thickness of insulator 280b. In addition, the thickness of insulator 280c is preferably smaller than the thickness of insulator 280b. The thickness of insulator 280a and insulator 280c is preferably greater than 1 nm and less than 15 nm, more preferably greater than 2 nm and less than 10 nm, further preferably greater than 3 nm and less than 7 nm, and further preferably greater than 3 nm and less than 5 nm. The thickness of insulator 280b is preferably greater than 3 nm and less than 30 nm, more preferably greater than 5 nm and less than 20 nm, and further preferably greater than 7 nm and less than 15 nm. By setting the thickness of insulators 280a to 280c within the above range, oxygen vacancies in the oxide semiconductor 230, especially oxygen vacancies in the channel formation region, can be reduced.

[0278] For example, it is preferable that the insulator 280a and the insulator 280c use silicon nitride, and the insulator 280b use silicon oxide. In this case, the insulator 280a and the insulator 280c contain at least silicon and nitrogen. In addition, the insulator 280b contains at least silicon and oxygen.

[0279] Notice, Fig.17A and Fig. 17B The insulator 280 is shown to have a three-layer stacked structure, but one embodiment of the present invention is not limited thereto. The insulator 280 may have a two-layer stacked structure or a four-layer stacked structure or more.

[0280] The insulator 283 preferably uses an insulator having hydrogen barrier properties as described in [Insulator] described later. Thus, it is possible to suppress the diffusion of hydrogen from the outside of the transistor through the insulator 250 to the oxide semiconductor 230. Since the silicon nitride film and the silicon oxynitride film have the characteristics of less release of impurities (for example, water and hydrogen) from themselves and less penetration of oxygen and hydrogen, they can be applied to the insulator 283.

[0281] In addition, as the insulator 283, it is preferable to use an insulator having a function of capturing or fixing hydrogen in the [insulator] described later. By adopting such a structure, it is possible to suppress the diffusion of hydrogen from above the insulator 283 to the oxide semiconductor 230, and it is possible to capture or fix hydrogen in the oxide semiconductor 230, thereby reducing the hydrogen concentration of the oxide semiconductor 230. As the insulator 283, magnesium oxide, aluminum oxide, or hafnium oxide can be used. For example, as the insulator 283, a stacked film of aluminum oxide and silicon nitride on the aluminum oxide can also be used.

[0282] Although Figure 1B and Figure 1C Although the structure of the region where the top surface of the conductor 120 contacts the bottom surface of the oxide semiconductor 230 is shown, the present invention is not limited thereto. For example, a conductor may be provided between the conductor 120 and the oxide semiconductor 230 .

[0283] For example, Fig.18A and Fig.18B As shown, a conductor 125 may be provided between the conductor 120 and the oxide semiconductor 230. As the conductor 125, it is preferable to use a conductive material containing oxygen in the [Conductor] described later. By using a conductive material containing oxygen as the conductor 125, the conductor 125 can maintain conductivity even if it absorbs oxygen. In addition, diffusion of oxygen in the oxide semiconductor 230 to the conductor 120 can be suppressed. As the conductor 125, for example, indium tin oxide, indium tin oxide added with silicon, indium zinc oxide, etc. can be used in a single layer or a stacked layer.

[0284] In addition, if Fig.18A and Fig.18B As shown, a structure may be adopted in which the side end of the insulator 130 is aligned with the side end of the conductor 115. By adopting such a structure, the insulator 130 and the conductor 115 can be formed using the same mask, thereby simplifying the manufacturing process of the memory device.

[0285] Figure 1B and Figure 1C The structure shown is that the oxide semiconductor 230 has a region in contact with the side surface of the conductor 240 in the opening 290 and a region in contact with a part of the top surface of the conductor 240. Note that the present invention is not limited to this.

[0286] For example, Fig.19B and Fig.19C As shown, the oxide semiconductor 230 may also have an area in contact with the conductor 240 in the opening 290. In this case, the height of the top surface of the oxide semiconductor 230 is consistent with the height of the top surface of the conductor 240. By adopting this structure, the distance from the interface between the conductor 240 in the opening 290 and the oxide semiconductor 230 to the side end of the conductor 240 in the Y direction can be shortened. Therefore, the width of the conductor 240 in the Y direction can be reduced, thereby reducing the interval at which the conductor 240 is configured. In this way, the storage device can be miniaturized or highly integrated. Note that Fig.19A yes Fig.19B and Fig.19C A plan view of the storage device is shown.

[0287] Figure 1B and Figure 1C The structure in which the conductor 240 is provided on the insulator 280 is shown. In addition, the structure in which the insulator 250 has a region in contact with the top surface of the insulator 280 in a region not overlapping with the conductor 240 is also shown. Note that the present invention is not limited to this.

[0288] For example, Fig. 20B and Fig. 20C As shown, an insulator 281 may be provided on the insulator 280 and the conductor 240 may be provided in a manner embedded in the insulator 281. In this case, the height of the top surface of the conductor 240 is preferably consistent with the height of the top surface of the insulator 281. By adopting this structure, the physical distance from the conductor 260 to the conductor 240 (especially the side end of the conductor 240) can be increased, and the conductor 260 and the conductor 240 can be prevented from short-circuiting. Note that Fig. 20A yes Fig. 20B and Fig. 20C A plan view of the storage device is shown.

[0289] Since the insulator 281 is used as an interlayer film, it is preferable to use a material with a low relative dielectric constant. By using a material with a low relative dielectric constant for the interlayer film, the parasitic capacitance generated between the wirings can be reduced. As the insulator 281, a single layer or a stack of insulators containing a material with a low relative dielectric constant described in [Insulator] described later can be used.

[0290] In addition, if Figure 1A and Figure 1C As shown in FIG. 1 , the conductor 260 is extended to be used as wiring. In addition, the conductor 260 is commonly used by a plurality of transistors. However, the present invention is not limited to this, and a conductor used as wiring may be provided on the conductor 260 .

[0291] For example, FIG. 21A to FIG. 21C As shown, a conductor 265 may also be provided on the conductor 260. FIG. 21A to FIG. 21C In the embodiment, one conductor 260 is provided in each transistor. Note that one conductor 260 does not necessarily need to be provided in each transistor. For example, the conductor 260 may be commonly used by a plurality of transistors.

[0292] In the above structure, the conductor 260 is preferably provided in a manner embedded in the insulator 287. At this time, the height of the top surface of the conductor 260 is preferably consistent with the height of the top surface of the insulator 287. By adopting this structure, the conductor 260 and the conductor 240 can be prevented from being short-circuited.

[0293] The conductor 265 is used as a wiring WL electrically connected to the gate of the transistor 200. As the conductor 265, a single layer or a stacked layer of the conductors described in the above-mentioned [Conductor] can be used. For example, as the conductor 265, a highly conductive material such as tungsten can be used.

[0294] The conductor 265 is preferably provided in a manner embedded in the insulator 289. At this time, the height of the top surface of the conductor 265 and the height of the top surface of the insulator 289 are preferably consistent.

[0295] Since insulator 287 and insulator 289 are used as interlayer films, it is preferable to use a material with a low relative dielectric constant. By using a material with a low relative dielectric constant for the interlayer film, the parasitic capacitance generated between wirings can be reduced. As insulator 287 and insulator 289, a single layer or a stack of insulators containing a material with a low relative dielectric constant described in [Insulator] above can be used.

[0296] exist Fig. 21B The side end of the conductor 265 is consistent with the side end of the conductor 260, but the present invention is not limited thereto. For example, the side end of the conductor 265 can be located outside the side end of the conductor 260, or inside the side end of the conductor 260.

[0297] <Constituent Materials of Storage Device> Next, constituent materials that can be used for the storage device are described.

[0298] [Substrate] As a substrate for forming the transistor 200 and the capacitor 100, for example, an insulator substrate, a semiconductor substrate or a conductor substrate can be used. As an insulator substrate, for example, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (yttria stabilized zirconia substrate, etc.), a resin substrate, etc. can be cited. In addition, as a semiconductor substrate, for example, a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate composed of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, etc. can be cited. In addition, a semiconductor substrate having an insulator region inside the above-mentioned semiconductor substrate, such as an SOI (Silicon On Insulator) substrate, etc. can also be cited. As a conductor substrate, a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, etc. can be cited. Alternatively, a substrate containing a metal nitride, a substrate containing a metal oxide, etc. can be cited. In addition, an insulator substrate provided with a conductor or a semiconductor, a semiconductor substrate provided with a conductor or an insulator, a conductor substrate provided with a semiconductor or an insulator, etc. can also be cited. Alternatively, a substrate provided with an element on these substrates can also be used. Examples of the element provided over the substrate include a capacitor, a resistor, a switching element, a light emitting element, and a memory element.

[0299] [Insulator] Examples of the insulator include oxides, nitrides, oxynitrides, oxynitrides, metal oxides, metal oxynitrides, and metal oxynitrides having insulating properties.

[0300] For example, when miniaturization and high integration of transistors are carried out, problems such as leakage current sometimes occur due to the thin film of the gate insulator. By using a high-k material as an insulator used as a gate insulator, it is possible to achieve low voltage when the transistor is operating while maintaining the physical thickness. In addition, the equivalent oxide thickness (EOT: Equivalent Oxide Thickness) of the insulator used as a gate insulator can be reduced. On the other hand, by using a material with a low relative dielectric constant for an insulator used as an interlayer film, the parasitic capacitance generated between the wirings can be reduced. Therefore, it is preferable to select the material according to the function of the insulator. In addition, a material with a low relative dielectric constant is also a material with a high dielectric strength.

[0301] Examples of materials with a high relative dielectric constant (high-k) include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0302] As materials with low relative dielectric constants, for example, inorganic insulating materials such as silicon oxide, silicon oxynitride and silicon nitride oxide, resins such as polyester, polyolefin, polyamide (nylon, aromatic polyamide, etc.), polyimide, polycarbonate and acrylic resin can be cited. In addition, as inorganic insulating materials with low relative dielectric constants other than the above, for example, silicon oxide added with fluorine, silicon oxide added with carbon, and silicon oxide added with carbon and nitrogen can be cited. In addition, silicon oxide with holes can be cited. In addition, these silicon oxides can also contain nitrogen.

[0303] In addition, by surrounding a transistor using a metal oxide with an insulator having a function of suppressing the transmission of impurities and oxygen, the electrical characteristics of the transistor can be stabilized. As an insulator having a function of suppressing the transmission of impurities and oxygen, for example, a single layer or a stack of insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium or tantalum can be used. Specifically, as an insulator having a function of suppressing the transmission of impurities and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon oxynitride, and silicon nitride can be used.

[0304] In addition, an insulator such as a gate insulator that contacts the semiconductor layer or an insulator that is disposed near the semiconductor layer is preferably an insulator having a region containing excess oxygen. For example, when an insulator having a region containing excess oxygen contacts the semiconductor layer, or when an insulator having a region containing excess oxygen is disposed near the semiconductor layer, oxygen vacancies in the semiconductor layer can be reduced. Examples of insulators that easily form a region containing excess oxygen include silicon oxide, silicon oxynitride, or silicon oxide having holes.

[0305] In addition, as an insulator having oxygen barrier properties, there can be mentioned an oxide containing one or both of aluminum and hafnium, an oxide containing hafnium and silicon (hafnium silicate), magnesium oxide, gallium oxide, gallium zinc oxide, indium gallium zinc oxide, silicon nitride, silicon oxynitride, etc. In addition, as an oxide containing one or both of aluminum and hafnium, there can be mentioned aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc.

[0306] In addition, examples of insulators having hydrogen barrier properties include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, and silicon nitride oxide.

[0307] An insulator having oxygen barrier properties and an insulator having hydrogen barrier properties can be said to be an insulator having barrier properties to one or both of oxygen and hydrogen.

[0308] In addition, as an insulator having the function of capturing or fixing hydrogen, an oxide containing magnesium or an oxide containing one or both of aluminum and hafnium can be cited. In addition, these oxides more preferably have an amorphous structure. Oxides having an amorphous structure sometimes have the following properties: oxygen atoms have dangling bonds and hydrogen is captured or fixed by the dangling bonds. In addition, these metal oxides preferably have an amorphous structure, but a portion thereof may also be formed with a crystalline region.

[0309] Note that in this specification, etc., a blocking insulating film refers to an insulating film having a barrier property. In addition, the barrier property refers to the property that the corresponding substance is not easily diffused (also referred to as the property that the corresponding substance is not easily permeable, the property that the corresponding substance has low permeability, or the function of inhibiting the diffusion of the corresponding substance). In addition, the function of capturing or fixing (also referred to as impurity absorption) the corresponding substance can be replaced by the term barrier property. In addition, hydrogen recorded as the corresponding substance refers to, for example, hydrogen atoms, hydrogen molecules, water molecules, and OH. - In addition, unless otherwise stated, the impurities recorded as corresponding substances refer to impurities in the channel formation region or in the semiconductor layer, for example, at least one of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), copper atoms, etc. In addition, oxygen recorded as corresponding substances refers to at least one of oxygen atoms, oxygen molecules, etc. Specifically, oxygen barrier property refers to the property that at least one of oxygen atoms, oxygen molecules, etc. is not easily diffused.

[0310] [Conductor] As the conductor, it is preferred to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium and lanthanum, an alloy with the above metal elements as a component, or an alloy combining the above metal elements, etc. As the alloy with the above metal elements as a component, the nitride of the alloy or the oxide of the alloy can also be used. For example, tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. are preferably used. In addition, semiconductors with high conductivity represented by polycrystalline silicon containing impurity elements such as phosphorus and silicides such as nickel silicide can also be used.

[0311] In addition, conductive materials containing nitrogen such as tantalum nitride, titanium nitride, molybdenum nitride, tungsten nitride, ruthenium nitride, tantalum and aluminum nitride or titanium and aluminum nitride, conductive materials containing oxygen such as ruthenium oxide, strontium and ruthenium oxide or lanthanum and nickel oxide, and materials containing metal elements such as titanium, tantalum or ruthenium are conductive materials that are not easily oxidized, conductive materials that have the function of inhibiting oxygen diffusion, or materials that maintain conductivity even when absorbing oxygen, so they are preferred. As conductive materials containing oxygen, indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium tin oxide added with silicon, indium zinc oxide, and indium zinc oxide containing tungsten oxide can be cited. In this specification, etc., a conductive film deposited using a conductive material containing oxygen is sometimes referred to as an oxide conductive film.

[0312] Furthermore, a conductive material mainly composed of tungsten, copper, or aluminum is preferred because of its high conductivity.

[0313] In addition, a plurality of conductive layers formed of the above-mentioned materials may be stacked. For example, a laminated structure in which a material containing the above-mentioned metal element and a conductive material containing oxygen are combined may be used. In addition, a laminated structure in which a material containing the above-mentioned metal element and a conductive material containing nitrogen are combined may be used. In addition, a laminated structure in which a material containing the above-mentioned metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined may be used.

[0314] In addition, when a metal oxide is used in the channel formation region of the transistor, the conductor used as the gate electrode preferably adopts a laminated structure combining a material containing the above-mentioned metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably arranged on one side of the channel formation region. By arranging the conductive material containing oxygen on one side of the channel formation region, oxygen separated from the conductive material is easily supplied to the channel formation region.

[0315] In particular, as a conductor used as a gate electrode, it is preferred to use a conductive material containing a metal element contained in a metal oxide in which a channel is formed and oxygen. In addition, a conductive material containing the above-mentioned metal element and nitrogen can also be used. For example, a conductive material containing nitrogen such as titanium nitride and tantalum nitride can also be used. In addition, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide added with silicon can also be used. In addition, indium gallium zinc oxide containing nitrogen can also be used. By using the above-mentioned materials, hydrogen contained in the metal oxide in which a channel is formed can sometimes be captured. Alternatively, hydrogen mixed from an external insulator can sometimes be captured.

[0316] [Metal oxides] Metal oxides sometimes have lattice defects. Lattice defects refer to point defects such as atomic vacancies and foreign atoms, line defects such as dislocations, surface defects such as grain boundaries, and volume defects such as voids. In addition, the main causes of lattice defects include differences in the ratio of the number of atoms of constituent elements (excess or deficiency of constituent atoms) and impurities.

[0317] When a metal oxide is used for a semiconductor layer of a transistor, lattice defects in the metal oxide may lead to generation or capture of carriers, etc. Therefore, when a metal oxide with many lattice defects is used for a semiconductor layer of a transistor, the electrical characteristics of the transistor may be unstable. Therefore, it is preferred that the metal oxide used for the semiconductor layer of the transistor has fewer lattice defects.

[0318] In a transistor using a metal oxide, in particular, if oxygen vacancies (V O ) and impurities, the electrical properties are easily changed, sometimes reducing reliability. In addition, hydrogen near the oxygen vacancy forms a defect in which hydrogen enters the oxygen vacancy (V O H) and may generate electrons that become carriers. Thus, when the channel formation region in the metal oxide contains oxygen vacancies, the transistor tends to have a normally-on characteristic. Thus, in the channel formation region of the metal oxide, it is preferred to minimize oxygen vacancies and impurities. In other words, it is preferred that the carrier concentration in the channel formation region of the metal oxide is reduced and is i-typed (intrinsic) or substantially i-typed.

[0319] The type of lattice defects that are likely to exist in the metal oxide and the amount of the lattice defects that exist vary depending on the structure of the metal oxide, the method of depositing the metal oxide, and the like.

[0320] The structure of metal oxides is divided into single crystal structure and other structures (non-single crystal structure). As non-single crystal structures, there are CAAC structure, polycrystalline structure, nc structure, amorphous-like (a-like) structure and amorphous structure. The a-like structure has a structure between the nc structure and the amorphous structure. Note that the classification of crystal structures will be described later.

[0321] In addition, there are voids or low-density areas in metal oxides having an a-like structure and metal oxides having an amorphous structure. In other words, the crystallinity of metal oxides having an a-like structure and metal oxides having an amorphous structure is lower than that of metal oxides having a nc structure and metal oxides having a CAAC structure. In addition, the hydrogen concentration in the metal oxide of the metal oxide having an a-like structure is higher than that of the metal oxide having a nc structure and the metal oxide having a CAAC structure. Therefore, lattice defects are easily generated in metal oxides having an a-like structure and metal oxides having an amorphous structure.

[0322] Therefore, it is preferred to use a metal oxide with high crystallinity for the semiconductor layer of the transistor. For example, it is preferred to use a metal oxide with a CAAC structure or a metal oxide with a single crystal structure. By using the metal oxide for a transistor, a transistor with good electrical characteristics can be realized. In addition, a transistor with high reliability can be realized.

[0323] In addition, the channel formation region of the transistor preferably uses a metal oxide that increases the on-state current of the transistor. In order to increase the on-state current of the transistor, it is sufficient to increase the carrier mobility of the metal oxide used for the transistor. In order to improve the carrier mobility of the metal oxide, it is necessary to increase the transmission of carriers (electrons in the case of n-channel transistors) or reduce the scattering factors that affect the transmission of carriers. In addition, carriers flow from the source to the drain through the channel formation region. Therefore, by setting a channel formation region where carriers easily flow in the channel length direction, the on-state current of the transistor can be increased.

[0324] Here, the metal oxide having the channel formation region preferably adopts a metal oxide with high crystallinity. Furthermore, the crystal preferably has a crystal structure having multiple layers (e.g., a first layer, a second layer, and a third layer) stacked. In other words, the crystal has a layered crystal structure (also referred to as a layered crystal, a layered structure). At this time, the c-axis direction of the crystal is the direction in which multiple layers are stacked. Metal oxides having the crystal include, for example, single crystal oxide semiconductors, CAAC-OS, etc.

[0325] In addition, the c-axis of the crystal is preferably oriented in the normal direction of the formed surface or film surface of the metal oxide. Thus, the multiple layers are arranged in parallel or approximately parallel to the formed surface or film surface of the metal oxide. That is, the multiple layers extend in the channel length direction.

[0326] For example, the three-layered crystal structure has the following structure. The first layer has an atomic coordination structure of an oxygen octahedron in which the metal contained in the first layer exists at the center. In addition, the second layer has an atomic coordination structure of an oxygen triangular bipyramid or tetrahedron in which the metal contained in the second layer exists at the center. In addition, the third layer has an atomic coordination structure of an oxygen triangular bipyramid or tetrahedron in which the metal contained in the third layer exists at the center.

[0327] Examples of the crystal structure of the above-mentioned crystal include a YbFe2O4 type structure, a Yb2Fe3O7 type structure, and deformation structures thereof.

[0328] Furthermore, it is preferred that the first to third layers are all composed of one metal element or a plurality of metal elements having the same valence and oxygen. Note that it is preferred that the valence of the one or more metal elements constituting the first layer is the same as the valence of the one or more metal elements constituting the second layer. In addition, the first layer and the second layer may also contain the same metal element. In addition, it is preferred that the valence of the one or more metal elements constituting the first layer is different from the valence of the one or more metal elements constituting the third layer.

[0329] By adopting the above structure, the crystallinity of the metal oxide can be improved and the carrier mobility of the metal oxide can be improved. Therefore, by using the metal oxide in the channel formation region of the transistor, the on-state current of the transistor is increased and the electrical characteristics of the transistor can be improved.

[0330] As a metal oxide of one embodiment of the present invention, for example, indium oxide, gallium oxide and zinc oxide can be cited. The metal oxide of one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn). In addition, the metal oxide preferably contains two or three selected from indium, element M and zinc. Note that element M is a metal element or semi-metal element with high bonding energy with oxygen, for example, a metal element or semi-metal element with higher bonding energy with oxygen than indium. As element M, specifically, aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium and antimony can be cited. The element M contained in the metal oxide is preferably any one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin and yttrium, and further preferably gallium. In the case where the element M contained in the metal oxide is gallium, the metal oxide of one embodiment of the present invention preferably contains any one or more selected from indium, gallium and zinc. Note that in this specification and the like, metal elements and semi-metal elements may be collectively referred to as “metal elements”, and the “metal elements” described in this specification and the like may include semi-metal elements.

[0331] As a metal oxide semiconductor of one embodiment of the present invention, for example, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide, also referred to as AZO), indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO), etc. can be used. Alternatively, indium tin oxide, gallium tin oxide (Ga—Sn oxide), aluminum tin oxide (Al—Sn oxide) and the like containing silicon may be mentioned.

[0332] By increasing the atomic number ratio of indium relative to the total atomic number of all metal elements in the metal oxide, the field effect mobility of the transistor can be increased.

[0333] Note that the metal oxide may also contain one or more metal elements with a large periodic number in the periodic table instead of indium. Alternatively, the metal oxide may also contain one or more metal elements with a large periodic number in the periodic table in addition to indium. There is a tendency that the greater the orbital overlap of the metal element, the greater the carrier conduction in the metal oxide. Therefore, by including a metal element with a large periodic number in the periodic table, the field effect mobility of the transistor can sometimes be improved. As metal elements with a large periodic number in the periodic table, metal elements belonging to the 5th period and metal elements belonging to the 6th period can be cited. As the metal element, specifically, yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium and europium can be cited. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium and europium are called light rare earth elements.

[0334] In addition, the metal oxide may also contain one or more non-metallic elements. The inclusion of non-metallic elements in the metal oxide may sometimes improve the field effect mobility of the transistor. Examples of the non-metallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0335] In addition, by increasing the ratio of the number of zinc atoms to the total number of atoms of all metal elements in the metal oxide, the metal oxide can be made highly crystalline, thereby suppressing the diffusion of impurities in the metal oxide. Therefore, the variation of the electrical characteristics of the transistor can be suppressed and the reliability can be improved.

[0336] In addition, by increasing the atomic number ratio of the element M relative to the total atomic number of all metal elements in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, the generation of carriers due to oxygen vacancies is suppressed, thereby realizing a transistor with a small off-state current. In addition, the variation of the electrical characteristics of the transistor is suppressed and the reliability can be improved.

[0337] In addition, by increasing the atomic number ratio of In relative to the total atomic number of all metal elements in the metal oxide, the transistor can obtain a large on-state current and high frequency characteristics.

[0338] In this embodiment, In—Ga—Zn oxide is sometimes described as an example of a metal oxide.

[0339] In order to form the metal oxide having the layered crystal structure, it is preferable to deposit atoms layer by layer. In the method for depositing a metal oxide according to one embodiment of the present invention, since the ALD method is used, the metal oxide having the layered crystal structure can be easily formed.

[0340] Examples of the ALD method include a thermal ALD method in which a precursor and a reactant react using only thermal energy and a plasma ALD (PEALD: Plasma Enhanced ALD) method using a reactant excited by plasma.

[0341] The ALD method can deposit atoms layer by layer, and thus has the following effects: it can deposit very thin films; it can deposit structures with high aspect ratios; it can deposit in a manner with few defects such as pinholes; it can deposit with high coverage; it can deposit at low temperatures, etc. In addition, in the PEALD method, deposition can be performed at a lower temperature by using plasma, so it is sometimes preferred. In addition, the precursor used in the ALD method sometimes contains elements such as carbon or chlorine. Therefore, the film set by the ALD method sometimes contains more elements such as carbon or chlorine than the film set by other deposition methods. In addition, the quantification of these elements can be performed using XPS or secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry). Note that the deposition method of the metal oxide as one embodiment of the present invention uses the ALD method, but due to the use of one or both of the conditions of high substrate temperature during deposition and impurity removal treatment, the amount of carbon and chlorine contained in the film is sometimes less than when the ALD method is used without the above conditions.

[0342] The ALD method is different from a deposition method in which particles released from a target material are deposited, and is a film-forming method in which a film is formed due to a reaction on the surface of the object to be processed. Therefore, the ALD method is a deposition method that is not easily affected by the shape of the object to be processed and has good step coverage. In particular, the ALD method has good step coverage and thickness uniformity, so the ALD method is suitable for covering the surface of an opening with a high aspect ratio. However, the deposition rate of the ALD method is relatively slow, so it is sometimes preferably used in combination with other deposition methods such as sputtering or CVD methods with fast deposition rates. For example, a method in which a first metal oxide is deposited by sputtering and a second metal oxide is deposited on the first metal oxide by the ALD method can be cited. For example, in the case where the first metal oxide has a crystalline portion, the second metal oxide sometimes grows crystals with the crystalline portion as a core.

[0343] The ALD method can control the composition of the obtained film according to the amount of source gas introduced. For example, when the ALD method is used, a film of any composition can be deposited by adjusting the amount of source gas introduced, the number of introductions (also called the number of pulses), and the time required for one pulse (also called the pulse time). In addition, for example, when the ALD method is used, a film whose composition changes continuously can be deposited by changing the source gas while performing deposition. When deposition is performed while changing the source gas, since the time required for conveying or adjusting the pressure is not required, the deposition time can be shortened compared to the case where deposition is performed using multiple deposition chambers. Therefore, the productivity of the storage device can sometimes be improved.

[0344] [[Transistor including an oxide semiconductor]] Next, a case where a metal oxide (oxide semiconductor) is used for a transistor is described. Hereinafter, a transistor using an oxide semiconductor in a semiconductor layer may be referred to as an OS transistor, and a transistor using silicon in a semiconductor layer may be referred to as a Si transistor.

[0345] By using a metal oxide (oxide semiconductor) of one embodiment of the present invention for a transistor, a transistor with high field effect mobility can be realized. In addition, a transistor with high reliability can be realized. In addition, a miniaturized or highly integrated transistor can be realized. For example, a transistor with a channel length of more than 2nm and less than 30nm can be manufactured.

[0346] It is preferable to use an oxide semiconductor with a low carrier concentration in the channel formation region of the transistor. For example, the carrier concentration in the channel formation region of the oxide semiconductor can be 1×10 18 cm -3 Below, preferably 1×10 17 cm -3 Below, more preferably 1×10 15 cm -3 Below, more preferably 1×10 13 cm -3 Below, more preferably 1×10 11 cm -3 Below, more preferably less than 1×10 10 cm -3 , and is 1×10 -9 cm -3 Above. Note that, when the purpose is to reduce the carrier concentration of the oxide semiconductor film, it is sufficient to reduce the impurity concentration in the oxide semiconductor film to reduce the defect state density. In this specification, etc., a state in which the impurity concentration is low and the defect state density is low is referred to as high-purity intrinsic or substantially high-purity intrinsic. In addition, an oxide semiconductor with a low carrier concentration is sometimes referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.

[0347] Since the defect state density of a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film is low, the trap state density may also be low.

[0348] Furthermore, it takes a long time for charges trapped in trap states of an oxide semiconductor to disappear, and they may behave like fixed charges. Therefore, the electrical characteristics of a transistor having a channel formation region formed in an oxide semiconductor with a high trap state density may be unstable.

[0349] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In addition, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the nearby film. As impurities, hydrogen, carbon, nitrogen, etc. can be cited. Note that impurities in oxide semiconductors refer to, for example, elements other than the main components that constitute the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic% can be said to be an impurity.

[0350] In addition, the band gap of the oxide semiconductor is preferably larger than the band gap of silicon (typically 1.1 eV), preferably 2 eV or more, more preferably 2.5 eV or more, and further preferably 3.0 eV or more. By using an oxide semiconductor whose band gap is larger than that of silicon, the off-state current (also called Ioff) of the transistor can be reduced.

[0351] In addition, in Si transistors, the short channel effect (also called Short Channel Effect: SCE) appears as the miniaturization of transistors develops. Therefore, the miniaturization of Si transistors is difficult. One of the reasons for the short channel effect is that the band gap of silicon is small. On the other hand, OS transistors use oxide semiconductors as semiconductor materials with large band gaps, which can suppress the short channel effect. In other words, OS transistors are transistors with no short channel effect or very little short channel effect.

[0352] In addition, the short channel effect refers to the degradation of electrical characteristics that occurs with the miniaturization of transistors (reduction of channel length). Specific examples of the short channel effect include a reduction in threshold voltage, an increase in subthreshold swing value (sometimes recorded as S value), and an increase in leakage current. Here, the S value refers to the change in gate voltage in the subthreshold region that changes the drain current value by one digit with a fixed drain voltage.

[0353] In addition, as an indicator of resistance to short channel effects, characteristic length is widely used. Characteristic length refers to an indicator of the curvature of the potential in the channel formation region. The smaller the characteristic length, the more rapidly the potential rises, so it can be said that the ability to resist short channel effects is high.

[0354] OS transistors are accumulation-type transistors, and Si transistors are inversion-type transistors. Therefore, compared with Si transistors, the characteristic length between the source region and the channel formation region of OS transistors and the characteristic length between the drain region and the channel formation region are smaller. Therefore, compared with Si transistors, OS transistors have a higher ability to resist short channel effects. That is to say, in the case of manufacturing transistors with short channel lengths, OS transistors are more preferred than Si transistors.

[0355] When the carrier concentration of the oxide semiconductor is reduced until the channel formation region becomes i-type or substantially i-type, in a short channel transistor, the lower end of the conduction band of the channel formation region decreases due to the conduction-band-lowering (CBL) effect, and thus the energy difference between the lower end of the conduction band of the source region or the drain region and the channel formation region may be reduced to more than 0.1 eV and less than 0.2 eV. Therefore, the OS transistor can also be regarded as a channel formation region becoming n-type. - type region and the source region and drain region become n + n + / n - / n + Accumulation type junction-less transistor structure or n + / n - / n + Accumulation-type non-junction transistor structure.

[0356] By having the above structure, the OS transistor can have good electrical characteristics even if the storage device is miniaturized or highly integrated. For example, even if the channel length or gate length of the OS transistor is less than 20nm, less than 15nm, less than 10nm, less than 7nm or less than 6nm and more than 1nm, more than 3nm or more than 5nm, good electrical characteristics can be obtained. On the other hand, a short channel effect occurs in Si transistors, so it is sometimes difficult to set the gate length to less than 20nm or less than 15nm. Therefore, compared with Si transistors, OS transistors can be suitable for transistors with short channel lengths. Note that the gate length refers to the length of the gate electrode in the direction in which carriers migrate in the channel formation region when the transistor is operating.

[0357] In addition, by miniaturizing the OS transistor, the high-frequency characteristics of the transistor can be improved. Specifically, the cutoff frequency of the transistor can be increased. When the gate length of the OS transistor is within the above range, for example, the cutoff frequency of the transistor can be above 50 GHz, preferably above 100 GHz, and more preferably above 150 GHz at room temperature.

[0358] As described above, the OS transistor has advantages superior to the Si transistor, such as a small off-state current and the ability to manufacture a transistor with a short channel length.

[0359] [[Impurities in metal oxides]] Here, the influence of each impurity in the metal oxide (oxide semiconductor) is described.

[0360] When the oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, a defect state is formed in the oxide semiconductor. Thus, the carbon concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 20 atoms / cm 3 Below, preferably 5×10 19 atoms / cm 3 Below, more preferably 3×10 19 atoms / cm 3 Below, more preferably 1×10 19 atoms / cm 3 Below, more preferably 3×10 18 atoms / cm 3 Below, more preferably 1×10 18 atoms / cm 3 In addition, the silicon concentration in the channel formation region of the oxide semiconductor measured by SIMS was set to 1×10 20 atoms / cm 3 Below, preferably 5×10 19 atoms / cm 3 Below, more preferably 3×10 19 atoms / cm 3 Below, more preferably 1×10 19 atoms / cm 3 Below, more preferably 3×10 18 atoms / cm 3 Below, more preferably 1×10 18 atoms / cm 3 the following.

[0361] In addition, when the oxide semiconductor contains nitrogen, electrons as carriers are generated, which increases the carrier concentration and is easily converted to n-type. As a result, transistors using oxide semiconductors containing nitrogen as semiconductors tend to have normally-on characteristics. Alternatively, when the oxide semiconductor contains nitrogen, trap states are sometimes formed. As a result, the electrical characteristics of the transistor are sometimes unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 20 atoms / cm 3 Below, preferably 5×10 19 atoms / cm 3 Below, more preferably 1×10 19 atoms / cm 3 Below, more preferably 5×10 18 atoms / cm 3 Below, more preferably 1×1018 atoms / cm 3 Below, more preferably 5×10 17 atoms / cm 3 the following.

[0362] In addition, hydrogen contained in the oxide semiconductor reacts with oxygen bonded to metal atoms to generate water, thereby sometimes forming oxygen vacancies. When hydrogen enters the oxygen vacancy, electrons as carriers are sometimes generated. In addition, sometimes electrons as carriers are generated because part of the hydrogen is bonded to oxygen bonded to metal atoms. Therefore, transistors using oxide semiconductors containing hydrogen tend to have normally-on characteristics. Therefore, it is preferred to reduce the hydrogen in the channel formation region of the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to less than 1×10 20 atoms / cm 3 , preferably less than 5×10 19 atoms / cm 3 , more preferably less than 1×10 19 atoms / cm 3 , more preferably less than 5×10 18 atoms / cm 3 , and more preferably less than 1×10 18 atoms / cm 3 .

[0363] In addition, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, a defect state is sometimes formed to generate carriers. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have a normally-on characteristic. Thus, the concentration of the alkali metal or alkaline earth metal in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 18 atoms / cm 3 Below, preferably 2×10 16 atoms / cm 3 the following.

[0364] By using an oxide semiconductor in which impurities are sufficiently reduced for a channel formation region of a transistor, the transistor can have stable electrical characteristics.

[0365] [Other semiconductor materials] The oxide semiconductor 230 may be referred to as a semiconductor layer having a channel formation region of a transistor. The semiconductor material that can be used for the semiconductor layer is not limited to the above-mentioned metal oxides. As the semiconductor layer, a semiconductor material having a band gap (a semiconductor material that is not a zero band gap semiconductor) may also be used. For example, a single element semiconductor, a compound semiconductor, or a layered material (also referred to as an atomic layer material, a two-dimensional material, etc.) is preferably used for the semiconductor material.

[0366] Here, in this specification, etc., a layered material is a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked by bonds such as van der Waals forces that are weaker than covalent bonds and ionic bonds. A layered material has high conductivity in a unit layer, that is, has high two-dimensional conductivity. By using a material that is used as a semiconductor and has high two-dimensional conductivity in a channel formation region, a transistor with a large on-state current can be provided.

[0367] As single element semiconductors that can be used as semiconductor materials, silicon and germanium can be cited. As silicon that can be used for the semiconductor layer, single crystal silicon, polycrystalline silicon, microcrystalline silicon and amorphous silicon can be cited. As polycrystalline silicon, for example, low temperature polycrystalline silicon (LTPS: Low Temperature Poly Silicon) can be cited.

[0368] As compound semiconductors that can be used as semiconductor materials, silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide can be cited. Boron nitride that can be used for the semiconductor layer preferably has an amorphous structure. Boron arsenide that can be used for the semiconductor layer preferably includes crystals having a cubic crystal structure.

[0369] As layered materials, there are graphene, silicene, boron carbonitride, chalcogenides, etc. In boron carbonitride as a layered material, carbon atoms, nitrogen atoms and boron atoms are arranged in a hexagonal lattice structure on a plane. Chalcogenides are compounds containing chalcogen elements. In addition, chalcogen elements are a general term for elements belonging to Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and lead. In addition, as chalcogenides, transition metal chalcogenides, Group 13 chalcogenides, etc. can be cited.

[0370] As the semiconductor layer, for example, a transition metal chalcogenide used as a semiconductor is preferably used. As the transition metal chalcogenide that can be used as a semiconductor layer, specifically molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), zirconium selenide (typically ZrSe2), etc. can be cited. By using the above-mentioned transition metal chalcogenides for the semiconductor layer, a storage device with a large on-state current can be provided.

[0371] <Example 1 of a method for manufacturing a storage device> Next, use FIG. 22A to FIG. 32C illustrate Figures 1A to 1C A method for manufacturing a storage device according to one embodiment of the present invention is shown.

[0372] exist FIG. 22A to FIG. 32C In each of the drawings, A is a plan view. In addition, B in each of the drawings is a cross-sectional view of a portion along the dashed line A1-A2 in A in each of the drawings. C in each of the drawings is a cross-sectional view of a portion along the dashed line A3-A4 in A in each of the drawings. Note that in the plan view of A in each of the drawings, some components are omitted for clarity.

[0373] Hereinafter, insulating materials for forming insulators, conductive materials for forming conductors, or semiconductor materials for forming semiconductors can be appropriately deposited using sputtering, CVD, molecular beam epitaxy (MBE), pulsed laser deposition (PLD), ALD, or the like.

[0374] In addition, as a sputtering method, there can be RF sputtering method using a high frequency power supply for a sputtering power supply, DC sputtering method using a direct current power supply, and pulse DC sputtering method changing the voltage applied to the electrode in a pulsed manner. RF sputtering method is mainly used when depositing insulating films, and DC sputtering method is mainly used when depositing metal conductive films. In addition, pulse DC sputtering method is mainly used when depositing compounds such as oxides, nitrides, and carbides using a reactive sputtering method.

[0375] Note that the CVD method can be divided into a plasma CVD (PECVD) method using plasma, a thermal CVD (TCVD: Thermal CVD) method using heat, a photo CVD (Photo CVD) method using light, etc. Furthermore, it can be divided into a metal CVD (MCVD: Metal CVD) method and an organic metal CVD (MOCVD: Metal Organic CVD) method according to the source gas used.

[0376] By utilizing the plasma CVD method, a high-quality film can be obtained at a lower temperature. In addition, since plasma is not used in the thermal CVD method, plasma damage to the object being processed can be reduced. For example, the wiring, electrodes, components (transistors, capacitors, etc.) included in the storage device sometimes receive charges from plasma and generate charge accumulation (charge up). At this time, the wiring, electrodes, components, etc. included in the storage device are sometimes damaged by the accumulated charges. On the other hand, since the above-mentioned plasma damage does not occur when the thermal CVD method that does not use plasma is used, the yield of the storage device can be improved. In addition, when the thermal CVD method is used, plasma damage during deposition does not occur, so a film with fewer defects can be obtained.

[0377] As the ALD method, a thermal ALD method in which a precursor and a reactant react using only thermal energy, a PEALD method using a reactant excited by plasma, or the like can be used.

[0378] The CVD method and the ALD method are different from the sputtering method in which particles released from a target material or the like are deposited. Therefore, the CVD method and the ALD method are deposition methods that are not easily affected by the shape of the object to be processed and have good step coverage. In particular, the ALD method has good step coverage and thickness uniformity, so the ALD method is suitable for covering the surface of an opening with a high aspect ratio, etc. However, the deposition rate of the ALD method is relatively slow, so it is sometimes preferred to use it in combination with other deposition methods such as the CVD method with a fast deposition rate.

[0379] In addition, when the CVD method is used, a film of any composition can be deposited according to the flow ratio of the source gas. For example, when the CVD method is used, a film whose composition continuously changes can be deposited by changing the flow ratio of the source gas while performing deposition. When deposition is performed while changing the flow ratio of the source gas, since the time required for conveying or adjusting the pressure is not required, the deposition time can be shortened compared to the case where deposition is performed using multiple deposition chambers. Therefore, the productivity of the storage device can sometimes be improved.

[0380] In addition, when the ALD method is used, a film of any composition can be deposited by introducing different multiple precursors at the same time. In addition, when introducing different multiple precursors, a film of any composition can be deposited by controlling the number of cycles of each precursor.

[0381] First, a substrate (not shown) is prepared and an insulator 140 is formed on the substrate (see FIG. 22A to FIG. 22C ). The above-mentioned insulating materials can be appropriately used as the insulator 140. When depositing the insulator 140, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. can be appropriately used.

[0382] Next, the conductor 110 is formed on the insulator 140. As the conductor 110, the above-mentioned conductive materials can be used appropriately. When depositing the conductor 110, sputtering, CVD, MBE, PLD, ALD, etc. can be used appropriately. For example, as the conductor 110, a stacked film in which tungsten and titanium nitride are deposited in sequence can be formed by CVD.

[0383] In addition, the conductor 110 may be processed into a shape extending in the X direction or the Y direction. The conductor 110 may be processed by photolithography. Dry etching or wet etching may be used as the above processing. Processing by dry etching is suitable for micro-processing. By performing this processing, the side end of the conductor 110 is covered by the insulator 130 to be formed later.

[0384] Note that in photolithography, first, the resist is exposed through a mask. Then, a developer is used to remove or leave the exposed area to form a resist mask. Then, an etching process is performed through the resist mask to process the conductor, semiconductor, or insulator into a desired shape. For example, a resist mask can be formed by exposing the resist using KrF excimer laser, ArF excimer laser, EUV (Extreme Ultraviolet) light, etc. In addition, a liquid immersion technique in which the exposure is performed in a state where a liquid (e.g., water) is filled between the substrate and the projection lens can also be used. In addition, an electron beam or an ion beam can also be used instead of the above light. Note that when an electron beam or an ion beam is used, a mask is not required. In addition, the resist mask can be removed by performing a dry etching process such as ashing, performing a wet etching process, performing a wet etching process after a dry etching process, or performing a dry etching process after a wet etching process.

[0385] In addition, as a dry etching device, a capacitively coupled plasma (CCP: Capacitively Coupled Plasma) etching device including parallel plate electrodes can be used. The capacitively coupled plasma etching device including parallel plate electrodes can also adopt a structure in which a high-frequency voltage is applied to one of the parallel plate electrodes. Alternatively, a structure in which multiple different high-frequency voltages are applied to one of the parallel plate electrodes can be adopted. Alternatively, a structure in which a high-frequency voltage with the same frequency is applied to each of the parallel plate electrodes can be adopted. Alternatively, a structure in which a high-frequency voltage with different frequencies is applied to each of the parallel plate electrodes can be adopted. Alternatively, a dry etching device with a high-density plasma source can be used. For example, as a dry etching device with a high-density plasma source, an inductively coupled plasma (ICP: Inductively Coupled Plasma) etching device or the like can be used.

[0386] Next, an insulator 180 is formed on the conductor 110 (see FIG. 22A to FIG. 22C ). The above-mentioned insulating materials can be appropriately used as the insulator 180. When depositing the insulator 180, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. can be appropriately used. For example, as the insulator 180, a silicon oxide film can be deposited by sputtering. In addition, the insulator 180 is preferably subjected to a CMP (Chemical Mechanical Polishing) treatment after deposition to flatten its top surface. In addition, sometimes a CMP treatment is not required. At this time, the top surface of the insulator 180 has a curved surface shape that is convex upward. By not performing a flattening treatment, the yield rate can be improved while reducing the manufacturing cost.

[0387] Here, the thickness of the insulator 180 corresponds to the electrostatic capacitance of the capacitor 100 , and therefore the thickness of the insulator 180 may be appropriately set according to the design value of the electrostatic capacitance of the capacitor 100 .

[0388] In addition, by utilizing a sputtering method that does not require the use of molecules containing hydrogen as a deposition gas, the hydrogen concentration in the insulator 180 can be reduced.

[0389] Next, a portion of the insulator 180 is processed to form an opening 190 that reaches the conductor 120 (see FIG. 23A to FIG. 23C ). The opening 190 can be formed by photolithography. Note that the shape of the opening 190 when viewed from a plane is circular, but is not limited to this. For example, the shape of the opening 190 when viewed from a plane may be a substantially circular shape such as an ellipse, a polygonal shape such as a quadrangle, or a shape in which the corners of a polygon such as a quadrangle are curved.

[0390] As described above, the side wall of the opening 190 is preferably perpendicular to the top surface of the conductor 110. With such a structure, the storage device can be miniaturized or highly integrated. The side wall of the opening 190 may also have a tapered shape. By making the side wall of the opening 190 have a tapered shape, the coverage of the conductive film or the like that will become the conductor 115 described later is improved, thereby reducing defects such as voids.

[0391] The maximum width of the opening 190 (the maximum diameter when the opening 190 is circular when viewed from a plane) is preferably fine. For example, the maximum width of the opening 190 is preferably less than 100 nm, less than 60 nm, less than 50 nm, less than 40 nm, or less than 30 nm, and is greater than 5 nm or greater than 10 nm. In this way, in order to perform microfabrication on the opening 190, it is preferable to use photolithography using short-wavelength light such as EUV light or electron beams.

[0392] Since the aspect ratio of the opening 190 is high, it is preferable to process a part of the insulator 180 by anisotropic etching. In particular, processing by dry etching is suitable for micro-processing and is therefore preferable.

[0393] As described above, the maximum width of the opening 190 is larger than the maximum width of the opening 290, so it is difficult to use the same mask when the opening 190 and the opening 290 are formed by anisotropic etching. Therefore, after forming the opening by processing a part of the insulator 180 by anisotropic etching, the width of the opening can be enlarged by isotropic etching to form the opening 190. When the opening 190 is formed by the above process, the same mask can be used in the anisotropic etching performed when forming the opening 190 and the opening 290. As a result, the number of masks can be reduced, and the cost of the storage device can be reduced.

[0394] Next, a conductive film to be the conductor 115 is deposited in such a manner as to be in contact with the bottom and side walls of the opening 190 and at least a portion of the top surface of the insulator 180. As the conductive film, a conductive material that can be used as the above-mentioned conductor 115 can be appropriately used. When depositing the conductive film, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. can be appropriately used. Here, the conductive film is preferably formed in such a manner as to be in contact with the bottom and side walls of the opening 190 having a high aspect ratio. Therefore, when depositing the conductive film, it is preferred to use a deposition method with good coverage, and it is more preferred to use a CVD method or an ALD method, etc. For example, a titanium nitride film can be deposited as the conductive film using the CVD method.

[0395] Next, the conductive film to be the conductor 115 is processed by photolithography to form the conductor 115 (see FIG. 24A to FIG. 24C). Thus, a portion of the conductor 115 is formed in the opening 190 . In addition, the conductor 115 is in contact with a portion of the side surface and the top surface of the insulator 180 .

[0396] Note that in manufacturing 7A to 7C In the case of the memory device shown, it is preferable to perform CMP treatment after depositing a conductive film to be the conductor 115. By performing CMP treatment, the conductor 115 whose top surface is at the same height as the top surface of the insulator 180 can be formed.

[0397] Next, an insulator 130 is deposited on the conductor 115 and the insulator 180 (see FIG. 25A to FIG. 25C As the insulator 130, the above-mentioned High-k material or a material having ferroelectricity can be appropriately used. When depositing the insulator 130, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. can be appropriately used. For example, as the insulator 130, a stacked film of zirconium oxide, aluminum oxide, and zirconium oxide can be formed by sequentially depositing zirconium oxide, aluminum oxide, and zirconium oxide by the ALD method.

[0398] Next, a conductive film 120A is deposited on the insulator 130 (see FIG. 25A to FIG. 25C ). The conductive film 120A may be made of the above conductive materials. When depositing the conductive film 120A, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. may be appropriately used. For example, as the conductive film 120A, a stacked film in which titanium nitride and tantalum nitride are deposited in sequence may be formed by the CVD method. Alternatively, for example, as the conductive film 120A, a stacked film in which titanium nitride and tungsten are deposited in sequence may be formed by the CVD method.

[0399] Alternatively, the top surface of the conductive film 120A may be planarized by CMP or the like. By planarizing the conductive film 120A, the top surface of the conductor 120 formed by processing the conductive film 120A is planarized, so that the transistor 200 can be appropriately formed on the capacitor 100 .

[0400] Next, the conductive film 120A is processed to form the conductive body 120 (see FIG. 26A to FIG. 26C ). The conductor 120 can be formed by photolithography. The conductive film 120A can be processed by dry etching or wet etching. Dry etching is suitable for micro-processing.

[0401] Through the above steps, the capacitor 100 including the conductor 115 , the insulator 130 , and the conductor 120 can be formed.

[0402] Next, an insulator 280 is formed on the insulator 130 and the conductor 120 (see FIG. 27A to FIG. 27C). As the insulator 280, the above-mentioned insulating materials can be appropriately used. When depositing the insulator 280, the sputtering method, CVD method, MBE method, PLD method, ALD method, etc. can be appropriately used. For example, as the insulator 280, a silicon oxide film can be deposited by sputtering. In addition, the insulator 280 is preferably subjected to CMP treatment after deposition to flatten its top surface. By performing a flattening treatment on the insulator 280, the conductor 240 used as wiring can be appropriately formed. In addition, aluminum oxide can also be deposited on the insulator 280, for example, by a sputtering method, and then a CMP treatment is performed until it reaches the insulator 280. By performing this CMP treatment, the surface of the insulator 280 can be flattened and smoothed. By arranging the aluminum oxide on the insulator 280 and performing the CMP treatment, it is easy to detect the end point of the CMP treatment.

[0403] In addition, sometimes CMP treatment is not required. In this case, the top surface of the insulator 280 has a curved surface shape that is convex upward. By not performing the planarization treatment, the manufacturing cost can be reduced and the yield can be improved.

[0404] Here, the thickness of the insulator 280 on the conductor 120 corresponds to the channel length of the transistor 200 , and therefore the thickness of the insulator 280 may be appropriately set according to the design value of the channel length of the transistor 200 .

[0405] In addition, by depositing the insulator 280 by sputtering in an oxygen-containing atmosphere, the insulator 280 containing excess oxygen can be formed. In addition, by using a sputtering method that does not require the use of molecules containing hydrogen as a deposition gas, the hydrogen concentration in the insulator 280 can be reduced. In this way, by depositing the insulator 280, oxygen can be supplied from the insulator 280 to the channel formation region of the oxide semiconductor 230, thereby reducing oxygen vacancies and V O H.

[0406] Next, a conductive film 240A is deposited on the insulator 280 (see FIG. 27A to FIG. 27C As the conductive film 240A, the above-mentioned conductive materials can be used as appropriate. When depositing the conductive film 240A, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like can be used as appropriate.

[0407] Next, a portion of the conductive film 240A and a portion of the insulator 280 are processed to form an opening 290 that reaches the conductor 120 (see FIG. 28A to FIG. 28C ).like Fig.28A As shown in FIG. 1 , the opening 290 is preferably formed in a manner having an area overlapping with the opening 190. The opening 290 can be formed by photolithography. Fig.28AThe shape of the middle opening 290 when viewed from a plane is circular, but is not limited thereto. For example, the shape of the opening 290 when viewed from a plane may also be a substantially circular shape such as an ellipse, a polygonal shape such as a quadrangle, or a shape in which the corners of a polygon such as a quadrangle are curved.

[0408] As described above, the side wall of the opening 290 is preferably perpendicular to the top surface of the conductor 120. With such a structure, the storage device can be miniaturized or highly integrated. The side wall of the opening 290 may also have a tapered shape. By making the side wall of the opening 290 have a tapered shape, the coverage of the oxide semiconductor film or the like that will become the oxide semiconductor 230 described later is improved, thereby reducing defects such as voids.

[0409] The maximum width of the opening 290 (the maximum diameter when the opening 290 is circular when viewed from a plane) is preferably fine. For example, the maximum width of the opening 290 is preferably 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, or 20 nm or less, and 1 nm or more or 5 nm or more. In this way, in order to perform microfabrication on the opening 290, it is preferable to use photolithography using light with a short wavelength such as EUV light or an electron beam.

[0410] Since the aspect ratio of the opening 290 is high, it is preferable to process a part of the conductive film 240A and a part of the insulator 280 by anisotropic etching. In particular, processing by dry etching is suitable for fine processing and is therefore preferable. In addition, the processing may be performed under different conditions. Note that, as described above, depending on the conditions for processing a part of the conductive film 240A and a part of the insulator 280, the inclination of the side surface of the conductor 240 in the opening 290 and the inclination of the side surface of the insulator 280 in the opening 290 may be different from each other.

[0411] Next, heat treatment may also be performed. The heat treatment may be performed at a temperature of 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, and more preferably 320°C or higher and 450°C or lower. In addition, the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas or in an atmosphere containing an oxidizing gas of 10 ppm or higher, 1% or higher, or 10% or higher. For example, when heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the ratio of oxygen gas may be set to about 20%. In addition, the heat treatment may also be performed under reduced pressure. Alternatively, heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas, and then heat treatment may be performed in an atmosphere containing an oxidizing gas of 10 ppm or higher, 1% or higher, or 10% or higher to compensate for the oxygen that has been separated. By performing the above-mentioned heat treatment, impurities such as water contained in the insulator 280 or the like may be reduced before the deposition of the oxide semiconductor film that will become the oxide semiconductor 230, which will be described later.

[0412] In addition, the gas used in the above-mentioned heat treatment is preferably highly purified. For example, the amount of water contained in the gas used in the above-mentioned heat treatment is 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By using a highly purified gas for heat treatment, it is possible to prevent moisture and the like from being absorbed by the insulator 280 and the like as much as possible.

[0413] Next, an oxide semiconductor film that will become the oxide semiconductor 230 is deposited in a manner that contacts the bottom and side walls of the opening 290 and at least a portion of the top surface of the conductive film 240A. As the oxide semiconductor film, the above-mentioned metal oxide that can be used for the oxide semiconductor 230 can be appropriately used. When depositing the oxide semiconductor film, sputtering, CVD, MBE, PLD, ALD, etc. can be appropriately used. Here, the oxide semiconductor film is preferably formed in a manner that contacts the bottom and side walls of the opening 290 with a high aspect ratio. Therefore, when depositing the oxide semiconductor film, it is preferred to use a deposition method with good coverage, and more preferably to use a CVD method or an ALD method. For example, In-Ga-Zn oxide can be deposited as the oxide semiconductor film using the ALD method.

[0414] As the precursor containing indium, an organic precursor such as trimethylindium, triethylindium, tri(2,2,6,6-tetramethyl-3,5-heptanedione)indium, cyclopentadienylindium, indium(III) acetylacetonate, or (3-(dimethylamino)propyl)dimethylindium can be used.

[0415] As the precursor containing gallium, an organic precursor such as trimethylgallium, triethylgallium, tris(dimethylamide)gallium, gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedione)gallium, dimethylgallium chloride, diethylgallium chloride, or dimethylgallium isopropoxide can be used.

[0416] As the precursor containing zinc, an organic precursor such as dimethyl zinc, diethyl zinc, bis(2,2,6,6-tetramethyl-3,5-heptanedione) zinc, or zinc acetate can be used.

[0417] In order to perform deposition using the ALD method while heating the substrate, the decomposition temperature of the precursor used for the above deposition is preferably high. For example, the decomposition temperature of the precursor is preferably above 200°C and below 700°C, and more preferably above 300°C and below 600°C. As such a precursor with a high decomposition temperature, an inorganic precursor that does not contain hydrocarbons is preferably used. Inorganic precursors generally tend to have a higher decomposition temperature than organic precursors, so even if deposition is performed while heating the substrate as described above, the precursor is not easily decomposed.

[0418] As an inorganic precursor containing indium, a halogen indium compound such as indium trichloride, indium tribromide, or indium triiodide can be used. In addition, as an inorganic precursor containing gallium, a halogen gallium compound such as gallium trichloride, gallium tribromide, or gallium triiodide can be used. In addition, as an inorganic precursor containing zinc, a halogen zinc compound such as zinc dichloride, zinc dibromide, or zinc diiodide can be used.

[0419] Note that the above-mentioned precursor may contain one or both of carbon and chlorine in addition to the metal element. A film formed using a precursor containing carbon may contain carbon. In addition, a film formed using a precursor containing halogen such as chlorine may contain halogen such as chlorine.

[0420] As the oxidizing agent, ozone, oxygen, water or the like can be used.

[0421] Note that when the side wall of the opening 290 has a tapered shape, the deposition method of the oxide semiconductor film to be the oxide semiconductor 230 is not limited to the CVD method or the ALD method, and for example, a sputtering method may be used.

[0422] In addition, if Fig.16A and Fig. 16B As shown, in the case where the oxide semiconductor 230 has a stacked structure, the deposition methods of the layers included in the oxide semiconductor 230 may be the same or different. For example, in the case where the oxide semiconductor 230 has a two-layer stacked structure, the lower layer of the oxide semiconductor film may be deposited by sputtering and the upper layer of the oxide semiconductor film may be deposited by ALD. The oxide semiconductor film deposited by sputtering tends to have crystallinity. Thus, by providing a crystalline oxide semiconductor film as the lower layer of the oxide semiconductor film, the crystallinity of the upper layer of the oxide semiconductor film can be improved. Thus, even if a pinhole or a disconnection is formed in the lower layer of the oxide semiconductor film deposited by sputtering, the portion overlapping with the pinhole or disconnection can be blocked by the upper layer of the oxide semiconductor film deposited by the ALD method with good coverage.

[0423] Here, the oxide semiconductor film to be the oxide semiconductor 230 is preferably formed in contact with the top surface of the conductor 120 in the opening 290, the side surface of the insulator 280 in the opening 290, the side surface of the conductor 240 in the opening 290, and the top surface of the conductor 240. When the oxide semiconductor film is formed in contact with the conductor 120, the conductor 120 is used as one of the source electrode and the drain electrode of the transistor 200. When the oxide semiconductor film is formed in contact with the conductor 240, the conductor 240 is used as the other of the source electrode and the drain electrode of the transistor 200.

[0424] Next, heat treatment is preferably performed. The heat treatment can be performed within a temperature range in which the oxide semiconductor film does not undergo polycrystallization, and can be performed at a temperature above 250°C and below 650°C, preferably above 400°C and below 600°C. In addition, the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas or in an atmosphere containing an oxidizing gas of more than 10 ppm, more than 1%, or more than 10%. For example, when heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the ratio of the oxygen gas can be set to about 20%. In addition, the heat treatment can also be performed under reduced pressure. Alternatively, heat treatment can be performed in an atmosphere of nitrogen gas or an inert gas, and then heat treatment is performed in an atmosphere of an oxidizing gas of more than 10 ppm, more than 1%, or more than 10% to compensate for the detached oxygen.

[0425] In addition, the gas used in the above-mentioned heat treatment is preferably highly purified. For example, the amount of water contained in the gas used in the above-mentioned heat treatment is 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By using a highly purified gas for heat treatment, it is possible to prevent moisture and the like from being absorbed by the above-mentioned oxide semiconductor film and the like as much as possible.

[0426] Here, the heat treatment is preferably performed while the insulator 280 containing excess oxygen is in contact with the oxide semiconductor film. By performing the heat treatment in this way, oxygen can be supplied from the insulator 280 to the channel formation region of the oxide semiconductor 230, thereby reducing oxygen vacancies and V O H.

[0427] In addition, when an oxide semiconductor film is deposited by the ALD method, impurities such as hydrogen or carbon contained in the oxide semiconductor film can be removed by performing the above-mentioned heat treatment. For example, carbon in the oxide semiconductor film can be released as CO2 and CO, and hydrogen in the oxide semiconductor film can be released as H2O. In addition, while removing the above-mentioned impurities, metal atoms and oxygen atoms are rearranged, so that crystallinity can be improved. Thus, an oxide semiconductor 230 with a layered crystal structure having high crystallinity can be formed.

[0428] Note that in the above description, the heat treatment is performed after the oxide semiconductor film is deposited, but the present invention is not limited to this. Alternatively, the heat treatment may be performed in a subsequent step.

[0429] In addition, it is preferred that microwave treatment is performed in an oxygen-containing atmosphere after the oxide semiconductor film is deposited to reduce the concentration of impurities in the oxide semiconductor film. As impurities, hydrogen and carbon can be mentioned in particular. Here, microwave treatment refers to, for example, treatment using an apparatus including a power supply that generates high-density plasma using microwaves.

[0430] By performing microwave treatment in an oxygen-containing atmosphere, the oxygen gas can be plasmatized using microwaves or high frequencies such as RF to allow the oxygen plasma to act. In addition, as oxygen acting on the oxide semiconductor film, there are various forms such as oxygen atoms, oxygen molecules, oxygen ions, and oxygen free radicals (also known as atoms, molecules, or ions with unpaired electrons, also known as O free radicals). In addition, the oxygen acting on the oxide semiconductor film can be one or more of the above forms, and oxygen free radicals are particularly preferred.

[0431] In addition, heating the substrate during the microwave treatment in the oxygen-containing atmosphere is preferred because the impurity concentration in the oxide semiconductor film can be further reduced. The substrate may be heated at a temperature of 100° C. to 650° C., preferably 200° C. to 600° C., and more preferably 300° C. to 450° C.

[0432] When the substrate is heated during microwave treatment in the above oxygen-containing atmosphere, the carbon concentration in the metal oxide measured by SIMS can be reduced to less than 1×10 20 atoms / cm 3 , preferably less than 1×10 19 atoms / cm 3 , more preferably less than 1×10 18 atoms / cm 3 .

[0433] Note that the above shows a structure in which the oxide semiconductor film is subjected to microwave treatment in an oxygen-containing atmosphere, but is not limited thereto. For example, the insulating film located near the oxide semiconductor may be subjected to microwave treatment in an oxygen-containing atmosphere, and more specifically, the silicon oxide film may be subjected to microwave treatment. For example, in the process shown in FIG. 31 described later, microwave treatment may be performed after the insulator 250 is deposited. By subjecting the silicon oxide film to microwave treatment in an oxygen-containing atmosphere, hydrogen contained in the silicon oxide film may be released to the outside as H2O. By releasing hydrogen from the silicon oxide film located near the oxide semiconductor, a highly reliable storage device may be provided.

[0434] Next, the oxide semiconductor film to be the oxide semiconductor 230 is processed by photolithography to form the oxide semiconductor 230 (see FIG. 29A to FIG. 29C ). Thus, a portion of the oxide semiconductor 230 is formed in the opening 290. In addition, the oxide semiconductor 230 is in contact with a portion of the side surface and the top surface of the conductor 240. Therefore, the area of ​​the region where the oxide semiconductor 230 and the conductor 240 are in contact can be increased.

[0435] Next, the conductive film 240A is processed to form the conductive body 240 (see FIG. 30A to FIG. 30CThe conductor 240 can be formed by photolithography. The conductive film 240A can be processed by dry etching or wet etching. Dry etching is suitable for micro-processing.

[0436] Here, a method of forming the conductor 240 and the oxide semiconductor 230 which is different from the above-described method will be described.

[0437] To deposition FIG. 27A to FIG. 27C The method of forming the conductive film 240A is the same as described above.

[0438] Next, the conductive film 240A is processed to form the conductor 240. The method of forming the conductor 240 and the like can refer to the above description.

[0439] Next, a portion of the conductor 240 and a portion of the insulator 280 are processed to form an opening 290 that reaches the conductor 120. The method of forming the opening 290 and the like can refer to the above description.

[0440] Then, a heat treatment may be performed. The conditions of the heat treatment and the like can refer to the above description.

[0441] Next, an oxide semiconductor film to be the oxide semiconductor 230 is deposited in contact with the bottom and sidewall of the opening 290 and at least a portion of the top surface of the conductor 240. At this time, the oxide semiconductor film has a region in contact with the top surface of the insulator 280. The deposition method of the oxide semiconductor film and the like can refer to the above description.

[0442] Next, heat treatment is preferably performed. The conditions of the heat treatment and the like can refer to the above description.

[0443] Next, the oxide semiconductor film to be the oxide semiconductor 230 is processed by photolithography to form the oxide semiconductor 230 (see FIG. 30A to FIG. 30C ).

[0444] The following methods for manufacturing storage devices can all be carried out using the same method.

[0445] Next, an insulator 250 is deposited on the oxide semiconductor 230, the conductor 240, and the insulator 280 (see FIG. 31A to FIG. 31C ). As the insulator 250, the above-mentioned insulating materials can be appropriately used. When depositing the insulator 250, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. can be appropriately used. Here, the insulator 250 is preferably formed in a manner of contacting the oxide semiconductor 230 provided in the opening 290 with a high aspect ratio. Therefore, when depositing the insulator 250, it is preferred to use a deposition method with good coverage, and it is more preferred to use a CVD method or an ALD method, etc. For example, as the insulator 250, silicon oxide can be deposited by the ALD method.

[0446] Note that, when the side wall of the opening 290 has a tapered shape, the deposition method of the insulator 250 is not limited to the CVD method or the ALD method, and for example, a sputtering method may be used.

[0447] By depositing the insulator 250 after forming the oxide semiconductor 230, the side end of the oxide semiconductor 230 is covered by the insulator 250. Therefore, it is possible to prevent the oxide semiconductor 230 from being short-circuited with the conductor 260. In addition, by adopting the above structure, the side end of the conductor 240 is covered by the insulator 250. Therefore, it is possible to prevent the conductor 240 from being short-circuited with the conductor 260.

[0448] Next, a conductive film 260A is deposited so as to be embedded in the recessed portion of the insulator 250 (see FIG. 31A to FIG. 31C ). As the conductive film 260A, the above-mentioned conductive materials can be appropriately used. When depositing the conductive film 260A, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. can be appropriately used. Here, the conductive film 260A is preferably formed in a manner in contact with the insulator 250 provided in the opening 290 with a high aspect ratio. Therefore, when depositing the conductive film 260A, it is preferred to use a deposition method with good coverage or embedding properties, and it is more preferred to use a CVD method or an ALD method. For example, titanium nitride can be deposited as the conductive film 260A by a CVD method or an ALD method.

[0449] Note that when the conductive film 260A is deposited by CVD, the average surface roughness of the top surface of the conductive film 260A may become larger. In this case, it is preferable to planarize the conductive film 260A by CMP. In this case, a silicon oxide film or a silicon oxynitride film may be deposited on the conductive film 260A before CMP treatment, and CMP treatment may be performed until the silicon oxide film or the silicon oxynitride film is removed.

[0450] In the above description, the conductive film 260A is provided so as to be embedded in the opening 290, but the present invention is not limited thereto. For example, a concave portion reflecting the shape of the opening 290 may be formed in the central portion of the conductive film 260A. Alternatively, the concave portion may be filled with an inorganic insulating material or the like.

[0451] Next, the conductive film 260A is processed to form the conductive body 260 (see FIG. 32A to FIG. 32C ). The conductor 260 can be formed by photolithography. Dry etching or wet etching can be used as the above-mentioned processing. Processing by dry etching is suitable for micro-processing.

[0452] Here, if Figure 1A and Figure 1BAs shown in FIG. 1 , when viewed from a plane, the side end of the conductor 260 is preferably located inside the side end of the oxide semiconductor 230. Thus, a short circuit between the conductor 260 and the oxide semiconductor 230 can be prevented.

[0453] Through the above steps, the transistor 200 including the conductor 120 , the conductor 240 , the oxide semiconductor 230 , the insulator 250 , and the conductor 260 can be formed.

[0454] Next, the insulator 283 is deposited to cover the conductor 260 and the insulator 250. The above-mentioned insulating materials can be appropriately used as the insulator 283. When depositing the insulator 283, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like can be appropriately used.

[0455] Through the above process, it is possible to manufacture Figures 1A to 1D In addition, a storage device including the storage unit 150 can be manufactured. Figures 1A to 1D A storage device with transistor 200 and capacitor 100 is shown.

[0456] <Example 2 of the method for manufacturing a storage device> Next, explain FIG. 10A to FIG. 10C The method for manufacturing a memory device according to one embodiment of the present invention is shown. Note that the steps up to the step of forming the insulator 180 can refer to the contents described in the above-mentioned <Example 1 of the method for manufacturing a memory device>.

[0457] Next, a portion of the insulator 180 is processed to form an opening 190 that reaches the conductor 120 (see FIG. 33A to FIG. 33C ) The method for forming the opening 190 may refer to the above description.

[0458] Next, a conductive film to be the conductor 115 is deposited in contact with the bottom and sidewalls of the opening 190 and at least a portion of the top surface of the insulator 180. The deposition method of the conductive film and the like can refer to the above description. After the conductive film is deposited, a CMP treatment is performed. By performing the CMP treatment, the conductor 115 (see FIG. 34A to FIG. 34C ). At this time, the height of the top surface of the conductor 115 is consistent with the height of the top surface of the insulator 180.

[0459] Next, an insulator 130 is deposited on the conductor 115 and the insulator 180 (see FIG. 35A to FIG. 35C ). The deposition method of the insulator 130 and the like can refer to the above description.

[0460] Next, a conductive film to be the conductor 120 is deposited on the insulator 130. The deposition method of the conductive film can refer to the description of the conductive film 120A. For example, a stacked film of titanium nitride and tungsten deposited in this order can be formed by CVD.

[0461] Next, a CMP treatment is performed to remove a portion of the conductive film that will become the conductor 120, thereby exposing the insulator 130. As a result, the conductor 120 remains only in the opening 190. Note that a portion of the insulator 130 may be removed by the CMP treatment. Alternatively, a portion of the conductive film that will become the conductor 120 may be removed by a method other than the CMP treatment.

[0462] Next, etching is performed to remove the top of the conductor 120 (see FIG. 35A to FIG. 35C ). Thus, the top surface of the conductor 120 is lower than the top surface of the insulator 130. When etching the conductor 120, dry etching or wet etching can be used. From the viewpoint of microfabrication, dry etching is more preferable.

[0463] Next, a conductive film 121A is deposited on the insulator 130 and the conductor 120 (see FIG. 36A to FIG. 36C ) For example, titanium nitride can be deposited as the conductive film 121A by a CVD method or an ALD method.

[0464] Next, the conductive film 121A is anisotropically etched to form the conductive body 121 in contact with the side surface of the insulator 130 in the opening 190 (see FIG. 37A to FIG. 37C ). The anisotropic etching of the conductive film 121A can be performed by, for example, dry etching. Note that when the lower layer of the conductor 120 and the conductor 121 are formed of the same material, it may be difficult to clearly detect the boundary between the lower layer of the conductor 120 and the conductor 121.

[0465] Through the above steps, the capacitor 100 including the conductor 115 , the insulator 130 , the conductor 120 , and the conductor 121 can be formed.

[0466] An insulator 182 is formed on the insulator 130, the conductor 121, and the conductor 120 (see FIG. 37A to FIG. 37C ). The above-mentioned insulating materials can be used appropriately for the insulator 182. When depositing the insulator 182, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. can be used appropriately. For example, a silicon oxide film can be deposited by sputtering as the insulator 182. In addition, the insulator 182 is preferably subjected to a CMP treatment after deposition to flatten its top surface.

[0467] Next, an opening that reaches the conductor 120 is formed in the insulator 182. The opening can be formed by photolithography. The opening can be etched by dry etching or wet etching. Dry etching is suitable for micro-fabrication.

[0468] Next, a conductive film to be the conductor 122 is deposited in such a manner as to be embedded in the opening formed in the insulator 182. As the conductive film, the above-mentioned conductive materials can be used as appropriate. When depositing the conductive film, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. can be used as appropriate. For example, as the conductive film, a stacked film in which tantalum nitride and tungsten are deposited in this order can be formed by sputtering.

[0469] Next, a portion of the conductive film on the insulator 182 that will become the conductor 122 is removed to form the conductor 122 inside the opening of the insulator 182 (see FIG. 38A to FIG. 38C ). When forming the conductor 122, the conductive film may be subjected to CMP treatment until the top surface of the insulator 182 is exposed.

[0470] Next, an insulator 280 is formed on the insulator 182 and the conductor 120. The deposition method of the insulator 280 and the like can refer to the above description.

[0471] Note that the steps after forming the insulator 280 (after the step of depositing the conductive film 240A) can refer to the contents described in the above-mentioned <Example 1 of the method for manufacturing a memory device>.

[0472] Through the above process, it is possible to manufacture FIG. 10A to FIG. 10C In addition, a storage device including the storage unit 150 can be manufactured. FIG. 10A to FIG. 10C A storage device with transistor 200 and capacitor 100 is shown.

[0473] <Example 3 of the method for manufacturing a storage device> Next, explain FIG. 20A to FIG. 20C The method for manufacturing a memory device according to one embodiment of the present invention is shown. Note that the steps up to the step of forming the insulator 280 can refer to the contents described in the above-mentioned <Example 1 of the method for manufacturing a memory device>.

[0474] An insulator 281 is formed on the insulator 280. The above-mentioned insulating materials can be used appropriately for the insulator 281. When depositing the insulator 281, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. can be used appropriately. For example, a silicon oxide film can be deposited by a sputtering method as the insulator 281. In addition, the insulator 281 is preferably subjected to a CMP treatment after deposition to flatten its top surface.

[0475] Next, an opening reaching the insulator 280 is formed in the insulator 281. A conductor 240 serving as wiring is formed inside the opening so that the opening can extend in the X direction. When forming the opening, photolithography can be used. In addition, when etching the opening, dry etching or wet etching can be used. Processing using dry etching is suitable for micro-processing.

[0476] Alternatively, a structure may be adopted in which the insulator 280 has a stacked structure and an insulator serving as an etching stopper film is provided on the uppermost surface of the insulator 280. This insulator corresponds to the insulator 280c in the structure shown in Fig. 17. For example, when silicon oxide or silicon oxynitride is used as the insulator 281 forming the above-mentioned opening, silicon nitride, aluminum oxide, hafnium oxide, or the like is preferably used as the etching stopper film.

[0477] Next, a conductive film to be the conductor 240 is deposited in such a manner as to be embedded in the opening formed in the insulator 281. As the conductive film, the above-mentioned conductive materials can be used as appropriate. When depositing the conductive film, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. can be used as appropriate. For example, a stacked film in which tantalum nitride and tungsten are deposited in sequence can be formed by sputtering as the conductive film.

[0478] Next, a portion of the conductive film to be the conductor 240 on the insulator 281 is removed to form the conductor 240 inside the opening of the insulator 281. When forming the conductor 240, the conductive film may be subjected to CMP treatment until the top surface of the insulator 281 is exposed.

[0479] Note that the steps after forming the conductor 240 (after the step of forming the opening 290 ) can refer to the contents described in the above-mentioned <Example 1 of the method for manufacturing a memory device>.

[0480] Through the above process, it is possible to manufacture FIG. 20A to FIG. 20C In addition, a storage device including the storage unit 150 can be manufactured. FIG. 20A to FIG. 20C A storage device with transistor 200 and capacitor 100 is shown.

[0481] According to one embodiment of the present invention, a novel transistor, a novel semiconductor device, and a novel storage device can be provided. In addition, a storage device capable of miniaturization or high integration can be provided. In addition, a storage device with good frequency characteristics can be provided. In addition, a storage device with a high operating speed can be provided. In addition, a storage device with high reliability can be provided. In addition, a storage device with low power consumption can be provided. In addition, a storage device including a transistor with a large on-state current can be provided. In addition, a storage device with small non-uniformity in transistor characteristics can be provided. In addition, a storage device with good electrical characteristics can be provided.

[0482] The memory cell 150 including the transistor 200 and the capacitor 100 shown in this embodiment can be used as a memory cell of a memory device. The transistor 200 is a transistor whose channel is formed in a semiconductor layer including an oxide semiconductor. Since the off-state current of the transistor 200 is small, the storage content can be maintained for a long time by using it in a memory device. In other words, since no refresh operation is required or the frequency of the refresh operation is extremely low, the power consumption of the memory device can be substantially reduced. In addition, since the frequency characteristics of the transistor 200 are high, high-speed reading and writing of the memory device can be performed.

[0483] In addition, use Fig.39A and Fig.39B An example of a memory device in which two memory cells 150 (hereinafter referred to as a memory cell 150 a and a memory cell 150 b ) are connected to the same wiring will be described. Fig.39A is a plan view of the storage device. Fig.39B It is along Fig.39A The cross-sectional view of the portion along the dashed line A1-A2 in FIG. Fig.39A In the plan view, some components are omitted for clarity.

[0484] Here, Fig.39A and Fig.39B The memory cell 150a and the memory cell 150b shown in the figure have the same structure as the memory cell 150. The memory cell 150a includes a capacitor 100a and a transistor 200a, and the memory cell 150b includes a capacitor 100b and a transistor 200b. Fig.39A and Fig.39B In the memory device shown, the same reference numerals are used for components having the same functions as those of the memory device shown in Fig. 1. In this section, the memory device may also use the materials described in detail in <Configuration Example of Memory Device>.

[0485] like Fig.39A and Fig.39B As shown, the conductor 260 used as the wiring WL is provided in the memory cell 150a and the memory cell 150b respectively. In addition, the conductor 240 used as a part of the wiring BL is provided in both the memory cell 150a and the memory cell 150b. In other words, the conductor 240 contacts the oxide semiconductor 230 of the memory cell 150a and the oxide semiconductor 230 of the memory cell 150b.

[0486] Here, Fig.39A and Fig.39BThe memory device shown includes a conductor 245 and a conductor 246 which are electrically connected to the memory cells 150a and 150b and serve as plugs (which may also be referred to as connection electrodes). The conductor 245 is arranged in the openings formed in the insulators 180, 130, 280, and 140 and is in contact with the bottom surface of the conductor 240. In addition, the conductor 246 is arranged in the openings formed in the insulators 287, 283, and 250 and is in contact with the top surface of the conductor 240. In addition, as the conductor 245 and the conductor 246, the conductive material that can be used for the conductor 240 can be used.

[0487] Since the insulator 287 is used as an interlayer film, its relative dielectric constant is preferably low. By using a material with a low relative dielectric constant for the interlayer film, the parasitic capacitance generated between the wirings can be reduced. As the insulator 287, a single layer or a stack of insulators containing a material with a low relative dielectric constant described in the above-mentioned [Insulator] can be used.

[0488] In addition, the concentration of impurities such as water and hydrogen in the insulator 287 is preferably reduced. This can prevent impurities such as water and hydrogen from entering the channel formation region of the oxide semiconductor 230 .

[0489] Conductors 245 and 246 are used as plugs or wirings for electrically connecting circuit elements, wirings, electrodes or terminals such as switches, transistors, capacitors, inductors, resistors and diodes to memory cells 150a and 150b. For example, the following structure can be adopted: conductor 245 is electrically connected to a sense amplifier (not shown) provided under the memory device shown in FIG. 39, and conductor 246 is electrically connected to the same memory device (not shown) provided on the memory device shown in FIG. 39. In this case, conductors 245 and 246 are used as part of wiring BL. In this way, by providing a memory device above or below the memory device shown in FIG. 39, the storage capacity per unit area can be increased.

[0490] In addition, the memory cell 150a and the memory cell 150b are linearly symmetrical with the perpendicular bisector of the dot-dash line A1-A2 as the axis of symmetry. Therefore, the transistor 200a and the transistor 200b are also arranged linearly symmetrically with the conductor 245 and the conductor 246 sandwiched therebetween. Here, the conductor 240 serves as the other of the source electrode and the drain electrode of the transistor 200a and the other of the source electrode and the drain electrode of the transistor 200b. In addition, the transistor 200a and the transistor 200b share the conductor 245 and the conductor 246 used as the plug. In this way, by adopting the above structure as the connection relationship between the two transistors and the plug, a storage device capable of miniaturization or high integration can be provided.

[0491] In addition, the conductor 110 used as the wiring PL may be provided in each of the memory cell 150a and the memory cell 150b, or may be provided in both of the memory cell 150a and the memory cell 150b. Fig.39B As shown, the conductor 110 is disposed in a manner separated from the conductor 245 to prevent the conductor 110 and the conductor 245 from being short-circuited.

[0492] In addition, by arranging the memory cells 150 in a matrix and three-dimensional manner, a memory cell array can be formed. As an example of a memory cell array, Fig.40A and Fig.40B An example of a storage device in which four×two×four storage cells 150 are arranged in the X direction, the Y direction, and the Z direction is shown. Fig.40A is a plan view of the storage device. Fig.40B It is along Fig.40A The cross-sectional view of the portion along the dashed line A1-A2 in FIG. Fig.40A In the plan view, some components are omitted for clarity.

[0493] Here, Fig.40A and Fig.40B The memory cells 150a to 150d shown have the same structure as the memory cell 150. The memory cell 150a includes a capacitor 100a and a transistor 200a, the memory cell 150b includes a capacitor 100b and a transistor 200b, the memory cell 150c includes a capacitor 100c and a transistor 200c, and the memory cell 150d includes a capacitor 100d and a transistor 200d. Fig.40A and Fig.40B In the memory device shown, the same reference numerals are used for components having the same functions as those of the memory device shown in Fig. 1. In this section, the memory device may also use the materials described in detail in <Configuration Example of Memory Device>.

[0494] Hereinafter, a storage device composed of the storage cells 150a to 150d will be referred to as a memory cell. Fig.40A and Fig.40BThe memory device shown includes memory cells 160 [1, 1] to 160 [2, 4]. In addition, memory cells 160 [1, 1] to 160 [2, 4] are sometimes collectively referred to as memory cells 160 below. Memory cell 160 [1, 2] is disposed on memory cell 160 [1, 1], memory cell 160 [1, 3] is disposed on memory cell 160 [1, 2], and memory cell 160 [1, 4] is disposed on memory cell 160 [1, 3]. Memory cell 160 [2, 1] is adjacent to memory cell 160 [1, 1] in the Y direction. Memory cell 160 [2, 2] is disposed on memory cell 160 [2, 1], memory cell 160 [2, 3] is disposed on memory cell 160 [2, 2], and memory cell 160 [2, 4] is disposed on memory cell 160 [2, 3].

[0495] like Fig.40B As shown, in the memory cell 160, the memory cell 150c is arranged outside the memory cell 150a and the memory cell 150d is arranged outside the memory cell 150b with the conductor 245 as the center. In other words, it can also be said that the memory cell 160 is a memory device in which the memory cell 150c is arranged adjacent to the memory cell 150a and the memory cell 150d is arranged adjacent to the memory cell 150b in the memory device shown in FIG. 39 .

[0496] like Fig.40A and Fig.40B As shown, the memory cells 150 adjacent to each other in the Y direction share the conductor 260 used as the wiring WL. In addition, the conductor 240 used as a part of the wiring BL is shared in the same memory cell. In other words, the conductor 240 is in contact with the oxide semiconductor 230 in each of the memory cells 150a to 150d.

[0497] The conductor 245 is disposed between the conductors 240 included in the memory cells adjacent to each other in the Z direction. Fig.40B As shown in FIG. 40 , the conductor 245 is provided in a manner in contact with the top surface of the conductor 240 in the memory cell 160 [1, 1] and the bottom surface of the conductor 240 in the memory cell 160 [1, 2]. In this way, the conductor 240 and the conductor 245 provided in each memory cell 160 form a wiring BL. The conductor 245 is electrically connected to a sense amplifier (not shown) provided under the memory device shown in FIG. 40 . In this way, by stacking a plurality of memory cells in the memory device shown in FIG. 40 , the storage capacity per unit area can be increased.

[0498] In addition, the memory cell 150a and the memory cell 150c and the memory cell 150b and the memory cell 150d are linearly symmetrical with the perpendicular bisector of the dot-dash line A1-A2 as the symmetry axis. Therefore, the transistor 200a and the transistor 200c and the transistor 200b and the transistor 200d are also arranged linearly symmetrically with the conductor 245 sandwiched therebetween. Here, the conductor 240 is used as the other of the source electrode and the drain electrode of the transistor 200a to the transistor 200d. In addition, the transistor 200a to the transistor 200d share the conductor 245 used as a plug. In this way, by adopting the above structure as the connection relationship between the four transistors and the plug, a storage device capable of miniaturization or high integration can be provided.

[0499] As shown in FIG40, by stacking a plurality of memory cells, the cells can be integratedly configured without increasing the occupied area of ​​the memory cell array. That is, a 3D memory cell array can be formed. Note that FIG40 shows an example of a structure having four stacked layers including two memory cells, but the present invention is not limited to this. In the memory device, one layer including at least one memory cell 150 can be included, and two or more of the above layers can be stacked.

[0500] 40 shows a structure in which the conductor 245 used as a plug is arranged between the memory cells 150. In other words, FIG40 shows a structure in which the conductor 245 used as a plug is arranged inside the memory cell 160. Note that the present invention is not limited to this. The conductor 245 may be arranged outside the memory cell.

[0501] As an example of a memory cell array, Fig.41A and Fig.41B An example of a storage device is shown in which three×three×four storage cells 150 are arranged in the X direction, the Y direction, and the Z direction. Fig.41A is a plan view of the storage device. Fig.41B It is along Fig.41A The cross-sectional view of the portion along the dashed line A1-A2 in FIG. Fig.41A In the plan view, some components are omitted for clarity.

[0502] Fig.41A and Fig.41B The memory device shown has a structure in which m (m is an integer greater than or equal to 2) layers including memory cells 150 are stacked. Fig.41BIn the above, the layer disposed at the first layer (the bottom layer) is referred to as layer 170[1], the layer disposed at the second layer is referred to as layer 170[2], the layer disposed at the (m-1)th layer is referred to as layer 170[m-1], and the layer disposed at the mth layer (the top layer) is referred to as layer 170[m]. That is, the storage device of one embodiment of the present invention may include a plurality of layers including the storage unit 150, and may have a structure in which a plurality of layers are stacked.

[0503] like Fig.41A and Fig.41B As shown, the conductor 245 may also be provided outside the memory cell. In addition, the conductor 245 may also be electrically connected to a wiring provided in an upper layer of the layer including the conductor 245. For example, the conductor 245 provided in the layer 170[1] is electrically connected to a wiring provided in the layer 170[2]. In addition, the wiring provided in the layer 170[2] is provided in the same layer as the lower electrode (conductor 110) of the memory cell 150 included in the layer 170[2]. That is, the wiring may be formed in the same process as the conductor 110.

[0504] Note that although FIG. 41 shows a structure in which the conductor 245 is electrically connected to a wiring provided in a layer above the layer including the conductor 245, the present invention is not limited thereto. For example, the conductor 245 may be electrically connected to a wiring provided in a layer including the conductor 245. For example, the conductor 245 provided in the layer 170[1] may be electrically connected to a wiring provided in the layer 170[1]. In addition, the wiring provided in the layer 170[1] is provided in the same layer as the lower electrode (conductor 110) of the memory cell 150 included in the layer 170[1]. That is, the wiring may be formed in the same process as the conductor 110.

[0505] Here, Fig.42A Show Fig.41A Specifically, in Fig.42A In the planar layout of FIG. 1 , a region including 4×4 memory cells 150 is shown. In addition, a conductor 260 used as a wiring WL, a conductor 240 used as a wiring BL, and an opening 290 are shown. In addition, the memory cell 150 is provided in the region where the conductor 260 and the conductor 240 overlap with the opening 290. In other words, the opening 290 is provided in the region where the conductor 240 and the conductor 260 intersect.

[0506] Fig.42AThe structure in which the memory cells 150 are arranged in a matrix is ​​shown. In addition, the structure in which the openings 290 are arranged in a matrix is ​​also shown. In addition, the structure in which the conductor 260 extends in the Y direction and the conductor 240 extends in the X direction is shown. In other words, the structure in which the conductor 260 is orthogonal to the conductor 240 is shown. In addition, the structure in which the width of the conductor 260 in the direction (X direction) perpendicular to the extension direction of the conductor 260 is constant and the width of the conductor 240 in the direction (Y direction) perpendicular to the extension direction of the conductor 240 is constant is shown. Note that the present invention is not limited to this.

[0507] Fig.42B Another example of a planar layout of a storage device is shown. Fig.42A Likewise, in Fig.42B The plan layout of FIG. 1 shows the conductor 260 , the conductor 240 , the memory cell 150 , and the opening 290 . Fig.42B The storage device shown is Fig.42A The main differences between the illustrated memory devices are: the arrangement of the memory cells 150 (openings 290 ); the shape of the conductors 240 ; and the extending direction of the conductors 260 .

[0508] like Fig.42B As shown, the memory cells 150 (openings 290) may be arranged in such a manner that half of the repetition unit of the memory cells 150 (openings 290) is shifted between odd-numbered rows and even-numbered rows. In addition, the memory cells 150 (openings 290) may be arranged in such a manner that half of the repetition unit is shifted between odd-numbered columns and even-numbered columns.

[0509] exist Fig.42B In the embodiment, the storage cell adjacent to the first storage cell in the X direction is referred to as the second storage cell, and the storage cell adjacent to the first storage cell and the second storage cell in the Y direction is referred to as the third storage cell. For example, it is preferred that the center of the third storage cell is located on a straight line passing through the middle of the first storage cell and the second storage cell and parallel to the Y direction. In this case, it can also be said that the third storage cell is located at a position offset by half in the X direction relative to the first storage cell and the second storage cell.

[0510] In addition, if Fig.42BAs shown, the conductor 240 includes a first region and a second region. The first region is the opening 290 and the region in the vicinity thereof, and the width of the first region in the Y direction is referred to as the first width. When viewed from a plane, it can be said that the first region has a quadrilateral shape with arc-shaped corners. In addition, the second region is the region between adjacent openings 290 in a conductor 240, and the width of the second region in the Y direction is referred to as the second width. At this time, the second width is preferably smaller than the first width. By adopting this structure, when the storage cells 150 (openings 290) are arranged in a manner that staggers half of the repetitive units in each row or column, the physical distance between the conductors 240 can be reduced. In this way, miniaturization and high integration of the storage device can be achieved.

[0511] In addition, Fig.42B In the figure, the extension direction of the conductor 260 is inclined to the Y direction. That is, the extension direction of the conductor 260 may not be perpendicular to the extension direction of the conductor 240 depending on the arrangement of the memory cell 150 (opening 290). In other words, it is preferable that the conductor 260 intersects with the conductor 240.

[0512] Fig.42C Another example of a planar layout of a storage device is shown. Fig.42B Likewise, in Fig.42C The plan layout of FIG. 1 shows the conductor 260 , the conductor 240 , the memory cell 150 , and the opening 290 . Fig.42C The storage device shown is Fig.42B The memory device shown differs mainly in the shape of the first region of the electrical conductor 240 .

[0513] Fig.42B The first region of the conductor 240 shown has a quadrangular shape with curved corners when viewed from a plane, and one side of the quadrangular shape is parallel to the X direction or the Y direction. Fig.42C The first region of the conductor 240 shown has a quadrangular shape with curved corners when viewed from a plane, and the diagonal lines of the quadrangular shape are parallel to the X direction or the Y direction. By adopting this structure, when the memory cells 150 (openings 290) are arranged in a manner that the repetition units are shifted by half in each row or column, the physical distance between the conductors 240 can be reduced. As a result, miniaturization and high integration of the memory device can be achieved.

[0514] Fig.42B and Fig.42C An example is shown in which the first region of the conductor 240 has a quadrangular shape with curved corners when viewed from a plane, but the present invention is not limited thereto.

[0515] Fig.43A Another example of a planar layout of a storage device is shown. Fig.42B Likewise, in Fig.43A The plan layout of FIG. 1 shows the conductor 260 , the conductor 240 , the memory cell 150 , and the opening 290 . Fig.43A The storage device shown is Fig.42B or Fig.42C The memory device shown differs mainly in the shape of the first region of the electrical conductor 240 .

[0516] Fig.43A The first region of the conductor 240 shown has a circular shape when viewed from a plane. By adopting this structure, when the memory cells 150 (openings 290) are arranged in a manner that the repetition unit is shifted by half in each row or column, the physical distance between the conductors 240 can be reduced. As a result, miniaturization and high integration of the memory device can be achieved.

[0517] Note that the first region of the conductor 240 when viewed from above is not limited to the above shape. For example, the first region of the conductor 240 when viewed from above may have a substantially circular shape such as an ellipse, a polygon such as a quadrangle, or a polygon such as a quadrangle with curved corners.

[0518] in addition, Fig.43A The structure in which the width of the conductor 260 in the direction perpendicular to the extending direction of the conductor 260 is constant is shown, but the present invention is not limited thereto.

[0519] Fig.43B Another example of a planar layout of a storage device is shown. Fig.43A Likewise, in Fig.43B The plan layout of FIG. 1 shows the conductor 260 , the conductor 240 , the memory cell 150 , and the opening 290 . Fig.43B The storage device shown is Fig.43A The memory devices shown differ primarily in the shape of the electrical conductor 260 .

[0520] Similar to the conductor 240, Fig.43B The conductor 260 shown includes a first region and a second region. The first region is an opening 290 and a region in the vicinity thereof, and has a circular shape when viewed from a plane. In addition, the second region is a region between adjacent openings 290 in one conductor 260. Note that the first region of the conductor 260 overlaps with the first region of the conductor 240. By adopting this structure, when the memory cells 150 (openings 290) are arranged in a manner that staggers a half of the repetition unit in each row or column, the physical distance between the conductors 240 can be reduced. As a result, miniaturization and high integration of the memory device can be achieved.

[0521] Fig.43C Another example of a planar layout of a storage device is shown. Fig.43A Likewise, in Fig.43C The plan layout of FIG. 1 shows the conductor 260 , the conductor 240 , the memory cell 150 , and the opening 290 . Fig.43C The storage device shown is Fig.43A The main difference between the illustrated memory devices is the shape and extension direction of the conductor 260 .

[0522] check Fig.43C The conductor 260 shown has a meandering shape like a triangular wave when viewed from a plane, and extends in the Y direction. By adopting this structure, when the memory cells 150 (openings 290) are arranged in a manner that staggers half of the repetition unit in each row or column, the physical distance between the conductors 240 can be reduced. As a result, miniaturization and high integration of the memory device can be achieved. Note that the conductor 260 when viewed from a plane is not limited to the above shape, and may also have a meandering shape, etc.

[0523] By adopting the above structure, one or both of the physical distance between the conductors 260 and the physical distance between the conductors 240 can be reduced, and the miniaturization and high integration of the storage device can be achieved.

[0524] Fig.44 An example of a cross-sectional structure of a memory device in which a layer including memory cells is stacked on a layer including a driver circuit including a sense amplifier.

[0525] exist Fig.44 In the embodiment, the capacitor 100 is disposed above the transistor 300 , and the transistor 200 is disposed above the transistor 300 and the capacitor 100 .

[0526] The transistor 300 is one of the transistors included in the sense amplifier.

[0527] Fig.44 The structure of the illustrated memory cell 150 (transistor 200 and capacitor 100 ) is as described above.

[0528] like Fig.44 As shown in FIG. 1 , the bit line can be shortened by adopting a structure in which the sense amplifier is provided so as to overlap the memory cell 150. As a result, the bit line capacitance is reduced, and the storage capacitance of the memory cell can be reduced.

[0529] Furthermore, by placing the transistor 200 above the capacitor 100, the transistor 200 is not affected by the heat treatment during the manufacture of the capacitor 100. Therefore, the degradation of the electrical characteristics of the transistor 200, such as the variation in threshold voltage and the increase in parasitic resistance, and the increase in the unevenness of the electrical characteristics caused by the degradation of the electrical characteristics can be suppressed.

[0530] Fig.44The memory device shown may correspond to the memory device 80 described in Embodiment 2. Specifically, the transistor 300 corresponds to the transistor included in the sense amplifier 46 in the memory device 80. In addition, the memory cell 150 corresponds to the memory cell 32, the transistor 200 corresponds to the transistor 37, and the capacitor 100 corresponds to the capacitor 38.

[0531] The transistor 300 is provided on a substrate 311 and includes a conductor 316 used as a gate, an insulator 315 used as a gate insulator, a semiconductor region 313 formed by a portion of the substrate 311, and a low resistance region 314a and a low resistance region 314b used as a source region or a drain region. The transistor 300 may be a p-channel type or an n-channel type.

[0532] Here, in Fig.44 In the transistor 300 shown, the semiconductor region 313 (a part of the substrate 311) forming the channel has a convex shape. In addition, a conductor 316 is provided in a manner that covers the side and top surfaces of the semiconductor region 313 via an insulator 315. In addition, a material that adjusts the work function can also be used for the conductor 316. Because the convex portion of the semiconductor substrate is utilized, this transistor 300 is also referred to as a FIN-type transistor. In addition, an insulator having a mask for forming a convex portion in a manner that contacts the upper surface of the convex portion can also be provided. In addition, although a portion of the semiconductor substrate is processed to form a convex portion is shown here, an SOI substrate can also be processed to form a semiconductor film having a convex portion.

[0533] Notice, Fig.44 The structure of the transistor 300 shown is just an example and is not limited to the above structure, and an appropriate transistor can be used according to the circuit structure or driving method.

[0534] A wiring layer including an interlayer film, wiring, and plugs may also be provided between each structure. In addition, the wiring layer may be provided in multiple layers according to the design. Here, in a conductor having the function of a plug or wiring, the same symbol is sometimes used to represent multiple structures. In addition, in this specification, wiring and a plug electrically connected to the wiring may also be a component. That is, a part of the conductor is sometimes used as wiring, and a part of the conductor is sometimes used as a plug.

[0535] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked as interlayer films on the transistor 300. Furthermore, a conductor 328 is embedded in the insulator 320 and the insulator 322, and a conductor 330 is embedded in the insulator 324 and the insulator 326. Furthermore, the conductor 328 and the conductor 330 are used as plugs or wirings.

[0536] In addition, the insulator used as the interlayer film can be used as a planarization film to cover the concavo-convex shape thereunder. For example, in order to improve the flatness of the top surface of the insulator 322, the top surface can also be planarized by a planarization process using a CMP method or the like.

[0537] Alternatively, a wiring layer may be formed on the insulator 326 and the conductor 330. Fig.44 In the embodiment, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. In addition, a conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 is used as a plug or wiring.

[0538] As the insulator 352 and the insulator 354 serving as an interlayer film, the insulators described above that can be used in a memory device can be used.

[0539] As the conductor used as a plug or wiring, for example, conductor 328, conductor 330, and conductor 356, the conductors in the above-mentioned [conductor] can be used. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is preferably used. Alternatively, it is preferable to use a low-resistance conductive material such as aluminum or copper. By using a low-resistance conductive material, the wiring resistance can be reduced.

[0540] The conductor 240 included in the transistor 200 is electrically connected to the low resistance region 314 b serving as a source region or a drain region of the transistor 300 through the conductor 643 , the conductor 642 , the conductor 644 , the conductor 645 , the conductor 646 , the conductor 356 , the conductor 330 , and the conductor 328 .

[0541] Conductor 643 is embedded in insulator 280. Conductor 642 is provided on insulator 130 and embedded in insulator 641. Conductor 642 can be manufactured using the same material and process as conductor 120. Conductor 644 is embedded in insulator 180 and insulator 130. Conductor 645 is embedded in insulator 647. Conductor 645 can be manufactured using the same material and process as conductor 110. Conductor 646 is embedded in insulator 648. Transistor 300 is electrically insulated from conductor 110 by insulator 648.

[0542] According to one embodiment of the present invention, a novel transistor, semiconductor device, and storage device can be provided. In addition, a transistor, semiconductor device, and storage device that can achieve miniaturization or high integration can be provided. In addition, a transistor, semiconductor device, and storage device with good reliability can be provided. In addition, a transistor with a large on-state current, a semiconductor device and a storage device including the transistor can be provided. In addition, a semiconductor device and a storage device with less uneven transistor characteristics can be provided. In addition, a transistor with good electrical characteristics, a semiconductor device and a storage device including the transistor can be provided. In addition, a semiconductor device and a storage device with low power consumption can be provided. In addition, a storage device with good frequency characteristics can be provided. In addition, a storage device with a fast operating speed can be provided.

[0543] This embodiment mode can be combined with other embodiment modes and examples as appropriate.

[0544] (Implementation Method 2) In this embodiment, refer to Figures 45 to 48 A memory device according to one embodiment of the present invention will be described. In this embodiment, a memory device configuration example in which a layer including memory cells is stacked on a layer including a driver circuit including a sense amplifier will be described.

[0545] <Storage Device Configuration Example 3> Fig.45 : is a block diagram showing a configuration example of a storage device 80 according to one embodiment of the present invention. Fig.45 The illustrated memory device 80 includes the layer 20 and the stacked layer 70 .

[0546] Layer 20 is a layer including Si transistors. In the stacked layer 70, element layers 30[1] to 30[m] (m is an integer greater than or equal to 2) are stacked. Element layers 30[1] to 30[m] are layers including OS transistors. Layer 70 including layers including OS transistors can be stacked on layer 20.

[0547] Elements such as OS transistors and capacitors included in the element layers 30 [ 1 ] to 30 [ m ] constitute memory cells. Fig.45 An example is shown in which the element layers 30 [ 1 ] to 30 [ m ] include a plurality of memory cells 32 arranged in a matrix of m rows and n columns (n ​​is an integer greater than or equal to 2).

[0548] exist Fig.45, the 1st row and 1st column storage cell 32 is represented as storage cell 32[1, 1], and the mth row and nth column storage cell 32 is represented as storage cell 32[m, n]. In addition, in the present embodiment, etc., sometimes "row i" is recorded to represent an arbitrary row. In addition, sometimes "column j" is recorded to represent an arbitrary column. Therefore, i is an integer greater than 1 and less than m, and j is an integer greater than 1 and less than n. In addition, in the present embodiment, etc., the i-th row and j-th column storage cell 32 is represented as storage cell 32[i, j]. Note that in the present embodiment, etc., when expressed as "i+α" (α is a positive integer or a negative integer), "i+α" is not less than 1 and not greater than m. Similarly, when expressed as "j+α", "j+α" is not less than 1 and not greater than n.

[0549] Also, as an example, Fig.45 m wirings WL extending in the row direction, m wirings PL extending in the row direction, and n wirings BL extending in the column direction are shown. In the present embodiment and the like, the first (1st row) wiring WL is represented as wiring WL[1], and the mth (mth row) wiring WL is represented as wiring WL[m]. Similarly, the first (1st row) wiring PL is represented as wiring PL[1], and the mth (mth row) wiring PL is represented as wiring PL[m]. Similarly, the first (1st column) wiring BL is represented as wiring BL[1], and the nth (nth column) wiring BL is represented as wiring BL[n]. Note that the number of layers of the element layers 30[1] to 30[m] and the number of wirings WL (and wirings PL) may be different.

[0550] The plurality of memory cells 32 arranged in the i-th row are electrically connected to the i-th row wiring WL (wiring WL[i]) and the i-th row wiring PL (wiring PL[i]). The plurality of memory cells 32 arranged in the j-th column are electrically connected to the j-th column wiring BL (wiring BL[j]).

[0551] Wiring BL is used as a bit line for writing and reading data. Wiring WL is used as a word line for controlling the on or off (conductive state or non-conductive state) of an access transistor used as a switch. Wiring PL is used as a constant potential line connected to a capacitor. Wiring CL (not shown) may be provided separately as a wiring for transmitting a back gate potential.

[0552] The memory cells 32 included in the element layers 30[1] to 30[m] are connected to the sense amplifier 46 via wiring BL. The wiring BL can be arranged in a direction parallel to or perpendicular to the substrate surface on which the layer 20 is provided. By forming the wiring BL extending from the memory cells 32 included in the element layers 30[1] to 30[m] by wiring arranged in a direction parallel to the substrate surface and wiring arranged in a direction perpendicular to the substrate surface, the wiring length between the element layer 30 and the sense amplifier 46 can be shortened. Since the signal transmission distance between the memory cell and the sense amplifier can be shortened and the resistance and parasitic capacitance of the bit line can be greatly reduced, the power consumption and signal delay can be reduced. Thus, the power consumption and signal delay of the memory device 80 can be reduced. In addition, the memory device 80 can operate even if the capacitance of the capacitor included in the memory cell 32 is reduced. Thus, the memory device 80 can be miniaturized.

[0553] The layer 20 includes a PSW 71 (power switch), a PSW 72, and a peripheral circuit 22. The peripheral circuit 22 includes a drive circuit 40, a control circuit 73 (Control Circuit), and a voltage generation circuit 74. Note that each circuit included in the layer 20 is a circuit including Si transistors.

[0554] In the storage device 80, each circuit, each signal and each voltage can be appropriately selected as needed. Alternatively, other circuits or other signals can be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1 and PON2 are signals input from the outside, and signal RDA is a signal output to the outside. Signal CLK is a clock signal.

[0555] In addition, the signal BW, the signal CE and the signal GW are control signals. The signal CE is a chip enable signal, the signal GW is a global write enable signal, and the signal BW is a byte write enable signal. The signal ADDR is an address signal. The signal WDA is write data, and the signal RDA is read data. The signals PON1 and PON2 are power gating control signals. In addition, the signals PON1 and PON2 can also be generated in the control circuit 73.

[0556] The control circuit 73 is a logic circuit that has the function of controlling the overall operation of the storage device 80. For example, the control circuit performs a logic operation on the signal CE, the signal GW, and the signal BW to determine the operation mode (for example, writing operation, reading operation) of the storage device 80. Alternatively, the control circuit 73 generates a control signal for the drive circuit 40 to execute the above operation mode.

[0557] The voltage generating circuit 74 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 74. For example, when the signal WAKE is applied with an H level signal, the signal CLK is input to the voltage generating circuit 74, and the voltage generating circuit 74 generates a negative voltage.

[0558] The driving circuit 40 is a circuit for writing and reading data to and from the memory cell 32. The driving circuit 40 includes the above-mentioned sense amplifier 46 in addition to the row decoder 42, the column decoder 44, the row driver 43, the column driver 45, the input circuit 47, and the output circuit 48.

[0559] The row decoder 42 and the column decoder 44 have the function of decoding the signal ADDR. The row decoder 42 is a circuit for specifying a row to be accessed, and the column decoder 44 is a circuit for specifying a column to be accessed. The row driver 43 has the function of selecting the wiring WL specified by the row decoder 42. The column driver 45 has the following functions: a function of writing data into the memory cell 32; a function of reading data from the memory cell 32; a function of holding the read data, etc.

[0560] The input circuit 47 has a function of holding a signal WDA. The data held in the input circuit 47 is output to the column driver 45. The output data of the input circuit 47 is the data (Din) written to the memory cell 32. The data (Dout) read from the memory cell 32 by the column driver 45 is output to the output circuit 48. The output circuit 48 has a function of holding Dout. In addition, the output circuit 48 has a function of outputting Dout to the outside of the memory device 80. The data output from the output circuit 48 is a signal RDA.

[0561] PSW71 has a function of controlling the supply of VDD to the peripheral circuit 22. PSW72 has a function of controlling the supply of VHM to the row driver 43. Here, the high power supply voltage of the storage device 80 is VDD, and the low power supply voltage is GND (ground potential). In addition, VHM is a high power supply voltage for making the word line high, which is higher than VDD. The on / off of PSW71 is controlled by the signal PON1, and the on / off of PSW72 is controlled by the signal PON2. Fig.45 In the embodiment, the number of power domains to which VDD is supplied in the peripheral circuit 22 is one, but it may be more than one. In this case, a power switch may be provided for each power domain.

[0562] Element layers 30 [ 1 ] to 30 [ m ] may be disposed in an overlapping manner on layer 20 . Fig.46A 1 is a perspective view of a storage device 80 showing a state in which five (m=5) element layers 30 [ 1 ] to 30 [ 5 ] are stacked on a layer 20 .

[0563] exist Fig.46A In the embodiment, the element layer 30 provided in the first layer is referred to as element layer 30[1], the element layer 30 provided in the second layer is referred to as element layer 30[2], and the element layer 30 provided in the fifth layer is referred to as element layer 30[5]. Fig.46A The wiring WL and the wiring PL extending in the X direction and the wiring BL and the wiring BLB extending in the Y direction and the Z direction (directions perpendicular to the substrate surface on which the drive circuit is provided) are shown. The wiring BLB is an inversion bit line. Note that in order to make the drawings easier to understand, a part of the wiring WL and the wiring PL included in each of the element layers 30 is omitted.

[0564] Fig.46B Yes Description Fig.46A The schematic diagram of the structural example of the memory cell 32 included in the sense amplifier 46 connected to the wiring BL and the wiring BLB and the element layers 30[1] to 30[5] connected to the wiring BL and the wiring BLB is shown. In addition, the structure in which multiple memory cells (memory cells 32) are electrically connected to one wiring BL and the wiring BLB is also called a "memory string".

[0565] Fig.46B An example of a circuit structure of a memory cell 32 connected to the wiring BLB is shown. The memory cell 32 includes a transistor 37 and a capacitor 38. Regarding the transistor 37, the capacitor 38, and each wiring (BL, WL, etc.), for example, the wiring BL[1] and the wiring WL[1] are sometimes referred to as the wiring BL and the wiring WL, etc. As the memory cell 32, for example, the memory cell 150 shown in the above embodiment can be used. That is, the transistor 200 can be used as the transistor 37, and the capacitor 100 can be used as the capacitor 38. In addition, the transistor 300 (see Fig.44 ).

[0566] In the memory cell 32, one of the source and the drain of the transistor 37 is connected to the wiring BL. The other of the source and the drain of the transistor 37 is connected to one electrode of the capacitor 38. The other electrode of the capacitor 38 is connected to the wiring PL. The gate of the transistor 37 is connected to the wiring WL.

[0567] The wiring PL is a wiring for supplying a constant potential for maintaining the potential of the capacitor 38. By connecting a plurality of wirings PL together as one wiring, the number of wirings can be reduced.

[0568] In one embodiment of the present invention, while stacking OS transistors, wiring used as bit lines is arranged in a direction perpendicular to the substrate surface on which layer 20 is provided. Furthermore, transistors 37 and capacitors 38 included in memory cells 32 are arranged in a direction perpendicular to the substrate surface on which layer 20 is provided. By arranging each element and each wiring in a direction perpendicular to the substrate surface, the wiring length between element layers can be shortened, and the density of elements arranged per unit area can be increased. Thus, a memory device excellent in reducing storage capacity and power consumption can be realized.

[0569] [Configuration Example of Memory Cell 32 and Sense Amplifier 46] Fig.47A and Fig.47B 1 is a diagram illustrating a circuit diagram corresponding to the storage unit 32 and a circuit block corresponding to the circuit diagram. Fig.47A and Fig.47B As shown, the memory cell 32 is sometimes shown as a block in the drawings and the like. In addition, when the wiring BL is replaced with the wiring BLB, it is also possible to Fig.47A and Fig.47B The wiring BL shown similarly represents the wiring BLB.

[0570] in addition, Fig.47C and Fig.47D 1 is a diagram for explaining a circuit diagram corresponding to the sense amplifier 46 and a circuit block corresponding to the circuit diagram. The sense amplifier 46 shows a switch circuit 82, a precharge circuit 83, a precharge circuit 84, and an amplifier circuit 85. In addition to the wiring BL and the wiring BLB, the wiring SA_OUT and the wiring SA_OUTB for outputting the read signal are shown.

[0571] like Fig.47C As shown, the switch circuit 82 includes, for example, n-channel transistors 82_1 and 82_2. The transistors 82_1 and 82_2 switch the conduction state of the wiring pair of wiring SA_OUT and wiring SA_OUTB and the wiring pair of wiring BL and wiring BLB according to the signal CSEL.

[0572] like Fig.47C As shown in FIG. 1 , the precharge circuit 83 is composed of n-channel transistors 83_1 to 83_3. The precharge circuit 83 is a circuit for performing precharge so that the wiring BL and the wiring BLB reach an intermediate potential VPRE corresponding to the potential VDD / 2 according to the signal EQ.

[0573] like Fig.47CAs shown, the precharge circuit 84 is composed of p-channel transistors 84_1 to 84_3. The precharge circuit 84 is a circuit for performing precharge so that the wiring BL and the wiring BLB reach an intermediate potential VPRE corresponding to the potential VDD / 2 according to the signal EQB.

[0574] like Fig.47C As shown, the amplifier circuit 85 is composed of p-channel transistors 85_1 and 85_2 and n-channel transistors 85_3 and 85_4 connected to wiring SAP or wiring SAN. Wiring SAP or wiring SAN is a wiring having a function of supplying VDD or VSS. Transistors 85_1 to 85_4 are transistors constituting an inverter loop.

[0575] also, Fig.47D It is a description corresponding to Fig.47C FIG. 4 is a diagram of a circuit block of the sense amplifier 46 described in FIG. Fig.47D As shown, the sense amplifier 46 is sometimes represented as a block in drawings and the like.

[0576] Fig.48 yes Fig.45 A circuit diagram of the storage device 80 is shown. Fig.48 Use in FIG. 47A to FIG. 47D The circuit blocks described in .

[0577] like Fig.48 As shown, the layer 70 having the element layer 30[m] includes the memory cell 32. As an example, Fig.48 The memory cell 32 shown is connected to a pair of wiring BL[1] and wiring BLB[1] or wiring BL[2] and wiring BLB[2]. The memory cell 32 connected to the wiring BL is a memory cell that performs data writing or reading.

[0578] The wiring BL[1] and the wiring BLB[1] are connected to the sense amplifier 46[1], and the wiring BL[2] and the wiring BLB[2] are connected to the sense amplifier 46[2]. The sense amplifier 46[1] and the sense amplifier 46[2] can be connected according to Fig.47C The data is read out by using the various signals described in .

[0579] This embodiment mode can be combined with other embodiment modes and examples as appropriate.

[0580] (Implementation method 3) In this embodiment, using FIG. 49 to FIG. Fig.52An application example of a semiconductor device according to one embodiment of the present invention is described. For example, a semiconductor device according to one embodiment of the present invention can be used in electronic components, electronic devices, large computers, space equipment, and data centers (also referred to as DC). Electronic components, electronic devices, large computers, space equipment, and data centers using a semiconductor device according to one embodiment of the present invention are effective in achieving high performance such as low power consumption.

[0581] [Electronic components] Fig.49A A perspective view of a substrate (circuit board 704 ) on which an electronic component 700 is mounted is shown. Fig.49A The electronic component 700 shown includes a semiconductor device 710 within a mold 711. Fig.49A 700 is partially omitted to show the inside thereof. The electronic component 700 includes a land 712 on the outside of the mold 711. The land 712 is electrically connected to the electrode pad 713, and the electrode pad 713 is electrically connected to the semiconductor device 710 through the lead 714. The electronic component 700 is mounted on, for example, a printed circuit board 702. By combining a plurality of these electronic components and electrically connecting them on the printed circuit board 702, a circuit board 704 is completed.

[0582] In addition, the semiconductor device 710 includes a driving circuit layer 715 and a storage layer 716. The storage layer 716 has a structure in which a plurality of memory cell arrays are stacked. The structure in which the driving circuit layer 715 and the storage layer 716 are stacked can be a monolithic stack. In the monolithic stack structure, it is possible to connect the layers without using through-electrode technologies such as TSV (Through Silicon Via) and bonding technologies such as Cu-Cu direct bonding. When the driving circuit layer 715 and the storage layer 716 are stacked in a monolithic manner, for example, a so-called on-chip memory structure in which a memory is directly formed on a processor can be realized. By adopting the on-chip memory structure, high-speed operation of the interface portion between the processor and the memory can be achieved.

[0583] In addition, by adopting an on-chip memory structure, the size of the connection wiring can be reduced compared to the technology using through-electrodes such as TSV, so the number of pins can be increased. By increasing the number of pins, parallel operation can be performed, thereby increasing the bandwidth of the memory (also called memory bandwidth).

[0584] In addition, it is preferred that multiple memory cell arrays in the storage layer 716 are formed using OS transistors, and the multiple memory cell arrays are stac...

Claims

1. A storage device, comprising: a first storage unit; a second storage unit; a first insulator; as well as a second insulator on the first insulator, The first storage unit includes a first capacitor and a first transistor on the first capacitor. The second storage unit includes a second capacitor and a second transistor on the second capacitor, The first insulator includes a first opening and a second opening, at least a portion of the first capacitor is disposed in the first opening; disposing at least a portion of the second capacitor in the second opening, The second insulator includes a third opening and a fourth opening, at least a portion of the first transistor is disposed in the third opening; at least a portion of the second transistor is disposed in the fourth opening; The first opening has a region overlapping with the third opening, The second opening has an area overlapping with the fourth opening, The distance between the centers of the first opening and the second opening is consistent with the distance between the centers of the third opening and the fourth opening. The maximum width of the first opening portion and the maximum width of the third opening portion are different from each other, Furthermore, a maximum width of the second opening portion and a maximum width of the fourth opening portion are different from each other.

2. The storage device according to claim 1, wherein the maximum width of the first opening is greater than the maximum width of the third opening, And the maximum width of the second opening is greater than the maximum width of the fourth opening.

3. The storage device according to claim 1, wherein a channel length of the first transistor is smaller than a channel width of the first transistor, And a channel length of the second transistor is smaller than a channel width of the second transistor.

4. The storage device according to claim 1, wherein each semiconductor layer of the first transistor and the second transistor comprises an oxide semiconductor, And the oxide semiconductor contains one or more selected from In, Ga and Zn.

5. The storage device according to claim 1, The first capacitor and the second capacitor both include a first conductor, a third insulator on the first conductor, and a second conductor on the third insulator, The third insulator includes a first zirconium oxide, an aluminum oxide on the first zirconium oxide, and a second zirconium oxide on the aluminum oxide.

6. The storage device according to any one of claims 1 to 5, further comprising: a plurality of layers including the first storage unit and the second storage unit, A plurality of said layers are stacked.

7. A storage device, comprising: a first electrical conductor; a storage unit on the first electrical conductor; a first insulator on the first electrical conductor; as well as The second insulator, The storage unit includes a capacitor and a transistor on the capacitor. The capacitor includes a second conductor, a third insulator on the second conductor, and a third conductor on the third insulator. The first insulator is provided with a first opening reaching the first conductor, At least a portion of the second conductor, at least a portion of the third insulator, and at least a portion of the third conductor are disposed in the first opening. The second conductor, the third insulator, and the third conductor are provided with the second insulator. The transistor includes the third conductor, a fourth conductor on the second insulator, an oxide semiconductor, a fourth insulator, and a fifth conductor. The second insulator and the fourth conductor are provided with a second opening reaching the third conductor, At least a portion of the oxide semiconductor is disposed in the second opening. The oxide semiconductor includes a region in the second opening that contacts the top surface of the third conductor, a region in the second opening that contacts the side surface of the fourth conductor, and a region that contacts at least a portion of the top surface of the fourth conductor. The fourth insulator is arranged on the oxide semiconductor so that at least a part of the fourth insulator is located in the second opening. The fifth conductor is arranged on the fourth insulator in such a manner that at least a portion of the fifth conductor is located in the second opening. Furthermore, a maximum width of the first opening portion and a maximum width of the second opening portion are different from each other.

8. The storage device according to claim 7, The maximum width of the first opening is greater than the maximum width of the second opening.

9. The storage device according to claim 7, The second opening has an area overlapping with the first opening.

10. The storage device according to claim 7, The channel length of the transistor is smaller than the channel width of the transistor.

11. The storage device according to claim 7, The third insulator includes a first zirconium oxide, an aluminum oxide on the first zirconium oxide, and a second zirconium oxide on the aluminum oxide.

12. The storage device according to claim 7, The oxide semiconductor includes one or more selected from In, Ga and Zn.

13. The storage device according to any one of claims 7 to 12, wherein the fifth conductor extends in the first direction, The fourth conductor extends in the second direction, And the first direction is orthogonal to the second direction.

14. The storage device according to claim 13, further comprising: a plurality of layers including said storage unit, Wherein, a plurality of said layers are stacked.

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