SIMT stack and thread scheduling optimization method and device for GPGPU branch instruction, medium and GPGPU architecture

Abstract

The invention relates to the technical field of GPGPU (General Purpose Graphics Processing Unit), and relates to an SIMT stack and thread scheduling optimization method and device for GPGPU (General Purpose Graphics Processing Unit) branch instructions, a medium and a GPGPU architecture. The method comprises the steps that in a GPGPU, an SIMT stack is optimized, an SM unit is expanded to be a double-instruction assembly line, and a main thread beam scheduler and an auxiliary thread beam scheduler are arranged. And in a non-branch state, half threads of each tube of the scheduler are executed in parallel by the assembly line. When a branch instruction is encountered, instruction addresses, thread masks and branch reunion points of the two branch paths are pressed into the SIMT stack. Judging conflicts according to the thread masks; if conflicts exist, performing serial execution; and if no conflict exists, executing on double pipelines in parallel. And when the branch is completed to a reunion point, the SIMT stack pops up an entry, and the execution is continued. The method has remarkable effects in the aspects of improving the thread resource utilization rate, improving the calculation efficiency, simplifying the branch control complexity, enhancing the GPGPU flexibility and the like.

Description

Technical Field

[0001] The present application relates to the technical field of general-purpose computing graphics processing units, and to a SIMT stack and thread scheduling optimization method, device, medium and GPGPU architecture for GPGPU branch instructions. Background Art

[0002] At present, with the rapid development of computer technology, GPU (Graphics Processing Unit) is no longer limited to traditional graphics rendering tasks, but its computing power has been expanded to various general computing tasks through GPGPU (General-Purpose computing on Graphics Processing Units) technology. GPGPU is not only widely used in scientific computing, data analysis, image processing and other fields, but also has shown excellent performance in the hot fields of deep learning and artificial intelligence in recent years.

[0003] The core advantage of GPGPU lies in its highly parallel computing capability. Multiple threads are operated internally in warps, and all threads in each warp execute the same instruction, which is called single instruction multiple threads (SIMT) technology. This parallel computing mode greatly improves the execution efficiency of computing tasks, especially when dealing with large-scale parallel tasks. However, in actual applications, the GPGPU instruction set is not entirely parallel computing instructions, but also includes a large number of branch instructions, such as if-else, while, for, etc.

[0004] When processing branch instructions, GPGPU introduces SIMT stack and active thread mask to control branch jumps. Specifically, SIMT stack is responsible for saving the instruction pointer (PC), thread mask (ActiveMask) and branch reunion point (RPC) of each branch. When encountering a branch instruction, according to the conditional judgment results of each thread, GPGPU will push the PC, thread mask and RPC of the corresponding branch into the SIMT stack, and execute each branch one by one in the order of the top instruction of the stack.

[0005] However, the traditional SIMT stack and thread scheduling mechanism has obvious resource waste problems when processing branch instructions. Since the SIMT mechanism stipulates that a thread warp can only execute one instruction at the same time, when a branch instruction is executed, even if only some threads meet the branch conditions and perform corresponding operations, other threads in the thread warp will be idle and unable to participate in the calculation of other tasks. This state leads to a serious waste of computing resources and limits the computing efficiency of GPGPU.

[0006] Therefore, there is an urgent need for a method that can effectively optimize the SIMT stack and thread scheduling of GPGPU branch instructions to improve the utilization of computing resources and the overall performance of GPGPU.

[0007] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0008] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical components or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0009] The embodiments of the present disclosure provide a method, device, medium and GPGPU architecture for optimizing the SIMT stack and thread scheduling of GPGPU branch instructions. By improving the structure of the SIMT stack and the strategy of thread scheduling, the GPGPU can process branch instructions more efficiently and achieve higher computing efficiency and performance.

[0010] In some embodiments, the method comprises:

[0011] An optimized SIMT stack is set in the GPGPU, wherein each entry of the SIMT stack includes instruction addresses PCL and PCR of two branch paths, thread masks MaskL and MaskR of the two branch paths, and a branch reunion point RPC;

[0012] The single instruction pipeline of the SM unit is expanded into a dual instruction pipeline, and the thread scheduling of the dual instruction pipeline is implemented by the main and secondary thread warp schedulers; the specific method of thread scheduling is as follows:

[0013] When GPGPU executes non-branch instructions, the main and secondary warp schedulers schedule half of the threads in the warp respectively, and two instruction pipelines execute the instructions of the threads respectively;

[0014] When GPGPU executes a branch instruction, the starting instruction addresses PC of the two branches of the branch instruction, the corresponding thread mask Mask, and the instruction address RPC of the branch reunion point are pushed into the SIMT stack;

[0015] GPGPU determines whether the active threads of the two branches conflict based on the thread masks of branch 1 and branch 2;

[0016] If there is a conflict, one of the branches will be scheduled to enter the instruction pipeline for execution first, and then the other branch will be scheduled for execution after the execution of the branch is completed;

[0017] If there is no conflict, the main warp scheduler schedules one of the branches to enter the first instruction pipeline for execution, and the secondary warp scheduler schedules the other branch to enter the second instruction pipeline for execution, and the two branches are executed simultaneously;

[0018] When any branch executes to its branch reunion point, the entry for that branch is popped from the SIMT stack and execution of subsequent instructions continues.

[0019] Preferably, when a branch instruction is executed and active threads of two branch paths need to be scheduled by two warp schedulers simultaneously, a serial scheduling method is adopted, that is, one of the branch paths is executed first, and after it is executed, the other branch path is executed.

[0020] Preferably, when a branch instruction is executed and active threads of two branch paths are independently controlled by the main warp scheduler and the secondary warp scheduler respectively, the two branch paths can enter the dual instruction pipeline for execution at the same time.

[0021] Preferably, the two branch paths in the entry of the SIMT stack have no priority relationship.

[0022] In some embodiments, the GPGPU architecture includes a Host and a GPGPU;

[0023] The Host part is composed of a CPU and memory. The CPU is used to establish, allocate, schedule and release computing tasks, and compile the programs written on the CPU into hardware instructions that can be parsed by GPGPU through a compiler.

[0024] The GPGPU part is used as a coprocessor to process computationally intensive computing tasks, including a PCIE control module, a thread block scheduling module, a global memory, an L2 Cache, a constant parameter memory, and a SM;

[0025] Among them, the PCIE control module is used to realize the communication between the CPU and GPGPU, and to establish a data transmission channel between the GPGPU memory and the Host memory; the thread block scheduling module is used to schedule and allocate thread blocks to each SM; the GPGPU configuration module is used to initialize the GPGPU and configure its control parameters; the L2 Cache is used to prefetch data in the global memory by merging memory accesses; the global memory is used to store data to be processed and compiled hardware control instructions, and the constant parameter memory is used as a read-only memory to store constant parameters during the calculation process.

[0026] Preferably, each SM includes two pipelines, a SIMT stack, a register file, an L1 Cache, a shared memory, and at least one warp scheduling module, wherein:

[0027] The two pipelines complete instruction fetch, decoding, emission, execution, and result write-back through a five-stage pipeline. In the execution stage, the threads in the warp are assigned to each SP for parallel execution;

[0028] The SIMT stack is used to handle the jump of branch instructions;

[0029] Register files are used to cache data and intermediate calculation results during the operation process;

[0030] Shared memory is used for data exchange between warps and threads;

[0031] L1 Cache prefetches data and instructions from L2 Cache.

[0032] In some embodiments, the device includes a processor and a memory storing program instructions, and the processor is configured to execute the SIMT stack and thread scheduling optimization method for GPGPU branch instructions when running the program instructions.

[0033] In some embodiments, the storage medium stores program instructions, and when the program instructions are run, they execute the SIMT stack and thread scheduling optimization method for GPGPU branch instructions.

[0034] The embodiments of the present disclosure provide a method, device, medium and GPGPU architecture for optimizing SIMT stack and thread scheduling of GPGPU branch instructions, which can achieve the following technical effects:

[0035] When executing branch instructions in traditional GPGPU, a thread warp can only execute one instruction at a time, and threads that do not meet the conditions will be idle and cannot be effectively utilized. However, the present invention realizes the simultaneous execution and scheduling of branch instruction dual paths by introducing a dual instruction pipeline architecture and a primary and secondary thread warp scheduler, so that code blocks of different branches can be executed simultaneously by different threads in the same thread warp, significantly improving the utilization rate of thread resources.

[0036] In traditional methods, code blocks of different branches can only be executed serially, resulting in a waste of resources and reduced computing efficiency. However, the present invention optimizes the SIMT stack and thread scheduling mechanism to allow instructions of different branches to be executed simultaneously to a certain extent. This parallel execution mechanism greatly improves the computing speed and overall performance of GPGPU.

[0037] The present invention optimizes the stack entry and exit logic of the branch path by optimizing the SIMT stack, making the branch control simpler and more efficient. Under the dual instruction pipeline architecture, each SIMT entry contains the instruction address, thread mask and branch reunion point of the two branch paths. This design reduces the redundant information of the stack and improves the accuracy and efficiency of control.

[0038] The application of this method is not limited to a specific GPGPU architecture, but can be implemented in a variety of GPGPU designs, with strong flexibility and scalability. By optimizing thread scheduling and instruction execution processes, this method can adapt to different types of computing tasks and application scenarios, improving the versatility and adaptability of GPGPU.

[0039] In summary, the SIMT stack and thread scheduling optimization method for GPGPU branch instructions proposed in the present invention has significant beneficial effects in improving thread resource utilization, improving computing efficiency, simplifying branch control complexity, and enhancing GPGPU flexibility, and is of great significance for promoting the development and application of GPGPU technology.

[0040] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein:

[0042] Figure 1 It is a schematic flow chart of the method of the present invention;

[0043] Figure 2 is a schematic diagram of a branch instruction provided by an embodiment of the present disclosure;

[0044] Figure 3 It is a schematic diagram of a traditional SIMT stack and thread scheduling process provided by an embodiment of the present disclosure;

[0045] Figure 4 is a schematic diagram of a dual instruction pipeline architecture of an embodiment of the present disclosure;

[0046] Figure 5 It is a schematic diagram of a dual-path SIMT stack and thread scheduling process provided by an embodiment of the present disclosure;

[0047] Figure 6 It is a schematic diagram of the structure of a nonlinear pipeline architecture GPGPU provided by an embodiment of the present disclosure;

[0048] Figure 7 It is a schematic diagram of the device structure provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0049] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0050] The terms "first", "second", etc. in the specification and claims of the embodiments of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so as to describe the embodiments of the embodiments of the present disclosure described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0051] Example 1

[0052] like Figure 1 As shown, a SIMT stack and thread scheduling optimization method for GPGPU branch instructions includes:

[0053] S1: setting an optimized SIMT stack in the GPGPU, wherein each entry of the SIMT stack includes instruction addresses PCL and PCR of two branch paths, thread masks MaskL and MaskR of the two branch paths, and a branch reunion point RPC;

[0054] S2: Expand the single instruction pipeline of the SM unit into a dual instruction pipeline, and implement thread scheduling of the dual instruction pipeline by the main and secondary warp schedulers; the specific method of thread scheduling is as follows:

[0055] S201: When GPGPU executes a non-branch instruction:

[0056] The main and secondary warp schedulers schedule half of the threads in the warp respectively, and two instruction pipelines execute the instructions of the threads respectively;

[0057] S202: When GPGPU executes a branch instruction:

[0058] S2021: Push the starting instruction addresses PC of the two branches of the branch instruction, the corresponding thread mask Mask, and the instruction address RPC of the branch reunion point into the SIMT stack;

[0059] S2022: GPGPU determines whether active threads of branch 1 and branch 2 conflict with each other according to thread masks of the two branches;

[0060] S2023: If there is a conflict, one of the branches is scheduled to enter the instruction pipeline for execution first, and the other branch is scheduled for execution after the execution of the branch is completed;

[0061] If there is no conflict, the main warp scheduler schedules one of the branches to enter the first instruction pipeline for execution, and the secondary warp scheduler schedules the other branch to enter the second instruction pipeline for execution, and the two branches are executed simultaneously;

[0062] S2024: When any branch is executed to its branch reunion point, the entry of the branch is popped from the SIMT stack, and subsequent instructions are continued to be executed.

[0063] As a refinement of the above embodiment, when a branch instruction is executed and active threads of two branch paths need to be scheduled by two warp schedulers at the same time, a serial scheduling method is adopted, that is, one of the branch paths is executed first, and after it is executed, the other branch path is executed.

[0064] When the GPGPU executes a branch instruction and the active threads of the two branch paths need to be scheduled by two warp schedulers at the same time, the present invention adopts a serial scheduling method. This strategy ensures that even in the case of resource conflicts, the branch paths can be executed in an orderly manner, avoiding the waste caused by idle resources in traditional methods.

[0065] As a refinement of the above embodiment, when a branch instruction is executed and active threads of two branch paths are independently controlled by the primary warp scheduler and the secondary warp scheduler, the two branch paths can simultaneously enter the dual instruction pipeline for execution.

[0066] When the active threads of the two branch paths are independently controlled by the main thread warp scheduler and the secondary thread warp scheduler, the present invention allows the two branch paths to enter the dual instruction pipeline for execution at the same time. This parallel processing method greatly improves the utilization rate of thread resources, allowing GPGPU to perform complex computing tasks more efficiently.

[0067] As a refinement of the above embodiment, the two branch paths in the entry of the SIMT stack have no priority relationship.

[0068] By optimizing the SIMT stack, the present invention simplifies the stack entry and exit logic of the branch path, making the branch control more intuitive and efficient. Each SIMT stack entry contains the instruction address, thread mask and branch reunion point of two branch paths. This design makes the execution and scheduling of branch instructions more flexible and convenient.

[0069] Combine the following Figure 2 - Figure 6 The example in the following describes the technical solution of this application in detail:

[0070] When GPGPU executes branch instructions, it usually implements instruction jumps and conditional branch maintenance through the SIMT stack. Figure 2 The figure shows a branch instruction situation. A thread warp contains four threads. The thread mask is 4 bits. Each bit indicates whether the corresponding thread is active. 1 indicates active and 0 indicates idle. After executing code block A, branches B and F appear on GPGPU. When executing code block B, branches C and D appear. At the same time, C and D converge at E, and E and F converge at G. Generally, E and G are called branch reunion points. Figure 2 Taking the branch scenario shown as an example, the optimization implementation process of SIMT and thread scheduling by the method described in this embodiment is described.

[0071] (1) Traditional SIMT stack and thread scheduling

[0072] Each entry in the traditional SIMT stack consists of an instruction pointer (PC), a thread mask (Active Mask), and a branch reunion point (RPC). The results and implementation of branch instructions are as follows: Figure 3 As shown, it is assumed that a warp consists of 4 threads.

[0073] by Figure 2 Taking the branch instruction shown in the figure as an example, when GPGPU executes code block A, the SIMT stack is as follows Figure 3 As shown in (a), when code block A executes to the last branch instruction, when branches B and F appear, GPGPU pushes the branch PC, thread mask and branch reunion point into the stack, as shown in Figure 3 As shown in (b), the SIMT stack pushes branches B and F and the branch reunion point G. F is at the head of the stack and branch F is executed first. PC is the first instruction address of code block F. The current instruction of GPGPU jumps to the address of code block F according to this PC to execute the instruction. The thread mask is 1000, which means that only thread 3 is active, and threads 0, 1 and 2 are idle. The branch reunion point is E, which is the first instruction address of code block E, indicating that the current branch is completed after executing this instruction.

[0074] When the last instruction of code block F is executed, the instruction address is the same as the address of branch reunion point G, indicating that the branch reunion point has been reached. The entry is popped from the SIMT stack and the next entry B is executed, such as Figure 3 (c) As shown in the figure, GPGPU jumps to the first instruction address of code block B according to the PC value of entry B and continues to execute code block B. When executing to the last instruction of code block B, branches D and C appear. SIMT stacks branches D and C and branch reunion point E, as shown in the figure. Figure 3As shown in (d), C is at the head of the stack. C is popped out first to execute branch C. The address of the last instruction of code block C is the same as the address of branch reunion point E. The entry is popped out from the SIMT stack and the next entry D is executed. Similarly, the address of the last instruction of code block D is the same as the address of branch reunion point E. The entry is popped out from the SIMT stack and the next entry E is executed. Figure 3 (e) When the code block E executes to the last instruction, the instruction address is the same as the address of the branch reunion point G. The entry is popped from the SIMT stack and the next entry G is executed, as shown in Figure 3 As shown in (f), at this point, all branches have been executed.

[0075] In the traditional method, all threads in a thread bundle can only execute the same instruction. When executing branch instructions, code blocks of different branches can only be executed serially, such as Figure 3 As shown in (g), when executing branch F, only thread T3 of the four threads in the thread bundle is active, and T0 to T2 are all idle. The thread bundle needs to execute branch F before executing branch B. Similarly, for branches C and D, the thread bundle needs to execute branch C before executing branch D. This thread scheduling method results in that even if only one thread executes a branch, the other thread resources of the thread bundle can only be idle and cannot be called by other thread bundles, resulting in a great waste of thread resources, low resource utilization, and reduced computing efficiency.

[0076] (2) SIMT stack and thread scheduling optimization method

[0077] In view of the above problems, this embodiment optimizes the SIMT stack structure and thread scheduling method, expands the single instruction pipeline of the SM unit into a dual instruction pipeline, and implements the scheduling and control of the dual instruction pipeline by the main and auxiliary thread warp schedulers. The structure is as follows: Figure 4 As shown in the figure. When GPGPU executes general operation instructions, the two instruction pipelines each take on half of the threads of a thread bundle. For example, if a thread bundle contains 32 threads, when GPGPU executes operation instructions, the two instruction pipelines each take on the execution tasks of 16 threads. When GPGPU executes branch instructions, for different branches, the two pipelines can execute different branch instructions at the same time to a certain extent according to the branch situation, thereby improving thread resource utilization and computing efficiency.

[0078] In order to meet the control characteristics of the thread scheduling method and the dual instruction pipeline architecture described in this embodiment during branch instructions, the traditional SIMT stack is optimized, and the structure is as follows: Figure 5As shown, each SIMT entry contains five parts: the instruction addresses of the two branch paths (PCL and PCR), the thread masks (MaskL and MaskR), and the branch reunion point RPC. The branch reunion points of the two branch paths are the same, so only one identifier is required. The two branch paths are identified by L and R, and there is no priority relationship.

[0079] Taking the scheduling of a warp containing four threads as an example, the warp in the initial state executes code block A, such as Figure 5 As shown in (a), the SIMT stack stores the instruction address PCL and thread mask MaskL of code block A. There is no branch, so PCR, MaskR and RPC are empty. When the last instruction of code block A is executed, branches F and B appear. At this time, the PC and Mask of branches F and B are pushed into the stack, and the reunion point G of the two branches is also pushed into the stack, as shown in Figure 5 As shown in (b), both F and B can be set to L or R. The figure is just an example.

[0080] At this time, the two branch paths can enter the two instruction pipelines for scheduling and execution at the same time. The main and secondary thread warp schedulers jump to the corresponding address according to PCL and PCR, and the two instruction pipelines execute the corresponding code blocks at the same time, but the two branches may not be completed at the same time. Figure 5 As shown in (c), branch F is executed first, that is, the address of the last instruction is the same as the address of the first instruction of G, and the branch reunion point is reached, but branch B is not completed. At this time, it is necessary to wait for branch B to be executed. When the last instruction of branch B is executed, new branches C and D appear. At this time, the PC and Mask of branches C and D are pushed into the stack, and the reunion point E of the two branches is also pushed into the stack, as shown in Figure 5 (d) As shown. Branches C and D are scheduled by the main and secondary warp schedulers to enter the two instruction pipelines and start execution. The two branches C and D are executed at the same time. That is, the last address of the two code blocks is the same as the first instruction address of the branch reunion point E, indicating that the branch reunion point has been reached. At this time, this entry is popped from the SIMT stack and the next entry, code block E, is executed. Figure 5 (e) When the code block E executes to the last instruction, the instruction address is the same as the first instruction address of G, and the branch reunion point is reached. The SIMT stack pops this entry and executes the next entry G, as shown in Figure 5 As shown in (f), at this point, all branches have been executed.

[0081] The method described in this embodiment is scheduled by the main and secondary warp schedulers in thread scheduling, and enters two instruction pipelines for execution. Taking this example, Figure 5As shown in (g), warp 0 is split into warp 0-0 and warp 0-1. Warp 0-0 contains threads T0~T1, which is scheduled and controlled by the main warp scheduler, and the instruction execution is completed by pipeline 1. Warp 0-1 contains threads T2~T3, which is scheduled and controlled by the secondary warp scheduler, and the instruction execution is completed by pipeline 2. The scheduling and execution of warp 0-0 and warp 0-1 are independent of each other.

[0082] When GPGPU executes branches B and F, the main and secondary warp schedulers determine whether to execute based on the thread mask. At this time, the thread mask of B is 0111, and the active threads are located in warp 0-0 and warp0-1 at the same time, which means that the main and secondary warp schedulers need to schedule at the same time to execute the code block. Therefore, branches B and F cannot be scheduled and executed at the same time, but can only be executed serially. In this example, code block F is executed first, and then code block B. When executing branches C and D, the thread mask of C is 0100, and the active thread is located in warp 0-1. The thread mask of D is 0011, and the active thread is located in warp 0-0. At this time, the main and secondary warp schedulers can schedule branches C and D to enter two pipelines for simultaneous execution, making maximum use of thread resources and improving resource utilization and computing efficiency.

[0083] The specific implementation process of thread scheduling is as follows:

[0084] 1) When GPGPU executes non-branch instructions, the main and secondary warp schedulers respectively schedule and control half of the threads in the warp, and two instruction pipelines respectively complete the instruction execution of half of the threads.

[0085] 2) When GPGPU executes a branch instruction, the starting instruction address PC and thread mask Mask of branch 1 and branch 2 and the instruction address of the branch reunion point are pushed into the SIMT stack.

[0086] 3)GPGPU determines whether the active threads of branch 1 and branch 2 conflict based on the thread masks of the two branches.

[0087] 4) If the active thread of branch 1 or branch 2 needs to be scheduled by two warp schedulers at the same time, there is a conflict between the active threads of the two branches, and steps 5) to 8) are executed.

[0088] 5) The main and secondary warp schedulers first schedule one of the two branches to enter the two instruction pipelines for execution.

[0089] 6) When the address of the last instruction of the branch is the same as the address of the branch reunion point, it means that the branch reunion point has been reached and the branch execution is completed.

[0090] 7) The main and secondary warp schedulers schedule another branch to enter the instruction pipeline for execution.

[0091] 8) When the other branch also reaches the branch reunion point, this entry is popped from the SIMT stack to complete the branch execution.

[0092] 9) If the active threads of branch 1 and branch 2 only need to be scheduled by one of the warp schedulers, there is no conflict between the active threads of the two branches, and steps 10) to 11) are executed.

[0093] 10) The main warp scheduler schedules one of the branches to enter instruction pipeline 1 for execution, and the secondary warp scheduler schedules the other branch to enter instruction pipeline 2 for execution.

[0094] 11) After waiting for both branches to reach the branch reunion point, this entry is popped from the SIMT stack to complete the branch execution.

[0095] 12) GPGPU continues to execute the next instruction. When the branch instruction is executed again, steps 2) to 11) are repeated.

[0096] Example 2

[0097] like Figure 6 As shown, a GPGPU architecture includes a Host and a GPGPU;

[0098] The Host part is composed of a CPU and memory. The CPU is used to establish, allocate, schedule and release computing tasks, and compile the programs written on the CPU into hardware instructions that can be parsed by GPGPU through a compiler.

[0099] The GPGPU part is used as a coprocessor to process computationally intensive computing tasks, including a PCIE control module, a thread block scheduling module, a global memory, an L2 Cache, a constant parameter memory, and a SM;

[0100] Among them, the PCIE control module is used to realize the communication between the CPU and GPGPU, and to establish a data transmission channel between the GPGPU memory and the Host memory; the thread block scheduling module is used to schedule and allocate thread blocks to each SM; the GPGPU configuration module is used to initialize the GPGPU and configure its control parameters; the L2 Cache is used to prefetch data in the global memory by merging memory accesses; the global memory is used to store data to be processed and compiled hardware control instructions, and the constant parameter memory is used as a read-only memory to store constant parameters during the calculation process.

[0101] Preferably, each SM includes two pipelines, a SIMT stack, a register file, an L1 Cache, a shared memory, and at least one warp scheduling module, wherein:

[0102] SM (streaming multiprocessor) is the computing unit of GPGPU, which is composed of two pipelines, SIMT stack, register file, L1 Cache, shared memory and pipeline. SITM stack mainly handles the jump of branch instructions, register file is used to cache data and intermediate calculation results during the operation, shared memory is used for data exchange between warps and threads, and L1 Cache pre-fetches data and instructions from L2 Cache to further reduce the memory access time of the pipeline.

[0103] The pipeline is the key to SM's computing function. The method described in this paper consists of two pipelines in each SM. Similarly, two warp scheduling modules implement the scheduling and maintenance of warps. The pipeline completes instruction fetching, decoding, emission, execution, and result writing through a five-stage pipeline. The efficiency of the pipeline directly determines the computing performance of GPGPU. Among them, the execution stage of the pipeline will assign several threads in a warp to each SP for execution.

[0104] SP (streaming processor) is the smallest computing unit of GPGPU, which completes ALU, SFU, FPU and other operations. The number of SPs determines the parallelism of thread execution in a warp. Generally speaking, when the number of SPs is the same as the number of threads in a warp, the parallelism is the highest, and all threads in the warp can be fully parallel in the execution phase.

[0105] Combination Figure 7 As shown, the embodiment of the present disclosure provides a SIMT stack and thread scheduling optimization device 300 for GPGPU branch instructions, including a processor (processor) 304 and a memory (memory) 301. Optionally, the device may also include a communication interface (Communication Interface) 302 and a bus 303. Among them, the processor 304, the communication interface 302, and the memory 301 can communicate with each other through the bus 303. The communication interface 302 can be used for information transmission. The processor 304 can call the logic instructions in the memory 301 to execute the SIMT stack and thread scheduling optimization method for GPGPU branch instructions of the above embodiment.

[0106] In addition, the logic instructions in the memory 301 described above can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product.

[0107] The memory 301 is a computer-readable storage medium that can be used to store software programs and computer executable programs, such as program instructions / modules corresponding to the method in the embodiment of the present disclosure. The processor 304 executes the functional application and data processing by running the program instructions / modules stored in the memory 301, that is, the SIMT stack and thread scheduling optimization method of the GPGPU branch instruction in the above embodiment is implemented.

[0108] The memory 301 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application required for at least one function; the data storage area may store data created according to the use of the terminal device, etc. In addition, the memory 301 may include a high-speed random access memory and may also include a non-volatile memory.

[0109] An embodiment of the present disclosure provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are configured to execute the SIMT stack and thread scheduling optimization method of the above-mentioned GPGPU branch instruction.

[0110] The computer-readable storage medium mentioned above may be a transient computer-readable storage medium or a non-transitory computer-readable storage medium.

[0111] The technical solution of the embodiment of the present disclosure can be embodied in the form of a software product, which is stored in a storage medium and includes one or more instructions for enabling a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in the embodiment of the present disclosure. The aforementioned storage medium may be a non-transient storage medium, including: a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and other media that can store program codes, or a transient storage medium.

[0112] The above description and the accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent only possible changes. Unless explicitly required, separate components and functions are optional, and the order of operation may vary. The parts and features of some embodiments may be included in or replace the parts and features of other embodiments. Moreover, the words used in this application are only used to describe the embodiments and are not used to limit the claims. As used in the description of the embodiments and the claims, unless the context clearly indicates, the singular forms of "a", "an" and "the" are intended to include plural forms as well. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of listings containing one or more associated ones. In addition, when used in the present application, the term "comprise" and its variants "comprises" and / or comprising refer to the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the presence of other identical elements in the process, method or device comprising the elements. In this article, each embodiment may focus on the differences from other embodiments, and the same and similar parts between the embodiments may refer to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can refer to the description of the method part.

[0113] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software may depend on the specific application and design constraints of the technical solution. The technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the embodiments of the present disclosure. The technicians may clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here.

[0114] In the embodiments disclosed herein, the disclosed methods and products (including but not limited to devices, equipment, etc.) can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units can be only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between each other shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to implement this embodiment. In addition, each functional unit in the embodiment of the present disclosure may be integrated in a processing unit, or each unit may exist physically alone, or two or more units may be integrated in one unit.

[0115] The flowchart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to the embodiment of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of the code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. In some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. In the description corresponding to the flowchart and the block diagram in the accompanying drawings, the operations or steps corresponding to different boxes can also occur in a different order from the order disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. Each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified functions or actions, or may be implemented by a combination of dedicated hardware and computer instructions.

Claims

1. A SIMT stack and thread scheduling optimization method for GPGPU branch instructions, characterized in that: include: An optimized SIMT stack is set in the GPGPU, wherein each entry of the SIMT stack includes instruction addresses PCL and PCR of two branch paths, thread masks MaskL and MaskR of the two branch paths, and a branch reunion point RPC; The single instruction pipeline of the SM unit is expanded into a dual instruction pipeline, and the thread scheduling of the dual instruction pipeline is implemented by the main and auxiliary thread warp schedulers; the specific method of thread scheduling is as follows: When GPGPU executes non-branch instructions, the main and secondary warp schedulers schedule half of the threads in the warp respectively, and two instruction pipelines execute the instructions of the threads respectively; When GPGPU executes a branch instruction, the starting instruction addresses PC of the two branches of the branch instruction, the corresponding thread mask Mask, and the instruction address RPC of the branch reunion point are pushed into the SIMT stack; GPGPU determines whether the active threads of the two branches conflict based on the thread masks of branch 1 and branch 2; If there is a conflict, one of the branches will be scheduled to enter the instruction pipeline for execution first, and then the other branch will be scheduled for execution after the execution of the branch is completed; If there is no conflict, the main warp scheduler schedules one of the branches to enter the first instruction pipeline for execution, and the secondary warp scheduler schedules the other branch to enter the second instruction pipeline for execution, and the two branches are executed simultaneously; When any branch executes to its branch reunion point, the entry for that branch is popped from the SIMT stack and execution of subsequent instructions continues.

2. The SIMT stack and thread scheduling optimization method for GPGPU branch instructions according to claim 1, characterized in that: When a branch instruction is executed and the active threads of the two branch paths need to be scheduled by two warp schedulers at the same time, a serial scheduling method is adopted, that is, one of the branch paths is executed first, and after it is executed, the other branch path is executed.

3. The SIMT stack and thread scheduling optimization method for GPGPU branch instructions according to claim 1, characterized in that: When a branch instruction is executed and the active threads of the two branch paths are independently controlled by the main warp scheduler and the secondary warp scheduler, the two branch paths can enter the dual instruction pipeline for execution at the same time.

4. The SIMT stack and thread scheduling optimization method for GPGPU branch instructions according to claim 1, characterized in that: The two branch paths in the entry of the SIMT stack have no priority relationship.

5. A GPGPU architecture for executing the method according to any one of claims 1 to 4, characterized in that: Including Host and GPGPU; The Host part is composed of a CPU and memory. The CPU is used to establish, allocate, schedule and release computing tasks, and compile the programs written on the CPU into hardware instructions that can be parsed by GPGPU through a compiler. The GPGPU part is used as a coprocessor to process computationally intensive computing tasks, including a PCIE control module, a thread block scheduling module, a global memory, an L2 Cache, a constant parameter memory and a SM.

6. The GPGPU architecture according to claim 5, characterized in that: The PCIE control module is used to realize the communication between CPU and GPGPU, and to establish the data transmission channel between GPGPU memory and Host memory; the thread block scheduling module is used to schedule and allocate thread blocks to each SM; the GPGPU configuration module is used to initialize GPGPU and configure its control parameters; the L2 Cache is used to prefetch data in the global memory by merging memory access; the global memory is used to store the data to be processed and the compiled hardware control instructions, and the constant parameter memory is used as a read-only memory to store the constant parameters in the operation process.

7. The GPGPU architecture according to claim 6, characterized in that: Each SM includes two pipelines, a SIMT stack, a register file, an L1 cache, a shared memory, and at least one warp scheduling module.

8. The GPGPU architecture according to claim 7, characterized in that: The two pipelines complete instruction fetch, decoding, emission, execution, and result write-back through a five-stage pipeline. In the execution stage, the threads in the warp are assigned to each SP for parallel execution; The SIMT stack is used to handle the jump of branch instructions; Register files are used to cache data and intermediate calculation results during the operation process; Shared memory is used for data exchange between warps and threads; L1 Cache prefetches data and instructions from L2 Cache.

9. A SIMT stack and thread scheduling optimization device for GPGPU branch instructions, comprising a processor and a memory storing program instructions, characterized in that: The processor is configured to execute the SIMT stack and thread scheduling optimization method for GPGPU branch instructions according to any one of claims 1 to 4 when running the program instructions.

10. A storage medium storing program instructions, characterized in that: When the program instructions are running, the SIMT stack and thread scheduling optimization method for GPGPU branch instructions according to any one of claims 1 to 4 is executed.

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