High-speed low-power-consumption differential driver based on three-state gate MUX and complementary CML

Abstract

The invention provides a high-speed low-power-consumption differential driver based on a three-state gate MUX and a complementary CML. The high-speed low-power-consumption differential driver comprises the three-state gate MUX and a complementary CML driver. The output end of the three-state gate multiplexer MUX is connected with the input end of the complementary CML driver through a buffer circuit, multiple paths of input signals of the three-state gate multiplexer MUX are selected and multiplexed through a high-resistance state and conduction state switching mechanism, and a path of high-speed differential signal is output; the complementary CML driver converts the high-speed differential signal into a high-speed large-swing differential signal and drives an external load. According to the invention, full-rate nodes can be reduced, the signal integrity is improved, and the burr phenomenon caused by switching delay mismatching is inhibited; the amplitude of the differential signal is larger, and the anti-noise performance is enhanced; the buffer is added at the output end of the MUX, and the branch of the complementary CML driver is symmetrically designed, so that the time sequence competition in signal switching is solved, and the signal integrity is improved.

Description

Technical Field

[0001] The invention relates to the technical field of drivers, in particular to a high-speed and low-power differential driver based on a tri-state gate MUX and a complementary CML. Background Art

[0002] In high-speed communication systems, the serializer / deserializer (SerDes) transmitter (TX) is one of the key modules in the system, and its main task is to convert high-speed digital signals into differential analog signals suitable for transmission channels. With the rapid increase in data rates, such as 100Gbps or even higher in PAM4 or NRZ signals, the performance of the driver directly determines the signal integrity and system reliability. In current technologies, tri-state gate multiplexers (MUX) and current mode logic (CML) drivers are widely used for signal processing and signal driving, respectively. However, traditional drivers face many challenges in high-speed applications.

[0003] 1. In the existing TX circuit, the signal after MUX often needs to be processed by an additional driving circuit, which significantly increases the circuit complexity and power consumption. It is also easy to cause signal reflection or interference. Secondly, the swing amplitude cannot be effectively controlled, resulting in the need for the subsequent driver to add an additional swing amplitude control circuit or level shift circuit, further increasing power consumption and delay.

[0004] 2. In the design of high-speed SerDes drivers, driver reliability is an important indicator. Especially when the supply voltage is gradually increased to increase the swing, the voltage stress problem of transistors is particularly prominent:

[0005] 1) When the driver is turned off, the drain voltage of the output transistor is close to the supply voltage, while the gate voltage remains constant, which may cause excessive Vgd stress and thus cause oxide breakdown.

[0006] 2) Under high voltage and high frequency environments, the reliability of transistors is further reduced, and long-term performance degradation or failure may occur.

[0007] 3. The traditional three-state gate MUX has the function of signal multiplexing, and can select one of the multiple input signals as the output by selecting the control signal. However, this MUX mainly focuses on the selective multiplexing of signals, and its output driving capability is weak, which makes it difficult to directly meet the driving capability requirements of high-speed signal transmission. Especially in high-frequency scenarios, the signal swing at the output of the MUX is small and the noise resistance performance is poor, which increases the design complexity of the subsequent driver stage.

[0008] 4. The traditional CML driver is essentially a fixed differential signal amplification unit and lacks multiplexing function. In scenarios where multiple signal input selection is required, the CML driver usually requires an external MUX module for signal selection, which not only increases the circuit complexity, but also may introduce additional signal delays and switching glitches. Summary of the invention

[0009] In view of the deficiencies in the prior art, the present invention provides a high-speed, low-power differential driver based on a tri-state gate MUX and complementary CML. The present invention organically combines the signal selection function of the tri-state gate MUX with the high swing and high-speed driving capability of the CML driver to solve the technical problems of signal integrity, power consumption, output swing and reliability in the existing high-speed SerDes TX driver.

[0010] The technical solution of the present invention is: a high-speed low-power differential driver based on a three-state gate MUX and a complementary CML, comprising a three-state gate multiplexer MUX and a complementary CML driver; the output end of the three-state gate multiplexer MUX is connected to the input end of the complementary CML driver through a buffer circuit, the multiple input signals of the three-state gate multiplexer MUX are selected and multiplexed through a high-impedance state and a conduction state switching mechanism, and a high-speed differential signal is output; the complementary CML driver amplifies the high-speed differential signal into a high-speed large-swing differential signal, and drives an external load.

[0011] Preferably, the three-state gate multiplexer MUX comprises two groups of three-state gates arranged in parallel, and the output ends of the two groups of three-state gates are connected to complementary CML drivers through buffer circuits; the two groups of three-state gates of the three-state gate multiplexer MUX respectively control the input signal to enter the high-impedance state or the on state to realize the signal selection and multiplexing function.

[0012] Preferably, each group of three-state gates of the three-state gate multiplexer MUX includes an upper branch and a lower branch, and the upper branch and the lower branch are symmetrically arranged.

[0013] Preferably, the buffer circuit is composed of a plurality of inverters, the input end of the inverter is connected to the output of the three-state gate multiplexer MUX; the output end of the inverter is connected to the complementary CML driver.

[0014] Preferably, the complementary CML driver comprises a symmetrically arranged first branch and a second branch, wherein the first branch comprises transistors D1, D2, D5, and D6; and the second branch comprises transistors D3, D4, D7, and D8. The source of the transistor D1 is connected to the input power supply VDD; the gate of the transistor D1 is connected to the NAND gate of the first group of three-state gates of the three-state gate multiplexer MUX through an inverter; the NOR gate of the first group of three-state gates of the three-state gate multiplexer MUX is connected to the gate of the transistor D4 through an inverter; the drain of the transistor D1 is connected to the source of the transistor D2; the drain of the transistor D2 is connected to the drain of the transistor D3; the source of the transistor D3 is connected to the drain of the transistor D4; the source of the transistor D4 is grounded; and the gates of the transistors D2 and D3 are also connected to the gate voltages VC_P and VC_N;

[0015] The source of the transistor D5 is connected to the input power supply VDD; the gate of the transistor D5 is connected to the NAND gate of the second group of three-state gates of the three-state gate multiplexer MUX through an inverter; the NOR gate of the second group of three-state gates of the three-state gate multiplexer MUX is connected to the gate of the transistor D8 through an inverter; the drain of the transistor D5 is connected to the source of the transistor D6; the drain of the transistor D6 is connected to the drain of the transistor D7; the source of the transistor D7 is connected to the drain of the transistor D8; the source of the transistor D8 is grounded;

[0016] The gates of the transistors D6 and D7 are connected to gate voltages VC_P and VC_N respectively;

[0017] The drains of the transistors D2 and D6 and the drains of the transistors D3 and D7 are connected together and serve as the output terminals of the complementary CML driver.

[0018] Preferably, the output end of the complementary CML driver is further connected to a common mode power supply VCM, and the output end of the complementary CML driver is further connected to resistors R1 and R2.

[0019] Preferably, when transistors D1 and D5 are turned on, transistors D2 and D4 are turned off, or when transistors D1 and D5 are turned off, transistors D2 and D4 are turned on; by adjusting the gate DC voltage of the transistor, the gate voltage of D2, D3, D6, and D7 is finally fixed to adjust the driving state of the driver, thereby optimizing the voltage distribution and reducing voltage stress.

[0020] Preferably, the complementary CML driver input signal controls the conduction state of the differential pair to generate a high-swing, high-speed differential output signal.

[0021] The beneficial effects of the present invention are:

[0022] 1. The present invention organically combines the signal selection function of the three-state gate MUX with the high swing and high-speed driving capability of the CML driver to form an integrated structure with multiplexing and driving capabilities; it can reduce full-rate nodes, improve signal integrity, and suppress burr phenomena caused by switching delay mismatch; the differential signal swing is larger and the anti-noise performance is enhanced; it also reduces the circuit area required for the separate design of two modules, and significantly reduces the overall power consumption by reducing the number of inter-stage buffers;

[0023] 2. The present invention realizes efficient integration of signal multiplexing and driving capability by introducing a buffer circuit between the MUX output terminal and the CML driver input terminal; and the branches of the MUX and CML driver are both symmetrically designed to achieve high-swing output of high-speed signals, solve the timing competition in signal switching, and improve signal integrity;

[0024] 3. The present invention optimizes the signal switching matching between the MUX and the CML driver through a buffer circuit, thereby improving the overall signal integrity, suppressing the burr phenomenon caused by the mismatch of the switching delay, solving the respective limitations of the MUX and CML driver in the traditional technology, and providing an integrated differential driver solution suitable for high-speed communication;

[0025] 4. The present invention can reduce the voltage stress of the output transistor, especially the Vgd stress, and extend the life of the device; by reasonably selecting the current source and the load resistor, a larger differential swing is achieved, and the removal of the buffer stage significantly reduces the power consumption;

[0026] 5. The present invention achieves a larger differential signal swing output and enhances noise immunity through the efficient design of complementary CML drivers, and is suitable for high-frequency and high-speed application scenarios, such as PAM4 or NRZ signal transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a structural framework diagram of the driver of the present invention;

[0028] Figure 2 An application framework diagram for achieving balance of the driver of Embodiment 1 of the present invention;

[0029] Figure 3 This is an eye diagram simulation result diagram of Example 1 of the present invention in which the input data is 28 Gbps and the output data is 56 Gbps, but the data does not pass through the channel;

[0030] Figure 4 This is an eye diagram simulation result diagram of Example 1 of the present invention in which the input data is 28Gbps and the output data is 56Gbps, passing through the channel but without equalization;

[0031] Figure 5This is an eye diagram simulation result diagram of Example 1 of the present invention when the input data is 28 Gbps and the output data is 56 Gbps, passing through the channel with equalization turned on. DETAILED DESCRIPTION

[0032] The specific implementation of the present invention will be further described below in conjunction with the accompanying drawings:

[0033] Example 1

[0034] like Figure 1 As shown, this embodiment provides a high-speed, low-power differential driver based on a three-state gate MUX and complementary CML, including a three-state gate multiplexer MUX and a complementary CML driver; the output of the three-state gate multiplexer MUX is connected to the complementary CML driver through a buffer circuit, and the multiple input signals of the three-state gate multiplexer MUX are selected and multiplexed through a high-impedance state and a conduction state switching mechanism to output a high-speed differential signal; the complementary CML driver converts the high-speed differential signal into a high-speed, large-swing differential signal and drives an external load. This embodiment improves the driving capability of the output signal of the three-state gate multiplexer MUX by setting a buffer circuit.

[0035] As a preferred embodiment of the present invention, the three-state gate multiplexer MUX can realize two or more differential input signals. In the present embodiment, the three-state gate multiplexer MUX includes two groups of three-state gates arranged in parallel, and each group of three-state gates of the three-state gate multiplexer MUX includes an upper branch and a lower branch, and the upper branch and the lower branch are symmetrically arranged to further reduce signal competition. IN1 and F IN2 As the input ends of the two groups of three-state gates of the three-state gate multiplexer MUX.

[0036] Moreover, this embodiment adjusts the on-resistance of the tri-state gate to keep the on and off speeds consistent, thereby avoiding delay differences causing glitches. IN1 and F IN2 connected to the signal input end; the output ends of the two tri-state gates are connected to the complementary CML driver through a buffer circuit; the two tri-state gates of the tri-state gate multiplexer MUX respectively control the input signal to enter the high-impedance state or the on state to realize the signal selection and multiplexing function.

[0037] As a preferred embodiment of the present invention, the present embodiment optimizes the timing matching of signal switching by setting a buffer circuit between the three-state gate multiplexer MUX and the complementary CML driver. The present embodiment can control the transition time of signal switching within a shorter time. The buffer circuit is composed of a plurality of inverters, the input end of the inverter is connected to the output of the three-state gate multiplexer MUX; and the output end of the inverter is connected to the complementary CML driver.

[0038] As a preferred embodiment of the present invention, the complementary CML driver comprises a symmetrically arranged first branch and a second branch, wherein the first branch comprises transistors D1, D2, D5, and D6; the second branch comprises transistors D3, D4, D7, and D8; the source of the transistor D1 is connected to the input power supply VDD; the gate of the transistor D1 is connected to the NAND gate of the first group of three-state gates of the three-state gate multiplexer MUX through an inverter; the NOR gate of the first group of three-state gates of the three-state gate multiplexer MUX is connected to the gate of the transistor D4 through an inverter; the drain of the transistor D1 is connected to the source of the transistor D2; the drain of the transistor D2 is connected to the drain of the transistor D3; the source of the transistor D3 is connected to the drain of the transistor D4; the source of the transistor D4 is grounded; and the gates of the transistors D2 and D3 are also connected to the gate voltages VC_P and VC_N;

[0039] The source of the transistor D5 is connected to the input power supply VDD; the gate of the transistor D5 is connected to the NAND gate of the second group of three-state gates of the three-state gate multiplexer MUX through an inverter; the NOR gate of the second group of three-state gates of the three-state gate multiplexer MUX is connected to the gate of the transistor D8 through an inverter; the drain of the transistor D5 is connected to the source of the transistor D6; the drain of the transistor D6 is connected to the drain of the transistor D7; the source of the transistor D7 is connected to the drain of the transistor D8; the source of the transistor D8 is grounded;

[0040] The gates of the transistors D6 and D7 are connected to gate voltages VC_P and VC_N respectively;

[0041] The drains of the transistors D2 and D6 and the drains of the transistors D3 and D7 are connected together and serve as the output terminals of the complementary CML driver.

[0042] As a preferred embodiment of the present invention, the output end of the complementary CML driver is further connected to a common mode power supply VCM, and the output end of the complementary CML driver is further connected to resistors R1 and R2.

[0043] As a preferred embodiment of the present invention, when transistors D1 and D5 are turned on, transistors D2 and D4 are turned off, or when transistors D1 and D5 are turned off, transistors D2 and D4 are turned on; by adjusting the gate DC voltage of the transistors, the gate voltage of D2, D3, D6, and D7 is finally fixed, and the driving state is adjusted by controlling the input power supply VDD, thereby optimizing the voltage distribution and reducing the voltage stress.

[0044] As a preferred embodiment of the present invention, the complementary CML driver input signal controls the conduction state of the differential pair to generate a high-swing, high-speed differential output signal.

[0045] In this embodiment, CK / CKB is the clock input to the tri-state gate multiplexer MUX.

[0046] In this embodiment, Figure 2 As shown, this embodiment can realize 3tap (Pre Tap, Main Tap, Post Tap) FFE equalization, wherein the Main Tap adopts a Tailless CML structure, while the Pre Tap and Post Tap adopt a Cascode CML structure, which has a wide tuning range and high output resistance, and can achieve a larger intensity control range by adjusting its bias current source. In this embodiment, Id is a CML tail current source.

[0047] like Figure 3 As shown, this embodiment can output 56 Gbps data and drive a certain load by inputting 28 Gbps data, and its function can be proved to be normal by observing the eye diagram.

[0048] like Figure 4 As shown in the figure, the output signal has passed a certain channel attenuation (6dB), and the eye diagram can be used to determine that the signal integrity has been severely damaged. Figure 5 The eye diagram after equalization shows that this embodiment has a good equalization effect.

[0049] Example 2

[0050] In this embodiment, the buffer circuit can be deleted on the basis of the embodiment 1, and the output end of the three-state gate multiplexer MUX is directly connected to the input end of the complementary CML driver. In this embodiment, the structure of the three-state gate multiplexer MUX and the complementary CML driver is consistent with that of the embodiment 1. This embodiment is suitable for scenarios with low signal integrity requirements, such as medium and low speed signal multiplexing.

[0051] At the same time, this embodiment can also be expanded to more input signals according to needs, such as 4 or 8 channels; after expansion, the selection logic of the three-state gate can be generated by a simple logic circuit, and can also be combined with a decoder design to reduce the number of control signals.

[0052] The above embodiments and descriptions are only for illustrating the principles and best embodiments of the present invention. Without departing from the spirit and scope of the present invention, the present invention may be subject to various changes and improvements, all of which fall within the scope of the present invention to be protected.

Claims

1. A high-speed, low-power differential driver based on tri-state gate MUX and complementary CML, characterized in that: The invention comprises a three-state gate multiplexer MUX and a complementary CML driver; the output end of the three-state gate multiplexer MUX is connected to the input end of the complementary CML driver through a buffer circuit; the multiple input signals of the three-state gate multiplexer MUX are selected and multiplexed through a high-impedance state and a conduction state switching mechanism, and a high-speed differential signal is output; the complementary CML driver converts the high-speed differential signal into a high-speed large-swing differential signal and drives an external load.

2. The high-speed, low-power differential driver based on tri-state gate MUX and complementary CML according to claim 1, characterized in that: The three-state gate multiplexer MUX comprises two groups of three-state gates arranged in parallel, and the output ends of the two groups of three-state gates are connected to complementary CML drivers through buffer circuits; the two groups of three-state gates of the three-state gate multiplexer MUX respectively control the input signal to enter the high-impedance state or the on state to realize the signal selection and multiplexing function.

3. The high-speed, low-power differential driver based on tri-state gate MUX and complementary CML according to claim 2, characterized in that: Each group of three-state gates of the three-state gate multiplexer MUX comprises an upper branch and a lower branch, and the upper branch and the lower branch are symmetrically arranged.

4. The high-speed, low-power differential driver based on tri-state gate MUX and complementary CML according to claim 2, characterized in that: The buffer circuit is composed of a plurality of inverters, the input end of the inverter is connected to the output end of the three-state gate multiplexer MUX; the output end of the inverter is connected to the input end of the complementary CML driver.

5. The high-speed, low-power differential driver based on tri-state gate MUX and complementary CML according to claim 4, characterized in that: The complementary CML driver comprises a first branch and a second branch which are symmetrically arranged, wherein the first branch comprises transistors D1, D2, D5 and D6; the second branch comprises transistors D3, D4, D7 and D8; the gate of the transistor D1 is connected to the NAND gate of the first group of three-state gates of the three-state gate multiplexer MUX through an inverter; the NOR gate of the first group of three-state gates of the three-state gate multiplexer MUX is connected to the gate of the transistor D4 through an inverter; the drain of the transistor D1 is connected to the source of the transistor D2; the drain of the transistor D2 is connected to the drain of the transistor D3; the source of the transistor D3 is connected to the drain of the transistor D4; the source of the transistor D4 is grounded; The gate of the transistor D5 is connected to the NAND gate of the second group of three-state gates of the three-state gate multiplexer MUX through an inverter; the NOR gate of the second group of three-state gates of the three-state gate multiplexer MUX is connected to the gate of the transistor D8 through an inverter; the drain of the transistor D5 is connected to the source of the transistor D6; the drain of the transistor D6 is connected to the drain of the transistor D7; the source of the transistor D7 is connected to the drain of the transistor D8; the source of the transistor D8 is grounded.

6. The high-speed, low-power differential driver based on tri-state gate MUX and complementary CML according to claim 5, characterized in that: The sources of the transistor D1 and the transistor D5 are connected to the input power supply VDD.

7. The high-speed, low-power differential driver based on tri-state gate MUX and complementary CML according to claim 5, characterized in that: The gates of the transistors D2, D3, D6, and D7 are also connected to gate voltages VC_P and VC_N.

8. The high-speed, low-power differential driver based on tri-state gate MUX and complementary CML according to claim 7, characterized in that: The drains of the transistors D2 and D6 and the drains of the transistors D3 and D7 are connected together and serve as the output terminals of the complementary CML driver.

9. The high-speed, low-power differential driver based on tri-state gate MUX and complementary CML according to claim 8, characterized in that: When transistors D1 and D5 are turned on, transistors D2 and D4 are turned off, or when transistors D1 and D5 are turned off, transistors D2 and D4 are turned on; by adjusting the gate DC voltage of the transistor, the gate voltage of D2, D3, D6, and D7 is finally fixed to adjust the driving state of the driver, thereby optimizing the voltage distribution and reducing the voltage stress.

10. The high-speed, low-power differential driver based on tri-state gate MUX and complementary CML according to claim 5, characterized in that: The complementary CML driver input signal controls the conduction state of the differential pair to generate a high-swing, high-speed differential output signal.

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