Multi-core processor module, starting method and interconnection system and method

Abstract

The invention discloses a multi-core processor module, a starting method and an interconnection system and method, and relates to the technical field of processors, the multi-core processor module comprises M multi-core DIEs, and each DIE is connected with a channel signal selection module through a QSPI interface; the external FLASH chip is used for storing BIOS information started by DIE; the external FLASH chip is connected with the channel signal selection module through a QSPI interface. The CPLD is used for generating an input selection signal and an interaction signal between the CPLD and the multi-core processor module; the channel signal selection module is also connected with the CPLD and is used for selecting communication of different DIEs according to received input selection signals so as to read BIOS information in an external FLASH chip; according to the multi-core processor, the multiple DIEs of the multi-core processor and the multiplexer share one external FLASH chip through the QSPI interface, so that the hardware cost is reduced, and the system complexity and cost are reduced.

Description

Technical Field

[0001] The present invention relates to the field of processors, and in particular to a multi-chip processor module and a startup method and an interconnection system and method. Background Art

[0002] The development of multi-chip technology in domestic processors has gradually emerged in recent years as chip manufacturing technology approaches physical limits in order to continue to improve performance and integration. Multi-chip processors can achieve higher performance and flexibility by integrating multiple small chips with different functions into one large chip. The application of this technology in domestic processors can be traced back to the period of rapid development of domestic processor technology in the past decade.

[0003] In the early verification and tuning stage of the current domestic multi-chip processor, taking four identical DIEs as an example to synthesize a CPU, the hardware external interface of each DIE is basically the same, and a QSPI interface controller is integrated to load off-chip firmware information. Since the QSPI interface function of each DIE needs to be fully verified, each DIE needs to be connected to a separate QSPIFLASH.

[0004] In addition, when designing a multi-chip processor verification board, due to screening and structural limitations, a verification board can only hold a single multi-chip processor, and most of the previous domestic processors are not multi-chip architectures, so there is no need to test and verify the interconnection performance between the chips.

[0005] So the current problems are: 1) Complexity and cost: Connecting each DIE to an external QSPI FLASH will undoubtedly increase the hardware cost.

[0006] 2) Increased debugging difficulty: Each DIE and its external FLASH need to be debugged and tested separately, which increases the complexity of development and verification. In a multi-DIE processor system, debugging and problem location become more difficult when the problem involves the interaction between processors.

[0007] The background description provided herein is for the purpose of generally presenting the context of the present application. Unless otherwise indicated herein, the materials described in this section are not prior art to the claims of this application and are not admitted to be prior art by inclusion in this section. Summary of the invention

[0008] In view of the above technical problems in the related art, the present invention proposes a multi-chip processor module and a startup method and an interconnection system and method.

[0009] In order to achieve the above-mentioned invention object, the present invention adopts the following technical scheme: In a first aspect, the present invention provides a multi-chip processor module, the multi-chip processor module comprising: M DIEs, a channel signal selection module, a CPLD and an external FLASH chip: Each DIE is provided with a QSPI interface; each DIE is connected to a channel signal selection module via the QSPI interface; The external FLASH chip is used to store the BIOS information started by the DIE; the external FLASH chip is connected to the channel signal selection module through the QSPI interface; The CPLD is used to generate an input selection signal and an interaction signal between the CPLD and the DIE; The channel signal selection module is also connected to the CPLD and is used to select the connectivity of different DIEs according to the received input selection signal, so as to read the BIOS information in the external FLASH chip.

[0010] Specifically, the channel signal selection module includes N multiplexers, which are connected to each DIE and select different DIEs according to different input selection signals, thereby controlling the DIEs to read the BIOS information in the external FLASH chip in sequence.

[0011] Specifically, M=4, N=3, and the multiplexer is a dual-channel four-to-one switch chip.

[0012] Specifically, each dual-channel four-to-one switch chip is used to control the input selection of four DIEs of the multi-chip processor module according to two input selection signals; The dual-channel four-select-one switch chip includes an X channel and a Y channel, each channel includes four data input signals and one data output signal; the X channel data input signal is X0&X1&X2&X3, and the data output signal is a first output signal X; the Y channel data input signal is Y0&Y1&Y2&Y3, and the data output signal is a second output signal Y; the input selection signal includes a first input selection signal A and a second input selection signal B.

[0013] Specifically, the method of selecting different DIEs according to different input selection signals, thereby controlling the DIEs to sequentially read the BIOS information in the external FLASH chip is as follows: Divide the 6 signals of QSPI into three groups, each group has two signals, and each group of signals corresponds to a dual-channel four-to-one switch chip in the channel signal selection module; the 6 signals of QSPI include a clock signal CLK, a chip selection signal CS and 4 data bit signals DATA[0:3]; The CPLD controls the input of the dual-channel four-to-one switch chip by controlling the values ​​of the first input selection signal A and the second input selection signal B, and determines which DIE's QSPI interface signal is connected to the external FLASH chip.

[0014] Specifically, the CPLD controls the input of the dual-channel four-to-one switch chip by controlling the values ​​of the first input selection signal A and the second input selection signal B, and determines which DIE QSPI interface signal is connected to the external FLASH chip: When A=0, B=0, DIE0 is connected to the external FLASH chip; When A=1, B=0, DIE1 is connected to the external FLASH chip; When A=0, B=1, DIE2 is connected to the external FLASH chip; When A=1, B=1, DIE3 is connected to the external FLASH chip.

[0015] In a second aspect, the present invention provides a method for starting a multi-core processor module, based on a multi-core processor module described in any one of the first aspects, wherein the multi-core processor module includes DIE0, DIE1, DIE2 and DIE3; the interaction signals between the CPLD and the multi-core processor module include: CRU_FLASH_DONE signal, D2D_EN signal, CRU_D2D_GOOD signal, POR_N signal, RST_N signal; and the method includes the following steps: S1, the system is powered on, CPLD sets DIE3_RST_N and DIE3_POR_N high, and sets the first input selection signal A to 1 and the second input selection signal B to 1, DIE3 reads the BIOS information on the external FLASH chip; After S2 and DIE3 finish reading the BIOS information, they set the DIE3_CRU_FLASH_DONE signal to 1 and pass it to the CPLD; S3. After CPLD detects that the DIE3_CRU_FLASH_DONE signal is 1, it sets DIE2_RST_N and DIE2_POR_N high, sets the first input selection signal A to 0 and the second input selection signal B to 1, and DIE2 reads the BIOS information on the external FLASH chip; S4. After DIE2 finishes reading the BIOS information, it sets the DIE2_CRU_FLASH_DONE signal to 1 and passes it to the CPLD. S5. After CPLD detects that the DIE2_CRU_FLASH_DONE signal is 1, it sets DIE1_RST_N and DIE1_POR_N high, sets the first input selection signal A to 1 and the second input selection signal B to 0, and DIE1 reads the BIOS information on the external FLASH chip; S6. After DIE1 finishes reading the BIOS information, it sets the DIE1_CRU_FLASH_DONE signal to 1 and passes it to the CPLD. S7. After CPLD detects that the DIE1_CRU_FLASH_DONE signal is 1, it sets DIE0_RST_N and DIE0_POR_N high, sets the first input selection signal A to 0 and the second input selection signal B to 0, and DIE0 reads the BIOS information on the external FLASH chip; S8. After DIE0 finishes reading the BIOS information, it sets the DIE0_CRU_FLASH_DONE signal to 1 and passes it to CPLD, and the startup is completed. S9. After all DIEs of the multi-core processor module are started, the training between DIEs begins; In the steps, DIE3_RST_N represents the CRU_FLASH_DONE signal of DIE3, DIE2_RST_N represents the CRU_FLASH_DONE signal of DIE2, and the other signals in the steps are the interaction signals between CPLD and multi-chip processor module, and so on.

[0016] In a third aspect, the present invention provides a multi-chip processor module interconnection system, comprising two main boards, namely a first main board and a second main board, both main boards comprising a plurality of MCIO connectors and the multi-chip processor module as described in the first aspect; the multi-chip processor module comprises a CPLD; The two main boards are connected using an MCIO connector, and the DIE of the multi-core processor module of the first main board is interconnected with the DIE of the multi-core processor module of the second main board in a one-to-one correspondence; the multi-core processor module of the first main board and the multi-core processor module of the second main board are interconnected with C2C high-speed signals and C2C synchronization and control signals; The C2C high-speed signal includes a TX signal and a RX signal; The MCIO connector includes side A and side B, where side A is connected to the RX signal of the multi-chip processor module, and side B is connected to the TX signal of the multi-chip processor module. The MCIO cable realizes the interconnection mode of AB and BA, and realizes the interconnection of TX signal & RX signal between multi-chip processor modules; The C2C synchronization and control signal includes a C2C synchronization signal; M_C2C_TX_EN for sending and S_C2C_RX_EN for receiving are C2C synchronization signals; The M_C2C_TX_EN sent by the CPLD on the first mainboard and the S_C2C_RX_EN received by the CPLD on the first mainboard are respectively connected to the MCIO connector of the first mainboard; The M_C2C_TX_EN sent by the CPLD on the second mainboard and the S_C2C_RX_EN received by the CPLD on the second mainboard are respectively connected to the MCIO connector of the second mainboard; The first mainboard is synchronized with the second mainboard via a C2C synchronization signal.

[0017] Specifically, the C2C synchronization and control signal also includes a C2C control signal; The C2C control signal includes: M_PWR_EN: The power enable signal sent by the first mainboard is received by the second mainboard and transmitted to the S_PWR_EN signal, so that the power of the first mainboard and the second mainboard can be powered on and off synchronously; M_RST_EN: The reset signal sent by the first mainboard is received by the second mainboard and transmitted to the S_RST_EN signal, so that the first mainboard and the second mainboard can be reset synchronously; S_PWR_DONE: The power-on completion signal sent by the second mainboard is received by the first mainboard and transmitted to the S_PWR_DONE signal; the power-on completion signal of the first mainboard and the second mainboard is synchronized to ensure the synchronization of the remaining timing; S_C2C_GOOD: The C2C handshake completion signal sent by the second mainboard is received by the first mainboard and transmitted to the S_C2C_GOOD signal; the handshake completion signals of the first and second mainboards are synchronized to ensure the synchronization of the remaining timing.

[0018] Specifically, the mainboard is provided with an external DIP switch, which is used to distinguish the master-slave relationship of the mainboard by configuring the external DIP switch.

[0019] In a fourth aspect, the present invention provides a method for interconnecting a multi-core processor module, based on a multi-core processor module interconnection system described in any one of the third aspects, after the multi-core processor module in the mainboard completes the reading of an external FLASH chip and the DIE TO DIE Training of four DIEs inside the processor, the C2C high-speed signal and the C2C synchronization and control signal transmitted through the MCIO connector and the MCIO cable complete the C2C handshake between the multi-core processor modules.

[0020] Specifically, the C2C high-speed signal and the C2C synchronization and control signal transmitted through the MCIO connector and the MCIO cable complete the C2C handshake between the multi-core processor modules. Specifically includes: the C2C synchronization signal and the C2C high-speed signal are transmitted between the first mainboard and the second mainboard through the MCIO high-speed connector and the MCIO high-speed cable, and when M_C2C_TX_EN&S_C2C_RX_EN=1, the C2C high-speed signal handshake is performed between the multi-core processors of the first mainboard and the second mainboard.

[0021] The multi-chip processor module provided by the present invention allows multiple DIEs processed by the multi-chip to share an external FLASH chip through a QSPI interface and a multiplexer, thereby reducing hardware costs, system complexity and costs; The invention provides a multi-chip processor module startup method, which uses CPLD control signals to realize the polling process of multiple DIEs on QSPI FLASH, so as to achieve the effect of starting DIEs in sequence, and is helpful for the synchronization of multiple DIEs and firmware maintenance at the software level; The present invention proposes a multi-core processor module interconnection system, which realizes the synchronization of power timing between two multi-core processors and the synchronization of C2C interconnection timing through the synchronization control signal on the MCIO cable, thereby ensuring the stability and performance of the system and realizing the synchronization between the multi-core processor modules: and through the standard MCIO interface and signal definition, when a single multi-core processor module verification board does not need to be interconnected, the MCIO interface on the verification board can be connected to a standard PCIE device or board through a cable, enriching the application scenarios of the verification board, providing support for subsequent design, and improving the design flexibility.

[0022] In addition, through the MCIO standard interface and cable, the meaning of some sideband signals is customized, and the interconnection of high-speed signals and key synchronization signals between multi-chip processor modules is realized, which helps to verify the interconnection and synchronization between multi-chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0024] Figure 1 is a schematic diagram of a multi-chip processor module structure provided according to an embodiment of the present invention; Figure 2 It is a schematic diagram of signals for interaction between a CPLD and a multi-chip processor module according to an embodiment of the present invention; Figure 3 is a schematic diagram of a multi-core processor module startup method provided according to an embodiment of the present invention; Figure 4 It is a schematic diagram of the process of using the QSPI interface of four DIEs to read an external FLASH chip according to an embodiment of the present invention; Figure 5 is a schematic diagram of a multi-chip processor module interconnection system provided according to an embodiment of the present invention; Figure 6 It is a schematic diagram of a high-speed signal connection method between multi-chip processor modules provided in an embodiment of the present invention; Figure 7 is a schematic diagram of the interconnection of sideband signals at other positions of the MCIO provided by an embodiment of the present invention; Figure 8 4 is a schematic diagram of a C2C handshake process between multi-chip processor modules provided according to an embodiment of the present invention. DETAILED DESCRIPTION

[0025] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present invention.

[0026] In the description of the present invention, if there is a description of first, second, etc., it is only for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0027] In the description of the present invention, it should be understood that descriptions involving orientation, such as orientation or positional relationship indicated as up, down, etc., are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0028] In the description of the present invention, it should be noted that, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in the present invention in combination with the specific content of the technical solution.

[0029] Embodiment 1 refer to Figure 1This embodiment proposes a multi-chip processor module, which enables multiple DIEs of the multi-chip processor to share an external FLASH chip, and reads BIOS information from the external FLASH chip by polling, thereby reducing hardware costs, thereby solving the problem of high hardware costs caused by each DIE of the current multi-chip server being connected to an external FLASH chip separately; The multi-chip processor module includes M DIEs, a channel signal selection module, a CPLD and an external FLASH chip; Each DIE is provided with a QSPI interface; each DIE is connected to a channel signal selection module via the QSPI interface; The number of DIEs is determined when the multi-chip processor package is designed.

[0030] The external FLASH chip is used to store the BIOS information started by the DIE; the external FLASH chip is connected to the channel signal selection module through the QSPI interface; In this example, the external FLASH chip is a QSPI FLASH chip; It is understandable that the external FLASH chip can also be used to store other configuration information or firmware. This is a prior art and will not be described in detail here.

[0031] For the CPU, the CPU DIE is the basic unit that constitutes the CPU. One or more CPU DIEs can be packaged to form a CPU package. In this context, the CPU DIE is referred to as DIE.

[0032] QSPI is the abbreviation of Quad SPI, which means 6-wire SPI, including 6 signals, including a clock signal CLK, a chip select signal CS and 4 data bit signals DATA[0:3]. This is the prior art and will not be described here.

[0033] BIOS (Basic Input Output System) is a startup program that cannot be tampered with and is engraved on the motherboard ROM chip. BIOS is responsible for calculating the system self-test program (POST, Power On Self Test) and the system self-starting program, so it is the first program after the computer system starts. Due to its non-tamperability, the program is stored in the ROM chip and can still maintain the original settings after power failure.

[0034] CPLD (Complex Programmable Logic Device) is a programmable logic device that contains multiple logic units and programmable interconnection resources. It is usually used in servers for logic configuration and signal processing to ensure stable operation of the system.

[0035] CPLD is used to generate input selection signals and interaction signals between CPLD and multi-chip processor module; The CPLD and multi-chip processor module interaction signals include: CRU_FLASH_DONE signal: DIE completes reading FLASH information, and is output by DIE to CPLD.

[0036] D2D_EN signal: Training enable signal between DIE and DIE, output by CPLD to DIE.

[0037] CRU_D2D_GOOD signal: Training completion signal between DIEs, output by DIE to CPLD.

[0038] POR_N signal: power-on reset signal of DIE, output by CPLD to DIE.

[0039] RST_N signal: global reset signal of DIE, output by CPLD to DIE.

[0040] The channel signal selection module is also connected to the CPLD and is used to select the connectivity of different DIEs according to the received input selection signal, so as to read the BIOS information in the external FLASH chip.

[0041] Specifically, the channel signal selection module includes N multiplexers, which are connected to each DIE and select different DIEs according to different input selection signals, thereby controlling the DIEs to read the BIOS information in the external FLASH chip in sequence.

[0042] Specifically, the multi-chip processor module in this embodiment includes 4 DIEs, namely: DIE0, DIE1, DIE2, DIE3; the channel signal selection module includes 3 multiplexers, and the multiplexer is a dual-channel four-to-one switch chip; The dual-channel four-to-one switch chip includes an X channel and a Y channel, and each channel includes four data input signals and one data output signal. The X channel data input signal is X0&X1&X2&X3, and the data output signal is the first output signal X; the Y channel data input signal is Y0&Y1&Y2&Y3, and the data output signal is the second output signal Y, that is, the dual-channel four-to-one switch chip has two output results, including the first output signal X and the second output signal Y.

[0043] Divide the six signals of QSPI into three groups, each with two signals; the three groups of signals correspond to three dual-channel four-to-one switch chips, that is, each group of signals corresponds to a dual-channel four-to-one switch chip in the channel signal selection module; Specifically, the QSPI bus has 6 signal lines, which are divided into three groups, each containing two signals. The three groups of signals are: The first group: clock signal CLK and chip select signal CS; The second group: the first data bit signal DATA[0] and the second data bit signal DATA[1]; The third group: the third data bit signal DATA[2] and the fourth data bit signal DATA[3]; Three dual-channel four-to-one switch chips are used to control the signals of the QSPI bus. The dual-channel four-to-one switch chips are referred to as switch chips below: The first switch chip controls the clock signal CLK and the chip select signal CS; The second switch chip controls the first data bit signal DATA[0] and the second data bit signal DATA[1]; The third switch chip controls the third data bit signal DATA[2] and the fourth data bit signal DATA[3]; In this embodiment, the input selection signal includes a first input selection signal A and a second input selection signal B; The dual-channel four-to-one switch chip receives two input selection signals including a first input selection signal A and a second input selection signal B for selecting a data output signal; When A=0, B=0, X=X0, Y=Y0; When A=1, B=0, X=X1, Y=Y1; When A=0, B=1, X=X2, Y=Y2; When A=1,B=1,X=X3,Y=Y3.

[0044] Each dual-channel four-to-one switch chip is used to control the input selection of four DIEs of the multi-chip processor module according to two input selection signals; The CPLD controls the input of the dual-channel four-to-one switch chip by controlling the values ​​of the first input selection signal A and the second input selection signal B, thereby determining which DIE's QSPI interface signal is connected to the QSPI FLASH chip. Specifically, When A=0, B=0, DIE0 is connected to the external FLASH chip; When A=1, B=0, DIE1 is connected to the external FLASH chip; When A=0, B=1, DIE2 is connected to the external FLASH chip; When A=1, B=1, DIE3 is connected to the external FLASH chip.

[0045] In this way, each DIE can access the QSPI FLASH chip independently to read the BIOS information without interfering with each other.

[0046] Preferably, the dual-channel four-to-one switch chip in this embodiment is the SGM84782 chip of Shengbang Micro Corporation.

[0047] The present embodiment provides a startup system for a multi-chip processor module, which allows multiple DIEs processed by the multi-chip to share an external FLASH chip through a QSPI interface and a multiplexer, thereby reducing hardware costs and system complexity and costs.

[0048] Embodiment 2 refer to Figure 3 , Figure 4 This embodiment provides a method for starting a multi-core processor module. Based on the multi-core processor module in the first embodiment, the multi-core processor module includes DIE0, DIE1, DIE2 and DIE3; the interaction signals between the CPLD and the multi-core processor module include: CRU_FLASH_DONE signal, D2D_EN signal, CRU_D2D_GOOD signal, POR_N signal, RST_N signal; the method includes the following steps: S1, the system is powered on, CPLD sets DIE3_RST_N and DIE3_POR_N high, and sets the first input selection signal A to 1 and the second input selection signal B to 1, DIE3 reads the BIOS information on the external FLASH chip; From the first embodiment, it can be seen that the interaction signal between the CPLD and the multi-chip processor module includes: CRU_FLASH_DONE signal: DIE completes reading FLASH information, and is output by DIE to CPLD.

[0049] D2D_EN signal: Training enable signal between DIE and DIE, output by CPLD to DIE.

[0050] CRU_D2D_GOOD signal: Training completion signal between DIEs, output by DIE to CPLD.

[0051] POR_N signal: power-on reset signal of DIE, output by CPLD to DIE.

[0052] RST_N signal: global reset signal of DIE, output by CPLD to DIE.

[0053] When the system is powered on, the CPLD and the multi-chip processor module start to supply power; after the CPLD is powered on, it executes the internal initialization program, prepares the control signals and manages the startup process. The CPLD sets the global reset signal and the power-on reset signal of DIE3 high to ensure that DIE3 is in a known state and ready to start.

[0054] For the sake of easy distinction, this embodiment uses the naming method of "DIE name_interaction signal" to facilitate identification of which DIE the interaction signal is input into; for example: The CRU_FLASH_DONE signal of DIE3 is DIE3_CRU_FLASH_DONE; the CRU_FLASH_DONE signal of DIE2 is DIE2_CRU_FLASH_DONE; The POR_N signal of DIE3 is DIE3_POR_N; the POR_N signal of DIE2 is DIE2_POR_N; The RST_N signal of DIE3 is DIE3_RST_N; the RST_N signal of DIE2 is DIE2_RST_N; The D2D_EN signal of DIE3 is DIE3_D2D_EN; the RST_N signal of DIE2 is DIE2_D2D_EN; The CRU_D2D_GOO signal of DIE3 is DIE3_CRU_D2D_GOO; the RST_N signal of DIE2 is DIE2_CRU_D2D_GOO; The naming of DIE1 and DIE0 interaction signals with multi-chip processor modules is similar. If there are more DIEs, the above naming rules can also be used.

[0055] After S2 and DIE3 finish reading the BIOS information, they set the DIE3_CRU_FLASH_DONE signal to 1 and pass it to the CPLD; S3. After CPLD detects that the DIE3_CRU_FLASH_DONE signal is 1, it sets DIE2_RST_N and DIE2_POR_N high, sets the first input selection signal A to 0 and the second input selection signal B to 1, and DIE2 reads the BIOS information on the external FLASH chip; S4. After DIE2 finishes reading the BIOS information, it sets the DIE2_CRU_FLASH_DONE signal to 1 and passes it to the CPLD. S5. After CPLD detects that the DIE2_CRU_FLASH_DONE signal is 1, it sets DIE1_RST_N and DIE1_POR_N high, sets the first input selection signal A to 1 and the second input selection signal B to 0, and DIE1 reads the BIOS information on the external FLASH chip; S6. After DIE1 finishes reading the BIOS information, it sets the DIE1_CRU_FLASH_DONE signal to 1 and passes it to the CPLD. S7. After CPLD detects that the DIE1_CRU_FLASH_DONE signal is 1, it sets DIE0_RST_N and DIE0_POR_N high, sets the first input selection signal A to 0 and the second input selection signal B to 0, and DIE0 reads the BIOS information on the external FLASH chip; S8. After DIE0 finishes reading the BIOS information, it sets the DIE0_CRU_FLASH_DONE signal to 1 and passes it to CPLD, and the startup is completed. S9. After all DIEs of the multi-chip processor module are started, training between DIEs begins.

[0056] After all DIEs finish reading the BIOS information in the order of DIE3-DIE2-DIE1-DIE0, the CPLD confirms that all DIEs have successfully loaded the BIOS.

[0057] After all DIE BIOS are loaded, the system is ready to perform DIE TO DIE Training, which is to establish communication links and data transmission paths between DIEs.

[0058] This embodiment does not limit the startup sequence of the DIEs, and the startup sequence of the DIEs can be adjusted according to actual needs, and the adjusted startup sequence is included in the protection list.

[0059] This embodiment uses a solution in which the QSPI interfaces of multiple DIEs share an external FLASH chip, which reduces the hardware cost. At the same time, the CPLD control signal is used to realize the polling process of multiple DIEs on the QSPI FLASH, so as to achieve the effect of starting the DIEs in sequence, which is helpful for the synchronization of multiple DIEs and firmware maintenance at the software level.

[0060] Embodiment 3 refer to Figure 5This embodiment provides a multi-core processor module interconnection system, based on the startup system of the multi-core processor module in the first embodiment, including two main boards, namely a first main board and a second main board, both main boards include the multi-core processor module in the first embodiment and a plurality of MCIO connectors; the multi-core processor module of the first main board is interconnected with the multi-core processor module of the second main board by C2C high-speed signals and C2C synchronization and control signals; Specifically, the multi-chip processor module includes M DIEs, each DIE also includes a C2C high-speed signal; the multi-chip processor module includes a CPLD; each DIE of the two main boards is connected with an MCIO connector, and the DIEs of the multi-chip processor module of the first main board are interconnected with the DIEs of the multi-chip processor module of the second main board in a one-to-one correspondence; the C2C synchronization and control signals are interconnected between the CPLD of the multi-chip processor module of the first main board and the CPLD of the multi-chip processor module of the second main board.

[0061] The C2C high-speed signal is a group of x16 high-speed signals, which are formed by two MCIO x8 connectors; the C2C high-speed signals interconnecting the multi-chip processor modules include the C2C high-speed signals of all DIEs.

[0062] The C2C high-speed signal includes an RX signal and a TX signal; Specifically, each DIE of the two main boards is connected with a MCIO connector respectively, and the DIE of the multi-core processor module of the first main board is interconnected with the DIE of the multi-core processor module of the second main board in a one-to-one correspondence. Specifically, each DIE is connected with two MCIOx8 connectors respectively, and the MCIO connector of the DIE of the multi-core processor module of the first main board is connected with the MCIO connector of the DIE at the same position of the multi-core processor module of the second main board through an MCIO cable; the MCIO cable is an MCIO high-speed cable.

[0063] It can be understood that the MCIO connector provides an MCIO interface for connecting different devices including the MCIO interface.

[0064] This embodiment uses standard MCIO interface connectors and cables to connect high-speed signals and control signals required for interconnecting multi-chip processor modules, thereby realizing interconnection means when the multi-chip processor modules are located on different motherboards.

[0065] This embodiment uses two verification motherboards, namely the first motherboard and the second motherboard. The first motherboard and the second motherboard are designed exactly the same, each containing a multi-chip processor module and a number of MCIO connector interfaces; the multi-chip processor module contains a CPLD.

[0066] The multi-core processor modules are mainly interconnected by C2C high-speed signals, and the CPLDs of the multi-core processor modules of the two main boards are mainly interconnected by C2C synchronization and control signals.

[0067] Since the C2C high-speed signals interconnecting each DIE are currently a group of x16 signals, two standard MCIOx8 connectors will be used to form a group of x16 high-speed signals.

[0068] x16 signal channels: This means that 16 independent signal channels are required between each processor chip for data transmission. These channels can be high-speed signal lines for data, addresses, control signals, etc.

[0069] MCIO x8 connector: There are several different models of MCIO connectors, among which the x8 model connector can provide 8 signal channels. Therefore, in order to build a complete x16 signal channel, two such x8 connectors are required.

[0070] Therefore, by combining two MCIO x8 connectors, a connection with 16 signal channels can be formed to meet the high-speed signal interconnection requirements between each DIE. The two connectors will be responsible for the first 8 and last 8 signal channels in the x16 signal channel respectively, and jointly complete the data transmission.

[0071] refer to Figure 5 Take four identical DIEs synthesizing a multi-core processor module as an example: DIE0-DIE0, DIE1-DIE1, DIE2-DIE2, and DIE3-DIE3 of two multi-core processor modules are connected through their corresponding MCIO connectors using MCIO cables.

[0072] The MCIO connector includes side A and side B, wherein side A is connected to the RX signal of the C2C high-speed signal of the multi-chip processor module, and side B is connected to the TX signal of the C2C high-speed signal of the multi-chip processor module. The MCIO cable realizes the interconnection mode of AB, BA, realizes the interconnection of high-speed signal TX&RX signals between multi-chip processor modules, thereby realizing the interconnection of C2C high-speed signals of multi-chip processor modules.

[0073] The RX signal is the receiving end signal of the processor C2C high-speed signal, which is used to receive data or commands from other devices; The TX signal is the transmitter signal of the processor C2C high-speed signal, which is used to send data or commands to other devices.

[0074] The MCIO connector is a standard MCIO high-speed connector, and the MCIO cable is a standard MCIO high-speed cable; the standard MCIO high-speed cable and MCIO high-speed connector specifications define and distinguish between the A side and the B side.

[0075] In the case of interconnection of multi-chip processor modules in this embodiment, the RX signal is used to receive data from another multi-chip processor module, and the TX signal is used to send data to another multi-chip processor module.

[0076] Reference for high-speed signal connection between multi-core processor modules of two motherboards Figure 5 As shown, the two main boards are the first main board and the second main board. The first main board and the second main board are designed exactly the same, each including a multi-chip processor module and a plurality of MCIO connectors; the multi-chip processor module includes a CPLD.

[0077] The C2C synchronization and control signals include a C2C synchronization signal and a C2C control signal; M_C2C_TX_EN for sending and S_C2C_RX_EN for receiving are C2C synchronization signals; The M_C2C_TX_EN sent by the CPLD on the first mainboard and the S_C2C_RX_EN received by the CPLD on the first mainboard are respectively connected to the MCIO connector of the first mainboard; The M_C2C_TX_EN sent by the CPLD on the second mainboard and the S_C2C_RX_EN received by the CPLD on the second mainboard are respectively connected to the MCIO connector of the second mainboard; The first mainboard is synchronized with the second mainboard via a C2C synchronization signal.

[0078] The processor will send a signal to the CPLD, which will make a logical judgment and send it to the MCIO connector.

[0079] In this embodiment, motherboard-1 is the first motherboard, and motherboard-2 is the second motherboard; On the first motherboard, the A side of the MCIO connector is connected to the processor's RX signal, and the B side is connected to the TX signal. On the second motherboard, the situation is the same. When the two motherboards are connected using an MCIO high-speed cable: The A side (RX) of the MCIO connector of the first motherboard will be connected to the B side (TX) of the MCIO connector of motherboard 2 through the MCIO cable.

[0080] At the same time, the B side (TX) of the MCIO connector of motherboard 1 is connected to the A side (RX) of the MCIO connector of motherboard 2 through the MCIO cable.

[0081] In this way, the processor of motherboard 1 can send data through the TX signal, and this data will be received by the processor of motherboard 2 through its RX signal, and vice versa, realizing the AB, BA interconnection mode, thereby realizing high-speed signal TX&RX signal interconnection between multi-core processor modules.

[0082] The mainboard is provided with an external dip switch for distinguishing the master-slave relationship of the mainboard by configuring the external dip switch; In a possible implementation, the corresponding master-slave relationship can be established by the high and low levels of the external dip switch pins.

[0083] Specifically, in this embodiment, by setting the first pin of the external DIP switch of the first mainboard to a high level, the first mainboard becomes the master mainboard; by setting the first pin of the external DIP switch of the second mainboard to a low level, the second mainboard becomes the slave mainboard; In other possible implementations, the master-slave correspondence relationship is established by high and low levels of multiple pins, which is not limited here.

[0084] The first and second mainboards are distinguished by the configuration of the external dip switch. When the first pin of the external dip switch is at a high level, the mainboard is the Master and is defined as the first mainboard. When the first pin of the external dip switch is at a low level, the mainboard is the Slave and is defined as the second mainboard. Figure 6 .

[0085] Since all motherboards have the same design, they can all be used as the first motherboard (Master) or the second motherboard (Slave), that is, the master-slave relationship between the first motherboard and the second motherboard can be interchanged, as long as the configuration of the external DIP switch is modified accordingly.

[0086] The sideband signals on the rest of the MCIO connector can be used for C2C synchronization and control signals.

[0087] Under the current protocol standards, standard MCIO high-speed connectors and MCIO high-speed cables have defined fixed pin positions for high-speed signals and other pin positions for sideband signals. In this embodiment, the MICO connector is also provided with C2C synchronization and control signals. In this embodiment, the C2C high-speed signal connection is placed at the above-mentioned PIN position, and the C2C synchronization and control signals are placed at the sideband signal position.

[0088] like Figure 7 As shown: There are two C2C synchronization signals for C2C synchronization, namely M_C2C_TX_EN for sending and S_C2C_RX_EN for receiving; M_C2C_TX_EN is the signal sent by the CPLD on the first motherboard (received by the CPLD on the second motherboard) that the C2C handshake is ready for the multi-chip processor module on the first motherboard; S_C2C_RX_EN is the signal received by the CPLD on the first motherboard (sent by the CPLD on the second motherboard) indicating that the C2C handshake is ready for the multi-chip processor module on the second motherboard; When the internal logic code of the CPLD chip sets M_C2C_TX_EN&S_C2C_RX_EN=1, a synchronization signal is made (both signals are high at the same time) to start the C2C handshake.

[0089] There are four C2C control signals: M_PWR_EN: The power enable signal sent by the first mainboard is received by the second mainboard and transmitted to the S_PWR_EN signal, so that the power of the first mainboard and the second mainboard can be powered on and off synchronously.

[0090] M_RST_EN: The reset signal sent by the first mainboard is received by the second mainboard and transmitted to the S_RST_EN signal, so that the first mainboard and the second mainboard can be reset synchronously; S_PWR_DONE: The power-on completion signal sent by the second mainboard is received by the first mainboard and transmitted to the S_PWR_DONE signal; the power-on completion signal of the first mainboard and the second mainboard is synchronized to ensure the synchronization of the remaining timing.

[0091] S_C2C_GOOD: The C2C handshake completion signal sent by the second mainboard is received by the first mainboard and transmitted to the S_C2C_GOOD signal; the handshake completion signals of the first and second mainboards are synchronized to ensure the synchronization of the remaining timing.

[0092] Therefore, the MCIO connector needs to connect six CPLDs on the B side to send signals and six CPLDs on the A side to receive signals. In the interconnection mode of MCIO cables AB and BA, the C2C synchronization of the first mainboard and the second mainboard and the synchronization of control signals are realized.

[0093] The CPLD sending signal and the CPLD receiving signal are the above-mentioned C2C synchronization and control signals. Figure 7 The dashed line is the MCIO cable, and the solid line is the PCB trace on the verification board.

[0094] This embodiment uses the synchronization control signal on the MCIO cable to achieve the synchronization of power timing between two multi-core processors and the synchronization of C2C interconnection timing, thereby ensuring the stability and performance of the system and achieving synchronization between multi-core processor modules: and through the standard MCIO interface and signal definition, when a single multi-core processor module verification board does not need to be interconnected, the MCIO interface on the verification board can be connected to a standard PCIE device or board through a cable, enriching the application scenarios of the verification board, providing support for subsequent design, and improving the design flexibility.

[0095] This embodiment customizes the meaning of some sideband signals through the MCIO standard interface and cable, realizes the interconnection of high-speed signals and key synchronization signals between multi-chip processor modules, and helps to verify the interconnection and synchronization between multi-chips.

[0096] Embodiment 4 refer to Figure 8 This embodiment provides a method for interconnecting a multi-chip processor module. Based on the multi-chip processor module interconnection system described in Embodiment 3, after the multi-chip processor module on the main board (verification board) completes QSPI FLASH reading and DIE TO DIE Training of four DIEs inside the processor, the C2C handshake between the multi-chip processor modules is completed through the C2C high-speed signal transmitted by the MCIO connector and the MCIO cable as well as the C2C synchronization and control signal.

[0097] The C2C high-speed signal and the C2C synchronization and control signal transmitted through the MCIO connector and the MCIO cable complete the C2C handshake between the multi-core processor modules, specifically including: the C2C synchronization signal and the C2C high-speed signal are transmitted between the first mainboard and the second mainboard through the MCIO high-speed connector and the MCIO high-speed cable, and when M_C2C_TX_EN&S_C2C_RX_EN=1, the C2C high-speed signal handshake is performed between the multi-core processors of the first mainboard and the second mainboard.

[0098] The C2C synchronization signal (M_C2C_TX_EN and S_C2C_RX_EN) and the C2C high-speed signal are transmitted between the first motherboard and the second motherboard through the MCIO high-speed connector and the MCIO high-speed cable. When M_C2C_TX_EN&S_C2C_RX_EN=1, that is, M_C2C_TX_EN and S_C2C_RX_EN are both in the high-effective state, it means that the first motherboard and the second motherboard are already in the training completion state of the four DIEs inside the multi-core processor, and the C2C high-speed signal handshake between the two multi-core processors can be performed.

[0099] Placing two multi-core processor modules on two identical verification boards can reduce the loss caused by the verification board being scrapped due to design reasons or process problems encountered during the production process.

[0100] When a single multi-core processor module is on a verification board, you can first verify the operation and performance when working alone, eliminating the influence of interconnection, which is more conducive to analyzing and locating problems. After the verification of a single multi-core processor module is completed, the interconnection between multiple processors can be verified through MCIO cables.

[0101] It will be appreciated by those skilled in the art that all or some of the steps and systems in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. Some or all physical components may be implemented as a microprocessor, such as a central processing unit, a digital signal processor, or software executed by a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or transient medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0102] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A multi-chip processor module, characterized in that: The multi-chip processor module includes: M DIEs, a channel signal selection module, a CPLD and an external FLASH chip: Each DIE is provided with a QSPI interface; each DIE is connected to a channel signal selection module via the QSPI interface; The external FLASH chip is used to store the BIOS information started by the DIE; the external FLASH chip is connected to the channel signal selection module through the QSPI interface; The CPLD is used to generate an input selection signal and an interaction signal between the CPLD and the DIE; The channel signal selection module is also connected to the CPLD and is used to select the connectivity of different DIEs according to the received input selection signal, so as to read the BIOS information in the external FLASH chip.

2. The multi-chip processor module according to claim 1, characterized in that: The channel signal selection module includes N multiplexers, which are connected to each DIE and select different DIEs according to different input selection signals, thereby controlling the DIEs to read the BIOS information in the external FLASH chip in sequence.

3. The multi-chip processor module according to claim 2, characterized in that: The M=4, the N=3, and the multiplexer is a dual-channel four-to-one switch chip.

4. The multi-chip processor module according to claim 3, characterized in that: Each dual-channel four-to-one switch chip is used to control the input selection of four DIEs of the multi-chip processor module according to two input selection signals; The dual-channel four-select-one switch chip includes an X channel and a Y channel, each channel includes four data input signals and one data output signal; the X channel data input signal is X0&X1&X2&X3, and the data output signal is a first output signal X; the Y channel data input signal is Y0&Y1&Y2&Y3, and the data output signal is a second output signal Y; the input selection signal includes a first input selection signal A and a second input selection signal B.

5. The multi-chip processor module according to claim 4, characterized in that: The method of selecting different DIEs according to different input selection signals, thereby controlling the DIEs to sequentially read the BIOS information in the external FLASH chip is specifically as follows: Divide the 6 signals of QSPI into three groups, each group has two signals, and each group of signals corresponds to a dual-channel four-to-one switch chip in the channel signal selection module; the 6 signals of QSPI include a clock signal CLK, a chip selection signal CS and 4 data bit signals DATA[0:3]; The CPLD controls the input of the dual-channel four-to-one switch chip by controlling the values ​​of the first input selection signal A and the second input selection signal B, and determines which DIE's QSPI interface signal is connected to the external FLASH chip.

6. The multi-chip processor module according to claim 5, characterized in that: The CPLD controls the input of the dual-channel four-to-one switch chip by controlling the values ​​of the first input selection signal A and the second input selection signal B, and determines which DIE QSPI interface signal is connected to the external FLASH chip: When A=0, B=0, DIE0 is connected to the external FLASH chip; When A=1, B=0, DIE1 is connected to the external FLASH chip; When A=0, B=1, DIE2 is connected to the external FLASH chip; When A=1, B=1, DIE3 is connected to the external FLASH chip.

7. A method for starting a multi-chip processor module, based on a multi-chip processor module according to any one of claims 1 to 6, characterized in that: The multi-chip processor module includes DIE0, DIE1, DIE2 and DIE3; the interaction signals between the CPLD and the multi-chip processor module include: CRU_FLASH_DONE signal, D2D_EN signal, CRU_D2D_GOOD signal, POR_N signal, RST_N signal; the following steps are included: S1, the system is powered on, CPLD sets DIE3_RST_N and DIE3_POR_N high, and sets the first input selection signal A to 1 and the second input selection signal B to 1, DIE3 reads the BIOS information on the external FLASH chip; After S2 and DIE3 finish reading the BIOS information, they set the DIE3_CRU_FLASH_DONE signal to 1 and pass it to the CPLD; S3. After CPLD detects that the DIE3_CRU_FLASH_DONE signal is 1, it sets DIE2_RST_N and DIE2_POR_N high, sets the first input selection signal A to 0 and the second input selection signal B to 1, and DIE2 reads the BIOS information on the external FLASH chip; S4. After DIE2 finishes reading the BIOS information, it sets the DIE2_CRU_FLASH_DONE signal to 1 and passes it to the CPLD. S5. After CPLD detects that the DIE2_CRU_FLASH_DONE signal is 1, it sets DIE1_RST_N and DIE1_POR_N high, sets the first input selection signal A to 1 and the second input selection signal B to 0, and DIE1 reads the BIOS information on the external FLASH chip; S6. After DIE1 finishes reading the BIOS information, it sets the DIE1_CRU_FLASH_DONE signal to 1 and passes it to the CPLD. S7. After CPLD detects that the DIE1_CRU_FLASH_DONE signal is 1, it sets DIE0_RST_N and DIE0_POR_N high, sets the first input selection signal A to 0 and the second input selection signal B to 0, and DIE0 reads the BIOS information on the external FLASH chip; S8. After DIE0 finishes reading the BIOS information, it sets the DIE0_CRU_FLASH_DONE signal to 1 and passes it to CPLD, and the startup is completed. S9. After all DIEs of the multi-core processor module are started, the training between DIEs begins; In the steps, DIE3_RST_N represents the CRU_FLASH_DONE signal of DIE3, DIE2_RST_N represents the CRU_FLASH_DONE signal of DIE2, and the other signals in the steps are the interaction signals between CPLD and multi-chip processor module, and so on.

8. A multi-chip processor module interconnection system, characterized in that: The invention comprises two main boards, namely a first main board and a second main board, both main boards comprising a plurality of MCIO connectors and a multi-chip processor module as claimed in any one of claims 1 to 6; the multi-chip processor module comprises a CPLD; The two main boards are connected using an MCIO connector, and the DIE of the multi-core processor module of the first main board is interconnected with the DIE of the multi-core processor module of the second main board in a one-to-one correspondence; the multi-core processor module of the first main board and the multi-core processor module of the second main board are interconnected with C2C high-speed signals and C2C synchronization and control signals; The C2C high-speed signal includes a TX signal and a RX signal; The MCIO connector includes side A and side B, where side A is connected to the RX signal of the multi-chip processor module, and side B is connected to the TX signal of the multi-chip processor module. The MCIO cable realizes the interconnection mode of AB and BA, and realizes the interconnection of TX signal & RX signal between multi-chip processor modules; The C2C synchronization and control signal includes a C2C synchronization signal; M_C2C_TX_EN for sending and S_C2C_RX_EN for receiving are C2C synchronization signals; The M_C2C_TX_EN sent by the CPLD on the first mainboard and the S_C2C_RX_EN received by the CPLD on the first mainboard are respectively connected to the MCIO connector of the first mainboard; The M_C2C_TX_EN sent by the CPLD on the second mainboard and the S_C2C_RX_EN received by the CPLD on the second mainboard are respectively connected to the MCIO connector of the second mainboard; The first mainboard is synchronized with the second mainboard via a C2C synchronization signal.

9. The interconnection system according to claim 8, characterized in that The C2C synchronization and control signal also includes a C2C control signal; The C2C control signal includes: M_PWR_EN: The power enable signal sent by the first mainboard is received by the second mainboard and transmitted to the S_PWR_EN signal, so that the power of the first mainboard and the second mainboard can be powered on and off synchronously; M_RST_EN: The reset signal sent by the first mainboard is received by the second mainboard and transmitted to the S_RST_EN signal, so that the first mainboard and the second mainboard can be reset synchronously; S_PWR_DONE: The power-on completion signal sent by the second mainboard is received by the first mainboard and transmitted to the S_PWR_DONE signal; the power-on completion signal of the first mainboard and the second mainboard is synchronized to ensure the synchronization of the remaining timing; S_C2C_GOOD: The C2C handshake completion signal sent by the second mainboard is received by the first mainboard and transmitted to the S_C2C_GOOD signal; the handshake completion signals of the first and second mainboards are synchronized to ensure the synchronization of the remaining timing.

10. The interconnection system according to claim 9, characterized in that The main board is provided with an external DIP switch, which is used to distinguish the master-slave relationship of the main board by configuring the external DIP switch.

11. A multi-chip processor module interconnection method, based on a multi-chip processor module interconnection system according to any one of claims 8 to 10, characterized in that: After the multi-core processor module in the motherboard completes the external FLASH chip reading and the DIE TO DIE Training of the four DIEs inside the processor, the C2C handshake between the multi-core processor modules is completed through the C2C high-speed signal and the C2C synchronization and control signal transmitted through the MCIO connector and the MCIO cable.

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