A multi-die processor module, startup method, interconnection system, and method

Abstract

The present invention discloses a multi-die processor module, a startup method, an interconnection system and a method, relating to the technical field of processors. The multi-die processor module includes: M multi-die DIEs, each DIE is connected to a channel signal selection module through a QSPI interface; an external FLASH chip is used to store the BIOS information for DIE startup; the external FLASH chip is connected to the channel signal selection module through a QSPI interface; a CPLD is used to generate an input selection signal and the interaction signals between the CPLD and the multi-die processor module; the channel signal selection module is also connected to the CPLD and is used to select the connection of different DIEs according to the received input selection signal, so as to read the BIOS information in the external FLASH chip. The present invention shares one external FLASH chip for multiple DIEs of the multi-die processor through a QSPI interface and a multiplexer, reducing the hardware cost and lowering the system complexity and cost.

Description

Technical Field

[0001] The present invention relates to the field of processors, and more specifically, to a multi-chiplet processor module, a startup method, an interconnection system, and a method thereof. Background Art

[0002] The development of multi-chiplet technology for domestic processors has gradually emerged in recent years as the chip manufacturing process technology approaches the physical limit in order to continue to improve performance and integration. A multi-chiplet processor can integrate multiple small chips (Chiplets) with different functions into a large chip to achieve higher performance and flexibility. The application of this technology in domestic processors can be traced back to the period of rapid development of domestic processor technology in the past decade.

[0003] In the current pre-verification and optimization stage of domestic multi-chiplet processors, taking the synthesis of a CPU with four identical DIEs as an example, the hardware external interfaces of each DIE are basically the same, and each integrates a QSPI interface controller for loading off-chip firmware information. Since the QSPI interface function of each DIE needs to be comprehensively verified, each DIE needs to be separately externally connected to a QSPI FLASH.

[0004] In addition, when designing a multi-chiplet processor verification board, due to screening and structural limitations, only a single multi-chiplet processor can be placed on one verification board, and most of the previous domestic processors are not of a multi-chiplet architecture, so there is no need to test the interconnection performance between chiplets.

[0005] Therefore, the current problems are as follows:

[0006] 1) Complexity and cost: Separately externally connecting a QSPI FLASH to each DIE will undoubtedly increase the hardware cost.

[0007] 2) Increased debugging difficulty: It is necessary to separately debug and test each DIE and its external FLASH, which increases the complexity of development and verification. In a multi-DIE processor system, when problems involve interactions between processors, debugging and problem location become more difficult.

[0008] The background description provided in this article is for the purpose of generally presenting the context of the present application. Unless otherwise indicated in this article, the materials described in this section are not the prior art of the claims of this application and should not be admitted as prior art by including them in this section. Summary of the Invention

[0009] In view of the above technical problems in the related art, the present invention proposes a multi-chiplet processor module, a startup method, an interconnection system, and a method thereof.

[0010] To achieve the above-mentioned invention purposes, the present invention adopts the following technical solutions:

[0011] In a first aspect, the present invention provides a multi-die processor module, and the multi-die processor module includes: M DIEs, a channel signal selection module, a CPLD, and an external FLASH chip:

[0012] Each DIE is provided with a QSPI interface; each DIE is connected to the channel signal selection module through the QSPI interface;

[0013] The external FLASH chip is used to store BIOS information for DIE startup; the external FLASH chip is connected to the channel signal selection module through the QSPI interface;

[0014] The CPLD is used to generate input selection signals and CPLD-DIE interaction signals;

[0015] The channel signal selection module is also connected to the CPLD, and is used to select the connection of different DIEs according to the received input selection signals, so as to read the BIOS information in the external FLASH chip.

[0016] Specifically, the channel signal selection module includes N multiplexers, the multiplexers are connected to each DIE, and different DIEs are selected according to different input selection signals, so as to control the DIEs to sequentially read the BIOS information in the external FLASH chip.

[0017] Specifically, M = 4, N = 3, and the multiplexer is a dual-channel four-to-one switch chip.

[0018] Specifically, each dual-channel four-to-one switch chip is used to control the input selection of 4 DIEs of the multi-die processor module according to two input selection signals;

[0019] The dual-channel four-to-one switch chip includes an X channel and a Y channel, and each channel includes four data input signals and one data output signal; the X-channel data input signals are X0&X1&X2&X3, and the data output signal is the first output signal X; the Y-channel data input signals are Y0&Y1&Y2&Y3, and the data output signal is the second output signal Y; the input selection signals include a first input selection signal A and a second input selection signal B.

[0020] Specifically, the step of selecting different DIEs according to different input selection signals so as to control the DIEs to sequentially read the BIOS information in the external FLASH chip is specifically:

[0021] Divide the 6 signals of the QSPI into three groups, with two signals in each group, and each group of signals corresponds to a dual-channel four-to-one switch chip in the channel signal selection module; the 6 signals of the QSPI include a clock signal CLK, a chip select signal CS, and 4 data bit signals DATA[0:3].

[0022] The CPLD controls the input of the dual-channel four-to-one switch chip by controlling the values of the first input selection signal A and the second input selection signal B, and determines which DIE's QSPI interface signal is connected to the external FLASH chip.

[0023] Specifically, the CPLD controls the input of the dual-channel four-to-one switch chip by controlling the values of the first input selection signal A and the second input selection signal B, and determines which DIE's QSPI interface signal is connected to the external FLASH chip as follows:

[0024] When A = 0 and B = 0, DIE0 is connected to the external FLASH chip;

[0025] When A = 1 and B = 0, DIE1 is connected to the external FLASH chip;

[0026] When A = 0 and B = 1, DIE2 is connected to the external FLASH chip;

[0027] When A = 1 and B = 1, DIE3 is connected to the external FLASH chip.

[0028] In a second aspect, the present invention provides a method for starting a multi-die processor module, based on the multi-die processor module described in any one of the first aspects. The multi-die processor module includes DIE0, DIE1, DIE2, and DIE3; the signals interacted between the CPLD and the multi-die processor module include: CRU_FLASH_DONE signal, D2D_EN signal, CRU_D2D_GOOD signal, POR_N signal, RST_N signal; the method includes the following steps:

[0029] S1. When the system is powered on, the CPLD sets DIE3_RST_N and DIE3_POR_N high, sets the first input selection signal A to 1 and the second input selection signal B to 1, and DIE3 reads the BIOS information on the external FLASH chip;

[0030] S2. After DIE3 finishes reading the BIOS information, set the DIE3_CRU_FLASH_DONE signal to 1 and transmit it to the CPLD;

[0031] S3. After CPLD detects that the DIE3_CRU_FLASH_DONE signal is 1, it sets DIE2_RST_N and DIE2_POR_N high, sets the first input selection signal A to 0 and the second input selection signal B to 1, and DIE2 reads the BIOS information on the external FLASH chip;

[0032] S4. After DIE2 finishes reading the BIOS information, it sets the DIE2_CRU_FLASH_DONE signal to 1 and passes it to the CPLD.

[0033] S5. After CPLD detects that the DIE2_CRU_FLASH_DONE signal is 1, it sets DIE1_RST_N and DIE1_POR_N high, sets the first input selection signal A to 1 and the second input selection signal B to 0, and DIE1 reads the BIOS information on the external FLASH chip;

[0034] S6. After DIE1 finishes reading the BIOS information, it sets the DIE1_CRU_FLASH_DONE signal to 1 and passes it to the CPLD.

[0035] S7. After CPLD detects that the DIE1_CRU_FLASH_DONE signal is 1, it sets DIE0_RST_N and DIE0_POR_N high, sets the first input selection signal A to 0 and the second input selection signal B to 0, and DIE0 reads the BIOS information on the external FLASH chip;

[0036] S8. After DIE0 finishes reading the BIOS information, it sets the DIE0_CRU_FLASH_DONE signal to 1 and passes it to CPLD, and the startup is completed.

[0037] S9. After all DIEs of the multi-core processor module are started, the training between DIEs begins;

[0038] In the steps, DIE3_CRU_FLASH_DONE indicates the CRU_FLASH_DONE signal of DIE3, DIE2_CRU_FLASH_DONE indicates the CRU_FLASH_DONE signal of DIE2, and the same applies to other CPLD and multi-chip processor module interaction signals in the steps.

[0039] In a third aspect, the present invention provides a multi-chip processor module interconnection system, comprising two main boards, namely a first main board and a second main board, both main boards comprising a plurality of MCIO connectors and the multi-chip processor module as described in the first aspect; the multi-chip processor module comprises a CPLD;

[0040] Two mainboards are connected using an MCIO connector. The dies processed by multi-dielets on the first mainboard are interconnected one-to-one with the dies of the multi-dielet processor module on the second mainboard; C2C high-speed signals and C2C synchronization and control signals are interconnected between the multi-dielet processor module on the first mainboard and the multi-dielet processor module on the second mainboard;

[0041] The C2C high-speed signals include TX signals and RX signals;

[0042] The MCIO connector includes side A and side B. Among them, side A is connected to the RX signal of the multi-dielet processor module, and side B is connected to the TX signal of the multi-dielet processor module. The MCIO cable realizes the interconnection method of A-B and B-A, and realizes the interconnection of TX signals and RX signals between multi-dielet processor modules;

[0043] The C2C synchronization and control signals include C2C synchronization signals; M_C2C_TX_EN for sending and S_C2C_RX_EN for receiving are C2C synchronization signals;

[0044] The M_C2C_TX_EN sent by the CPLD on the first mainboard and the S_C2C_RX_EN received are respectively connected to the MCIO connector on the first mainboard;

[0045] The M_C2C_TX_EN sent by the CPLD on the second mainboard and the S_C2C_RX_EN received are respectively connected to the MCIO connector on the second mainboard;

[0046] The first mainboard and the second mainboard are synchronized through the C2C synchronization signal.

[0047] Specifically, the C2C synchronization and control signals further include C2C control signals;

[0048] The C2C control signals include:

[0049] M_PWR_EN: The power enable signal sent by the first mainboard, received by the second mainboard, and passed to the S_PWR_EN signal; realizes that the power supplies of the first mainboard and the second mainboard can be powered on and off synchronously;

[0050] M_RST_EN: The reset signal sent by the first mainboard, received by the second mainboard, and passed to the S_RST_EN signal; realizes that the first mainboard and the second mainboard can be reset synchronously;

[0051] S_PWR_DONE: The power-on completion signal sent by the second mainboard, received by the first mainboard, and passed to the S_PWR_DONE signal; realizes the synchronization of the power-on completion signals of the first mainboard and the second mainboard, and ensures the synchronization of the remaining timing;

[0052] S_C2C_GOOD: The C2C handshake completion signal sent by the second main board, received by the first main board, and transmitted to the S_C2C_GOOD signal; it realizes the synchronization of the handshake completion signals of the first main board and the second main board, and ensures the synchronization of the remaining timing.

[0053] Specifically, an external DIP switch is provided on the main board for distinguishing the master-slave relationship of the main boards by configuring the external DIP switch.

[0054] Fourthly, the present invention provides a method for interconnecting multi-die processor modules. Based on the multi-die processor module interconnecting system described in any one of the third aspects, after the multi-die processor modules in the main board complete the external FLASH chip reading and the DIE TO DIE Training of the four DIEs inside the processor, the C2C handshake between the multi-die processor modules is completed through the C2C high-speed signals and C2C synchronization and control signals transmitted by the MCIO connector and the MCIO cable.

[0055] Specifically, the C2C handshake between the multi-die processor modules completed through the C2C high-speed signals and C2C synchronization and control signals transmitted by the MCIO connector and the MCIO cable specifically includes: The C2C synchronization signal and the C2C high-speed signal are transmitted between the first main board and the second main board through the MCIO high-speed connector and the MCIO high-speed cable. When M_C2C_TX_EN&S_C2C_RX_EN = 1, the C2C high-speed signal handshake is performed between the multi-die processors of the first main board and the second main board.

[0056] A multi-die processor module provided by the present invention shares an external FLASH chip for multiple DIEs of multi-die processing through the QSPI interface and the multiplexer, reducing the hardware cost and lowering the system complexity and cost;

[0057] A multi-die processor module startup method provided by the present invention utilizes the CPLD control signal to realize the polling process of multiple DIEs for the QSPI FLASH, achieving the effect of starting the DIEs in sequence, which is helpful for the synchronization of multiple DIEs and firmware maintenance at the software level;

[0058] A multi-die processor module interconnection system proposed by the present invention realizes the synchronization of power supply timing and C2C interconnection timing between two multi-core processors through the synchronization control signal on the MCIO cable, thereby ensuring the stability and performance of the system and achieving the synchronization between multi-die processor modules. Moreover, through the standard MCIO interface and signal definition, when a single multi-die processor module verification board is not used for interconnection, the MCIO interface on the verification board can be externally connected to a standard PCIE device or board through a cable, enriching the application scenarios of the verification board, providing support for subsequent designs, and enhancing the flexibility of the design.

[0059] In addition, through the MCIO standard interface and cable, the meanings of some sideband signals are customized, realizing the interconnection of high-speed signals and key synchronization signals between multi-die processor modules, which helps to verify the interconnection and synchronization between multi-dies. Description of the Drawings

[0060] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0061] Figure 1 It is a schematic structural diagram of a multi-die processor module provided according to an embodiment of the present invention;

[0062] Figure 2 It is a schematic diagram of signals for the interaction between a CPLD and a multi-die processor module provided according to an embodiment of the present invention;

[0063] Figure 3 It is a schematic diagram of a method for starting a multi-die processor module provided according to an embodiment of the present invention;

[0064] Figure 4 It is a schematic flowchart of four DIEs reading an external FLASH chip through the QSPI interface provided according to an embodiment of the present invention;

[0065] Figure 5 It is a schematic diagram of a multi-die processor module interconnection system provided according to an embodiment of the present invention;

[0066] Figure 6 It is a schematic diagram of the docking method of high-speed signals between multi-die processor modules provided according to an embodiment of the present invention;

[0067] Figure 7 It is a schematic diagram of the interconnection of sideband signals at other positions of MCIO provided according to an embodiment of the present invention;

[0068] Figure 8 It is a schematic diagram of the C2C handshake process between multi-die processor modules provided according to an embodiment of the present invention. Specific implementation manners

[0069] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present invention.

[0070] In the description of the present invention, if the first, second, etc. are described only for the purpose of distinguishing technical features, it cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features or implicitly indicating the sequence relationship of the indicated technical features.

[0071] In the description of the present invention, it should be understood that for the orientation description, such as up, down, etc., the indicated orientation or positional relationship is based on the orientation or positional relationship shown in the accompanying drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present invention.

[0072] In the description of the present invention, it should be noted that unless otherwise clearly defined, words such as setting, installation, connection, etc. should be understood in a broad sense. Those skilled in the art can reasonably determine the specific meanings of the above words in the present invention in combination with the specific content of the technical solution.

[0073] Embodiment 1

[0074] Referring to Figure 1 , this embodiment proposes a multi-die processor module, enabling multiple DIEs of the multi-die processor to share an external FLASH chip. By polling to read BIOS information from the external FLASH chip, the hardware cost is reduced, thus solving the problem of high hardware cost caused by each DIE of the current multi-die server being separately externally connected to an external FLASH chip.

[0075] The multi-die processor module includes M DIEs, a channel signal selection module, a CPLD, and an external FLASH chip;

[0076] Each DIE is provided with a QSPI interface; each DIE is connected to the channel signal selection module through the QSPI interface;

[0077] The number of DIEs is determined during the packaging design of the multi-die processor.

[0078] The external FLASH chip is used to store the BIOS information for DIE startup; the external FLASH chip is connected to the channel signal selection module through the QSPI interface;

[0079] In this embodiment, the external FLASH chip is a QSPI FLASH chip;

[0080] It can be understood that the external FLASH chip can also be used to store other configuration information or firmware, which is prior art and will not be elaborated here.

[0081] For the CPU, the CPU DIE is the basic unit that constitutes the CPU. One or more CPU DIEs can be encapsulated to form a CPU package. In the context, the CPU DIE is simply referred to as DIE.

[0082] QSPI is the abbreviation of Quad SPI, which represents 6 - wire SPI and includes 6 signals, including the clock signal CLK, the chip - select signal CS, and 4 data - bit signals DATA[0:3]. This is prior art and will not be elaborated here.

[0083] BIOS (Basic Input Output System), that is, the basic input - output system, is a non - tamperable startup program engraved on the motherboard ROM chip. BIOS is responsible for the computer system self - test program (POST, Power On Self Test) and the system self - startup program. Therefore, it is the first program after the computer system starts. Due to its non - tamperability, the program is stored in the ROM chip and can still maintain the original settings after power - off.

[0084] CPLD (Complex Programmable Logic Device) is a programmable logic device that contains multiple logic units and programmable interconnection resources. It is usually used for logic configuration and signal processing in the server to ensure the stable operation of the system.

[0085] The CPLD is used to generate input selection signals and the CPLD - multi - die processor module interaction signals;

[0086] The CPLD - multi - die processor module interaction signals include:

[0087] CRU_FLASH_DONE signal: The signal indicating that the DIE has completed reading the FLASH information, which is output from the DIE to the CPLD.

[0088] D2D_EN signal: The enabling signal for Training between DIEs, which is output from the CPLD to the DIE.

[0089] CRU_D2D_GOOD signal: The training completion signal between DIEs, output from the DIE to the CPLD.

[0090] POR_N signal: The power-on reset signal of the DIE, output from the CPLD to the DIE.

[0091] RST_N signal: The global reset signal of the DIE, output from the CPLD to the DIE.

[0092] The channel signal selection module is also connected to the CPLD, and is used to select the connection of different DIEs according to the received input selection signal, so as to read the BIOS information in the external FLASH chip.

[0093] Specifically, the channel signal selection module includes N multiplexers, the multiplexers are connected to each DIE, and different DIEs are selected according to different input selection signals, so as to control the DIE to sequentially read the BIOS information in the external FLASH chip.

[0094] Specifically, in this implementation, the multi-die processor module includes 4 DIEs, namely: DIE0, DIE1, DIE2, DIE3; the channel signal selection module includes 3 multiplexers, and the multiplexers are dual-channel four-to-one switch chips;

[0095] The dual-channel four-to-one switch chip includes an X channel and a Y channel, and each channel includes four data input signals and one data output signal. The X-channel data input signals are X0&X1&X2&X3, and the data output signal is the first output signal X; the Y-channel data input signals are Y0&Y1&Y2&Y3, and the data output signal is the second output signal Y, that is, the dual-channel four-to-one switch chip has two output results, including the first output signal X and the second output signal Y.

[0096] The 6 signals of QSPI are divided into three groups, with two signals in each group; the three groups of signals respectively correspond to three dual-channel four-to-one switch chips, that is, each group of signals corresponds to one dual-channel four-to-one switch chip in the channel signal selection module;

[0097] Specifically, the QSPI bus has a total of 6 signal lines, and these signals are divided into three groups, with two signals in each group. The three groups of signals are respectively:

[0098] The first group: the clock signal CLK and the chip select signal CS;

[0099] The second group: the first data bit signal DATA[0] and the second data bit signal DATA[1];

[0100] The third group: the third data bit signal DATA[2] and the fourth data bit signal DATA[3];

[0101] Three dual-channel four-to-one multiplexer chips are used to control the signals of the QSPI bus. Hereinafter, the dual-channel four-to-one multiplexer chip is simply referred to as the multiplexer chip. Then:

[0102] The first multiplexer chip controls the clock signal CLK and the chip select signal CS;

[0103] The second multiplexer chip controls the first data bit signal DATA[0] and the second data bit signal DATA[1];

[0104] The third multiplexer chip controls the third data bit signal DATA[2] and the fourth data bit signal DATA[3];

[0105] In this embodiment, the input selection signals include a first input selection signal A and a second input selection signal B;

[0106] The dual-channel four-to-one multiplexer chip receives two input selection signals including a first input selection signal A and a second input selection signal B, and is used to select and output the data signal;

[0107] Wherein when A = 0 and B = 0, X = X0 and Y = Y0;

[0108] When A = 1 and B = 0, X = X1 and Y = Y1;

[0109] When A = 0 and B = 1, X = X2 and Y = Y2;

[0110] When A = 1 and B = 1, X = X3 and Y = Y3.

[0111] Each dual-channel four-to-one multiplexer chip is used to control the input selection of 4 DIEs of the multi-die processor module according to two input selection signals;

[0112] The CPLD controls the input of the dual-channel four-to-one multiplexer chip by controlling the values of the first input selection signal A and the second input selection signal B, so as to determine which DIE's QSPI interface signal is connected to the QSPI FLASH chip. Specifically,

[0113] When A = 0 and B = 0, DIE0 is connected to the external FLASH chip;

[0114] When A = 1 and B = 0, DIE1 is connected to the external FLASH chip;

[0115] When A = 0 and B = 1, DIE2 is connected to the external FLASH chip;

[0116] When A = 1 and B = 1, DIE3 is connected to the external FLASH chip.

[0117] In this way, each DIE can independently access the QSPI FLASH chip to read the BIOS information without interfering with each other.

[0118] Preferably, in this embodiment, the dual-channel four-to-one switch chip is the SGM84782 chip of Shengbang Microelectronics Co., Ltd.

[0119] The startup system of a multi-die processor module provided in this embodiment shares an external FLASH chip with a multiplexer through the QSPI interface for multiple DIEs of the multi-die processing, reducing the hardware cost and lowering the system complexity and cost.

[0120] Embodiment 2

[0121] Reference Figure 3 、 Figure 4 Based on the multi-die processor module described in Embodiment 1, this embodiment provides a method for starting up a multi-die processor module. The multi-die processor module includes DIE0, DIE1, DIE2, and DIE3. The interaction signals between the CPLD and the multi-die processor module include: CRU_FLASH_DONE signal, D2D_EN signal, CRU_D2D_GOOD signal, POR_N signal, and RST_N signal. The method includes the following steps:

[0122] S1. When the system is powered on, the CPLD sets DIE3_RST_N and DIE3_POR_N high, sets the first input selection signal A to 1 and the second input selection signal B to 1, and DIE3 reads the BIOS information on the external FLASH chip.

[0123] It can be known from Embodiment 1 that the interaction signals between the CPLD and the multi-die processor module include:

[0124] CRU_FLASH_DONE signal: The signal indicating that the DIE has completed reading the FLASH information, which is output from the DIE to the CPLD.

[0125] D2D_EN signal: The enabling signal for Training between DIEs, which is output from the CPLD to the DIE.

[0126] CRU_D2D_GOOD signal: The signal indicating that the Training between DIEs is completed, which is output from the DIE to the CPLD.

[0127] POR_N signal: The power-on reset signal of the DIE, which is output from the CPLD to the DIE.

[0128] RST_N signal: The global reset signal of the DIE, output from the CPLD to the DIE.

[0129] When the system is powered on, the CPLD and the multi-die processor module start to be powered; after the CPLD is powered on, it executes the internal initialization program, prepares the control signal and manages the startup process. The CPLD sets the global reset signal and the power-on reset signal of DIE3 high to ensure that DIE3 is in a known state and ready to start.

[0130] For the convenience of distinction, in this embodiment, the naming method of "DIE name_interaction signal" is used to facilitate distinguishing which DIE the interaction signal is input to; for example:

[0131] The CRU_FLASH_DONE signal of DIE3 is DIE3_CRU_FLASH_DONE; the CRU_FLASH_DONE signal of DIE2 is DIE2_CRU_FLASH_DONE;

[0132] The POR_N signal of DIE3 is DIE3_POR_N; the POR_N signal of DIE2 is DIE2_POR_N;

[0133] The RST_N signal of DIE3 is DIE3_RST_N; the RST_N signal of DIE2 is DIE2_RST_N;

[0134] The D2D_EN signal of DIE3 is DIE3_D2D_EN; the RST_N signal of DIE2 is DIE2_D2D_EN;

[0135] The CRU_D2D_GOO signal of DIE3 is DIE3_CRU_D2D_GOO; the RST_N signal of DIE2 is DIE2_CRU_D2D_GOO;

[0136] The naming of the interaction signals between DIE1, DIE0 and the multi-die processor module also follows the same pattern. If there are more DIEs, the above naming rules can also be adopted.

[0137] S2. After DIE3 reads the BIOS information and finishes, it sets the DIE3_CRU_FLASH_DONE signal to 1 and transmits it to the CPLD;

[0138] S3. After the CPLD detects that the DIE3_CRU_FLASH_DONE signal is 1, it sets DIE2_RST_N and DIE2_POR_N high, sets the first input selection signal A to 0 and the second input selection signal B to 1, and DIE2 reads the BIOS information on the external FLASH chip;

[0139] S4. After DIE2 finishes reading the BIOS information, set the DIE2_CRU_FLASH_DONE signal to 1 and send it to the CPLD;

[0140] S5. After the CPLD detects that the DIE2_CRU_FLASH_DONE signal is 1, set DIE1_RST_N and DIE1_POR_N high, set the first input selection signal A to 1 and the second input selection signal B to 0, and DIE1 reads the BIOS information on the external FLASH chip;

[0141] S6. After DIE1 finishes reading the BIOS information, set the DIE1_CRU_FLASH_DONE signal to 1 and send it to the CPLD;

[0142] S7. After the CPLD detects that the DIE1_CRU_FLASH_DONE signal is 1, set DIE0_RST_N and DIE0_POR_N high, set the first input selection signal A to 0 and the second input selection signal B to 0, and DIE0 reads the BIOS information on the external FLASH chip;

[0143] S8. After DIE0 finishes reading the BIOS information, set the DIE0_CRU_FLASH_DONE signal to 1 and send it to the CPLD, and the startup ends;

[0144] S9. After all DIEs of the multi-die processor module finish starting up, start the Training training between DIEs.

[0145] After all DIEs finish reading the BIOS information in the order of DIE3 - DIE2 - DIE1 - DIE0, the CPLD confirms that all DIEs have successfully loaded the BIOS.

[0146] After the BIOS of all DIEs is loaded, the system is ready to perform DIE TO DIE Training training, which is to establish a communication link and a data transmission path between DIEs.

[0147] In this embodiment, the startup order of DIEs is not limited, and the startup order of DIEs can be adjusted according to actual needs, and the adjusted startup orders are all within the scope of protection.

[0148] In this embodiment, through the scheme that the QSPI interfaces of multiple DIEs share an external FLASH chip, while reducing the hardware cost, the CPLD control signal is used to realize the polling process of multiple DIEs for QSPI FLASH, achieving the effect of starting DIEs in sequence, which is helpful for the synchronization of multiple DIEs and firmware maintenance at the software level.

[0149] Embodiment Three

[0150] Reference Figure 5 , this embodiment provides a multi-die processor module interconnection system. Based on the startup system of the multi-die processor module described in Embodiment 1, it includes two main boards, namely the first main board and the second main board. Both main boards include the multi-die processor module described in Embodiment 1 and several MCIO connectors; the multi-die processor module of the first main board is interconnected with the multi-die processor module of the second main board for C2C high-speed signals and C2C synchronization and control signals;

[0151] Specifically, the multi-die processor module contains M DIEs, and each DIE also contains C2C high-speed signals; the multi-die processor module includes a CPLD; each DIE of the two main boards is respectively connected to an MCIO connector, and the DIEs of the multi-die processor on the first main board are interconnected with the DIEs of the multi-die processor module of the second main board in a one-to-one correspondence; the CPLD of the multi-die processor module of the first main board is interconnected with the CPLD of the multi-die processor module of the second main board for C2C synchronization and control signals.

[0152] The C2C high-speed signal is a group of x16 high-speed signals, which are constituted by two MCIO x8 connectors; the C2C high-speed signals for the interconnection of the multi-die processor module include the C2C high-speed signals of all DIEs.

[0153] The C2C high-speed signal includes an RX signal and a TX signal;

[0154] Specifically, each DIE of the two main boards is respectively connected to an MCIO connector. The specific connection of the DIE of the multi-die processor on the first main board with the DIE of the multi-die processor module of the second main board in a one-to-one correspondence is as follows: each DIE is respectively connected to 2 MCIO x8 connectors, and the MCIO connectors of the DIE of the multi-die processor on the first main board are connected to the MCIO connectors of the DIE at the same position of the multi-die processor module of the second main board through MCIO cables; the MCIO cables are MCIO high-speed cables.

[0155] It can be understood that the MCIO connector provides an MCIO interface for connecting different devices with MCIO interfaces.

[0156] This embodiment uses connectors and cables with standard MCIO interfaces for the high-speed signals and control signals required for the interconnection of multi-die processor modules, realizing the interconnection means when the multi-die processor modules are located on different main boards.

[0157] In this embodiment, two verification mainboards are used, namely the first mainboard and the second mainboard. The designs of the first mainboard and the second mainboard are exactly the same, and each contains a multi-die processor module and several MCIO connector interfaces; a CPLD is included in the multi-die processor module.

[0158] The multi-die processor modules are mainly interconnected by C2C high-speed signals, and the CPLDs of the multi-die processor modules on the two mainboards are mainly interconnected by C2C synchronization and control signals.

[0159] Since the current C2C high-speed signals interconnected between each DIE are a group of x16 signals, two standard MCIO x8 connectors will be used to form a group of x16 high-speed signals.

[0160] x16 signal channels: This means that 16 independent signal channels are required between each processor chip for data transmission. These channels can be high-speed signal lines for data, address, control signals, etc.

[0161] MCIO x8 connector: There are multiple different models of MCIO connectors, and the x8 model connector can provide 8 signal channels. Therefore, in order to build a complete x16 signal channel, two such x8 connectors are needed.

[0162] Therefore, by combining two MCIO x8 connectors, a connection with 16 signal channels can be formed, meeting the high-speed signal interconnection requirements between each DIE. These two connectors will be responsible for the first 8 and the last 8 signal channels in the x16 signal channel respectively, and jointly complete the data transmission.

[0163] Reference Figure 5 , taking the example of synthesizing a multi-die processor module with four identical DIEs: DIE0 - DIE0, DIE1 - DIE1, DIE2 - DIE2, DIE3 - DIE3 of the two multi-die processor modules are respectively connected using MCIO cables through their corresponding MCIO connectors.

[0164] The MCIO connector includes side A and side B. Among them, side A is connected to the RX signal of the C2C high-speed signal of the multi-die processor module, and side B is connected to the TX signal of the C2C high-speed signal of the multi-die processor module. The MCIO cable realizes the interconnection method of A - B and B - A, realizing the interconnection of the TX & RX signals of the high-speed signals between the multi-die processor modules, thereby realizing the interconnection of the C2C high-speed signals of the multi-die processor modules.

[0165] The RX signal is the receiving end signal of the processor C2C high-speed signal, used to receive data or commands from other devices;

[0166] The TX signal is the transmission - end signal of the processor's C2C high - speed signal, which is used to send data or commands to other devices.

[0167] The MCIO connector is a standard MCIO high - speed connector, and the MCIO cable is a standard MCIO high - speed cable; the specifications of the standard MCIO high - speed cable and the MCIO high - speed connector will define and distinguish the A side and the B side.

[0168] In the case of the multi - die processor module interconnection in this embodiment, the RX signal is used to receive data from another multi - die processor module, and the TX signal is used to send data to another multi - die processor module.

[0169] The high - speed signal docking method between the multi - die processor modules of two motherboards is as shown in Figure 5 Two motherboards are the first motherboard and the second motherboard respectively. The designs of the first motherboard and the second motherboard are exactly the same, each containing a multi - die processor module and several MCIO connectors; the multi - die processor module contains a CPLD.

[0170] The C2C synchronization and control signals include C2C synchronization signals and C2C control signals; M_C2C_TX_EN for transmission and S_C2C_RX_EN for reception are C2C synchronization signals;

[0171] The M_C2C_TX_EN and S_C2C_RX_EN sent by the CPLD on the first motherboard are respectively connected to the MCIO connectors on the first motherboard;

[0172] The M_C2C_TX_EN and S_C2C_RX_EN sent by the CPLD on the second motherboard are respectively connected to the MCIO connectors on the second motherboard;

[0173] The first motherboard and the second motherboard are synchronized through C2C synchronization signals.

[0174] The processor will send signals to the CPLD, and after the CPLD makes logical judgments, it will send signals to the MCIO connectors.

[0175] In this embodiment, motherboard - 1 is the first motherboard and motherboard - 2 is the second motherboard;

[0176] On the first motherboard, the A side of the MCIO connector is connected to the RX signal of the processor, and the B side is connected to the TX signal. The situation is the same on the second motherboard. When using an MCIO high - speed cable to connect the two motherboards:

[0177] The A side (RX) of the MCIO connector on the first motherboard will be connected to the B side (TX) of the MCIO connector on motherboard 2 through the MCIO cable.

[0178] Meanwhile, the B side (TX) of the MCIO connector on motherboard 1 is connected to the A side (RX) of the MCIO connector on motherboard 2 via an MCIO cable.

[0179] In this way, the processor on motherboard 1 can send data via the TX signal, and this data will be received by the processor on motherboard 2 via its RX signal, and vice versa, realizing the interconnection method of A - B and B - A, thus achieving the high - speed signal interconnection between TX and RX signals of multi - die processor modules.

[0180] An external DIP switch is provided on the motherboard for distinguishing the master - slave relationship of the motherboard by configuring the external DIP switch;

[0181] In a possible implementation, the corresponding master - slave relationship can be established by the high and low levels of the pins of the external DIP switch.

[0182] Specifically, in this embodiment, by setting the first pin of the external DIP switch of the first motherboard to a high level, the first motherboard is the master motherboard; by setting the first pin of the external DIP switch of the second motherboard to a low level, the second motherboard is the slave motherboard;

[0183] In other possible implementations, the master - slave correspondence relationship can also be established by the high and low levels of multiple pins, which is not limited here.

[0184] The first motherboard and the second motherboard are distinguished by the configuration of the external DIP switch. When the first pin of the external DIP switch is at a high level, the motherboard is the Master, defined as the first motherboard. When the first pin of the external DIP switch is at a low level, the motherboard is the Slave, defined as the second motherboard. Refer to Figure 6 .

[0185] Since the designs of all motherboards are the same, any of them can potentially be the first motherboard (Master) or the second motherboard (Slave), that is, the master - slave relationship between the first motherboard and the second motherboard can be interchanged, as long as the configuration of the external DIP switch is modified accordingly.

[0186] The sideband signals at other positions of the MCIO connector can be used for C2C synchronization and control signals.

[0187] Under the current protocol standard, the standard MCIO high - speed connector and the MCIO high - speed cable have defined the fixed PIN positions of the connector and the cable for placing high - speed signals, and the remaining PIN positions for placing sideband signals;

[0188] In this embodiment, C2C synchronization and control signals are also provided on the MICO connector. In this embodiment, the C2C high - speed signal connections are placed at the above - mentioned PIN positions, and the C2C synchronization and control signals are placed at the positions of the sideband signals.

[0189] As Figure 7 shown below:

[0190] There are two C2C synchronization signals for C2C synchronization, namely M_C2C_TX_EN for transmission and S_C2C_RX_EN for reception;

[0191] M_C2C_TX_EN is the signal indicating that the multi-die processor module on the first motherboard is ready for C2C handshake sent by the CPLD on the first motherboard (received by the CPLD on the second motherboard);

[0192] S_C2C_RX_EN is the signal indicating that the multi-die processor module on the second motherboard is ready for C2C handshake received by the CPLD on the first motherboard (sent by the CPLD on the second motherboard);

[0193] When the internal logic code of the CPLD chip makes M_C2C_TX_EN & S_C2C_RX_EN = 1, it serves as a synchronization signal (both signals are high-level simultaneously), and the C2C handshake starts.

[0194] There are four C2C control signals:

[0195] M_PWR_EN: The power enable signal sent by the first motherboard, received by the second motherboard, and passed to the S_PWR_EN signal; it enables the power supplies of the first motherboard and the second motherboard to be powered on and off synchronously.

[0196] M_RST_EN: The reset signal sent by the first motherboard, received by the second motherboard, and passed to the S_RST_EN signal; it enables the first motherboard and the second motherboard to be reset synchronously;

[0197] S_PWR_DONE: The power-on completion signal sent by the second motherboard, received by the first motherboard, and passed to the S_PWR_DONE signal; it synchronizes the power-on completion signals of the first motherboard and the second motherboard to ensure the synchronization of the remaining timing.

[0198] S_C2C_GOOD: The C2C handshake completion signal sent by the second motherboard, received by the first motherboard, and passed to the S_C2C_GOOD signal; it synchronizes the handshake completion signals of the first motherboard and the second motherboard to ensure the synchronization of the remaining timing.

[0199] Therefore, six CPLD transmission signals need to be connected on the B side of the MCIO connector, and six CPLD reception signals need to be connected on the A side. In the interconnection mode of the MCIO cable A - B and B - A, the C2C synchronization and the synchronization of control signals between the first motherboard and the second motherboard are achieved.

[0200] The CPLD transmission signals and CPLD reception signals are the above-mentioned C2C synchronization and control signals,Figure 7 The dashed line is the MCIO cable, and the solid line is the PCB trace on the verification board.

[0201] In this embodiment, the synchronous control signal on the MCIO cable is used to achieve the synchronization of the power supply timing and the C2C interconnection timing between two multi-core processors, thereby ensuring the stability and performance of the system and realizing the synchronization between multi-core processor modules. Moreover, through the standard MCIO interface and signal definition, when the verification board of a single multi-core processor module is not used for interconnection, the MCIO interface on the verification board can be externally connected to a standard PCIE device or board through a cable, enriching the application scenarios of the verification board, providing support for subsequent designs, and improving the flexibility of the design.

[0202] In this embodiment, through the MCIO standard interface and cable, the meanings of some sideband signals are customized, realizing the interconnection of high-speed signals and key synchronous signals between multi-core processor modules, which helps to verify the interconnection and synchronization between multi-core chips.

[0203] Embodiment 4

[0204] Reference Figure 8 , this embodiment provides a method for interconnecting multi-core processor modules. Based on the multi-core processor module interconnection system described in Embodiment 3, after the multi-core processor module on the main board (verification board) completes the QSPI FLASH reading and the DIE TO DIE Training of the four DIEs inside the processor, the C2C handshake between the multi-core processor modules is completed through the C2C high-speed signal and the C2C synchronization and control signal transmitted by the MCIO connector and the MCIO cable.

[0205] The C2C handshake between the multi-core processor modules through the C2C high-speed signal and the C2C synchronization and control signal transmitted by the MCIO connector and the MCIO cable specifically includes: the C2C synchronization signal and the C2C high-speed signal are transmitted between the first main board and the second main board through the MCIO high-speed connector and the MCIO high-speed cable. When M_C2C_TX_EN & S_C2C_RX_EN = 1, the C2C high-speed signal handshake is performed between the multi-core processors of the first main board and the second main board.

[0206] The C2C synchronization signals (M_C2C_TX_EN and S_C2C_RX_EN) and C2C high-speed signals are transmitted between the first main board and the second main board through an MCIO high-speed connector and an MCIO high-speed cable. When M_C2C_TX_EN & S_C2C_RX_EN = 1, that is, when both M_C2C_TX_EN and S_C2C_RX_EN are in the active-high state, it means that both the first main board and the second main board have reached the completion state of the Training for the four DIEs inside the multi-die processor, and the C2C high-speed signal handshake between the two multi-die processors can be performed.

[0207] Place the two multi-die processor modules on two identical verification boards respectively to reduce the losses caused by the scrapping of the verification board due to design reasons or manufacturing process problems encountered during production.

[0208] When a single multi-die processor module is located on a verification board, the operation and performance when working alone can be verified first, excluding the influence of interconnection, which is more conducive to analyzing and locating problems. After the verification of a single multi-die processor module is completed, the interconnection between multiple processors can be verified through MCIO cables.

[0209] Those of ordinary skill in the art can understand that all or some of the steps and systems disclosed in the above methods can be implemented as software, firmware, hardware, and their appropriate combinations. Some physical components or all physical components can be implemented as a microprocessor, such as a central processing unit, a digital signal processor, or software executed by a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include a computer storage medium (or non-transitory medium) and a communication medium (or transitory medium). As is well known to those of ordinary skill in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information such as computer-readable instructions, data structures, program modules, or other data. Computer storage media includes but is not limited to RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cassette, tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, as is well known to those of ordinary skill in the art, a communication medium typically includes computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and can include any information delivery medium.

[0210] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims

1. A multi-die processor module interconnection system, characterized in that, It includes two main boards, namely the first main board and the second main board. Both main boards include a number of MCIO connectors and multi-die processor modules; The multi-die processor module includes: M DIEs, a channel signal selection module, a CPLD, and an external FLASH chip: Each DIE is provided with a QSPI interface; each DIE is connected to the channel signal selection module through the QSPI interface; The external FLASH chip is used to store the BIOS information for DIE startup; the external FLASH chip is connected to the channel signal selection module through the QSPI interface; The CPLD is used to generate input selection signals and CPLD-DIE interaction signals; The channel signal selection module is also connected to the CPLD and is used to select the connection of different DIEs according to the received input selection signals, so as to read the BIOS information in the external FLASH chip; The two main boards are connected by MCIO connectors. The DIEs of the multi-die processor on the first main board are interconnected with the DIEs of the multi-die processor module on the second main board one by one; C2C high-speed signals and C2C synchronization and control signals are interconnected between the multi-die processor modules on the first main board and the multi-die processor modules on the second main board; The C2C high-speed signals include TX signals and RX signals; The MCIO connector includes side A and side B. Among them, side A is connected to the RX signal of the multi-die processor module, and side B is connected to the TX signal of the multi-die processor module. The MCIO cable realizes the interconnection method of A-B and B-A to realize the interconnection of TX signals and RX signals between multi-die processor modules; The C2C synchronization and control signals include C2C synchronization signals; M_C2C_TX_EN for sending and S_C2C_RX_EN for receiving are C2C synchronization signals; The M_C2C_TX_EN sent by the CPLD on the first main board and the S_C2C_RX_EN received are respectively connected to the MCIO connector on the first main board; The M_C2C_TX_EN sent by the CPLD on the second main board and the S_C2C_RX_EN received are respectively connected to the MCIO connector on the second main board; The first main board and the second main board are synchronized through the C2C synchronization signal.

2. The interconnect system according to claim 1, wherein The C2C synchronization and control signals also include C2C control signals; The C2C control signals include: M_PWR_EN: A power enable signal sent by the first main board, received by the second main board, and passed to the S_PWR_EN signal; realizing that the power supplies of the first main board and the second main board can be powered on and off synchronously; M_RST_EN: A reset signal sent by the first main board, received by the second main board, and passed to the S_RST_EN signal; realizing that the first main board and the second main board can be reset synchronously; S_PWR_DONE: A power-on completion signal sent by the second main board, received by the first main board, and passed to the S_PWR_DONE signal; realizing the synchronization of the power-on completion signals of the first main board and the second main board to ensure the synchronization of the remaining timing; S_C2C_GOOD: The C2C handshake completion signal sent by the second main board, received by the first main board, and then passed to the S_C2C_GOOD signal; it realizes the synchronization of the handshake completion signals between the first main board and the second main board, ensuring the synchronization of the remaining timing.

3. The interconnect system according to claim 2, wherein, An external DIP switch is provided on the main board for distinguishing the master-slave relationship of the main boards by configuring the external DIP switch.

4. The multi-die processor module interconnection system according to claim 1, wherein The channel signal selection module includes N multiplexers. The multiplexers are connected to each DIE and select different DIEs according to different input selection signals, thereby controlling the DIEs to sequentially read the BIOS information in the external FLASH chip.

5. The multi-die processor module interconnection system according to claim 4, wherein M = 4, N = 3, and the multiplexer is a dual-channel four-to-one switch chip.

6. The multi-die processor module interconnection system according to claim 5, wherein Each dual-channel four-to-one switch chip is used to control the input selection of 4 DIEs of the multi-die processor module according to two input selection signals. The dual-channel four-to-one switch chip includes an X channel and a Y channel. Each channel includes four data input signals and one data output signal; the X-channel data input signals are X0&X1&X2&X3, and the data output signal is the first output signal X; the Y-channel data input signals are Y0&Y1&Y2&Y3, and the data output signal is the second output signal Y; the input selection signals include a first input selection signal A and a second input selection signal B.

7. The multi-die processor module interconnection system according to claim 6, wherein The specific process of selecting different DIEs according to different input selection signals to control the DIEs to sequentially read the BIOS information in the external FLASH chip is as follows: The 6 signals of QSPI are divided into three groups, with two signals in each group. Each group of signals corresponds to one dual-channel four-to-one switch chip in the channel signal selection module; the 6 signals of QSPI include a clock signal CLK, a chip select signal CS, and 4 data bit signals DATA[0:3]. The CPLD controls the input of the dual-channel four-to-one switch chip by controlling the values of the first input selection signal A and the second input selection signal B, determining which DIE's QSPI interface signal is connected to the external FLASH chip.

8. The multi-die processor module interconnection system according to claim 7, wherein The specific process of the CPLD controlling the input of the dual-channel four-to-one switch chip by controlling the values of the first input selection signal A and the second input selection signal B, determining which DIE's QSPI interface signal is connected to the external FLASH chip is as follows: When A = 0 and B = 0, DIE0 is connected to the external FLASH chip. When A = 1 and B = 0, DIE1 is connected to the external FLASH chip. When A = 0 and B = 1, DIE2 is connected to the external FLASH chip. When A = 1 and B = 1, DIE3 is connected to the external FLASH chip.

9. A multi-die processor module interconnection method, based on the multi-die processor module interconnection system according to any one of claims 1-8, characterized in that, After the multi-die processor module in the main board completes the reading of the external FLASH chip and the DIE TO DIE Training of the four DIEs inside the processor, the C2C high-speed signal and the C2C synchronization and control signal transmitted through the MCIO connector and the MCIO cable complete the C2C handshake between the multi-die processor modules.

10. A method for starting a multi-die processor module, based on the multi-die processor module interconnection system according to any one of claims 1-8, characterized in that, The multi-chip processor module includes DIE0, DIE1, DIE2 and DIE3; the interaction signals between the CPLD and the multi-chip processor module include: CRU_FLASH_DONE signal, D2D_EN signal, CRU_D2D_GOOD signal, POR_N signal, RST_N signal; the following steps are included: S1, the system is powered on, CPLD sets DIE3_RST_N and DIE3_POR_N high, and sets the first input selection signal A to 1 and the second input selection signal B to 1, DIE3 reads the BIOS information on the external FLASH chip; After S2 and DIE3 finish reading the BIOS information, they set the DIE3_CRU_FLASH_DONE signal to 1 and pass it to the CPLD; S3. After CPLD detects that the DIE3_CRU_FLASH_DONE signal is 1, it sets DIE2_RST_N and DIE2_POR_N high, sets the first input selection signal A to 0 and the second input selection signal B to 1, and DIE2 reads the BIOS information on the external FLASH chip; S4. After DIE2 finishes reading the BIOS information, it sets the DIE2_CRU_FLASH_DONE signal to 1 and passes it to the CPLD. S5. After CPLD detects that the DIE2_CRU_FLASH_DONE signal is 1, it sets DIE1_RST_N and DIE1_POR_N high, sets the first input selection signal A to 1 and the second input selection signal B to 0, and DIE1 reads the BIOS information on the external FLASH chip; S6. After DIE1 finishes reading the BIOS information, it sets the DIE1_CRU_FLASH_DONE signal to 1 and passes it to the CPLD. S7. After CPLD detects that the DIE1_CRU_FLASH_DONE signal is 1, it sets DIE0_RST_N and DIE0_POR_N high, sets the first input selection signal A to 0 and the second input selection signal B to 0, and DIE0 reads the BIOS information on the external FLASH chip; S8. After DIE0 finishes reading the BIOS information, it sets the DIE0_CRU_FLASH_DONE signal to 1 and passes it to CPLD, and the startup is completed. S9. After all DIEs of the multi-core processor module are started, the training between DIEs begins; In the steps, DIE3_CRU_FLASH_DONE indicates the CRU_FLASH_DONE signal of DIE3, DIE2_CRU_FLASH_DONE indicates the CRU_FLASH_DONE signal of DIE2, and the same applies to other CPLD and multi-chip processor module interaction signals in the steps.

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