Ring communication method, ring communication device and equipment

Abstract

The invention provides a ring communication method, a ring communication device and equipment, and the method is applied to the ring communication device, and comprises the steps: a processor determines a previous processor and a next processor which are adjacent in a ring topological structure based on a connection sequence corresponding to the ring topological structure; when a data packet sent by an upper computer is received, the processor allocates task data to the plurality of computing units according to the data packet, the task data of each computing unit comprises a plurality of data blocks, and the data transmission direction of each data block is determined based on a preset rule; for each computing unit, data in the current data block is sent to the previous processor or the next processor according to the corresponding data transmission direction, and data sent by the other processor in the next data block is processed, so that two-way communication is realized in a ring topology structure formed by the plurality of processors; the data transmission efficiency and the calculation performance of multiple processors can be simply and effectively improved.

Description

Technical Field

[0001] The present disclosure relates to the field of processors, and in particular to a ring communication method, a ring communication device and equipment. Background Art

[0002] In modern high-performance computing and deep learning applications, the use of multi-processor systems is becoming increasingly popular. These systems can significantly improve data processing speed and parallel computing capabilities. In order to achieve efficient communication between multiple processors, the following technologies are currently used: shared memory, P2P (Peer-to-Peer) communication, NVIDIA's proprietary NVLINK technology, and Socket based on network interface card (NIC) and Ethernet protocol (such as RoCEv2); these technologies each have certain advantages, such as shared memory is simple and easy to use, P2P communication provides high transmission efficiency, NVLINK supports extremely high bandwidth and low latency, and Socket is suitable for large-scale distributed computing environments.

[0003] However, existing multi-processor communication technologies generally have limitations in terms of cost or performance. For example, the shared memory method relies on CPU participation, resulting in lower performance and additional data handling overhead; P2P has high requirements for hardware configuration and poor support from server platforms; NVLINK is limited to products from specific manufacturers, limiting the interoperability of cross-brand devices; the Socket method requires additional expensive hardware such as optical modules and switches, which has high deployment costs and complex maintenance; in addition, in existing multi-processor communication technologies, multiple computing units within the processor will act as a whole and transmit in a single direction in sequence, which cannot achieve fine-grained two-way communication and limits data transmission efficiency; therefore, there is a need for a solution that can improve the data transmission efficiency and computing performance of multi-processors at a low cost. Summary of the invention

[0004] The embodiments of the present disclosure provide a ring communication method, a ring communication device and a device, which can improve the data transmission efficiency and computing performance of multiple processors at a low cost.

[0005] According to one aspect of the present disclosure, a ring communication method is provided, which is applied to a ring communication device, wherein the ring communication device includes a plurality of processors that are physically connected in sequence to form a ring topology structure, and each of the processors includes a plurality of computing units; for each of the processors in the ring topology structure, the method includes: the processor determines its own adjacent previous processor and next processor in the ring topology structure based on a connection sequence corresponding to the ring topology structure; when receiving a data packet sent by a host computer, the processor allocates task data required for executing computing tasks to the plurality of computing units according to the data packet, the task data of each computing unit includes a plurality of data blocks, and the data transmission direction of each data block is determined based on a preset rule; for each computing unit, the data in the current data block is sent to the previous processor or the next processor according to the corresponding data transmission direction, and data processing is performed on the data sent by another processor in the next data block.

[0006] Optionally, in some embodiments, the preset rule includes: determining the data transmission direction of the data block based on the unit sequence number of the computing unit; or determining the data transmission direction of the data block based on the data number of the data block.

[0007] Optionally, in some embodiments, determining the data transmission direction of the data block based on the unit serial number of the computing unit includes: for each of the computing units: if the unit serial number of the computing unit is an odd number, determining one of the previous processor and the next processor as the data transmission direction of all data blocks in the computing unit; if the unit serial number of the computing unit is an even number, determining the other of the previous processor and the next processor as the data transmission direction of all data blocks in the computing unit.

[0008] Optionally, in some embodiments, sending the data in the current data block to the previous processor or the next processor according to the corresponding data transmission direction includes: if the unit sequence number of the computing unit is an odd number, sending the data in the current data block to the corresponding data block of another computing unit with an odd number in the next processor; if the unit sequence number of the computing unit is an even number, sending the data in the current data block to the corresponding data block of another computing unit with an even number in the previous processor.

[0009] Optionally, in some embodiments, for each of the computing units, the method further includes: determining a data block currently to be sent as a current data block from the multiple data blocks based on the connection order, and determining a data block receiving data from another processor for processing as a next data block.

[0010] Optionally, in some embodiments, after processing the data sent by another processor in the next data block, the method further includes: updating the next data block to a new current data block, so as to send the data obtained after the data processing in the next data block to the previous processor or the next processor according to the corresponding data transmission direction, and determine a new next data block from the multiple data blocks.

[0011] Optionally, in some embodiments, each of the processors further includes a data transmission unit, the data transmission unit including a first transmission interface and a second transmission interface, the data transmission unit being physically connected to the second transmission interface of the previous processor through the first transmission interface, and the data transmission unit being physically connected to the first transmission interface of the next processor through the second transmission interface; sending the data in the current data block to the previous processor or the next processor according to the data transmission direction through the data transmission unit includes: when the sending target corresponding to the data transmission direction is the previous processor, sending the data in the current data block through the first transmission interface; when the sending target corresponding to the data transmission direction is the next processor, sending the data in the current data block through the second transmission interface.

[0012] Optionally, in some embodiments, the data processing on the data sent by another processor in the next data block includes: when the computing unit sends the data in the current data block to the previous processor, data processing on the data sent by the next processor in the next data block, so as to send the data obtained after the data processing to the previous processor; when the computing unit sends the data in the current data block to the next processor, data processing on the data sent by the previous processor in the next data block, so as to send the data obtained after the data processing to the next processor.

[0013] According to another aspect of the present disclosure, a ring communication device is provided, comprising: a plurality of processors physically connected in sequence to form a ring topology structure, each of the processors comprising a plurality of computing units; wherein, for each of the processors in the ring topology structure, the processor is used to: determine the previous processor and the next processor adjacent to itself in the ring topology structure based on the connection sequence corresponding to the ring topology structure; when receiving a data packet sent by a host computer, assigning task data required for executing computing tasks to the plurality of computing units according to the data packet, the task data of each computing unit comprising a plurality of data blocks, and the data transmission direction of each data block being determined based on a preset rule; for each of the computing units, sending the data in the current data block to the previous processor or the next processor according to the corresponding data transmission direction, and performing data processing on the data sent by another processor in the next data block.

[0014] Optionally, in some embodiments, the processor further includes a command processing unit and a data transmission unit, and the command processing unit is communicatively connected to the data transmission unit and the plurality of computing units respectively; wherein the command processing unit is used to allocate task data required to execute computing tasks to the plurality of computing units according to the data packet, and the data transmission unit includes a first transmission interface and a second transmission interface, and the data transmission unit is physically connected to the second transmission interface of the previous processor through the first transmission interface, and the data transmission unit is physically connected to the first transmission interface of the next processor through the second transmission interface.

[0015] Optionally, in some embodiments, the plurality of processors are deployed in the same server node, and the plurality of processors are physically connected via board-level copper wires.

[0016] According to another aspect of the present disclosure, an electronic device is provided, comprising the ring communication device as described in any one of the above embodiments.

[0017] According to the ring communication method, ring communication device and equipment provided by the present disclosure, at least the following beneficial effects are achieved: the present disclosure proposes a multi-processor ring communication method, which is applied to a ring communication device, wherein the ring communication device includes a plurality of processors that are physically connected in sequence to form a ring topology structure, each processor includes a plurality of computing units, and for each computing unit, data in a data block can be sent to a corresponding computing unit in an upper processor or a next processor according to a corresponding data transmission direction to achieve two-way communication; it can be understood that, in the traditional scheme, although each processor contains a plurality of computing units, the plurality of computing units usually share a single transmission channel for communicating with an external device or other processors, and the data of the plurality of processors are transmitted in sequence in a single direction as a whole, resulting in that the two-way traffic of the communication port cannot be fully utilized, and the embodiment of the present disclosure introduces a finer-grained transmission control When any processor in the ring topology receives task data sent by the host computer, the processor will allocate task data to multiple computing units according to the data packet. The task data of each computing unit includes multiple data blocks. The data transmission direction of each data block can be determined based on the preset rules, so that each computing unit can send the data in the current data block to the previous processor or the next processor according to the corresponding data transmission direction, and process the data sent by another processor in the next data block, so that the bidirectional traffic of the communication port between the processors can be effectively utilized, so that the data can flow in two directions at the same time, and then realize bidirectional communication in the ring topology formed by multiple processors, so as to avoid the waste of communication resources and improve the data transmission efficiency and computing performance of multiple processors; and because the embodiment of the present disclosure does not require additional network equipment such as switches during the implementation process, it can effectively reduce the deployment cost and complexity of the multi-processor system. In summary, the embodiment of the present disclosure provides a multi-processor ring communication method, ring topology structure and equipment, which can improve the data transmission efficiency and computing performance of multiple processors at a low cost.

[0018] Other features and advantages of the present disclosure will be described in the following description, and partly become apparent from the description, or understood by practicing the present disclosure. The purpose and other advantages of the present disclosure can be realized and obtained by the structures particularly pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings are used to provide further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure.

[0020] Figure 1is a schematic diagram of a ring topology structure formed by sequentially physically connecting multiple processors in some embodiments of the present disclosure;

[0021] Figure 2 is a main flow chart of a ring communication method in some embodiments of the present disclosure;

[0022] Figure 3 is a schematic diagram of each computing unit dividing data segments in some embodiments of the present disclosure;

[0023] Figure 4 is a schematic diagram of data transmission based on the unit sequence number of the computing unit in some embodiments of the present disclosure;

[0024] Figure 5 is a schematic diagram of data transmission based on data numbers of data blocks in some embodiments of the present disclosure;

[0025] Figure 6 is a schematic diagram of a loop data workflow in some embodiments of the present disclosure;

[0026] Figure 7 It is a schematic diagram of the effect of one-way communication in the existing scheme;

[0027] Figure 8 is a schematic diagram of the effect of two-way communication in a ring communication method in some embodiments of the present disclosure;

[0028] Fig. 9 is another schematic diagram of a ring topology structure formed by sequentially physically connecting multiple processors in some embodiments of the present disclosure;

[0029] Fig.10 is a main flow chart of sending data in a current data block in some embodiments of the present disclosure;

[0030] Fig.11 It is a specific schematic diagram of a ring topology structure formed by sequentially physically connecting multiple processors in some embodiments of the present disclosure. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solution and advantages of the present disclosure more clear, the present disclosure is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present disclosure and are not used to limit the present disclosure.

[0032] Before further describing the embodiments of the present disclosure in detail, the nouns and terms involved in the embodiments of the present disclosure are described. The nouns and terms involved in the embodiments of the present disclosure are subject to the following interpretations:

[0033] Processor: used to process data, widely used in high-performance computing, deep learning, scientific computing and other fields. In the present disclosure, multiple processors are physically connected in sequence to form a ring topology structure. Each processor node in the ring topology structure is connected to two adjacent nodes to form a closed loop, allowing data to flow in the loop.

[0034] Connection order: refers to the arrangement order of multiple processors in a ring topology. Each processor is assigned a connection number based on its position to determine its relative position in the network.

[0035] Previous processor / Next processor: For a specific processor, its "previous" processor refers to the previous processor in its connection order, and its "next" processor refers to the next processor. For example, in a ring topology of 8 processors, for processor numbered 3, its previous processor is processor numbered 2, and its next processor is processor numbered 4.

[0036] Data processing module: The module inside the processor that is responsible for executing computing tasks. It may include a command processing unit and multiple computing units, which are used to parse task instructions, assign computing tasks, perform calculations, and integrate results.

[0037] Data transmission unit: a module inside a processor responsible for data transmission, which may include two transmission interfaces, for example, a first transmission interface and a second transmission interface, which are used to communicate with the adjacent previous processor and next processor respectively.

[0038] Command Processing Unit (CP): Responsible for parsing task instructions, allocating computing tasks, and coordinating operations between computing units and data transmission units, ensuring seamless connection between computing and transmission.

[0039] Computing unit: Multiple independent computing units in the data processing module are responsible for performing specific computing tasks. Each computing unit can process different data blocks in parallel to improve computing efficiency.

[0040] Transmission interface: A physical interface in a data transmission unit used to exchange data with other processors. For example, each processor has two transmission interfaces, which are connected to the adjacent previous processor and the next processor respectively.

[0041] RoCEv2 protocol: A remote direct memory access (RDMA) protocol based on Ethernet that allows efficient data transfer, especially in a distributed computing environment. For example, in the present disclosure, data transfer between processors is implemented via the RoCEv2 protocol to ensure low latency and high bandwidth.

[0042] Board-level copper wires are wires used to physically connect multiple processors, which enables multiple processors in the present disclosure to be integrated on a server motherboard.

[0043] Server node: can be a physical server, including multiple processors and other computing resources, such as CPU, memory, etc. In the present disclosure, multiple processors are deployed in the same server node and physically connected through board-level copper wires to form a ring topology.

[0044] In modern high-performance computing and deep learning applications, the use of multi-processor systems is becoming increasingly popular. These systems can significantly improve data processing speed and parallel computing capabilities. In order to achieve efficient communication between multiple processors, the following technologies are currently used: shared memory, P2P (Peer-to-Peer) communication, NVIDIA's proprietary NVLINK technology, and Socket based on network interface card (NIC) and Ethernet protocol (such as RoCEv2); these technologies each have certain advantages, such as shared memory is simple and easy to use, P2P communication provides high transmission efficiency, NVLINK supports extremely high bandwidth and low latency, and Socket is suitable for large-scale distributed computing environments. However, existing multi-processor communication technologies generally have limitations in terms of cost or performance. For example, the shared memory method relies on CPU participation, resulting in lower performance and additional data handling overhead; P2P has high requirements for hardware configuration and poor support from server platforms; NVLINK is limited to products from specific manufacturers, limiting the interoperability of cross-brand devices; the Socket method requires additional expensive hardware such as optical modules and switches, which has high deployment costs and complex maintenance; in addition, in existing multi-processor communication technologies, multiple computing units within the processor will act as a whole and transmit in a single direction in sequence, which cannot achieve fine-grained two-way communication and limits data transmission efficiency; therefore, there is a need for a solution that can improve the data transmission efficiency and computing performance of multi-processors at a low cost.

[0045] Based on this, the present disclosure proposes a ring communication method, a ring topology structure and a device. The method is applied to a ring communication device, which includes multiple processors that are physically connected in sequence to form a ring topology structure. Each computing unit in each processor can send data in a data block to the corresponding computing unit in the previous processor or the next processor based on the data transmission direction corresponding to the data block, so as to realize two-way communication, which can improve the data transmission efficiency and computing performance of multiple processors at a low cost.

[0046] In some embodiments, the processor may be a computing component such as a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose graphics processing unit computing (GPGPU), a neural network processor (NPU), a tensor processing unit (TPU), etc. These different processor types are each used to process specific types of tasks; for example, when the task involves graphics processing related work, such as image recognition, animation rendering, and other operations that require a large amount of parallel computing, a graphics processing unit (GPU) can be selected as the computing component deployed in the method of the present application, and for running an operating system, executing conventional applications or other wide-ranging computing tasks, a central processing unit (CPU) can be selected as the computing component deployed in the method of the present application to efficiently manage system resources and execute various types of instructions. In addition, for deep learning and artificial intelligence applications, a neural network processor (NPU) or a tensor processing unit (TPU) can also be selected as the computing component deployed in the method of the present application to process large-scale matrix operations and machine learning algorithm tasks; it can be understood that according to specific application scenarios and technical requirements, those skilled in the art can select corresponding computing components to execute the method of the present application to effectively improve the performance and efficiency of the system.

[0047] The embodiments disclosed in this application are further described below in conjunction with the accompanying drawings.

[0048] Description of the ring topology structure applied in the embodiment of the present disclosure, and the overall implementation method of the ring communication method in the embodiment of the present disclosure

[0049] refer to Figure 1 , Figure 1 In some embodiments of the present disclosure, taking a graphics processor as an example, a plurality of graphics processors 110 are physically connected in sequence to form a ring topology structure 100. The ring communication method in the present disclosure is applied to a ring communication device, and the ring communication device may include the following: Figure 1 As shown, a plurality of graphics processors 110 are physically connected in sequence to form a ring topology structure 100 , and each graphics processor 110 includes a plurality of computing units 112 , a command processing unit 111 and a data transmission unit 113 .

[0050] refer to Figure 2 , Figure 2 is a main flow chart of a ring communication method in some embodiments of the present disclosure, wherein for each processor in the ring topology structure 100, the ring communication method includes at least the following steps:

[0051] Step S210, the processor determines the previous processor and the next processor adjacent to itself in the ring topology structure based on the connection sequence corresponding to the ring topology structure;

[0052] Step S220, when receiving a data packet sent by the host computer, the processor allocates task data to multiple computing units according to the data packet, the task data of each computing unit includes multiple data blocks, and the data transmission direction of each data block is determined based on a preset rule;

[0053] Step S230, for each computing unit, the data in the current data block is sent to the previous processor or the next processor according to the corresponding data transmission direction, and data processing is performed on the data sent by another processor in the next data block.

[0054] In some embodiments, the preset rule includes: determining the data transmission direction of the data block based on the unit sequence number of the computing unit; or determining the data transmission direction of the data block based on the data number of the data block.

[0055] Wherein, based on the above steps S210 to S230, Figure 1Taking the multiple graphics processors 110 in the example, the method of the present disclosure can be applied to the physical ring topology structure 100 formed by directly connecting multiple graphics processors 110 through board-level copper wires. In this structure, each computing unit 112 in each processor can select the data transmission direction based on its own unit number, or determine the data transmission direction of the data block based on the data number of the data block, and then send the data in the data block to the corresponding computing unit 112 in the previous processor or the next processor according to the corresponding data transmission direction to achieve two-way communication; it can be understood that, in the traditional solution, although each processor contains multiple computing units 112, the multiple computing units 112 usually share a single transmission channel for communicating with external devices or other processors, and the data of the multiple processors are transmitted in sequence in a single direction as a whole, resulting in that the two-way traffic of the communication port cannot be fully utilized, and the embodiment of the present disclosure uses A finer-grained transmission control is introduced. When any processor in the ring topology receives task data sent by the host computer, the processor will allocate task data to multiple computing units according to the data packet. The task data of each computing unit includes multiple data blocks. The data transmission direction of each data block can be determined based on preset rules, so that each computing unit can send the data in the current data block to the previous processor or the next processor according to the corresponding data transmission direction, and process the data sent by another processor in the next data block, so that the bidirectional traffic of the communication port between each processor can be effectively utilized, so that data can flow in two directions at the same time, and then realize bidirectional communication in the ring topology formed by multiple processors, so as to avoid the waste of communication resources and improve the data transmission efficiency and computing performance of multiple processors; and because the embodiment of the present disclosure does not require additional network equipment such as switches during implementation, it can effectively reduce the deployment cost and complexity of the multi-processor system. In summary, the embodiment of the present disclosure provides a multi-processor ring communication method, ring topology structure and equipment, which can improve the data transmission efficiency and computing performance of multiple processors at a low cost.

[0056] It is worth noting that in traditional multi-processor communication schemes, multi-processors can usually only send information to the next adjacent processor, that is, only one-way data transmission is supported. Specifically, traditional multi-processor communication schemes lack fine-grained transmission control. In a ring topology, all data flows in a fixed direction, such as clockwise or counterclockwise. This means that at any time, only half of the traffic in the corresponding direction of the communication port in the ring link is used for actual data transmission, while the other half in the opposite direction is idle. One-way transmission causes the bidirectional traffic of the communication port to be unable to be fully utilized, and the overall transmission performance can only reach half of the system's maximum transmission capacity. It is understandable that the above design limits the efficiency of data transmission, especially in application scenarios that require high bandwidth and low latency. In contrast, based on the embodiments of the present disclosure, taking the graphics processor as an example, when any graphics processor 110 in the ring topology 100 receives task data sent by the host computer, the graphics processor 110 will process the data and send the processed data to the previous or next graphics processor 130 according to the preset rules. For example, when the preset rule is to determine the data transmission direction of the data block based on the unit sequence number of the computing unit, each graphics processor 110 can determine its own transmission direction according to its connection sequence number. The odd-numbered graphics processors 110 can choose one direction, and the even-numbered graphics processors 110 can choose another direction, so that the data on the ring can flow in two directions at the same time, and the communication port is no longer idle, thereby avoiding the waste of resources in unidirectional transmission, improving the efficiency of data transmission, and making full use of the bandwidth of the entire ring link. Because the communication channels in both directions can be used at the same time point, the transmission performance of the present disclosure can be theoretically doubled.

[0057] Each step is described in detail below.

[0058] In step 210, Figure 1For example, the graphics processor 110 determines its own connection position in the ring topology 100, as well as its own adjacent previous graphics processor 120 and next graphics processor 130 in the ring topology 100 based on the connection sequence corresponding to the ring topology 100; it can be understood that in the ring topology 100, each graphics processor 110 is assigned a unique connection sequence number. For example, from 0 to 7. These sequences are arranged in sequence according to the order of physical connection to form a closed loop, and each graphics processor 110 can know its position in the network and its adjacent graphics processors 110 through physical connection; for example, in the ring topology of 8 graphics processors 110, the previous graphics processor 110 numbered 0 is the graphics processor 110 numbered 7, and the next is the graphics processor 110 numbered 1; the previous graphics processor 110 numbered 1 is the graphics processor 110 numbered 0, and the next is the graphics processor 110 numbered 2, and so on. Each graphics processor 110 can determine its previous graphics processor 120 and next graphics processor 130 according to its connection sequence number. For example, for a graphics processor 110 numbered 3, its previous one is a graphics processor 110 numbered 2, and its next one is a graphics processor 110 numbered 4.

[0059] In step S220, Figure 1 For example, when the graphics processor 110 receives a data packet sent by the host computer, the graphics processor 110 can allocate specific task data to the internal multiple computing units 112 according to the content of the data packet. At the same time, in order to achieve efficient data transmission, the graphics processor 110 can determine in which direction the data of each computing unit 112 should be transmitted based on the unit sequence number of each computing unit 112, so that when each computing unit 112 receives the task data divided by the graphics processor 110 for it, the task data can be re-divided into multiple data blocks, and different data parts can be processed concurrently; or, when the graphics processor 110 receives a data packet sent by the host computer, the graphics processor 110 can also divide the data packet according to the content to obtain multiple data blocks, and send the multiple data blocks as task data to the multiple computing units 112 respectively, so that the task data of the multiple computing units 112 include multiple data blocks, and the data transmission direction of each data block can be determined based on the data number of the data block.

[0060] In step S230, Figure 1Taking the multiple graphics processors 110 in the example, each computing unit will transfer the data of the current data block to the adjacent processor according to the data transmission direction corresponding to the assigned data blocks, and while sending the data of the current data block, process the data sent to the next data block from the adjacent processor on the other side to form a continuous data processing flow, so that each computing unit can process the incoming data in the order of the data blocks and output the processed results to the adjacent processor, thereby realizing two-way communication in the ring topology formed by multiple processors.

[0061] refer to Figure 3 and Figure 4 , Figure 3 is a schematic diagram of data transmission based on data blocks in some embodiments of the present disclosure;

[0062] Figure 4 is a main flow chart of a ring communication method in some embodiments of the present disclosure; in some embodiments, Figure 3 For example, the ring topology may include GPU0-GPU1-GPU2-GPU3 connected in sequence, wherein each GPU includes two computing units: computing unit 0 and computing unit 1, and each computing unit divides the corresponding task data into four data blocks:

[0063] The data blocks of GPU0-computing unit 0 are a0, a1, a2, a3; the data blocks of GPU0-computing unit 1 are e0, e1, e2, e3;

[0064] The data blocks of GPU1-computing unit 0 are b0, b1, b2, b3; the data blocks of GPU1-computing unit 1 are f0, f1, f2, f3;

[0065] The data blocks of GPU2-computing unit 0 are c0, c1, c2, c3; the data blocks of GPU2-computing unit 1 are g0, g1, g2, g3;

[0066] The data blocks of GPU3-computing unit 0 are d0, d1, d2, d3; the data blocks of GPU3-computing unit 1 are h0, h1, h2, h3;

[0067] Among them, according to the connection order of the processors in the ring topology structure, the previous processor and the next processor of each processor can be determined, for example, the initial current data block of GPU0-computing unit 0 is a0, and the next data block is a3; the initial current data block of GPU1-computing unit 0 is b0, and the next data block is b3; the initial current data block of GPU2-computing unit 0 is c0, and the next data block is c3; the initial current data block of GPU3-computing unit 0 is d0, and the next data block is d3; the initial current data block of GPU0-computing unit 1 is e0, and the next data block is e1; the initial current data block of GPU1-computing unit 1 is f0, and the next data block is f1; the initial current data block of GPU2-computing unit 1 is g0, and the next data block is g1; the initial current data block of GPU3-computing unit 1 is h0, and the next data block is h1.

[0068] Corresponding to the above step S230, the current area can be understood as a0 of GPU0-C0, and the next area can be understood as a3 of GPU0-C0. After receiving the data packet from the host computer, GPU0-C0 sends the current area a0 to the next processor b0 of GPU1-C0, and processes the data (d3) sent by another processor GPU3-C0 in the next data block a3.

[0069] In some embodiments, after dividing the corresponding task data into multiple data blocks, the method also includes: determining the data block to be sent as the current data block from the multiple data blocks based on the connection order, and determining the data block receiving data from another processor for processing as the next data block; after processing the task data sent by another processor in the next data block, the method also includes: updating the next data block as the new current data block, so as to send the data obtained after data processing in the next data block to the previous processor or the next processor according to the corresponding data transmission direction, and determine the new next data block from the multiple data blocks.

[0070] It can be understood that the initial positions of the current data block and the next data block in the present application scheme can be determined according to the connection order of the processors, and are subsequently updated according to the sending and receiving of data. For example, after processing the data (d3) sent by another processor GPU3-C0 in the next data block a3, GPU0-C0 determines and updates a3 as the new current area, sends the processed d3 to b3 of GPU1-C0, and re-determines a2 as the new next data block.

[0071] In some embodiments, corresponding to Figure 4, arrow ① indicates that a0 of GPU0-computing unit 0 is sent to b0 of GPU1-computing unit 0, arrow ② indicates that b1 of GPU1-computing unit 0 is sent to c1 of GPU2-computing unit 0, arrow ③ indicates that c2 of GPU2-computing unit 0 is sent to d2 of GPU3-computing unit 0, arrow ④ indicates that d3 of GPU3-computing unit 0 is sent to a3 of GPU0-computing unit 0, and arrow ⑤ indicates that a3 of GPU0-computing unit 0 is sent to b3 of GPU1-computing unit 0, wherein each computing unit of each processor can concurrently process multiple data blocks of task data in the order shown in the figure, thereby realizing bidirectional communication in the ring topology structure formed by multiple processors.

[0072] refer to Figure 5 is a schematic diagram of data transmission based on data blocks in some embodiments of the present disclosure; in some embodiments, determining the data transmission direction of a data block based on the data number of the data block includes: allocating a data transmission direction for the data block from a previous processor and a next processor according to the size or parity of the data number of the data block; Figure 5 As shown, when the data blocks of GPU0 include a0, a1, a2, a3, a4, a5, a6, and a7, GPU0 can determine the data transmission direction of a0, a1, a2, and a3 as GPU1, and determine the data transmission direction of a4, a5, a6, and a7 as GPU3 according to the size of the data numbers.

[0073] It can be understood that the scheme of determining the data transmission direction of the data block based on the unit serial number of the computing unit does not need to assign a direction to each data block separately, and can quickly and effectively determine the transmission direction; and compared with the scheme of determining the data transmission direction of the data block based on the unit serial number of the computing unit, by determining the data transmission direction of the data block based on the data number of the data block, the present application does not need to assign a fixed data transmission direction to each computing unit. Each computing unit can directly send the data in the current data block to the previous processor or the next processor according to the corresponding data transmission direction in the data block, and process the data sent by another processor in the next data block, and can perform fine-grained transmission control more flexibly, so that the transmission data of each computing unit can flow in two directions simultaneously, thereby realizing two-way communication in the ring topology formed by multiple processors.

[0074] It is worth noting that in the scheme of determining the data transmission direction of a data block based on the data number of the data block, since the transmission direction of the data block is determined by the corresponding data number, how to allocate task data to each computing unit or how each computing unit is specifically scheduled will not affect the implementation of the above scheme, and technical personnel in this field can choose from the above two preset rules according to transmission requirements, thereby realizing different types of two-way communications.

[0075] refer to Figure 6 , Figure 6 is a schematic diagram of a loop data workflow in some embodiments of the present disclosure, Figure 6 The detailed steps of a complete loop data workflow in a ring communication method are shown; in some embodiments, corresponding to step 0 to step 6, the specific explanations are as follows:

[0076] In step 0, the system is in the initialization state. Each GPU (GPU0, GPU1, GPU2, GPU3) contains a set of initial data blocks. The data blocks of each GPU are distributed as follows:

[0077] GPU0:a0,a1,a2,a3; GPU1:b0,b1,b2,b3;

[0078] GPU2:c0,c1,c2,c3; GPU3:d0,d1,d2,d3;

[0079] The computing unit of each GPU determines the transmission direction of the data block according to a preset rule. At this time, the data block has not yet started to be transmitted, and all data resides in their respective GPUs.

[0080] In step 1, each GPU determines the transmission direction of the data block according to a preset rule (such as the unit sequence number of the computing unit), and starts to send the data block to the previous processor or the next processor. For example, GPU0 sends a0 to GPU1, and GPU1 stores it at the position of b0 to obtain a0+b0; at the same time, each GPU receives the data block sent by the adjacent processor and stores it in the corresponding receiving buffer. For example, GPU0 receives d3 sent by GPU3 and stores it at the position of a3 to obtain d3+a3; it can be understood that this step is the process of sending the data in the current data block to the previous processor or the next processor according to the corresponding data transmission direction in the present application, and processing the data sent by another processor in the next data block.

[0081] In step 2, each GPU needs to determine that the data block received from another processor for processing is the next data block, and update the next data block to the new current data block, so as to send the data obtained after data processing in the next data block to the previous processor or the next processor according to the corresponding data transmission direction, and determine the new next data block from multiple data blocks. For example, GPU0 receives GPU3 data in step 1 and stores it at position a3 to obtain d3+a3, which is the new current data block. Therefore, in step 2, GPU0 can send d3+a3 to GPU1, and GPU1 stores it at position b3 to obtain d3+a3+b3; conversely, GPU0 will receive c2+d2 sent by GPU3 in step 2 and store it at position a2 to obtain c2+d2+a2, which is the new next data block.

[0082] In step 3, each GPU will again determine that the data block receiving data from another processor for processing is the next data block, and update the next data block to the new current data block, and determine the new next data block from multiple data blocks, thereby realizing the traversal of multiple data blocks in the GPU, so that each data block involves the reception and transmission of data, thereby forming a loop data workflow to realize two-way control of data; for example, GPU0 receives GPU3 data in step 2 and stores it at position a2, and obtains c2+d2+a2, which is the new current data block, so in step 3 GPU0 can send c2+d2+a2 to GPU1, and GPU1 stores it at position b2, and obtains c2+d2+a2+b2; conversely, GPU0 will receive b1+c1+d1 sent by GPU3 in step 3, and store it at position a1, and obtain b1+c1+d1+a1, which is the new next data block.

[0083] Through the above step 0 to step 3, the loop data workflow and bidirectional control in the ring communication can be realized. Similarly, in step 4 to step 6, each GPU can still transmit and receive data in multiple data blocks in turn according to the determined data of the current data block and the next data block in step 1 to step 3, so that the data blocks of each GPU can complete data accumulation. As shown in step 6, each data unit in each GPU accumulates corresponding a, b, c and d data. For example, the a0 position of GPU0 accumulates a0, b0, c0 and d0 data. Through the above steps, Figure 6The complete process of the loop data workflow in the ring communication method is demonstrated. Each GPU determines the transmission direction of the data block according to preset rules, and realizes efficient data transmission and processing through bidirectional control. It can fully utilize the bidirectional communication capability of the ring topology structure, thereby improving data transmission efficiency and computing performance.

[0084] refer to Figure 7 and Figure 8 , Figure 7 It is a schematic diagram of the effect of one-way communication in the existing scheme; Figure 8 1 is a schematic diagram of the effect of bidirectional communication in the ring communication method of multiple graphics processors 110 in some embodiments of the present disclosure; TxBuffer represents the transmission buffer of the graphics processor 110, corresponding to the process of communication and transmission of task data among multiple computing units in the graphics processor, T0 represents the period of communication and transmission of task data, and in some embodiments, it is specifically described as follows:

[0085] exist Figure 7 In the figure, we can see that multiple computing units (computing unit 0 to computing unit 7) in the graphics processor transmit data through unidirectional communication. Multiple computing units can only send data to the computing unit of the next adjacent processor through Port0 in turn. This unidirectional communication method causes the two-way traffic of the communication port to be unable to be fully utilized, because at a point in time, only one direction of the communication channel is used, while the other direction is idle, which limits the efficiency of data transmission.

[0086] exist Figure 8 In the figure, it can be seen that the bidirectional communication method in the embodiment of the present disclosure, each computing unit can choose to send data to the computing unit in the previous or next adjacent processor according to the preset rules. For example, computing unit 0, computing unit 2, computing unit 4, and computing unit 6 can respectively send data to the computing unit in the previous adjacent processor through Port0, and computing unit 1, computing unit 3, computing unit 5, and computing unit 7 can respectively send data to the computing unit in the next adjacent processor through Port1, so that data can flow in two directions simultaneously in the ring topology structure 100, thereby effectively utilizing the bidirectional traffic of the communication ports between each graphics processor 110.

[0087] In some embodiments, corresponding to Figure 8Taking the graphics processor as an example, each graphics processor 110 determines the data transmission direction from the previous graphics processor 120 and the next graphics processor 130 based on a preset rule. When the graphics processor 110 receives the data packet sent by the host computer, the graphics processor 110 can allocate task data to multiple computing units according to the data packet, and allocate data transmission directions to the multiple computing units based on the unit sequence numbers of the computing units; for each computing unit, the corresponding task data is divided into multiple data blocks, and the data in the current data block is sent to the previous processor or the next processor according to the corresponding data transmission direction, and data processing is performed on the data sent by another processor in the next data block.

[0088] In summary, the present disclosure enables each graphics processor 110 to know its own connection position and the adjacent graphics processor 110 after deployment, and determines the sending direction based on the preset rules configured in advance, and determines the data transmission direction corresponding to the connection position from the previous graphics processor 120 and the next graphics processor 130. Then, when receiving the computing task data from the host computer, the processed data is sent according to the data transmission direction, so that each graphics processor 110 can send data to the adjacent previous graphics processor 120 or the next graphics processor 130 according to the connection position, thereby realizing two-way communication in the loop formed by multiple graphics processors 110, effectively utilizing the two-way traffic of the communication port, and improving the transmission performance.

[0089] Detailed description of allocating data transmission directions for multiple computing units based on the unit sequence number of the computing units

[0090] In some embodiments, reference Figure 1 It can be understood that, since the position and adjacent nodes of each graphics processor 110 in the ring topology 100 are fixed, in order to maximize the use of the bidirectional traffic of the communication port and optimize the data transmission path, a mechanism is needed to dynamically determine the data transmission direction; based on this, the present application can be for each computing unit: if the unit sequence number of the computing unit is an odd number, one of the previous processor and the next processor is determined as the data transmission direction of all data blocks in the computing unit; if the unit sequence number of the computing unit is an even number, the other of the previous processor and the next processor is determined as the data transmission direction of all data blocks in the computing unit. Further, in the process of sending the data in the current data block to the previous processor or the next processor according to the corresponding data transmission direction, the unit sequence number can be judged. If the unit sequence number of the computing unit is an even number, the other of the previous processor and the next processor is determined as the data transmission direction of all data blocks in the computing unit; if the unit sequence number of the computing unit is an even number, the data in the current data block is sent to the corresponding data block of another computing unit with an even number in the previous processor.

[0091] In some embodiments, if the unit sequence number of a computing unit is an odd number (e.g., 1, 3, 5, 7, etc.), the computing unit will select one of the previous processor or the next processor as its data transmission direction. For example, in a ring topology, the computing unit with an odd number will send data to the corresponding computing unit in the next adjacent processor. Specifically, assuming that the unit sequence number of a computing unit in a graphics processor is an odd number, it will send the data of the current data block to the odd-numbered computing unit in the next processor.

[0092] In some embodiments, if the unit sequence number of a computing unit is an even number (e.g., 0, 2, 4, 6, etc.), the computing unit will select the other of the previous processor or the next processor as its data transmission direction. For example, in a ring topology, the computing unit with an even number will send data to the corresponding computing unit in the previous adjacent processor. Specifically, assuming that the unit sequence number of a computing unit in a graphics processor is an even number, it will send the data of the current data block to the even-numbered computing unit in the previous processor.

[0093] refer to Fig. 9 , Fig. 9 is another schematic diagram of a ring topology structure formed by sequentially physically connecting multiple processors in some embodiments of the present disclosure; each processor includes a command processing unit 111, a data transmission unit 113, and multiple computing units 112, the data transmission unit includes a first transmission interface and a second transmission interface, the data transmission unit is physically connected to the second transmission interface of the previous processor through the first transmission interface, and the data transmission unit is physically connected to the first transmission interface of the next processor through the second transmission interface; wherein, Figure 8 It can be seen that the graphics processor 110, the previous graphics processor 120, and the next graphics processor 130 are physically connected to form a ring topology 100, wherein the command processing unit 111 is responsible for receiving and parsing commands from the host computer, and distributing the commands to the corresponding computing units 112, and the multiple computing units 112 perform specific computing tasks, process data and generate results; the first transmission interface Port0 is used for data transmission with the second transmission interface Port1 of the previous graphics processor 120; the second transmission interface Port1 is used for data transmission with the first transmission interface Port0 of the next graphics processor 130.

[0094] It can be understood that the graphics processor 110 receives data from the previous graphics processor 120 through the first transmission interface Port0, the command processing unit 111 parses the command, and distributes the data to the corresponding computing unit 112 for processing. After the computing unit 112 processes the data, it sends the result to the next graphics processor 130 through the first transmission interface Port0 of the data transmission unit 113. At the same time, the graphics processor 110 can also receive data from the next graphics processor 130 through the second transmission interface Port1 and perform corresponding processing. The above-mentioned bidirectional interface design ensures that data can flow bidirectionally in the ring topology 100.

[0095] In some embodiments, the computing unit performs data processing on the data sent by another processor in the next data block, which may include but is not limited to calculation, conversion or any other form of data operation, and outputs the generated processed task data, which is the result obtained after a series of operations on the first task data; specifically, Fig. 9 , the command processing unit 111 and the plurality of computing units 112 will send the processed task data together with the specified data transmission direction to the data transmission unit 113. The data transmission direction determines in which direction the next task data should be transmitted, to the upper graphics processor 120 or to the lower graphics processor 130, so as to ensure that the data transmission unit 113 clearly understands to which adjacent graphics processor 110 the processed task data should be sent, so as to maintain the orderly communication in the ring topology 100; the processed task data and the data transmission direction are input, and the data transmission unit 113 sends the processed task data to the upper graphics processor 120 or the next graphics processor 130 through its corresponding transmission interface, the first transmission interface or the second transmission interface according to the received data transmission direction indication, and the processed task data is successfully sent to the specified next processing node, that is, the corresponding computing unit in the upper graphics processor 120 or the next graphics processor 130, so as to continue the subsequent processing or forwarding.

[0096] It can be understood that the command processing unit is responsible for all tasks related to data processing, including receiving data packets as raw task data, performing necessary calculations or transformations, and generating processed task data. The data transmission unit 113 is used for physical transmission of data, and relies on a clear transmission direction to determine the direction of data flow, so as to allow the graphics processor 110 to not only receive data from two different directions, but also send data to one of the two directions, which enhances the flexibility and fault tolerance of the system. Through the above steps, the graphics processor 110 can effectively process and transmit task data, thereby realizing two-way communication in the ring topology formed by multiple processors, and can improve the data transmission efficiency and computing performance of multiple processors at a low cost.

[0097] refer to Fig.10 , Fig.10 The main flow chart of sending data in the current data block in some embodiments of the present disclosure; in some embodiments, sending the data in the current data block to the upper processor or the next processor according to the data transmission direction by the data transmission unit at least includes the following steps:

[0098] Step S1010, when the sending target corresponding to the data transmission direction is the previous processor, sending the data in the current data block through the first transmission interface;

[0099] Step S1020: When the sending target corresponding to the data transmission direction is the next processor, the data in the current data block is sent through the second transmission interface.

[0100] In some embodiments, the data transmission unit 113 includes a first transmission interface and a second transmission interface, the data transmission unit 113 is physically connected to the second transmission interface of the previous graphics processor 120 through the first transmission interface, and the data transmission unit 113 is physically connected to the first transmission interface of the next graphics processor 130 through the second transmission interface; the data transmission unit 113 sends the data in the current data block to the previous graphics processor 120 or the next graphics processor 130 according to the data transmission direction, including: when the sending target corresponding to the data transmission direction is the previous graphics processor 120, the data in the current data block is sent through the first transmission interface; when the sending target corresponding to the data transmission direction is the next graphics processor 130, the data in the current data block is sent through the second transmission interface; wherein, the design and implementation of the data transmission unit 113 is intended to ensure data exchange between graphics processors 110, and the module includes a first transmission interface and a second transmission interface, and the two interfaces are respectively used to physically connect with adjacent graphics processors 110.

[0101] Exemplarily, in some embodiments, the first transmission interface and the second transmission interface can be implemented based on high-speed interconnection technology, and for the sake of signal integrity during transmission, the transmission interface can use differential signal transmission. If the sending target corresponding to the data transmission direction is the previous graphics processor 120, it means that the data in the current data block will be transmitted to the previous graphics processor 120 along the reverse link; if the sending target corresponding to the data transmission direction is the next graphics processor 130, it means that the data in the current data block will be transmitted to the next graphics processor 130 along the forward link.

[0102] Exemplarily, in some embodiments, the first transmission interface and the second transmission interface can also be used for confirmation and feedback of data signals. After the data segment is sent out, the data transmission unit 113 can be used to wait for the confirmation signal from the receiver. For example, a confirmation message is used to indicate that the data has been successfully received and there are no errors. If no confirmation signal is received within a certain period of time, or a negative confirmation message is received, the data transmission unit 113 will start the retransmission mechanism and resend the entire data segment or only retransmit the damaged part.

[0103] In some embodiments, data processing is performed on data sent by another processor in a next data block, including: when the computing unit sends data in a current data block to an upper processor, data processing is performed on data sent by the next processor in a next data block, so as to send the data obtained after the data processing to the upper processor; when the computing unit sends data in a current data block to a next processor, data processing is performed on data sent by the upper processor in the next data block, so as to send the data obtained after the data processing to the next processor.

[0104] In some embodiments, the processor includes a command processing unit. When receiving a data packet sent by a host computer, the processor allocates task data to multiple computing units 112 according to the data packet. The data packet may include command information and raw data. The command processing unit may first parse the command information in the data packet. The command information may be an operation instruction sent by the host computer (such as a CPU), which includes information such as the operation type, parameters, and data addresses involved in the operation. The command processing unit can identify these instructions and determine the type of operation to be performed and the specific data involved in the operation. Further, according to the parsed command information, the command processing unit decomposes the entire task in the data packet into multiple subtasks, each of which corresponds to one or more computing units 112. This step can divide the task according to data blocks, thread groups, or other logical units to better utilize the parallel processing capabilities of multiple computing units 112. Further, the command processing unit will dynamically allocate appropriate computing resources to each subtask according to the task requirements and the current system status, such as a specific computing unit 112, cache resources, memory bandwidth, etc., to ensure efficient task execution. Further, once the resource allocation is completed, the command processing unit will distribute the subtask and its related data to the corresponding computing unit 112, ready to enter the execution phase.

[0105] In some embodiments, the subtasks and associated data distributed by the command processing unit, multiple computing units 112 simultaneously start to execute the subtasks they have received, and each computing unit 112 can support hundreds or even thousands of parallel threads according to its internal architecture. For example, in NVIDIA's GPU, the computing unit 112 may be a streaming multiprocessor (SMs), each SM containing multiple CUDA cores; it is understandable that in order to improve computing efficiency, the computing unit 112 can use a series of optimization techniques, such as vectorized operations, pipeline processing, branch prediction, loop unrolling, etc.

[0106] In some embodiments, the computing unit 112 may also be generally equipped with shared memory and register files for storing temporary results and frequently accessed data, thereby reducing latency and improving performance by reducing the number of global memory accesses through reasonable local storage management.

[0107] In some embodiments, the command processing unit 111 can maintain one or more task queues for storing tasks to be processed. These queues can be sorted according to factors such as task priority and dependencies to ensure that tasks can be executed in the optimal order, and can support asynchronous task execution mode so that tasks can continue to run in the background, and the command processing unit 111 can immediately return control to the caller. When the task is completed, the caller can be notified through a callback function or an event trigger mechanism. In addition, when encountering abnormal situations such as hardware failure and communication interruption during actual operation, the command processing unit 111 can have an error handling mechanism, including error detection, logging, automatic recovery and other functions to ensure the stability and reliability of the system.

[0108] In some embodiments, it can be understood that when the graphics processor 110 receives the second task data sent by the previous graphics processor 120, the graphics processor 110 processes the second task data to obtain third task data, and sends the third task data to the next graphics processor 130; when the graphics processor 110 receives the second task data sent by the next graphics processor 130, the graphics processor 110 processes the second task data to obtain fourth task data, and sends the fourth task data to the previous graphics processor 120.

[0109] It is understandable that the ring communication method involves not only the initial transmission of data, but also the process of processing the received data before sending it to the next node. The following are the detailed steps and technical details of the process: Through the first transmission interface, the graphics processor 110 receives the second task data from the previous graphics processor 120. The received data packet is first passed to the transport layer protocol stack to parse the protocol header and extract the actual data content and related metadata. Further, the command processing unit 111 determines the type of operation to be performed and the data involved in the operation according to the received metadata, and assigns the task to the computing unit 112 with the corresponding unit number. The computing unit 112 with the corresponding unit number starts to perform the corresponding task. Each computing unit 112 can support hundreds or even thousands of parallel threads according to its internal architecture to quickly complete complex computing operations. The command processing unit 111 is responsible for collecting the processing results from each computing unit 112 and generating the third task data. Further, the third task data is subjected to necessary post-processing, such as packaging, compression, adding metadata, etc., so that it is ready to be transmitted to the next graphics processor 130. According to the ring topology 100, the graphics processor 110 sends the third task data to the next graphics processor 130 through the second transmission interface, which means that the data will continue to be transmitted along the forward link.

[0110] In some embodiments, the graphics processor 110 may receive the second task data from the next graphics processor 130 through the second transmission interface, and the received data packet is passed to the transport layer protocol stack to parse the protocol header and extract the actual data content and related metadata. The command processing unit 111 determines the type of operation to be performed and the data involved in the operation according to the received metadata, and assigns the task to the computing unit 112 with the corresponding unit number. Further, the computing unit 112 with the corresponding unit number starts to perform the corresponding task and quickly completes the complex computing operation. The command processing unit 111 is responsible for collecting the processing results from each computing unit 112 and generating the fourth task data. The process may involve operations such as data format conversion, aggregation operation, error detection and correction, etc. Further, the entire fourth task data is subjected to necessary post-processing, such as packaging, compression, adding metadata, etc., so that it is ready to be transmitted to the previous graphics processor 120. According to the ring topology 100, the graphics processor 110 sends the fourth task data to the previous graphics processor 120 through the first transmission interface, which means that the data will continue to be transmitted along the reverse link.

[0111] It is worth noting that if the unit sequence number of the computing unit is an odd number, the data in the current data block is sent to the corresponding data block of another computing unit with an odd number in the next processor; if the unit sequence number of the computing unit is an even number, the data in the current data block is sent to the corresponding data block of another computing unit with an even number in the previous processor. Therefore, according to the unit sequence number of the computing unit (odd or even), the data will continue to be transmitted along the forward link (clockwise) or the reverse link (counterclockwise). For example, suppose there is a ring consisting of 4 graphics processors (GPU0, GPU1, GPU2, GPU3). In the topological structure, the computing unit 1 of GPU1 is an odd-numbered computing unit, which will send the data of the current data block to the computing unit 1 of GPU2. After sending the data, the computing unit 1 of GPU2 will continue to send the data to the computing unit 1 of GPU3, and so on, until the data completes the transmission of the entire ring network; the computing unit 0 of GPU1 is an even-numbered computing unit, which will send the data of the current data block to the computing unit 0 of GPU0. After sending the data, the computing unit 0 of GPU0 will continue to send the data to the computing unit 0 of GPU3, and so on, until the data completes the transmission of the entire ring network.

[0112] It can be understood that in the GPU 110 cluster, through the above mechanism, each GPU 110 can not only process the task data from the host computer, but also process the data from the adjacent GPU 110, and pass the processing results to the next node. The following is an overall solution combining the two task processing flows, and how to achieve two-way transmission through this combination: When the GPU 110 receives a data packet sent by the host computer, the GPU can allocate the first task data to multiple computing units according to the data packet, and allocate data transmission directions to the multiple computing units based on the unit sequence numbers of the computing units. For each computing unit, the corresponding first task data is divided into multiple data blocks, and the data in the current data block is sent to the upper processor or the next processor according to the corresponding data transmission direction, and the next processor is sent to the next processor. The graphics processor 110 processes the data sent by another processor in a data block; when the graphics processor 110 receives the second task data sent by the previous graphics processor 120, the graphics processor 110 processes the second task data according to the above process to obtain the third task data, and sends the third task data to the next graphics processor 130; when the graphics processor 110 receives the second task data sent by the next graphics processor 130, the graphics processor 110 processes the second task data again according to the above process to obtain the fourth task data, and sends the fourth task data to the previous graphics processor 120; the above process can realize bidirectional transmission, ensuring that each graphics processor 110 can simultaneously process data streams from two different directions, and send the processing results to the corresponding next node as needed.

[0113] In some embodiments, the first transmission interface of the data transmission unit 113 and the second transmission interface of the previous graphics processor 120 perform data transmission via the RoCEv2 protocol, and the second transmission interface of the data transmission unit 113 and the first transmission interface of the next graphics processor 130 perform data transmission via the RoCEv2 protocol, wherein the first transmission interface of the data transmission unit 113 and the second transmission interface of the previous graphics processor 120 perform data transmission via the RoCEv2 protocol, and the second transmission interface of the data transmission unit 113 and the first transmission interface of the next graphics processor 130 also perform data transmission via the RoCEv2 protocol. This design not only ensures efficient and low-latency data transmission, but also supports complex communication modes such as ring communication and load balancing; the RoCEv2 protocol has the following advantages: RoCEv2 allows data to be directly transferred from the memory of one device to the memory of another device without the intervention of the CPU. This greatly reduces the burden on the CPU and improves the efficiency of data transmission; RoCEv2 is based on the standard Ethernet protocol and can be implemented on the existing network infrastructure, reducing deployment costs and complexity; compared with the traditional TCP / IP protocol, RoCEv2 provides lower latency and higher bandwidth, which can effectively avoid network congestion and ensure the stability and reliability of data transmission.

[0114] In some embodiments, the ring communication method further includes: when the graphics processor 110 processes the first task data or the second task data and obtains the task result, the task result is sent to the host computer; it is understandable that when the computing unit in the graphics processor 110 receives the task data sent by the adjacent graphics processor 110, it will select another interface to send subsequent data based on the interface from which the data comes, so as to ensure bidirectional transmission of data. For example, after receiving the data sent by the previous graphics processor 120, the computing unit in the graphics processor 110 will send it to the next graphics processor 130 after processing. Similarly, after processing the data sent by the next graphics processor 130, it will transmit it to the previous graphics processor 120. At this time, there are two directions of data flow on the loop; and it is worth noting that when a graphics processor 110 completes its part of the data processing, it sends the result to the next graphics processor 110 for load balancing and parallel processing of multiple subtasks. The above process only involves the situation where the task is not fully completed and needs to be processed again by the next graphics processor 110. If the current graphics processor 110 has completed all necessary processing of the task data, it will stop sending and can return the task result to the host computer.

[0115] It can be understood that when the computing unit receives the second task data sent by the previous graphics processor 120, the computing unit processes the second task data to obtain the third task data, and sends the third task data to the next graphics processor 130; when the computing unit receives the second task data sent by the next graphics processor 130, the computing unit processes the second task data to obtain the fourth task data, and sends the fourth task data to the previous graphics processor 120; in addition, each graphics processor 110 monitors the status of the task in real time when processing the task. If the computing unit in the current graphics processor 110 has completed all necessary processing and no longer needs further processing by the computing unit in other graphics processors 110, it will stop sending data and return the task result to the host computer. For example, the command processing unit 111 performs necessary post-processing on the task result, such as packaging, compression, adding metadata, etc., to prepare it to be transmitted to the host computer, and sends the task result back to the host computer through a preset communication channel (such as PCIe or InfiniBand). After receiving the task result, the host computer will send a confirmation signal to the graphics processor 110 to ensure successful data transmission.

[0116] In some embodiments, in order to achieve load balancing and parallel processing of multiple subtasks, the host computer can dynamically adjust task allocation according to the current load conditions of each image processor node; for example, if a graphics processor 110 finds that its upstream node is lightly loaded, it can choose to pass part of the task to the upstream node; conversely, if the downstream node is lightly loaded, it can choose to pass it to the downstream node, so that each graphics processor 110 can simultaneously process new task data from the host computer and intermediate results from adjacent nodes, making full use of its parallel processing capabilities to accelerate the completion of the entire task.

[0117] Description of the ring communication device of the present disclosure

[0118] According to another aspect of the present disclosure, a ring communication device is provided. The ring communication device includes: a plurality of processors that are physically connected in sequence to form a ring topology structure, each processor including a plurality of computing units; wherein, for each processor in the ring topology structure, the processor is used to: determine its own connection position in the ring topology structure, and its own adjacent previous processor and next processor in the ring topology structure based on the connection sequence corresponding to the ring topology structure; determine the data transmission direction corresponding to the connection position from the previous processor and the next processor based on a preset rule; when receiving a data packet sent by a host computer, the processor allocates task data to the plurality of computing units according to the data packet, and allocates data transmission directions to the plurality of computing units based on the unit sequence number of the computing unit; for each computing unit, the corresponding task data is divided into a plurality of data blocks, and the data in the current data block is sent to the previous processor or the next processor according to the corresponding data transmission direction, and data processing is performed on the data sent by another processor in the next data block.

[0119] According to the ring topology structure 100 provided by the present disclosure, the ring communication method is applied to the physical ring topology structure 100 formed by directly connecting multiple processors through board-level copper wires. In this structure, each processor can identify its adjacent previous processor and next processor based on determining its own position in the ring link, and enable multiple computing units inside it to select the data transmission direction according to the unit number; it can be understood that, since each processor in the traditional solution can only send information to the next processor adjacent to it, that is, only one-way data transmission is supported, resulting in that the bidirectional traffic of the communication port cannot be fully utilized, because at a point in time, only the communication channel in one direction is used, while the other direction is idle, which limits the efficiency of data transmission. Based on the embodiment of the present disclosure, when the ring topology structure 10 When any processor in 0 receives a data packet sent by the upper computer, each processor includes multiple computing units. For each computing unit, the data in the data block can be transmitted according to the corresponding data transmission direction, thereby realizing two-way communication in the ring topology structure 100 formed by multiple processors, that is, in the entire loop, data can flow in two directions at the same time, thereby effectively utilizing the two-way traffic of the communication ports between each processor. By introducing the above-mentioned two-way communication mechanism, the embodiment of the present disclosure can ensure the maximum utilization of the communication port, avoid resource waste, and enable multiple processors on the same computing node to work together more efficiently to complete complex parallel computing tasks. Moreover, since the embodiment of the present disclosure does not require additional network devices such as switches during implementation, the deployment cost and complexity of the multi-processor system can be effectively reduced. In summary, the embodiment of the present disclosure provides a ring communication method, a ring topology structure 100, and a device, which can improve the data transmission efficiency and computing performance of multiple processors at a low cost.

[0120] In some embodiments, the processor may be a graphics processor, the graphics processor includes a data processing module and a data transmission unit, the data processing module includes a command processing unit and multiple computing units, the processor also includes a command processing unit and a data transmission unit, the command processing unit is respectively communicated with the data transmission unit and the multiple computing units; wherein the command processing unit is used to allocate task data to multiple computing units according to data packets, the data transmission unit includes a first transmission interface and a second transmission interface, the data transmission unit is physically connected to the second transmission interface of the previous processor through the first transmission interface, and the data transmission unit is physically connected to the first transmission interface of the next processor through the second transmission interface; wherein the command processing unit can flexibly allocate tasks to multiple computing units, make full use of the parallel computing capability of the processor, improve processing efficiency, and separate data processing and data transmission functions, so that the system design is more modular and easy to maintain and expand.

[0121] In some embodiments, the data transmission unit 113 includes a first transmission interface and a second transmission interface, and the data transmission unit 113 is physically connected to the second transmission interface of the previous graphics processor through the first transmission interface, and the data transmission unit 113 is physically connected to the first transmission interface of the next graphics processor through the second transmission interface; wherein, the first transmission interface is used to send data to the previous graphics processor, and the second transmission interface is used to send data to the next graphics processor; wherein, when any graphics processor in the ring topology structure 100 receives a data packet sent by the host computer, the graphics processor will process the data and send the processed data to the adjacent graphics processor according to preset rules, thereby realizing bidirectional communication in the ring topology structure 100 formed by multiple graphics processors, that is, in the entire loop, data can flow in two directions at the same time, thereby effectively utilizing the bidirectional traffic of the communication ports between each graphics processor.

[0122] In some embodiments, the preset rules include: determining the data transmission direction of the data block based on the unit sequence number of the computing unit; or determining the data transmission direction of the data block based on the data number of the data block. In the case where the data transmission direction of the data block is determined based on the unit sequence number of the computing unit, the computing unit is also used to: determine the data block currently to be sent as the current data block from multiple data blocks based on the connection order, and determine the data block receiving data from another processor for processing as the next data block, and after processing the task data sent by another processor in the next data block, update the next data block to the new current data block, so as to send the data obtained after the data processing in the next data block to the previous processor or the next processor according to the corresponding data transmission direction, and determine the new next data block from multiple data blocks.

[0123] It can be understood that for each computing unit: if the unit serial number of the computing unit is an odd number, one of the previous processor and the next processor is assigned as the corresponding data transmission direction; if the unit serial number of the computing unit is an even number, the other of the previous processor and the next processor is assigned as the corresponding data transmission direction. Therefore, the task data sent by the host computer may not carry specific transmission direction information, and thus the fusion of the graphics processor task computing instructions and the graphics processor data transmission instructions can be achieved, so that the graphics processor is responsible for the synchronization between computing and transmission based on the physical connection relationship of the hardware ring structure, so as to improve the overall performance.

[0124] In some embodiments, the graphics processor is also used to process the task data, and after obtaining the task result, send the task result to the host computer.

[0125] In some embodiments, the first transmission interface of the data transmission unit 113 and the second transmission interface of the previous graphics processor are used for data transmission via the RoCEv2 protocol, and the second transmission interface of the data transmission unit 113 and the first transmission interface of the next graphics processor are used for data transmission via the RoCEv2 protocol.

[0126] refer to Fig.11 , Fig.11 1 is a specific schematic diagram of a ring topology structure 100 formed by physically connecting multiple graphics processors in sequence in some embodiments of the present disclosure: in some embodiments, the ring topology structure 100 includes eight graphics processors physically connected in sequence in a ring shape, the data transmission unit 113 of each graphics processor includes eight computing units, multiple graphics processors are deployed on the same server node, and the multiple graphics processors are physically connected through board-level copper wires. In a multi-graphics processor system, a multi-card interconnection solution physically connected through board-level copper wires avoids the use of high-cost optical modules and switches, and simplifies the deployment and maintenance of the system; wherein each graphics processor includes a command processing unit, a data transmission unit 113 and eight computing units; the data transmission unit 113 has two ports (port0 and port1), which are respectively used for data transmission with adjacent graphics processors. Specifically: the data transmission unit 113 of each graphics processor is connected to port1 of the previous graphics processor through port0, and is connected to port0 of the next graphics processor through port1. This connection method ensures that data can be transmitted bidirectionally in a ring topology; each graphics processor contains eight computing units, which can process task data in parallel to improve overall processing efficiency; multiple graphics processors are physically connected through board-level copper wires to ensure the stability and low latency of data transmission.

[0127] It can be understood that the above-mentioned ring topology structure 100 can achieve load balancing and parallel processing of multiple subtasks by supporting efficient bidirectional data transmission. When each computing unit in the graphics processor processes the task data and obtains the task result, the task result can be sent to the host computer.

[0128] The electronic device ring topology structure 100 disclosed in the present invention is used to execute the ring communication method as in the above embodiment, and its specific processing process is the same as the ring communication method in the above embodiment, which will not be repeated here.

[0129] Description of the electronic device of the present disclosure

[0130] In some embodiments, the present disclosure provides an electronic device, including a ring communication device as in any of the above embodiments. According to the electronic device provided by the present disclosure, a ring communication method is applied to the ring communication device, and the ring communication device includes a physical ring topology structure formed by directly connecting multiple graphics processors through board-level copper wires. In this structure, each computing unit in each processor can select a data transmission direction based on its own unit number, and send the processed task data to the corresponding computing unit in the previous processor or the next processor to achieve two-way communication; it can be understood that in the traditional solution, although each processor contains multiple computing units, the multiple computing units usually share a single transmission channel for communicating with external devices or other processors, and the data of the multiple processors will be transmitted in sequence in a single direction as a whole, resulting in the inability to fully utilize the two-way traffic of the communication port, and the present invention The disclosed embodiment introduces finer-grained transmission control. When any processor in the ring topology receives a data packet sent by the host computer, the multiple computing units in the processor will perform data processing respectively and determine the data transmission direction according to their own unit numbers, and each divide the corresponding task data into multiple data blocks, and send the data in the current data block to the previous processor or the next processor according to the corresponding data transmission direction, and process the data sent by another processor in the next data block, so that the bidirectional traffic of the communication port between each processor can be effectively utilized, so that data can flow in two directions at the same time, and bidirectional communication can be realized in the ring topology formed by multiple processors to avoid waste of communication resources and improve the data transmission efficiency and computing performance of multiple processors; and because the disclosed embodiment does not require additional network equipment such as switches during implementation, it can effectively reduce the deployment cost and complexity of the multi-processor system. In summary, the disclosed embodiment provides a multi-processor ring communication method, ring topology structure and equipment, which can improve the data transmission efficiency and computing performance of multiple processors at a low cost.

[0131] The electronic device disclosed in the present invention includes a ring topology structure, which is used to execute the ring communication method as in the above embodiment. The specific processing process is the same as the ring communication method in the above embodiment, and will not be repeated here.

[0132] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present disclosure described herein can, for example, be implemented in an order other than those illustrated or described herein. In addition, the terms "comprises" and "comprising" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0133] It should be understood that in the present disclosure, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0134] It should be understood that in the description of the embodiments of the present disclosure, the meaning of multiple (or multiple items) is more than two, greater than, less than, exceed, etc. are understood as not including the number, and above, below, within, etc. are understood as including the number.

[0135] In the several embodiments provided in the present disclosure, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0136] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0137] In addition, each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0138] It should also be understood that the various implementations provided in the embodiments of the present disclosure can be combined arbitrarily to achieve different technical effects.

[0139] The above is a specific description of the implementation methods of the present disclosure, but the present disclosure is not limited to the above implementation methods. Technical personnel familiar with the art can also make various equivalent modifications or substitutions without violating the spirit of the present disclosure. These equivalent modifications or substitutions are all included in the scope defined by the claims of the present disclosure.

Claims

1. A ring communication method, characterized in that: Applied to a ring communication device, the ring communication device includes a plurality of processors that are physically connected in sequence to form a ring topology structure, each of the processors includes a plurality of computing units; for each of the processors in the ring topology structure, the method includes: The processor determines, based on a connection sequence corresponding to the ring topology, a previous processor and a next processor adjacent to the processor in the ring topology; When receiving a data packet sent by the host computer, the processor allocates task data required to perform a computing task to the plurality of computing units according to the data packet, wherein the task data of each computing unit includes a plurality of data blocks, and the data transmission direction of each data block is determined based on a preset rule; For each of the computing units, the data in the current data block is sent to the previous processor or the next processor according to the corresponding data transmission direction, and data processing is performed on the data sent by another processor in the next data block.

2. The ring communication method according to claim 1, characterized in that: The preset rules include: Determining a data transmission direction of the data block based on a unit sequence number of the computing unit; Alternatively, the data transmission direction of the data block is determined based on the data number of the data block.

3. The ring communication method according to claim 2, characterized in that: The determining the data transmission direction of the data block based on the unit sequence number of the computing unit includes: For each of the computing units: If the unit sequence number of the computing unit is an odd number, determining one of the previous processor and the next processor as the data transmission direction of all data blocks in the computing unit; If the unit sequence number of the computing unit is an even number, the other one of the previous processor and the next processor is determined as the data transmission direction of all data blocks in the computing unit.

4. The ring communication method according to claim 3, characterized in that: The sending the data in the current data block to the previous processor or the next processor according to the corresponding data transmission direction includes: If the unit sequence number of the computing unit is an odd number, the data in the current data block is sent to a corresponding data block of another computing unit in the next processor whose unit sequence number is an odd number; If the unit sequence number of the computing unit is an even number, the data in the current data block is sent to the corresponding data block of another computing unit in the previous processor whose unit sequence number is an even number.

5. The ring communication method according to claim 1, characterized in that: For each of the computing units, the method further includes: Based on the connection sequence, the data block to be sent currently is determined as the current data block from among the multiple data blocks, and the data block receiving data from another processor for processing is determined as the next data block.

6. The ring communication method according to claim 5, characterized in that: After processing the data sent by another processor in the next data block, the method further includes: The next data block is updated to a new current data block, so that the data obtained after the data processing in the next data block is sent to the previous processor or the next processor according to the corresponding data transmission direction, and a new next data block is determined from the multiple data blocks.

7. The ring communication method according to claim 1, characterized in that: Each of the processors includes a data transmission unit, the data transmission unit includes a first transmission interface and a second transmission interface, the data transmission unit is physically connected to the second transmission interface of the previous processor through the first transmission interface, and the data transmission unit is physically connected to the first transmission interface of the next processor through the second transmission interface; The sending the data in the current data block to the previous processor or the next processor according to the data transmission direction by the data transmission unit includes: When the transmission target corresponding to the data transmission direction is the previous processor, sending the data in the current data block through the first transmission interface; When the sending target corresponding to the data transmission direction is the next processor, the data in the current data block is sent through the second transmission interface.

8. The ring communication method according to claim 1, characterized in that: The processing of data sent by another processor in the next data block includes: When the computing unit sends the data in the current data block to the previous processor, data processing is performed on the data sent by the next processor in the next data block, so as to send the data obtained after the data processing to the previous processor; When the computing unit sends the data in the current data block to the next processor, data processing is performed on the data in the next data block sent by the previous processor to send the data obtained after the data processing to the next processor.

9. A ring communication device, characterized in that: include: A plurality of processors are physically connected in sequence to form a ring topology, each of the processors comprising a plurality of computing units; Among them, for each of the processors in the ring topology structure, the processor is used to: determine the previous processor and the next processor adjacent to itself in the ring topology structure based on the connection order corresponding to the ring topology structure; when receiving a data packet sent by the upper computer, allocate task data required to execute computing tasks to multiple computing units according to the data packet, and the task data of each computing unit includes multiple data blocks, and the data transmission direction of each data block is determined based on preset rules; for each computing unit, send the data in the current data block to the previous processor or the next processor according to the corresponding data transmission direction, and process the data sent by another processor in the next data block.

10. The ring communication device according to claim 9, characterized in that: The processor also includes a command processing unit and a data transmission unit, and the command processing unit is communicatively connected to the data transmission unit and the multiple computing units respectively; wherein the command processing unit is used to allocate task data required to execute computing tasks to the multiple computing units according to the data packet, and the data transmission unit includes a first transmission interface and a second transmission interface, and the data transmission unit is physically connected to the second transmission interface of the previous processor through the first transmission interface, and the data transmission unit is physically connected to the first transmission interface of the next processor through the second transmission interface.

11. The ring communication device according to any one of claims 9 to 10, characterized in that: The multiple processors are deployed in the same server node, and the multiple processors are physically connected via board-level copper wires.

12. An electronic device, characterized in that: The invention comprises a ring-shaped communication device as claimed in any one of claims 9 to 11.

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