Chip topological network of a neuron computer

Abstract

The application relates to a chip topology network of a neuron computer, which comprises M rows and N columns of modules, each module is composed of nodes, and each node is composed of a chip; each node is provided with a node controller, a data controller, a signal controller, a first data line arranged along the column direction of the chip and electrically connected with the column chip, a second data line arranged along the row direction of the chip and electrically connected with the row chip and a signal line, the first data line is connected with the data controller, and the second data line and the signal line are connected with the signal controller; the data controller sends received first pulse data to corresponding chips to be synchronized; the signal controller sends received second pulse data to corresponding chips to be synchronized, and controls the corresponding chips to be synchronized to perform time step synchronization calculation in response to a time step synchronization signal sent by the node controller. The chip topology network has high expansibility and can realize efficient interconnection operation of a multi-module chip array.

Description

Technical Field

[0001] This application relates to the field of neural computer technology, and in particular to a chip topology network for a neural computer. Background Technology

[0002] A neuromorphic computer is a new type of computer system based on neuromorphic hardware, which is usually composed of multiple neuromorphic hardware components.

[0003] STDP (Spike Time-Dependent Plasticity) is one of the most widely used learning algorithms in spiking neural networks. The computation of most neuromorphic chips needs to consider the concept of time steps that map to real time constraints. Therefore, all neurons involved in the neural network application must complete the spike data computation within a specific time step. In many-core architectures, this usually means that all involved neuromorphic cores must complete the spike computation within a specific time step. The iterative process of the time step is completed under the control of the time step synchronization module.

[0004] In general, the time step synchronization function of neuromorphic hardware is integrated into the on-chip network. However, for large-scale chip-integrated neuromorphic hardware systems, the time step synchronization between chips must take into account the data transmission and computation efficiency issues of on-chip and off-chip. Therefore, how to optimize the design of time step synchronization has become one of the goals explored by researchers. Summary of the Invention

[0005] Therefore, it is necessary to address the aforementioned technical problems by providing a neuron chip topology network that enables the orderly transmission and recognition of time step synchronization signals in large-scale neuromorphic hardware systems, thereby achieving scalable, highly available, and cascaded operation of large-scale neuromorphic hardware.

[0006] In a first aspect, this application provides a chip topology network for a neural network computer, the neural network chip topology network comprising modules of M rows × N columns, adjacent modules being interconnected via a first Ethernet interface, each module consisting of q × k nodes, each node consisting of m × n chips, and adjacent chips being interconnected via a GPIO interface.

[0007] Each node is equipped with a node controller, m data controllers and n signal controllers, and the node controller is communicatively connected to each of the data controllers and the signal controllers;

[0008] Each node is also provided with m first data lines arranged along the chip column direction and electrically connected to the chip in the column, n second data lines arranged along the chip row direction and electrically connected to the chip in the row, and n signal lines. The first data lines are connected to a data controller, and the second data lines and the signal lines are connected to a signal controller. The data controller is used to send the first pulse data received from the first Ethernet transmission of the first peer module to the corresponding chip to be synchronized through the first data lines.

[0009] The signal controller is used to send the second pulse data received from the second peer module transmitted by the first Ethernet to the corresponding chip to be synchronized via the second data line, and in response to the time step synchronization signal sent by the node controller, to control the corresponding chip to be synchronized to perform time step synchronization calculation via the signal line.

[0010] In one embodiment, a second Ethernet interface is provided between the adjacent modules. The second Ethernet interface is interconnected with the communication interface of an external software system and is used to transmit the third pulse data received by the external software system through the second Ethernet to the synchronization chip in the module through a first data line or a second data line.

[0011] In one embodiment, the signal controller is further configured to listen to the synchronization characteristic signal of the corresponding chip to be synchronized on the second data line in response to the first synchronization configuration information transmitted by the first Ethernet or the second Ethernet; if the synchronization characteristic signal is detected, the corresponding chip to be synchronized is controlled to perform time step synchronization calculation through the signal line in response to the time step synchronization signal sent by the node controller.

[0012] In one embodiment, the first synchronization configuration information includes master channel configuration information and slave channel configuration information;

[0013] The first signal controller is configured to listen to the first ready signal reported by the second signal controller in response to the main channel configuration information transmitted via the first Ethernet or the second Ethernet. If the first ready signal is detected, the second signal controller is triggered to activate the time step synchronization signal. The second signal controller responds to the time step synchronization signal and controls the corresponding chip to be synchronized to perform time step synchronization calculations via the signal line.

[0014] Wherein, the second signal controller is located in the same node as the first signal controller and responds to the slave channel configuration information transmitted by the first Ethernet or the second Ethernet.

[0015] The first ready signal is generated by the second signal controller after it detects the synchronization characteristic signal of the chip to be synchronized connected to it.

[0016] In one embodiment, a first node controller is configured to listen to a second ready signal reported by a second node controller in response to master node configuration information transmitted via a first Ethernet or a second Ethernet. If the second ready signal is detected, the first node controller triggers a time step synchronization signal of the second node controller. In response to the time step synchronization signal, the second node controller triggers a time step synchronization signal of a third signal controller that is communicatively connected to it.

[0017] The second node controller is located in the same module as the first node controller and responds to the slave node configuration information transmitted via the first Ethernet or the second Ethernet.

[0018] The third signal controller is communicatively connected to the second node controller and responds to the main channel configuration information transmitted via the first Ethernet or the second Ethernet.

[0019] The second ready signal is generated by the second node controller after it hears the third ready signal reported by the third signal controller; the third ready signal is generated by the third signal controller after it hears the synchronization characteristic signal of the chip to be synchronized connected to it and the fourth ready signal reported by the fourth signal controller.

[0020] The fourth signal controller is located within the same node as the third signal controller and responds to the slave channel configuration information transmitted via the first Ethernet or the second Ethernet; the fourth ready signal is generated by the fourth signal controller after it detects the synchronization characteristic signal of the chip to be synchronized connected to it.

[0021] In one embodiment, the first node controller is further configured to, in response to master node configuration information transmitted via a first Ethernet or a second Ethernet, listen to a fifth ready signal reported by a fifth signal controller with which it is communicatively connected; if the fifth ready signal is detected, the fifth signal controller triggers a time step synchronization signal; the fifth signal controller, in response to the time step synchronization signal, controls the corresponding chip to be synchronized to perform time step synchronization calculation and triggers the time step synchronization signal of the sixth signal controller via the signal line.

[0022] The fifth signal controller is located within the same node as the first node controller and responds to the main channel configuration information transmitted via the first Ethernet or the second Ethernet.

[0023] The sixth signal controller is located within the same node as the first node controller and responds to the slave channel configuration information transmitted via the first Ethernet or the second Ethernet.

[0024] The fifth ready signal is generated by the fifth signal controller after it listens to the synchronization feature signal reported by the chip to be synchronized connected to it and the sixth ready signal reported by the sixth signal controller.

[0025] The sixth ready signal is generated by the sixth signal controller after it listens to the synchronization feature signal reported by the chip to be synchronized connected to it.

[0026] In one embodiment, the synchronization feature signal includes a fixed-period time-step signal, a standby signal, and a first time-step separation signal.

[0027] The time step fixed period signal is the time step period prediction result generated by the chip to be synchronized after receiving the first pulse data, second pulse data, or third pulse data transmitted by the first data line or the second data line.

[0028] The standby signal is generated after the chip to be synchronized completes the first pulse data, second pulse data, or third pulse data of the previous time step;

[0029] The first time step separator signal is used to separate the calculated data for each time step of the third pulse data.

[0030] In one embodiment, the synchronization feature signal further includes: a second time step separation signal, used to separate the calculated data of each time step of the first pulse data or the second pulse data.

[0031] In one embodiment, the synchronization feature signal further includes: a timing delay signal.

[0032] The timing delay signal is a signal generated by the chip to be synchronized receiving the first pulse data or the second pulse data through the first data line or the second data line with a delay.

[0033] In one embodiment, q = k and m = n.

[0034] In the aforementioned chip topology network of the neural computer, a node controller, a data controller, and a signal controller are set up in each module, and the node controller is communicatively connected to each of the data controllers and the signal controllers. Each node is also provided with m first data lines arranged along the chip column direction and electrically connected to the chip in the column, n second data lines arranged along the chip row direction and electrically connected to the chip in the row, and n signal lines. The first data lines are connected to the data controller, and the second data lines and the signal lines are connected to the signal controller. The data controller is used to send the first pulse data received from the first Ethernet transmission of the first peer module to the corresponding chip to be synchronized through the first data lines. The signal controller is used to send the second pulse data received from the first Ethernet transmission of the second peer module to the corresponding chip to be synchronized through the second data lines, and responds to the time step synchronization signal sent by the node controller to control the corresponding chip to be synchronized to perform time step synchronization calculation through the signal lines. This constructs a novel chip topology network for neural computer hardware, which has high scalability and realizes efficient interconnection and operation of multi-module chip arrays. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 This is a block diagram of the chip topology network of a neural computer in one embodiment.

[0037] Figure 2 This is a structural block diagram of a module in one embodiment;

[0038] Figure 3 This is a schematic diagram of the structure in which time-step synchronization calculation is performed in the chip topology network of a neural computer using A in one embodiment;

[0039] Figure 4 This is a schematic diagram illustrating the timing relationship of simultaneous computation of multiple time steps in the chip topology network of a neural computer in one embodiment;

[0040] Figure 5 This is an internal structural diagram of a neuronal computing device in one embodiment. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0042] Unless otherwise defined, the technical or scientific terms used in this application shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms “a,” “an,” “an,” “the,” and similar words used in this application do not indicate quantity limitation and may indicate singular or plural. The terms “comprising,” “including,” “having,” and any variations thereof used in this application are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may also include steps or units not listed, or may include other steps or units inherent to these processes, methods, products, or devices. The terms “connected,” “linked,” “coupled,” and similar words used in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. “Multiple” used in this application refers to two or more. “And / or” describes the relationship between related objects, indicating that three relationships may exist; for example, “A and / or B” can represent: A alone, A and B simultaneously, and B alone. The character " / " generally indicates that the preceding and following objects are in an "or" relationship. The terms "first," "second," and "third" used in this application are merely to distinguish similar objects and do not represent a specific ordering of the objects.

[0043] In one embodiment, a neuronal chip topology network is provided, such as Figure 1 As shown, the neuron chip topology network includes modules arranged in M ​​rows × N columns, with adjacent modules interconnected via a first Ethernet interface. Figure 2 As shown, each module consists of q×k nodes, each node consists of m×n chips, and adjacent chips are interconnected through GPIO interfaces.

[0044] Where q and k are both positive integers, q = k. m and n are both positive integers, m = n.

[0045] Each node is equipped with a node controller, m data controllers and n signal controllers, and the node controller is communicatively connected to each of the data controllers and the signal controllers.

[0046] Each node is also provided with m first data lines arranged along the chip column direction and electrically connected to the chip in that column, m second data lines arranged along the chip row direction and electrically connected to the chip in that row, and m signal lines. The first data lines are connected to the data controller, and the second data lines and the signal lines are connected to the signal controller.

[0047] The data controller is used to send the first pulse data received from the first Ethernet transmission to the first peer module to the corresponding synchronization chip via the first data line.

[0048] The signal controller is used to send the second pulse data received from the second peer module transmitted by the first Ethernet to the corresponding chip to be synchronized via the second data line, and in response to the time step synchronization signal sent by the node controller, to control the corresponding chip to be synchronized to perform time step synchronization calculation via the signal line.

[0049] It should be noted that within each module, the chips between nodes only exchange pulse data, and the chip's time step synchronization signal needs to be transmitted via signal lines.

[0050] More specifically, a second Ethernet interface is provided between the adjacent modules, and the second Ethernet interface is interconnected with the communication interface of the external software system. The second Ethernet interface, interconnected with the communication interface of the external software system, is used to transmit the third pulse data received by the external software system via the second Ethernet to the synchronization chip within the module via a first data line or a second data line.

[0051] Preferably, the first Ethernet interface is a 10 Gigabit Ethernet interface, and the second Ethernet interface is a Gigabit Ethernet interface. The node is FPGA hardware.

[0052] In this embodiment, m data controllers and n signal controllers are mounted on a single node. The data controllers electrically connected to the chips in their respective column interface with the entire column of n chips, while the signal controllers also electrically connected to the chips in their respective column interface with the entire row of m chips, achieving time-step synchronization control of the m×n chip array. The chips are interconnected via GPIO pins. Each node's communication layer is equipped with 10 Gigabit and Gigabit communication networks. The Gigabit network is used for data I / O access with external software systems, while the 10 Gigabit network is used to interface with the 10 Gigabit Ethernet interfaces of other modules, enabling highly scalable interconnection and operation of multi-module chip arrays.

[0053] In one embodiment, the signal controller is further configured to listen to the synchronization feature signal of the corresponding chip to be synchronized on the second data line in response to the first synchronization configuration information transmitted by the first Ethernet or the second Ethernet; if the synchronization feature signal is detected, the corresponding chip to be synchronized is controlled to perform time step synchronization calculation through the signal line in response to the time step synchronization signal sent by the node controller.

[0054] Specifically, the synchronization characteristic signal includes at least one of a fixed-period time-step signal, a standby signal, a first time-step separation signal, a second time-step separation signal, and a timing delay signal.

[0055] The fixed-cycle time step signal is a time step period prediction result generated by the chip to be synchronized after receiving the first, second, or third pulse data transmitted through the first or second data line. The signal sensor monitors the fixed-cycle time step signals of all connected chips to be synchronized, confirming that all chips to be synchronized can process pulse data normally according to the time step period.

[0056] The standby signal is generated after the chip or array of chips to be synchronized completes the first, second, or third pulse data of the previous time step. After the signal controller detects the standby signals of all connected chips to be synchronized, it confirms that all chips are in an idle state. The signal controller can also determine the actual time taken by the chip from the start to the end of calculation in the previous time step based on the standby signal.

[0057] The first time-step separation signal is used to separate the calculated data for each time step of the third pulse data. The third pulse data is gigabit Ethernet data. When the chip to be synchronized receives the third pulse data via the first data line or the second data line and performs time-step calculations, the first time-step separation signal is triggered after each time-step calculation is completed. The signal controller listens to the first time-step separation signals of all chips to be synchronized connected to it, confirming that the chips to be synchronized have completed the calculation of the previous time step of the third pulse data.

[0058] The second time-step separation signal is used to separate the calculated data for each time step of the first pulse data or the second pulse data. The first pulse data or the second pulse data is 10 Gigabit Ethernet data. When the chip to be synchronized receives the first pulse data or the second pulse data through the first data line or the second data line and performs time-step calculations, the second time-step separation signal is triggered after each time-step calculation is completed. When the signal controller detects the second time-step separation signals of all the chips to be synchronized connected to it, it confirms that the chip to be synchronized has completed the calculation of the previous time step of the first pulse data or the second pulse data.

[0059] The timing delay signal is a signal generated by the chip to be synchronized receiving the first pulse data or the second pulse data via the first data line or the second data line with a delay. When the signal controller detects the timing delay signal, it can confirm the delay time generated by the transmission of the first pulse data or the second pulse data between modules via the first Ethernet.

[0060] Specifically, in the chip topology network of the neural computer, if time step synchronization calculation is to be performed on the chip to be synchronized within the same node or the same module, the signal controller responds to the first synchronization configuration information transmitted by the first Ethernet or the second Ethernet, and after listening to the time step fixed period signal, standby signal, and first time step separation signal of the chip to be synchronized on the second data line, it can respond to the time step synchronization signal sent by the node controller and control the corresponding chip to be synchronized to perform time step synchronization calculation through the signal line.

[0061] If time step synchronization of chips to be synchronized between modules is to be performed, the signal controller responds to the first synchronization configuration information transmitted by the first Ethernet or the second Ethernet, and after listening to the time step fixed period signal, standby signal, first time step separation signal, second time step separation signal, and timing delay signal of the corresponding chip to be synchronized on the second data line, it can respond to the time step synchronization signal sent by the node controller and control the corresponding chip to be synchronized to perform time step synchronization calculation through the signal line.

[0062] It should be noted that if time-step synchronization calculations are required between two modules, the second time-step separator signal and timing delay signal need to be considered. If time-step synchronization calculations are not required between two modules, or if time-step synchronization calculations are performed within the same node or module within a single module, then the second time-step separator signal and timing delay signal do not need to be considered. Therefore, in the chip topology network of the neural network computer in this application, in addition to supporting intra-node time-step synchronization calculations, intra-module time-step synchronization calculations, and inter-module time-step synchronization calculations, asynchronous time-step calculations between modules can also be realized.

[0063] In one embodiment, the first synchronization configuration information includes primary channel configuration information and secondary channel configuration information. Therefore, within the same node, the signal controller responding to the primary channel configuration information is used as the first signal controller, i.e., the primary channel synchronization source of the node, and the signal controller responding to the secondary channel configuration information is used as the second signal controller, i.e., the secondary channel synchronization source of the node.

[0064] The first signal controller is used to listen to the first ready signal reported by the second signal controller in response to the main channel configuration information transmitted by the first Ethernet or the second Ethernet. If the first ready signal is heard, the second signal controller is triggered to perform a time step synchronization signal. The second signal controller responds to the time step synchronization signal and controls the corresponding chip to be synchronized to perform time step synchronization calculation through the signal line.

[0065] The second signal controller is located within the same node as the first signal controller and responds to the slave channel configuration information transmitted via the first or second Ethernet. The first ready signal is generated by the second signal controller after it detects the synchronization characteristic signal of the chip to be synchronized connected to it.

[0066] In this embodiment, by configuring the primary and secondary relationship of signal controllers within the same node, each signal controller receives the synchronization characteristic signal of the chip to be synchronized connected to it. At the same time, the first signal controller, i.e. the primary channel synchronization source, centrally receives the first ready signal of all the second signal controllers, i.e. the secondary channel synchronization sources, and then triggers the time step synchronization signal of the second signal controller. This allows the time step synchronization signal to be transmitted and identified in an orderly manner among multiple channels of the same node, realizing the time step synchronization trigger calculation of the chips to be synchronized by each signal controller within the same node.

[0067] In one embodiment, in addition to the synchronization of all chips to be synchronized within the same node, this embodiment also proposes the synchronization of all chips to be synchronized across multiple nodes within the same module. The node controller that responds to the master node configuration information transmitted via the first Ethernet or the second Ethernet is designated as the first node controller, i.e., the master node synchronization source within the module. The node controller that responds to the slave node configuration information transmitted via the first Ethernet or the second Ethernet is designated as the second node controller, i.e., the secondary node synchronization source within the module.

[0068] The first node controller is configured to listen to the second ready signal reported by the second node controller in response to the master node configuration information transmitted via the first Ethernet or the second Ethernet. If the second ready signal is detected, the second node controller triggers the time step synchronization signal of the second node controller. In response to the time step synchronization signal, the second node controller triggers the time step synchronization signal of the third signal controller that is connected to it in communication.

[0069] The second node controller is located within the same module as the first node controller and responds to slave node configuration information transmitted via the first or second Ethernet. The third signal controller is communicatively connected to the second node controller and responds to the master channel configuration information transmitted via the first or second Ethernet. The second ready signal is generated by the second node controller after it detects the third ready signal reported by the third signal controller. The third ready signal is generated by the third signal controller after it detects the synchronization characteristic signal of the chip to be synchronized connected to it and the fourth ready signal reported by the fourth signal controller. The fourth signal controller is located within the same node as the third signal controller and responds to the slave channel configuration information transmitted via the first or second Ethernet. The fourth ready signal is generated by the fourth signal controller after it detects the synchronization characteristic signal of the chip to be synchronized connected to it.

[0070] In detail, although the second node controller is the synchronization source for secondary nodes, the third signal controller connected to the second node controller is the primary channel synchronization source within the node where the second node controller is located. After listening to the third ready signal reported by the third signal controller, the second node controller confirms that all chips to be synchronized within that node are ready for time-step synchronization calculation and generates a second ready signal. The first node controller, upon listening to the second ready signal from the second signal controller, confirms that all nodes within the same module are ready for time-step synchronization calculation and triggers the time-step synchronization signal of the second node controller. The second node controller then triggers the time-step synchronization signal of the third signal controller. The third signal controller triggers the time-step synchronization signals of the chips to be synchronized connected to it and the fourth signal controller. The fourth signal controller triggers the time-step synchronization signals of the chips to be synchronized connected to it. This achieves time-step synchronization calculation among multiple nodes within the same module.

[0071] In one embodiment, when multiple nodes within the same module perform time step synchronization calculations, the first node controller, in addition to listening to the third ready signal of the second node controller, also needs to listen to the fifth ready signal reported by the fifth signal controller connected to it to confirm whether the chip to be synchronized in the node where the first node controller is located is ready.

[0072] The first node controller is further configured to, in response to the master node configuration information transmitted via the first Ethernet or the second Ethernet, listen to the fifth ready signal reported by the fifth signal controller connected to it; if the fifth ready signal is heard, the fifth signal controller is triggered to activate the time step synchronization signal; the fifth signal controller, in response to the time step synchronization signal, controls the corresponding chip to be synchronized to perform time step synchronization calculation and triggers the time step synchronization signal of the sixth signal controller through the signal line.

[0073] The fifth signal controller is located within the same node as the first node controller and responds to the master channel configuration information transmitted via the first or second Ethernet. The sixth signal controller is located within the same node as the first node controller and responds to the slave channel configuration information transmitted via the first or second Ethernet. The fifth ready signal is generated by the fifth signal controller after it detects the synchronization characteristic signal reported by the chip to be synchronized connected to it and the sixth ready signal reported by the sixth signal controller. The sixth ready signal is generated by the sixth signal controller after it detects the synchronization characteristic signal reported by the chip to be synchronized connected to it.

[0074] In this embodiment, by configuring the primary and secondary relationships of nodes and channels within the same module, the first node controller listens to the fifth ready signal reported by the fifth signal controller connected to it to confirm whether the chip to be synchronized within the node where the first node controller is located is ready, thereby triggering the time step synchronization signal of the fifth signal controller; the fifth signal controller triggers the time step synchronization signals of the chip to be synchronized connected to it and the sixth signal controller; the sixth signal controller triggers the time step synchronization signals of the chip to be synchronized connected to it, ensuring that when time step synchronization calculation is required between multiple nodes within the same module, all chips to be synchronized from the primary node synchronization source and all chips to be synchronized from the secondary node synchronization source perform time step calculation simultaneously, enabling the orderly transmission and identification of time step synchronization signals between multiple nodes within the same module, improving the accuracy and efficiency of time step synchronization calculation within the same module.

[0075] In one embodiment, when time-step synchronization calculations are required between multiple modules, if a third node controller within one of the modules responds to the master module configuration information and master node configuration information transmitted via the first or second Ethernet, then that module containing the third node controller becomes the master module synchronization source among the multiple modules. The remaining modules then become secondary module synchronization sources for this time-step synchronization calculation. A fourth node controller within the secondary module synchronization sources responds to the secondary module configuration information and master node configuration information transmitted via the first or second Ethernet.

[0076] The third node controller is used to listen to the seventh ready signal reported by the fourth node controller in response to the master module configuration information transmitted via the first Ethernet or the second Ethernet. If the seventh ready signal is heard, the fourth node controller triggers the time step synchronization signal. In response to the time step synchronization signal, the fourth node controller triggers the time step synchronization signal of the seventh signal controller that is connected to it in communication.

[0077] The seventh signal controller and the fourth node controller reside within the same node and respond to the master channel configuration information transmitted via the first or second Ethernet. The seventh ready signal is generated by the fourth node controller after it detects the eighth ready signal reported by the seventh signal controller. The eighth ready signal is generated by the seventh signal controller after it detects the synchronization characteristic signal of the chip to be synchronized connected to it and the ninth ready signal reported by the ninth signal controller. The ninth signal controller and the seventh signal controller reside within the same node and respond to the slave channel configuration information transmitted via the first or second Ethernet. The ninth ready signal is generated by the ninth signal controller after it detects the synchronization characteristic signal of the chip to be synchronized connected to it.

[0078] In this embodiment, by configuring the primary and secondary relationships between multiple modules, the time step synchronization trigger calculation of the chip to be synchronized is realized between the primary module synchronization source and the secondary module synchronization source, so that the time step synchronization signal can be transmitted and recognized in an orderly manner among multiple modules, thus solving the synchronization problem of multi-scale spiking neural networks on neuromorphic hardware.

[0079] In a preferred embodiment, a method based on, for example Figure 2 The illustration shows a specific application scenario of the chip topology network of the neural computer. Each node's data controller and signal controller have corresponding channel numbers, and the channel numbers between adjacent modules correspond one-to-one, meaning that the data stream output from a channel will only flow to the channel with the same channel number in the opposite module.

[0080] Assume the numbering template for each controller is (a, b, c, d), where a and b represent the unit number of the module, c is the node number, and d is the channel number. Establish a 4×4 module unit topology network with the numbering range a∈[0,1], b∈[0,1], c∈[0,3], and d∈[1,8]. Deploy applications A, B, C, D, and E onto the 4×4 module unit topology network.

[0081] like Figure 3 As shown, each application has different synchronization ranges and control data flow directions. For example, application A involves synchronization signal controllers (1,0,1,1), (1,0,1,2), (1,0,1,3), (1,0,3,1), (1,0,3,2), (1,0,3,3), (1,0,3,4), (1,1,0,1), (1,1,0,2), (1,1,0,3), (1,1,0,4), (1,1,2,3), and (1,1,2,4). The synchronization channels controlled by these signal controllers maintain synchronization during the operation of this application. Figure 3 The unidirectional arrows in the diagram indicate the transmission direction of the time-step synchronization signal. From the transmission direction of the time-step synchronization signal in the diagram, it can be seen that the module-level synchronization sources for this application are modules (1,0), (0,1), and (1,1), with module (1,1) being the primary module synchronization source. Within modules (1,0) and (0,1), node controllers (1,0,1), (0,1,2), and (1,1,0) are the primary node synchronization sources, while the remaining node controllers are secondary node synchronization sources. Furthermore, signal controllers (1,0,1,3), (1,0,3,1), (0,1,2,1), (1,1,0,4), and (1,1,2,2) are the primary channel synchronization sources, while the remaining channel controllers are secondary channel synchronization sources.

[0082] Assuming the current time step is t, the detailed synchronization process is as follows: the Ready signal, which indicates that the pulse data calculation for time step t-1 is complete, is reported by the signal controller (1,1,2,2) to the node controller (1,1,1) connected to it. The node controller (1,1,1) then transmits the signal to the node controller (1,1,0). At the same time, the signal controller (1,1,0,4) also reports the synchronization characteristic signals of all the chips to be synchronized to the node controller (1,1,0).

[0083] After receiving all Ready signals, node controller (1,1,0) triggers the time step synchronization signal of node controller (1,1,1), and triggers the time step synchronization signals of the connected signal controllers (1,1,0,4), (1,1,0,1), (1,1,0,2), and (1,1,0,3).

[0084] The node controller (1,1,1) then successively triggers the time step synchronization signals of all the signal controllers connected to it, thereby triggering the calculation of the synchronization start time step t of all the chips to be synchronized in the module.

[0085] The pulse data calculated by module (1,1) will be sent to modules (1,0) and (0,1) via 10 Gigabit Ethernet. Similarly, after the signal controllers in modules (1,0) and (0,1) receive the Ready signal indicating that the pulse data calculation for time step t-1 is complete, they begin to wait for the time step separation signal in the pulse data transmitted by the main module (1,1). When this signal arrives, it can be reported to the node controllers (1,0,1), (0,1,2), and (1,1,0) in modules (1,0), (0,1,2), and (1,1,0). When each controller in node controllers (1,0,1), (0,1,2), and (1,1,0) receives all the signals connected to it, it can trigger the synchronization chip in modules (1,0) and (0,1) to calculate time step t. The synchronization process is the same as that in module (1,1).

[0086] In this preferred embodiment, the channel numbers of adjacent modules correspond one-to-one. The channel matching relationship between adjacent modules is as follows: signal controller (1,0,1,1) and signal controller (1,1,0,1), signal controller (1,0,1,2) and signal controller (1,1,0,2), signal controller (1,0,1,3) and signal controller (1,1,1,3), signal controller (1,0,3,3) and signal controller (1,1,2,3), signal controller (1,0,3,4) and signal controller (1,1,2,4), and signal controller (0,1,2,1) and signal controller (1,1,0,4).

[0087] According to the time-step synchronization method applied in the chip topology network of the neural computer described in this application, Figure 4 This demonstrates the timing relationships of a neuromorphic hardware system simultaneously computing multiple time steps. For the master node, the synchronous computation process generally involves two synchronization steps. Step one is acquiring channel resources, i.e., initiating synchronization. This means that the master node controller, the synchronization source of the master module, sends node synchronization configuration information to other node controllers within and between modules. Other node controllers read the configuration information and constrain the designated signal controllers to a synchronized state according to the configuration. After the configuration takes effect, they can enter the synchronization phase and transmit or wait for time step synchronization signals. Step two is releasing channel resources, i.e., ending synchronization. This means that after completing the computation of all time steps, the master node controller will send a configuration clearing command to all other node controllers to release channel resources and prepare for the next computation.

[0088] from Figure 4 It can also be seen that the timing of the third pulse data input to each node by the external software system may differ from the timing of the chip topology network of the neuron computer. This will be synchronized by the software scheduler on each node. After the third pulse data is calculated, the output timing of each part of the chip topology network may also be inconsistent. Similarly, the external software system will aggregate and process the output data to realize synchronous calculation of time steps within the module and asynchronous calculation of time steps between modules.

[0089] In this preferred embodiment, multi-scale synchronization across modules, nodes, and channels is divided into three synchronization levels, taking into account multiple synchronization scenarios such as single-chip synchronization, multi-chip synchronization within a single channel, multi-channel synchronization within a node, multi-node synchronization within a module, and multi-module synchronization. This allows synchronization computing signals to be transmitted and recognized in an orderly manner across multiple channels, nodes, and modules, thereby solving the synchronization problem of multi-scale pulse data on neuromorphic hardware. Furthermore, the time steps of different synchronization sources are isolated from each other, allowing multiple network applications to run concurrently.

[0090] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0091] In one exemplary embodiment, such as Figure 5 As shown, a neural network computing device is provided. This neural network computing device can be a terminal, and the computing device includes a processor, a memory, an input / output interface, a communication interface, a display unit, and an input device. The memory internally contains the chip topology network of the neural network computing device as described in the above embodiments.

[0092] The processor, memory, and input / output interfaces are connected via a system bus, while the communication interface, display unit, and input devices are also connected to the system bus via the input / output interfaces. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides the environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The input / output interfaces are used for exchanging information between the processor and external devices. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, Near Field Communication (NFC), or other technologies. The display unit is used to create a visually visible image and can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be an LCD screen or an e-ink screen. The input devices can be a touch layer covering the display screen, buttons, a trackball, or a touchpad on the computer device's casing, or an external keyboard, touchpad, or mouse.

[0093] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0094] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A chip topological network of a neuromorphic computer, characterized by, The chip topology network comprises M rows and N columns of modules, adjacent modules are interconnected through a first Ethernet interface, each module comprises q×k nodes, each node comprises m×n chips, and each chip is interconnected with adjacent chips through a GPIO interface; Each node is provided with a node controller, m data controllers, and n signal controllers, and the node controller is in communication connection with each data controller and signal controller; Each node is further provided with m first data lines arranged in the column direction of the chips and electrically connected with the column chips, n second data lines arranged in the row direction of the chips and electrically connected with the row chips, and n signal lines, the first data lines are connected with the data controllers, and the second data lines and the signal lines are connected with the signal controllers; the data controllers are used to transmit first pulse data transmitted by a first opposite module of the first Ethernet to the corresponding to-be-synchronized chips through the first data lines; The signal controllers are used to transmit second pulse data transmitted by a second opposite module of the first Ethernet to the corresponding to-be-synchronized chips through the second data lines, and to control the corresponding to-be-synchronized chips to perform time step synchronization calculation through the signal lines in response to a time step synchronization signal transmitted by the node controller.

2. The chip-topology network of neuron computers of claim 1, wherein, The adjacent modules are provided with a second Ethernet interface, the second Ethernet interface is interconnected with a communication interface of an external software system, and is used to transmit third pulse data transmitted by the external software system through a second Ethernet to the to-be-synchronized chips in the module through the first data lines or the second data lines.

3. The chip topology network of the neuron computer according to claim 2, wherein The signal controllers are further used to listen to a synchronization characteristic signal of the corresponding to-be-synchronized chips on the second data lines in response to first synchronization configuration information transmitted by the first Ethernet or the second Ethernet, and if the synchronization characteristic signal is listened to, the corresponding to-be-synchronized chips are controlled to perform time step synchronization calculation through the signal lines in response to a time step synchronization signal transmitted by the node controller.

4. The chip-topology network of neuron computers of claim 3, wherein, The first synchronization configuration information comprises master channel configuration information and slave channel configuration information; A first signal controller is used to listen to a first ready signal reported by a second signal controller in response to master channel configuration information transmitted by the first Ethernet or the second Ethernet, and if the first ready signal is listened to, a time step synchronization signal of the second signal controller is triggered; the second signal controller controls the corresponding to-be-synchronized chips to perform time step synchronization calculation through the signal lines in response to the time step synchronization signal; The second signal controller is in the same node as the first signal controller and responds to slave channel configuration information transmitted by the first Ethernet or the second Ethernet; The first ready signal is generated by the second signal controller after listening to the synchronization characteristic signal of the to-be-synchronized chips connected therewith.

5. The chip topology network of the neuron computer according to claim 4, wherein The first node controller is configured to listen to a second ready signal reported by a second node controller in response to master node configuration information transmitted by the first Ethernet or the second Ethernet, and trigger a time step synchronization signal of the second node controller if the second ready signal is listened to; the second node controller is configured to trigger a time step synchronization signal of a third signal controller in communication connection therewith in response to the time step synchronization signal; The second node controller is in the same module as the first node controller and is configured to respond to slave node configuration information transmitted by the first Ethernet or the second Ethernet; The third signal controller is in communication connection with the second node controller and is configured to respond to the master channel configuration information transmitted by the first Ethernet or the second Ethernet; The second ready signal is generated by the second node controller after the second node controller listens to a third ready signal reported by the third signal controller; the third ready signal is generated by the third signal controller after the third signal controller listens to a synchronization feature signal of a chip to be synchronized connected thereto and a fourth ready signal reported by a fourth signal controller; The fourth signal controller is in the same node as the third signal controller and is configured to respond to the slave channel configuration information transmitted by the first Ethernet or the second Ethernet; and the fourth ready signal is generated by the fourth signal controller after the fourth signal controller listens to the synchronization feature signal of the chip to be synchronized connected thereto.

6. The chip topology network of the neuron computer according to claim 5, wherein The first node controller is further configured to listen to a fifth ready signal reported by a fifth signal controller in communication connection therewith in response to master node configuration information transmitted by the first Ethernet or the second Ethernet, and trigger a time step synchronization signal of the fifth signal controller if the fifth ready signal is listened to; the fifth signal controller is configured to perform time step synchronization calculation on a corresponding chip to be synchronized through the signal line and trigger a time step synchronization signal of a sixth signal controller in response to the time step synchronization signal; The fifth signal controller is in the same node as the first node controller and is configured to respond to the master channel configuration information transmitted by the first Ethernet or the second Ethernet; The sixth signal controller is in the same node as the first node controller and is configured to respond to the slave channel configuration information transmitted by the first Ethernet or the second Ethernet; The fifth ready signal is generated by the fifth signal controller after the fifth signal controller listens to the synchronization feature signal reported by the chip to be synchronized connected thereto and a sixth ready signal reported by the sixth signal controller; The sixth ready signal is generated by the sixth signal controller after the sixth signal controller listens to the synchronization feature signal reported by the chip to be synchronized connected thereto.

7. The chip-topology network of neuron computers of claim 6, wherein, The synchronization feature signal includes a time step fixed period signal, a standby signal, a first time step separation signal, The time step fixed period signal is a time step period estimation result generated after the chip to be synchronized receives first pulse data or second pulse data or third pulse data transmitted by the first data line or the second data line; The standby signal is a standby signal generated after the chip to be synchronized completes first pulse data or second pulse data or third pulse data of a previous time step; The first time step separation signal is used to separate calculation data of each time step of the third pulse data.

8. The chip-topology network of neuron computers of claim 7, wherein, The synchronization feature signal further includes a second time step separation signal used to separate calculation data of each time step of the first pulse data or the second pulse data.

9. The chip-topology network of neuron computers as defined in claim 8, characterized in that The synchronization feature signal further includes a timing delay signal, The timing delay signal is a signal generated by the chip to be synchronized through the first data line or the second data line after delaying the received first pulse data or second pulse data.

10. The chip-topology network of neuron computers of claim 1, wherein, q=k, m=n.

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