Semiconductor package and manufacturing method thereof

Abstract

The invention discloses a semiconductor package and a method of fabricating the same, where the semiconductor package includes a redistribution layer interposer having a first surface and a second surface opposite the first surface; the fan-out connecting pad is arranged on the second surface; peripheral pads disposed on the second surface and arranged along the periphery of the redistribution layer interposer; a first semiconductor chip disposed on the first surface and electrically connected to the fan-out pad; a molding compound molding the first semiconductor chip and the first surface of the redistribution layer interposer; a through-mold via disposed in the molding compound around the first semiconductor chip; a peripheral solder bump disposed within the through-mold via and directly disposed on the peripheral pad; a through silicon via pad disposed on a back surface of the first semiconductor chip; and a second semiconductor chip bonded to the through-silicon via pads of the first semiconductor chip and the peripheral solder bumps within the through-mold vias.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an improved semiconductor package and a manufacturing method thereof. Background Art

[0002] The semiconductor industry is currently undergoing the most radical transformation in its history. Many new applications such as artificial intelligence (AI), augmented / virtual reality, and autonomous driving require massive computing power and processors optimized specifically for each application. At the same time, development cycles are becoming shorter and shorter, and the cost of new chip designs is rising exponentially.

[0003] The rising costs and complexity associated with process scaling have driven the semiconductor industry to turn to 3D integration and heterogeneous integration to improve the performance of next-generation devices that support these new applications. Die-to-wafer hybrid bonding is a process that accelerates the deployment of 3D / heterogeneous integration and enables a new generation of devices with high bandwidth, high performance and low power consumption. Summary of the invention

[0004] The main purpose of the present invention is to provide an improved 3DIC package and a manufacturing method thereof to solve the deficiencies or shortcomings of the prior art.

[0005] On the one hand, the present invention provides a semiconductor package, comprising: a redistribution layer interposer, having a first surface and a second surface opposite to the first surface; a plurality of fan-out pads, arranged on the second surface of the redistribution layer interposer; a plurality of peripheral pads, arranged on the second surface and arranged along the periphery of the redistribution layer interposer; a first semiconductor chip, arranged on the first surface of the redistribution layer interposer and electrically connected to the plurality of fan-out pads; a molding compound, molding the first semiconductor chip and the first surface of the redistribution layer interposer, wherein the top surface of the molding compound is coplanar with the back surface of the first semiconductor chip; a plurality of through-mold vias, arranged in the molding compound around the first semiconductor chip, wherein the plurality of through-mold vias respectively expose the plurality of peripheral pads; a plurality of peripheral solder bumps, arranged in the plurality of through-mold vias and directly placed on the plurality of peripheral pads respectively; a plurality of through-silicon via pads, arranged on the back surface of the first semiconductor chip; and a second semiconductor chip, bonded to the plurality of through-silicon via pads of the first semiconductor chip and the plurality of peripheral solder bumps in the plurality of through-mold vias.

[0006] According to an embodiment of the present invention, the plurality of peripheral pads surround the plurality of fan-out pads.

[0007] According to an embodiment of the present invention, the second semiconductor chip is bonded to the plurality of through silicon via pads of the first semiconductor chip through a plurality of first connectors.

[0008] According to an embodiment of the present invention, the plurality of first connecting members include micro-bumps.

[0009] According to an embodiment of the present invention, the second semiconductor chip is bonded to the plurality of peripheral solder bumps in the plurality of through-mold vias through a plurality of second connectors, and a diameter of the second connectors is greater than a diameter of the first connectors.

[0010] According to an embodiment of the present invention, the plurality of second connecting members include metal pillar bumps.

[0011] According to an embodiment of the present invention, the metal column bump includes a gold column bump, a silver column bump, an aluminum column bump or a copper column bump.

[0012] According to an embodiment of the present invention, the semiconductor package further includes: a plurality of third connectors disposed on the fan-out pad and the peripheral pad on the second surface of the redistribution layer interposer.

[0013] According to an embodiment of the present invention, the plurality of third connecting members include C4 bumps.

[0014] According to an embodiment of the present invention, the semiconductor package further comprises: a filling material layer disposed in the plurality of through-mold vias, wherein the filling material layer surrounds the peripheral solder bump and the second connector.

[0015] Another aspect of the present invention provides a method for forming a semiconductor package. First, a redistribution layer interposer is provided, which has a first surface and a second surface opposite to the first surface. A plurality of fan-out pads and a plurality of peripheral pads are formed on the second surface of the redistribution layer interposer. A first semiconductor chip is formed on the first surface of the redistribution layer interposer and electrically connected to the plurality of fan-out pads. A molding compound is formed to encapsulate the first semiconductor chip and the first surface of the redistribution layer interposer, wherein the top surface of the molding compound is coplanar with the back surface of the first semiconductor chip. A plurality of through-mold vias are formed in the molding compound surrounding the first semiconductor chip, wherein the plurality of through-mold vias respectively expose the plurality of peripheral pads. A plurality of peripheral solder bumps are directly formed in the plurality of through-mold vias and on the plurality of peripheral pads, respectively. A plurality of through-silicon via pads are formed on the back surface of the first semiconductor chip. The second semiconductor chip is bonded to the plurality of through-silicon via pads of the first semiconductor chip and the plurality of peripheral solder bumps in the plurality of through-mold vias.

[0016] According to an embodiment of the present invention, the plurality of peripheral pads surround the plurality of fan-out pads.

[0017] According to an embodiment of the present invention, the second semiconductor chip is bonded to the plurality of through silicon via pads of the first semiconductor chip through a plurality of first connectors.

[0018] According to an embodiment of the present invention, the plurality of first connecting members include micro-bumps.

[0019] According to an embodiment of the present invention, the second semiconductor chip is bonded to the plurality of peripheral solder bumps in the plurality of through-mold vias through a plurality of second connectors, and a diameter of the second connectors is greater than a diameter of the first connectors.

[0020] According to an embodiment of the present invention, the plurality of second connecting members include metal pillar bumps.

[0021] According to an embodiment of the present invention, the metal column bump includes a gold column bump, a silver column bump, an aluminum column bump or a copper column bump.

[0022] According to an embodiment of the present invention, the method further includes: forming a plurality of third connectors on the fan-out pad and the peripheral pad on the second surface of the redistribution layer interposer.

[0023] According to an embodiment of the present invention, the plurality of third connecting members include C4 bumps.

[0024] According to an embodiment of the present invention, the method further comprises: forming a filling material layer within the plurality of through-mold vias, wherein the filling material layer surrounds the peripheral solder bump and the second connector. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A cross-sectional schematic diagram of a semiconductor package according to an embodiment of the present invention;

[0026] Figures 2 to 7 It is a schematic diagram of a method for forming a semiconductor package according to an embodiment of the present invention.

[0027] Explanation of symbols

[0028] 1 Semiconductor packaging

[0029] 10 The first semiconductor chip

[0030] 10a Front

[0031] 10b Back

[0032] 100 Rewiring Layer Interposer

[0033] 110 Molding Compound

[0034] 110a Top surface

[0035] 110v Through-Mold Hole

[0036] 120 Through Silicon Via Pad

[0037] 210 pad

[0038] 220 Peripheral pads

[0039] 310 First connecting piece

[0040] 320 Second connecting piece

[0041] 330 Third connecting piece

[0042] 4 Circuit Board

[0043] 5 Electronic components

[0044] BP Peripheral Solder Bump

[0045] FA Fan-Out Package

[0046] G Clearance

[0047] GF filling material layer

[0048] PF Fan-out Pad

[0049] PP peripheral pads

[0050] S1 First Surface

[0051] S2 Second Surface

[0052] W Wafer DETAILED DESCRIPTION

[0053] In the following, the details will be described with reference to the accompanying drawings, which also constitute part of the detailed description of the specification and are illustrated in a specific way that the embodiment can be implemented. The following embodiments have been described in sufficient detail to enable a person skilled in the art to implement them.

[0054] Of course, other embodiments may be adopted, or any structural, logical, and electrical changes may be made without departing from the embodiments described herein. Therefore, the following detailed description should not be considered as limiting, but rather, the embodiments included therein will be defined by the appended claims.

[0055] See also Figure 1, which is a cross-sectional schematic diagram of a semiconductor package according to an embodiment of the present invention. The semiconductor package 1 includes a re-distribution layer (RDL) interposer 100, having a first surface S1 and a second surface S2 opposite to the first surface S1. A plurality of fan-out pads PF are disposed on the second surface S2 of the re-distribution layer interposer 100. A plurality of peripheral pads PP are also disposed on the second surface S2, arranged along the periphery of the re-distribution layer interposer 100. According to an embodiment of the present invention, on the second surface S2, a plurality of peripheral pads PP surround a plurality of fan-out pads PF.

[0056] According to an embodiment of the present invention, the semiconductor package 1 further includes a first semiconductor chip 10 disposed on the first surface S1 of the redistribution layer interposer 100 and electrically connected to a plurality of fan-out pads PF. According to an embodiment of the present invention, the first semiconductor chip 10 may be, for example, a logic chip or a memory chip, but is not limited thereto.

[0057] According to an embodiment of the present invention, the fan-out pads PF are electrically connected to the input / output (I / O) pads on the front side 10a of the first semiconductor chip 10 via the interconnect structure in the redistribution layer interposer 100. To simplify the description, the interconnect structure in the redistribution layer interposer 100 and the input / output pads of the first semiconductor chip 10 are not shown in the figure.

[0058] According to an embodiment of the present invention, the semiconductor package 1 further includes a molding compound 110, which molds the first semiconductor chip 10 and the first surface S1 of the redistribution layer interposer 100, wherein the top surface 110a of the molding compound 110 is coplanar with the back surface 10b of the first semiconductor chip 10. According to an embodiment of the present invention, the molding compound 110 does not cover the front surface 10a or the back surface 10b of the first semiconductor chip 10, but only covers the edge sidewalls surrounding the first semiconductor chip 10.

[0059] According to an embodiment of the present invention, the semiconductor package 1 further includes a plurality of through mold vias 110v, which are disposed in the molding material 110 around the first semiconductor chip 10. According to an embodiment of the present invention, the through mold vias 110v penetrate the molding material 110 and extend into the first surface S1 of the redistribution layer interposer 100 to a predetermined depth until a plurality of peripheral pads PP are exposed. According to an embodiment of the present invention, the plurality of through mold vias 110v respectively expose a plurality of peripheral pads PP.

[0060] According to an embodiment of the present invention, the semiconductor package 1 further includes a plurality of peripheral solder bumps BP, which are disposed in the plurality of through-mold vias 110v and are respectively directly placed on the plurality of peripheral pads PP. According to an embodiment of the present invention, the height of the peripheral solder bumps BP is, for example, greater than half the depth of the through-mold vias 110v, and the top surface of the peripheral solder bumps BP does not protrude from the top surface 110a of the molding compound 110.

[0061] According to an embodiment of the present invention, the semiconductor package 1 further includes a plurality of through silicon via (TSV) pads 120 disposed on the back side 10b of the first semiconductor chip 10. According to an embodiment of the present invention, the plurality of through silicon via pads 120 extend to a predetermined depth of the back side 10b of the first semiconductor chip 10, for example, the predetermined depth is approximately equal to the thickness of the semiconductor substrate 101 of the first semiconductor chip 10, but is not limited thereto.

[0062] According to an embodiment of the present invention, the semiconductor package 1 further includes a second semiconductor chip 20, which is bonded to a plurality of through silicon via pads 120 of the first semiconductor chip 10 and a plurality of peripheral solder bumps BP in a plurality of through-mold vias 110v. According to an embodiment of the present invention, the second semiconductor chip 20 may be, for example, a display driver IC (DDIC), but is not limited thereto. According to an embodiment of the present invention, the second semiconductor chip 20 is bonded to a plurality of through silicon via pads 120 of the first semiconductor chip 10 through a plurality of first connectors 310. According to an embodiment of the present invention, the plurality of first connectors 310 include microbumps. According to an embodiment of the present invention, the molding material 110 does not directly contact the second semiconductor chip 20, and a gap G is formed between the molding material 110 and the second semiconductor chip 20.

[0063] According to the embodiment of the present invention, the second semiconductor chip 20 is bonded to the plurality of peripheral solder bumps BP in the plurality of through-mold vias 110 v through the plurality of second connectors 320 , and the diameter of the second connectors 320 is greater than the diameter of the first connectors 310 .

[0064] According to an embodiment of the present invention, the first connector 310 electrically connects the pad 210 of the second semiconductor chip 20 and the through silicon via pad 120, and the second connector 320 electrically connects the peripheral pad 220 of the second semiconductor chip 20 and the peripheral solder bump BP. According to an embodiment of the present invention, the plurality of second connectors 320 include metal column bumps, for example, gold column bumps, silver column bumps, aluminum column bumps or copper column bumps. The above-mentioned metal column bumps can be formed using a wire bonding machine. According to an embodiment of the present invention, the size of the peripheral pad 220 of the second semiconductor chip 20 is larger than the size of the pad 210.

[0065] According to an embodiment of the present invention, the high-frequency signal between the first semiconductor chip 10 and the second semiconductor chip 20 can be transmitted via the first connector 310 and the through silicon via pad 120, and the high-voltage power signal required by the second semiconductor chip 20 can be transmitted via the second connector 320 and the peripheral solder bump BP.

[0066] According to an embodiment of the present invention, the semiconductor package 1 further comprises a filling material layer GF disposed in the plurality of through-mold vias 110v, wherein the filling material layer GF surrounds the peripheral solder bumps BP and the second connectors 320. According to an embodiment of the present invention, the filling material layer GF fills the gap G between the molding compound 110 and the second semiconductor chip 20, and surrounds the plurality of first connectors 310.

[0067] According to an embodiment of the present invention, the semiconductor package 1 further includes a plurality of third connectors 330, which are disposed on the fan-out pads PF and the peripheral pads PP on the second surface S2 of the redistribution layer interposer 100. According to an embodiment of the present invention, the plurality of third connectors 330 may include C4 (C4 is the abbreviation of Controlled Collapse Chip Connection) bumps, but are not limited thereto.

[0068] See also Figures 2 to 7 , which is a schematic diagram of a method for forming a semiconductor package according to an embodiment of the present invention. First, a fan-out package FA is provided, which includes a redistribution layer interposer 100. The redistribution layer interposer 100 has a first surface S1 and a second surface S2 opposite to the first surface S1. A plurality of fan-out pads PF are arranged on the second surface S2 of the redistribution layer interposer 100. A plurality of peripheral pads PP are also arranged on the second surface S2, arranged along the periphery of the redistribution layer interposer 100. According to an embodiment of the present invention, on the second surface S2, a plurality of peripheral pads PP surround a plurality of fan-out pads PF.

[0069] The fan-out package FA also includes a first semiconductor chip 10 disposed on a first surface S1 of a redistribution layer interposer 100 and electrically connected to a plurality of fan-out pads PF. According to an embodiment of the present invention, the first semiconductor chip 10 may be, for example, a through silicon via logic chip or a through silicon via memory chip, but is not limited thereto. According to an embodiment of the present invention, the fan-out pads PF are electrically connected to the input / output pads on the front side 10a of the first semiconductor chip 10 via an internal wiring structure within the redistribution layer interposer 100. To simplify the description, the internal wiring structure within the redistribution layer interposer 100 and the input / output pads of the first semiconductor chip 10 are not shown in the figure.

[0070] According to an embodiment of the present invention, a plurality of through silicon via pads 120 are disposed on the back side 10b of the first semiconductor chip 10. According to an embodiment of the present invention, the plurality of through silicon via pads 120 extend to a predetermined depth of the back side 10b of the first semiconductor chip 10, for example, the predetermined depth is approximately equal to the thickness of the semiconductor substrate 101 of the first semiconductor chip 10.

[0071] According to an embodiment of the present invention, the fan-out package FA further includes a molding compound 110 that molds the first semiconductor chip 10 , the first surface S1 of the redistribution layer interposer 100 , and a plurality of through silicon via pads 120 on the back side 10 b of the first semiconductor chip 10 .

[0072] like Figure 3 As shown, the molding material 110 is subjected to a grinding process, such as a chemical mechanical grinding process, so that the top surface 110a of the molding material 110 is coplanar with the back surface 10b of the first semiconductor chip 10. At this time, the molding material 110 does not cover the front surface 10a or the back surface 10b of the first semiconductor chip 10, but only covers the edge sidewalls surrounding the first semiconductor chip 10, exposing a plurality of through silicon via pads 120 on the back surface 10b of the first semiconductor chip 10.

[0073] like Figure 4 As shown, a plurality of through-mold vias 110v are then formed in the molding material 110 around the first semiconductor chip 10 by etching. According to an embodiment of the present invention, the through-mold vias 110v penetrate the molding material 110 and extend into the first surface S1 of the redistribution layer interposer 100 to a predetermined depth until a plurality of peripheral pads PP are exposed. According to an embodiment of the present invention, the plurality of through-mold vias 110v respectively expose a plurality of peripheral pads PP.

[0074] Next, a peripheral solder bump BP is formed on the peripheral pad PP in the through-mold via 110v. According to an embodiment of the present invention, the height of the peripheral solder bump BP is, for example, greater than half the depth of the through-mold via 110v, and the top surface of the peripheral solder bump BP does not protrude from the top surface 110a of the molding compound 110. At the same time, a first connector 310 is formed on the through-silicon via pad 120. According to an embodiment of the present invention, the first connector 310 includes a microbump. The diameter of the peripheral solder bump BP is greater than the diameter of the first connector 310.

[0075] like Figure 5 and Figure 6As shown, a wafer W formed with a plurality of second semiconductor chips 20 is then provided (each second semiconductor chip 20 is separated by a dotted line). According to an embodiment of the present invention, the second semiconductor chip 20 may be, for example, a display driver chip, but is not limited thereto. The second semiconductor chip 20 includes a pad 210 and a peripheral pad 220. According to an embodiment of the present invention, a second connector 320 is provided on the peripheral pad 220 of the second semiconductor chip 20. According to an embodiment of the present invention, the second connector 320 includes a metal column bump, for example, a gold column bump, a silver column bump, an aluminum column bump or a copper column bump. The above-mentioned metal column bump can be formed using a wire bonding machine.

[0076] Next, the chip is bonded to the wafer using a chip-to-wafer bonding method. Figure 4 The fan-out package FA in the wafer W is turned upside down and assembled onto each second semiconductor chip 20 of the wafer W. At this time, the pads 210 and the peripheral pads 220 of the second semiconductor chip 20 are respectively bonded to the through silicon via pads 120 of the first semiconductor chip 10 and the peripheral solder bumps BP in the through-mold vias 110v through the first connectors 310 and the second connectors 320. When performing chip-to-wafer bonding, the second connectors 320 on the second semiconductor chip 20 can be used as positioning posts to increase the positioning accuracy during assembly.

[0077] According to the embodiment of the present invention, the second semiconductor chip 20 is bonded to the plurality of through silicon via pads 120 of the first semiconductor chip 10 through the plurality of first connectors 310. According to the embodiment of the present invention, the first connectors 310 electrically connect the pads 210 of the second semiconductor chip 20 and the through silicon via pads 120, and the second connectors 320 electrically connect the peripheral pads 220 of the second semiconductor chip 20 and the peripheral solder bumps BP.

[0078] According to an embodiment of the present invention, the second semiconductor chip 20 is bonded to the plurality of peripheral solder bumps BP in the plurality of through-mold vias 110v through the plurality of second connectors 320, and the diameter of the second connectors 320 is greater than the diameter of the first connectors 310. According to an embodiment of the present invention, the size of the peripheral pads 220 of the second semiconductor chip 20 is greater than the size of the pads 210.

[0079] According to the embodiment of the present invention, the peripheral solder bump BP can be slightly squeezed and deformed by the second connector 320 to form a serrated sidewall profile. According to the embodiment of the present invention, the peripheral solder bump BP does not directly contact the molding material 110. A reflow process can be performed later to form a tight bond between the second connector 320 and the peripheral solder bump BP.

[0080] Subsequently, a wafer cutting process is performed, and the wafer W is cut along the imaginary lines to form a semiconductor package 1. A material layer GF is then filled in the plurality of through-mold vias 110v, for example, a resin or other suitable underfill, wherein the filling material layer GF surrounds the peripheral solder bumps BP and the second connectors 320. According to an embodiment of the present invention, the filling material layer GF fills the gap G between the molding compound 110 and the second semiconductor chip 20, and surrounds the plurality of first connectors 310.

[0081] like Figure 7 As shown, then, Figure 6 The semiconductor package 1 formed in the circuit board 4 is turned upside down and assembled to the circuit board 4 through the third connector 330. According to an embodiment of the present invention, the third connector 330 is arranged on the fan-out pad PF and the peripheral pad PP on the second surface S2 of the redistribution layer interposer 100. According to an embodiment of the present invention, the third connector 330 includes a C4 bump. According to an embodiment of the present invention, the circuit board 4 can be a printed circuit board (PCB) or a system board, but is not limited thereto. According to an embodiment of the present invention, an electronic component 5 can be further arranged on the circuit board 4.

[0082] According to the embodiment of the present invention, the high-frequency signal between the first semiconductor chip 10 and the second semiconductor chip 20 can be transmitted through the first connector 310 and the through-silicon via pad 120, and the high-voltage power signal required by the second semiconductor chip 20 can be directly transmitted by the circuit board 4 through the second connector 320 and the peripheral solder bump BP. In addition, the second semiconductor chip 20 can also directly transmit signals with the electronic component 5 through the path formed by the second connector 320 and the peripheral solder bump BP.

[0083] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A semiconductor package, comprising: A redistribution layer interposer having a first surface and a second surface opposite to the first surface; A plurality of fan-out pads are disposed on the second surface of the redistribution layer interposer; A plurality of peripheral pads are disposed on the second surface and arranged along the periphery of the redistribution layer interposer; A first semiconductor chip disposed on the first surface of the redistribution layer interposer and electrically connected to the plurality of fan-out pads; A molding compound, which molds the first semiconductor chip and the first surface of the redistribution layer interposer, wherein a top surface of the molding compound is coplanar with a back surface of the first semiconductor chip; A plurality of through-mold vias are disposed in the molding material around the first semiconductor chip, wherein the plurality of through-mold vias respectively expose the plurality of peripheral pads; A plurality of peripheral solder bumps are disposed in the plurality of through-mold vias and are respectively disposed directly on the plurality of peripheral pads; A plurality of through silicon via pads are disposed on the back side of the first semiconductor chip; and A second semiconductor chip is bonded to the plurality of TSV pads of the first semiconductor chip and the plurality of peripheral solder bumps within the plurality of TMVs.

2. The semiconductor package according to claim 1, wherein: The plurality of peripheral pads surround the plurality of fan-out pads.

3. The semiconductor package according to claim 1, wherein: The second semiconductor chip is bonded to the plurality of through silicon via pads of the first semiconductor chip through a plurality of first connectors.

4. The semiconductor package according to claim 3, wherein: The plurality of first connecting members include micro-bumps.

5. The semiconductor package according to claim 3, wherein: The second semiconductor chip is bonded to the plurality of peripheral solder bumps in the plurality of through-mold vias through a plurality of second connectors, and the diameter of the second connectors is greater than the diameter of the first connectors.

6. The semiconductor package according to claim 5, wherein: The plurality of second connecting members include metal pillar bumps.

7. The semiconductor package according to claim 6, wherein: The metal column bump includes a gold column bump, a silver column bump, an aluminum column bump or a copper column bump.

8. The semiconductor package according to claim 5, wherein: Also includes: A plurality of third connecting members are disposed on the fan-out pad and the peripheral pad on the second surface of the redistribution layer intermediate layer.

9. The semiconductor package according to claim 8, wherein: The plurality of third connecting members include C4 bumps.

10. The semiconductor package according to claim 5, wherein: Also includes: A filling material layer is disposed in the plurality of through-mold vias, wherein the filling material layer surrounds the peripheral solder bump and the second connector.

11. A method of forming a semiconductor package, comprising: Providing a redistribution layer interposer having a first surface and a second surface opposite to the first surface; forming a plurality of fan-out pads and a plurality of peripheral pads on the second surface of the redistribution layer interposer; forming a first semiconductor chip on the first surface of the redistribution layer interposer and electrically connected to the plurality of fan-out pads; Forming a molding compound encapsulating the first semiconductor chip and the first surface of the redistribution layer interposer, wherein a top surface of the molding compound is coplanar with a back surface of the first semiconductor chip; forming a plurality of through-mold vias in the molding material surrounding the first semiconductor chip, wherein the plurality of through-mold vias respectively expose the plurality of peripheral pads; Directly forming a plurality of peripheral solder bumps in the plurality of through-mold vias and on the plurality of peripheral pads respectively; forming a plurality of through silicon via pads on the back side of the first semiconductor chip; and The second semiconductor chip is bonded to the plurality of through silicon via pads of the first semiconductor chip and the plurality of peripheral solder bumps within the plurality of through mold vias.

12. The method of claim 11, wherein: The plurality of peripheral pads surround the plurality of fan-out pads.

13. The method of claim 11, wherein: The second semiconductor chip is bonded to the plurality of through silicon via pads of the first semiconductor chip through a plurality of first connectors.

14. The method of claim 13, wherein: The plurality of first connecting members include micro-bumps.

15. The method of claim 13, wherein: The second semiconductor chip is bonded to the plurality of peripheral solder bumps in the plurality of through-mold vias through a plurality of second connectors, and the diameter of the second connectors is greater than the diameter of the first connectors.

16. The method of claim 15, wherein: The plurality of second connecting members include metal pillar bumps.

17. The method of claim 16, wherein: The metal column bump includes a gold column bump, a silver column bump, an aluminum column bump or a copper column bump.

18. The method of claim 15, wherein: Also includes: A plurality of third connectors are formed on the fan-out pad and the peripheral pad on the second surface of the redistribution layer interposer.

19. The method of claim 18, wherein: The plurality of third connecting members include C4 bumps.

20. The method of claim 15, wherein: Also includes: A filling material layer is formed within the plurality of through-mold vias, wherein the filling material layer surrounds the peripheral solder bump and the second connector.

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