Package structure, semiconductor package and method of forming same

Abstract

A semiconductor package according to an embodiment of the present disclosure includes an interposer and a component mounted on the interposer. The assembly includes a first die and a second die disposed over the first die having a surface distal from the first die. The second die includes a metal pad. A top surface of the metal pad is coplanar with the surface. The metal pad is electrically floating. The embodiment of the invention also relates to a package structure, a semiconductor package and a method of forming the same.

Description

Technical Field

[0001] Embodiments of the present application relate to a packaging structure, a semiconductor package, and a method for forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced multiple generations of ICs, each with smaller and more complex circuits than the previous generation. In the course of IC development, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This shrinking process generally provides benefits by increasing production efficiency and reducing associated costs. Such shrinking has also increased the complexity of processing and manufacturing ICs.

[0003] In addition to smaller device sizes in each generation, packaging technology has evolved to further improve the performance of IC devices. For example, three-dimensional (3D) packaging technology has been introduced to vertically stack multiple IC devices. 3D packaging technology involves the bonding of semiconductor device dies. Summary of the invention

[0004] Some embodiments of the present application provide a semiconductor package, comprising: an interposer; and a component mounted on the interposer and comprising: a first die; and a second die disposed above the first die and comprising a surface away from the first die, wherein the second die comprises a metal pad, wherein a top surface of the metal pad is coplanar with the surface, and wherein the metal pad is electrically floating.

[0005] Some other embodiments of the present application provide a packaging structure, including: an interposer; and a component mounted on the interposer and including: a first die and a second die, the second die being arranged next to the first die, and a third die being arranged above the first die and the second die, wherein the third die includes a rectangular surface away from the first die and the second die, wherein the third die includes four (4) metal pads arranged at four (4) corners of the third die, wherein the top surfaces of the four (4) metal pads are coplanar with the rectangular surface, and wherein the four (4) metal pads are electrically floating.

[0006] Still other embodiments of the present application provide a method for forming a semiconductor package, comprising: forming a patterned mask over a die region on a wafer, the patterned mask exposing a peripheral area of ​​the die region; etching the die region using the patterned mask to form a peripheral groove; depositing a seed layer over the die region and the patterned mask; after depositing the seed layer, removing the patterned mask; after removing the patterned mask, depositing a metal layer over the seed layer; flattening the wafer to form a peripheral metal pad in the peripheral groove; dividing the die region into die; bonding the die to at least another die to form an assembly; and mounting the assembly on a packaging substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The disclosed embodiments are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustration purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 A flow chart of a method 100 for forming a package structure according to various aspects of an embodiment of the present disclosure is shown.

[0009] Figures 2 to 20 Shows the experience of various aspects according to the embodiments of the present disclosure Figure 1 Partial cross-sectional and top views of a wafer or a die region of a wafer at various steps of method 100 .

[0010] Figure 21 to Figure 24 Optional peripheral metal pad arrangements according to various aspects of embodiments of the present disclosure are shown. DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0012] For ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0013] In addition, when "about," "approximately," etc. are used to describe a value or a range of values, as understood by one of ordinary skill in the art, the terms are intended to encompass values ​​within a reasonable range that takes into account variations that inherently occur during manufacturing. For example, based on known manufacturing tolerances associated with manufacturing components having properties associated with the value, a value or range of values ​​encompasses a reasonable range that includes the described value, such as within + / - 10% of the described value. For example, a material layer having a thickness of "about 5 nm" may include a size range from 4.25 nm to 5.75 nm, where the manufacturing tolerance associated with depositing material layers known to one of ordinary skill in the art is + / - 15%.

[0014] Semiconductor packaging technology was once considered only a back-end process that facilitated the interface of chips with external circuits. Times have changed. Computing workloads have changed so much that packaging technology has been brought to the forefront of innovation. Modern packaging integrates multiple chips or dies into a single semiconductor device. Depending on the level of stacking, modern semiconductor packages can have a 3D structure. In a 3D packaging structure, at least two dies are stacked one on top of the other. In order to achieve die stacking, the die is thinned downward to facilitate substrate connection. The warping of the die poses a challenge to reliable die bonding because the warping may strain or damage the bonding structure. The thinning of the die further reduces the structural strength of the die and may aggravate the die warping, which puts additional strain on the bonding integrity. When a heat sink is set above the 3D structure, the die on the top serves as a heat conduction path to the heat sink for the die below. When the bond between two vertically stacked dies is defective, the heat conduction path is disturbed and the thermal resistance increases. The increase in thermal resistance is undesirable because it affects the satisfactory cooling of the die.

[0015] The disclosed embodiments provide a process for forming a peripheral metal pad at the corner of a die in a package structure or along the edge of a die in a package structure to reduce non-bonding between two vertically stacked dies and improve thermal performance. For one or more of the dies in the package structure, a photolithography and etching process is used to form a peripheral groove. After depositing the seed layer, an electrochemical plating technique is used to deposit a metal layer. Flattening of the metal layer above the peripheral groove forms a peripheral metal pad. The peripheral metal pad is electrically floating and is used to reduce die warpage and provide a high thermal conductivity heat conduction path.

[0016] Various aspects of the disclosed embodiments will now be described in more detail with reference to the accompanying drawings. Figure 1 1 is a flow chart illustrating a method 100 of forming a package structure. The method 100 is merely an example and is not intended to limit the disclosed embodiments to those explicitly shown in the method 100. Additional steps may be provided before, during, and after the method 100, and some of the steps described may be replaced, eliminated, or moved around for additional embodiments of the method. For the sake of simplicity, not all steps are described in detail herein. Figures 2 to 20 Describing method 100, Figures 2 to 20 are partial cross-sectional and top views of wafers, die regions, package components, and package structures at different stages of fabrication according to various embodiments of method 100 . Figure 21 to Figure 24 Alternative embodiments with different peripheral metal pad configurations are shown. For the avoidance of doubt, Figures 2 to 24 The X, Y and Z directions are perpendicular to each other. Throughout the embodiments of the present disclosure, the same reference numerals represent the same components unless otherwise explicitly described.

[0017] refer to Figure 1 and Figures 2 to 4 The method 100 includes a block 102 in which a wafer 20 having a die region 200 is thinned. Figure 2 As shown in , the wafer 20 may be circular in shape and have a diameter such as 200 mm (ie, 8 inches) or 300 mm (ie, 12 inches). Figure 3In some embodiments shown in , the wafer 20 includes a substrate 202 and an interconnect structure 201. The substrate 202 includes a front side 202F and a back side 202B. The interconnect structure 201 is manufactured above the front side 202F of the substrate 202. In the described embodiments, the wafer 20 has undergone front-end-of-line (FEOL), middle-end-of-line (MEOL), and back-end-of-line (BEOL) processes. Therefore, the substrate 202 includes active devices on the front side 202F. The active devices may include planar devices or multi-gate devices. A multi-gate device generally refers to a device having a gate structure or a portion thereof disposed above more than one side of a channel region. Fin field effect transistors (FinFETs) and full-all-around gate (GAA) transistors are examples of multi-gate devices, which have become popular and promising candidate devices for high-performance and low-leakage applications. FinFETs have an elevated channel wrapped by a gate on more than one side (e.g., a gate wraps around the top and sidewalls of a semiconductor material "fin" extending from a substrate). The GAA transistor has a gate structure that can extend partially or completely around the channel region to provide access to the channel region on two or more sides. Because its gate structure surrounds the channel region, the GAA transistor can also be called a surround gate transistor (SGT) or a multi-bridge channel (MBC) transistor. The channel region of the GAA transistor can be formed by nanowires, nanosheets or other nanostructures, and therefore, the GAA transistor can also be called a nanowire transistor or a nanosheet transistor. The interconnect structure 201 may include 5 to 20 metallization layers. Each of the metallization layers includes a metal wire disposed in an intermetallic dielectric (IMD) layer. In some embodiments, the interconnect structure 201 has a total thickness of less than 10 μm. Because the substrate 202 has a thickness on the order of hundreds of microns, the thickness of the substrate 202 accounts for most of the total thickness of the wafer 20.

[0018] The substrate 202 may include silicon. Alternatively, the substrate 202 may include other semiconductors, such as germanium (SiGe), silicon carbide (SiC), silicon germanium (SiGe), or diamond. In addition, the substrate 202 may optionally include an epitaxial layer (epi layer), may be strained for performance enhancement, may include a silicon-on-insulator (SOI) or germanium-on-insulator (GeOI) structure, and / or may have other suitable enhancement components. Although not explicitly shown in the figure, the substrate 202 may include various doping configurations for forming active devices. The doping configuration includes an n-type well and a p-type well formed on the wafer 20. The n-type well is doped with an n-type dopant that may include phosphorus (P), arsenic (As), or antimony (Sb). The p-type well is doped with a p-type dopant that may include boron (B) or gallium (Ga). The well is used to reduce leakage through the substrate. In some instances, an n-type active device is formed above the p-type well, and a p-type active device is formed above the n-type well. Suitable doping may be implemented using ion implantation and / or diffusion processes of dopants.

[0019] The substrate 202 in the wafer 20 has a first thickness T1. In some examples, the first thickness T1 ( Figure 3 ) is between about 750 μm and about 800 μm, such as 775 μm. Figure 2 As shown in FIG. 1 , wafer 20 includes a plurality of die regions 200. In block 102, as shown in FIG. Figure 4 As shown in , the back side 202B of the substrate 202 is subjected to a grinding and polishing step to have a reduced second thickness T2 that is less than the first thickness T1. The polishing step in box 102 may include chemical mechanical polishing (CMP). In some embodiments, the second thickness T2 may be between about 300 μm and about 350 μm. The second thickness T2 is less than the first thickness T1. In some instances, the second thickness T2 is less than half of the first thickness T1. For ease of illustration, the operations in boxes 104-114 are described below with respect to the die area 200 on the wafer 20, even though these operations are also performed on other die areas of the wafer 20. Because the thickness of the interconnect structure 201 is much less than the thickness of the substrate 202, the second thickness T2 is substantially similar to the total thickness of the wafer 20.

[0020] refer to Figure 1 , Figure 5 and Figure 6 The method 100 includes a block 104 in which a patterned mask 204 is formed over the die region 200 to expose the peripheral region 202P. After thinning the wafer 20, a patterned mask 204 is formed over the back side 202B of the thinned substrate 202, such as Figure 5 As shown in . The patterned mask 204 may include a photoresist. In one embodiment, the photoresist is a material that can be removed in a wet chemical stripping process. In an exemplary process, a photoresist layer is deposited over the back side 202B of the substrate 202. After a pre-bake process, the photoresist layer is exposed to radiation that passes through or is reflected from the photomask, baked in a post-bake process, and developed in a developer solution to form a patterned photoresist layer for use as the patterned mask 204. In the depicted embodiment, the patterned mask 204 includes a peripheral opening 205 (or a peripheral groove 205) to expose the peripheral area 202P. In Figure 6 In some embodiments shown in , each of the peripheral openings 205 is rectangular in shape and is disposed at one of the four (4) corners of the die area 200, which may be rectangular in shape. As will be further described below, in some embodiments, the peripheral openings 205 may extend along the periphery of the die area to have an annular shape. In some other embodiments, each of the peripheral openings 205 may have a triangular shape, a circular shape, or a polygonal shape, and may occupy one of the four (4) corners of the die area 200.

[0021] refer to Figure 1 and Figure 7 , method 100 includes box 106, in which the peripheral region 202P is etched to form a recess 206. With the patterned mask 204 in place, an anisotropic etch is performed in box 106 to recess the exposed peripheral region 202P. The anisotropic etch can be a dry etch performed using an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBr3), an iodine-containing gas, other suitable gases and / or plasmas, and / or combinations thereof. Figure 7 In some embodiments shown in , the groove 206 formed by the operation in frame 106 can have a groove depth R. In some examples, the groove depth R is between about 0.01% (i.e., 1%) and about 0.05% (i.e., 5%) of the second thickness T2 of the thinned substrate 202. That is, the ratio of the depth R to the second thickness T2 is between about 1 / 100 and about 1 / 20. In some examples, the depth R can be between about 3 μm and about 15 μm. The shape of the groove 206 generally follows the shape of the peripheral opening 205. When the peripheral opening 205 is rectangular, the groove 206 is rectangular. When the peripheral opening 205 extends along the periphery of the back side 202B of the substrate 202, the groove 206 is annular. When the peripheral opening 205 is circular, triangular, or polygonal, the groove 206 can have a circular, triangular, or polygonal profile in a top view.

[0022] refer to Figure 1 and Figure 8 , method 100 includes block 108, wherein a seed layer 208 is deposited over wafer 20 and patterned mask 204. In some embodiments, seed layer 208 may include titanium (Ti), copper (Cu), or a combination thereof. In some embodiments, seed layer 208 is deposited over back side 202B and patterned mask 204 using physical vapor deposition (PVD), sputtering, or metal organic chemical vapor deposition. In one embodiment, seed layer 208 is deposited by sputtering. In some embodiments, seed layer 208 may be about 1000 Å thick. Peace Between. Figure 8 As shown in , because the deposition of the seed layer 208 is not selective, it is deposited not only over the peripheral region 202P but also over the top surface and sidewalls of the patterned mask 204 .

[0023] refer to Figure 1 and Figures 9 and 10, method 100 includes block 110, wherein patterned mask 204 is removed. In some embodiments, patterned mask 204 is removed by a wet stripping process. An exemplary wet stripping process may include using a chemical stripper. An exemplary chemical stripper may be a mixture of sulfuric acid and hydrogen peroxide, which may be referred to as a sulfur peroxide mixture (SPM). Fig. 9 As shown in , the removal of the patterned mask 204 also removes the seed layer 208 deposited along the top surface and sidewalls of the patterned mask 204. Fig. 9 and Fig.10 As shown in FIG. 2 , after removing the patterned mask 204, the peripheral region 202P and the sidewall 202S of the substrate 202 exposed in the groove 206 remain covered by the seed layer 208. This is why in cross-sectional views such as Fig. 9 In the cross-sectional view shown in , the seed layer 208 may have an L-shaped profile. The seed layer 208 provides deposition selectivity in the subsequent metal layer deposition process and allows the metal layer deposited thereon to be denser. When the peripheral opening 205 is rectangular, the seed layer 208 in the peripheral region 202P is rectangular. When the peripheral opening 205 extends along the periphery of the back side 202B of the substrate 202 to form a ring, the seed layer 208 in the peripheral region 202P is annular. When the peripheral opening 205 is circular, triangular, or polygonal, the seed layer 208 in the peripheral region 202P may have a circular, triangular, or polygonal profile in a top view.

[0024] refer to Figure 1 and Fig.11 , method 100 includes box 112, in which a metal layer 210 is deposited. In some embodiments, the metal layer 210 includes aluminum (Al), copper (Cu) or aluminum copper (AlCu). In box 112, the metal layer 210 is deposited using an electrochemical plating (ECP) process. In an exemplary process, the wafer 20 is placed in a plating container filled with a plating solution. When the metal layer 210 includes copper (Cu), the plating solution may include a mixture of copper salts, acids, water, and various organic and inorganic additives that improve the properties of the deposited copper. Suitable copper salts in the plating solution may include copper sulfate, copper cyanide, copper sulfamate, copper chloride, copper formate, copper fluoride, copper nitrate, copper oxide, copper fluoroborate, copper trifluoroacetate, copper pyrophosphate, and copper methanesulfonate or a hydrate of any of the foregoing compounds. The ECP process may continue until the metal layer 210 reaches a thickness between 3 μm and about 15 μm. Although ECP is preferentially deposited above the seed layer 208, as Fig.11 As shown in , however, a thinner metal layer 210 may be formed over the exposed portions of the substrate 202 .

[0025] refer to Figure 1 and Figure 12 to Figure 13, the method 100 includes a block 114, in which the wafer 20 is planarized to form a peripheral metal pad 212 in the recess 206. In block 114, a chemical mechanical polishing (CMP) process is performed on the wafer 20 to provide a planar surface, in which the metal layer 210 and the top surface of the substrate 202 are coplanar. At this point, the planarized metal layer 210 and the underlying seed layer 208 can be collectively referred to as a peripheral metal pad 212 or a pad 212. Fig.13 In some embodiments shown in , each of the peripheral regions 202P is rectangular in shape, and the resulting pads 212 are also rectangular in shape. In some instances, the die region 200 is rectangular and has a first edge dimension D1, and each of the rectangular pads 212 may have a second edge dimension D2. The first edge dimension D1 may be between about 5000 μm and about 33000 μm. The second edge dimension D2 is less than the first edge dimension D1. The second edge dimension D2 may be between about 20 μm and about 500 μm. It has been observed that the corner non-bonding or delamination area may have a size of about 500 μm. However, in order to address the corner non-bonding situation, the pads may be much smaller. Depending on the design, the exposed back side 202B of the substrate 202 may include a semiconductor material (e.g., silicon) or a dielectric material (e.g., silicon oxide).

[0026] Figure 21 to Figure 24 An alternative embodiment is shown in which peripheral metal pad 212 comprises a different shape due to the shape of peripheral opening 205 of the patterned mask. Fig.21 An annular pad 212R is shown having a top surface that is coplanar with the substrate 202. The annular pad 212R extends continuously and completely around the perimeter of the die region 200. That is, the edges of the annular pad 212R and the edges of the die region 200 may be similar. Fig. 22 Four (4) triangular pads 212T are shown disposed at four (4) corners of the die region 200. The four (4) triangular pads 212T have a top surface coplanar with the back side 202B of the substrate 202. In some embodiments, in a top view, each of the four (4) triangular pads 212T has a shape of a right triangle with two legs (i.e., right angled sides). Each of the legs may have a length similar to the second edge dimension D2 described above. Fig.23 Four (4) circular pads 212C are shown disposed at four (4) corners of the die region 200. The four (4) circular pads 212C have a top surface coplanar with the back side 202B of the substrate 202. In some embodiments, in top view, each of the four (4) circular pads 212C has a circular, elliptical, or racetrack shape. The diameter, major axis, or length of the circular pads 212C may be similar to the second edge dimension D2 described above. Fig.24Four (4) polygonal pads 212P are shown disposed at the four (4) corners of the die region 200. The four (4) polygonal pads 212P have top surfaces that are coplanar with the back side 202B of the substrate 202. Fig.24 In some embodiments shown in the figure, in the top view, each of the four (4) polygonal pads 212P has a hexagonal shape. In some optional embodiments not explicitly shown in the figure, each of the four (4) polygonal pads 212P has a pentagonal or octagonal shape. The length or width of the polygonal pad 212P can be similar to the second edge dimension D2 described above.

[0027] refer to Figure 1 and Fig.14 , the method 100 includes a block 116, wherein a singulation process is performed to cut out the die 200 from the die region 200 of the wafer 20. The operations in the blocks 102-114 described above are performed when the die region 200 is a region of the wafer 20 and the wafer 20 is not singulated and undergoes these operations as a whole. In block 116, a singulation process is performed on the wafer 20 to cut out the die region 200 from the wafer 20 to form the die 200. The die 200 may be a system-on-chip (SoC) die, a logic die, or an application-specific integrated circuit (ASIC) die. It should be noted that the pads 212 (regardless of their shape) are disposed above the blank area of ​​the substrate 202. To this end, the pads 212 are not in contact with any contact components and are therefore electrically floating. Because the pads 212 are formed of metal, their coefficient of thermal expansion (CTE) and thermal conductivity are much greater than the substrate 202. The high CTE allows the pads 212 to control or counteract warping of the die 200 during a subsequent bonding process. By controlling the warping, the pads 212 prevent non-bonding with one or more dies or heat sinks disposed above or below the die 200. The high thermal conductivity of the pads 212 improves heat transfer to the die or heat sink that will be bonded to the back side 212B of the substrate.

[0028] refer to Figure 1 and Fig.15 , method 100 includes block 118, in which die 200 is bonded to at least one other die to form a first package assembly 250. Although not explicitly shown in the figures, die 200 may include contact pads on both sides and may include through substrate vias (TSVs) extending through substrate 202 to provide electrical connections through the entire thickness of die 200. Fig.15In some embodiments shown in , die 200 is bonded to die 300 and die 400. Like die 200, each of die 300 and die 400 can be a SoC die, a logic die or an ASIC die. In some embodiments, die 200 is bonded to die 300 and die 400 using direct bonding. When die 200 is bonded to die 300 and die 400 using direct bonding, the bonding contact pads on die 200 are vertically aligned with the bonding contact pads on die 300 and die 400. The bonding contact pads are surrounded by a dielectric layer. In an exemplary direct bonding process, after cleaning and treating the surfaces of the dielectric layer and the bonding contact pads with plasma, the die is heated and the bonding contact pads are aligned to form metal-to-metal and dielectric-to-dielectric bonding. The molding material can be disposed laterally between die 300 and die 400. The stacking structure of die 200 , die 300 , and die 400 may be collectively referred to as a first packaging assembly 250 .

[0029] refer to Figure 1 and Fig.16 , the method 100 includes block 120, wherein the first package component 250 is bonded to the package substrate 700. Fig.16 In some embodiments shown in , frame 120 first bonds the first package component 250 to the interposer 600 through the first connection component 260. In some embodiments, the first connection component 260 may include a microbump, a metal column, or a solder component. The space between the interposer 600 and the first package component 250 may be filled with a first bottom filler 280. The interposer 600 may include a semiconductor material or glass. In one embodiment, the interposer 600 includes silicon (Si). In some optional embodiments, the interposer 600 includes silicon germanium (SiGe) or silicon carbon (SiC). In the depicted embodiment, the memory package component 500 is also bonded to the interposer 600. In some embodiments, the memory package component 500 may include a high bandwidth memory (HBM) component. The memory package component 500 may include a controller die and a vertical stack of multiple memory dies. Each of the multiple memory dies may be a dynamic random access memory (DRAM) die, and the controller die is configured to read from the multiple memory dies and write to the multiple memory dies. Like package assembly 250, memory package assembly 500 may be bonded to interposer 600 by connection features similar to first connection features 260. The space between interposer 600 and memory package assembly 500 may be filled with an underfill similar to first underfill 280. In some examples, first underfill 280 may include a polymer or epoxy.

[0030] In block 120, the interposer 600 is bonded to the package substrate 700 via the second connection feature 620. The package substrate 700 includes a front side surface 700F and a back side surface 700B. Fig.16 In the embodiment of the present invention, the interposer 600 is bonded to the front side surface 700F of the package substrate 700. The third connection component 720 is deposited above the back side surface 700B of the package substrate 700. In some embodiments, the second connection component 620 may include a controlled collapse chip connection (C4) bump or other solder bump. The third connection component 720 may include a solder component or a solder ball, and may include a ball grid array (BGA). In some embodiments, the package substrate 700 may include a printed circuit board (PCB) or the like. Although not explicitly shown in the component, the package substrate 700 may include a substrate through hole (TSV) or a hole connector extending from the front side surface 700F to the back side surface 700B. In addition, in order to electrically couple to the interposer 600, the package substrate 700 may include a plurality of contact pads above the front side surface 700F. In order to electrically couple to the third connection component 720 above the back side surface 700B, the package substrate 700 may also include a plurality of contact pads or under-bump metal (UBM) components above the back side surface 700B. The space between the interposer 600 and the package substrate 700 is filled with a second underfill 640. Like the first underfill 280, the second underfill 640 may include a polymer or epoxy resin. Fig.16 It is not explicitly shown in FIG. 6 , but a molding material may be deposited around the sidewalls of the interposer 600 , the sidewalls of the memory package 500 , and the sidewalls of the package 250 .

[0031] Figures 17 to 20 An alternative multi-die package structure is shown that may similarly benefit from pads 212 formed using methods similar to method 100 described above.

[0032] First reference Fig.17 . Fig.17 A second package assembly 252 is shown. Instead of being bonded to dies 300 and 400 which do not have pads 212, die 200 is bonded to dies 302 and 402. Fig.17 In the embodiment shown in , each of the dies 302 and 402 includes pads similar to the pads 212 on the die 200. It should be understood that the pads on the dies 302 and 402 can be manufactured by following the method 100 described above. The dies 200, 302, and 402 are stacked and bonded together to form the second package assembly 252. In Fig.17In the multi-die package structure shown in FIG. 2 , the second package component 252 is bonded to the interposer 600 together with the memory package component 500 through the first connection component 260. The interposer 600 is bonded to the package substrate 700 using the second connection component 620. The package substrate 700 includes a third connection component 720 on the backside surface 700B, so that the package substrate 700 can be further bonded to other structures. Fig.17 The pad 212 shown in FIG. 1 may include a rectangular pad 212 ( Fig.13 ), annular pad 212R ( Fig.21 ), triangular pad 212T ( Fig. 22 ), circular pad 212C ( Fig.23 ) or polygonal pad 212P ( Fig.24 ).

[0033] Then refer to Fig.18 . Fig.18 A third package assembly 254 is shown. Fig.18 In the embodiment, die 200A is bonded to die 302 and 402 without any pads 212. Each of die 302 and 402 includes pads similar to pads 212 on die 200. It should be understood that the pads on die 302 and 402 can be manufactured by following method 100 described above. Die 200A, die 302, and die 402 are stacked and bonded together to form third package assembly 254. In Fig.18 In the multi-die package structure shown in FIG. 1 , the third package component 254 is bonded to the interposer 600 together with the memory package component 500 through the first connection component 260. The interposer 600 is bonded to the package substrate 700 using the second connection component 620. The package substrate 700 includes the third connection component 720 on the backside surface 700B, so that the package substrate 700 can be further bonded to other structures. Fig.18 The pad 212 shown in FIG. 1 may include a rectangular pad 212 ( Fig.13 ), annular pad 212R ( Fig.21 ), triangular pad 212T ( Fig. 22 ), circular pad 212C ( Fig.23 ) or polygonal pad 212P ( Fig.24 ).

[0034] Reference now Fig.19 . Fig.19A fourth package assembly 256 is shown next to package assembly 250. Fourth package assembly 256 includes die 302 and 402 bonded to die 200A without any pads 212. Instead of having die 200A on top of die 302 and 402, die 200A is disposed below die 302 and 402. Each of die 302 and 402 includes pads similar to pads 212 on die 200. It should be understood that the pads on die 302 and 402 may be manufactured by the following method 100 described above. Die 302, die 402, and die 200A are stacked and bonded together to form fourth package assembly 256. In Fig.19 In the multi-die package structure shown in FIG. 1 , the fourth package component 256 is bonded to the interposer 600 together with the package component 250 through the first connection feature 260. The interposer 600 is bonded to the package substrate 700 using the second connection feature 620. The package substrate 700 includes a third connection feature 720 on the backside surface 700B, so that the package substrate 700 can be further bonded to other structures. Fig.19 The pad 212 shown in FIG. 1 may include a rectangular pad 212 ( Fig.13 ), annular pad 212R ( Fig.21 ), triangular pad 212T ( Fig. 22 ), circular pad 212C ( Fig.23 ) or polygonal pad 212P ( Fig.24 ).

[0035] Then refer to Fig. 20 . Fig. 20 A fifth package assembly 258 is shown. Fig. 20 , the fifth package assembly 258 includes two dies 200, a die 302, and a die 402. The dies 302 and 402 are placed side by side and bonded to one of the two dies 200. The other of the two dies 200 is bonded over the dies 302 and 402. All the dies in the fifth package assembly 258 include pads 212. Fig. 20 In the multi-die package structure shown in FIG. 1 , the fifth package component 258 is bonded to the interposer 600 together with the optional memory package component 502 through the first connection feature 260. The optional memory package component 502 may include more memory dies than the memory package component 500. The interposer 600 is bonded to the package substrate 700 using the second connection feature 620. The package substrate 700 includes a third connection feature 720 on the backside surface 700B, so that the package substrate 700 can be further bonded to other structures. Fig. 20 The pad 212 shown in FIG. 1 may include a rectangular pad 212 ( Fig.13 ), annular pad 212R ( Fig.21 ), triangular pad 212T ( Fig. 22 ), circular pad 212C ( Fig.23 ) or polygonal pad 212P ( Fig.24 ).

[0036] The present disclosure provides many embodiments. In one aspect, the present disclosure provides a semiconductor package. The semiconductor package includes: an interposer; a component mounted on the interposer and including: a first die; and a second die disposed above the first die and including a surface away from the first die. The second die includes a metal pad. The top surface of the metal pad is coplanar with the surface. The metal pad is electrically floating.

[0037] In some embodiments, the semiconductor package further comprises: a high bandwidth memory (HBM) stack mounted on the interposer. In some embodiments, the metal pad is spaced apart from the second die by a seed layer. In some embodiments, the seed layer comprises titanium. In some embodiments, the metal pad comprises aluminum (Al), copper (Cu) or aluminum copper (AlCu). In some embodiments, the surface of the second die is rectangular in shape. The metal pad is one of four (4) metal pads disposed at four (4) corners of the second die. In some embodiments, each of the four (4) metal pads comprises a rectangular shape, a triangular shape, a ring shape or a polygonal shape. In some embodiments, the surface of the second die comprises a semiconductor or dielectric material.

[0038] On the other hand, an embodiment of the present disclosure provides a packaging structure. The packaging structure includes: an interposer; and a component mounted on the interposer and including: a first tube core and a second tube core, the second tube core is arranged next to the first tube core; a third tube core is arranged above the first tube core and the second tube core. The third tube core includes a rectangular surface away from the first tube core and the second tube core. The third tube core includes four (4) metal pads arranged at four (4) corners of the third tube core. The top surface of the four (4) metal pads is coplanar with the rectangular surface. The four (4) metal pads are electrically floating.

[0039] In some embodiments, each of the four (4) metal pads includes a seed layer and a metal layer disposed on the seed layer. In some embodiments, the seed layer includes titanium (Ti), and the metal layer includes aluminum (Al), copper (Cu) or aluminum copper (AlCu). In some embodiments, each of the four (4) metal pads includes a rectangular shape, a triangular shape, an annular shape, or a polygonal shape. In some embodiments, the four (4) metal pads have the same size. In some embodiments, the package structure further includes: a high bandwidth memory (HBM) stack mounted on the interposer. In some embodiments, the third die includes a semiconductor substrate, and the semiconductor substrate includes a first thickness. Each of the four (4) metal pads includes a second thickness, and a ratio of the first thickness to the second thickness is between about 20 and about 100.

[0040] In another aspect, the present disclosure provides a method. The method includes: forming a patterned mask over a die region on a wafer, the patterned mask exposing a peripheral area of ​​the die region; etching the die region using the patterned mask to form a peripheral groove; depositing a seed layer over the die region and the patterned mask; after depositing the seed layer, removing the patterned mask; after removing the patterned mask, depositing a metal layer over the seed layer; flattening the wafer to form a peripheral metal pad in the peripheral groove; dividing the die region into dies; bonding the die to at least another die to form an assembly; and mounting the assembly on a package substrate.

[0041] In some embodiments, the package substrate includes an interposer. In some embodiments, the deposition of the seed layer includes deposition of titanium by sputtering. In some embodiments, the seed layer includes about Peace In some examples, depositing the metal layer includes using electrochemical plating.

[0042] Some embodiments of the present application provide a semiconductor package, comprising: an interposer; and a component mounted on the interposer and comprising: a first die; and a second die disposed above the first die and comprising a surface away from the first die, wherein the second die comprises a metal pad, wherein a top surface of the metal pad is coplanar with the surface, and wherein the metal pad is electrically floating.

[0043] In some embodiments, the semiconductor package further comprises: a high bandwidth memory (HBM) stack mounted on the interposer. In some embodiments, the metal pad is spaced apart from the second die by a seed layer. In some embodiments, the seed layer comprises titanium. In some embodiments, the metal pad comprises aluminum (Al), copper (Cu), or aluminum copper (AlCu). In some embodiments, the semiconductor package, wherein the surface of the second die is rectangular in shape, wherein the metal pad is one of four (4) metal pads disposed at four (4) corners of the second die. In some embodiments, each of the four (4) metal pads comprises a rectangular shape, a triangular shape, a ring shape, or a polygonal shape. In some embodiments, the surface of the second die comprises a semiconductor or dielectric material.

[0044] Some other embodiments of the present application provide a packaging structure, including: an interposer; and a component mounted on the interposer and including: a first die and a second die, the second die being arranged next to the first die, and a third die being arranged above the first die and the second die, wherein the third die includes a rectangular surface away from the first die and the second die, wherein the third die includes four (4) metal pads arranged at four (4) corners of the third die, wherein the top surfaces of the four (4) metal pads are coplanar with the rectangular surface, and wherein the four (4) metal pads are electrically floating.

[0045] In some embodiments, each of the four (4) metal pads includes a seed layer and a metal layer disposed on the seed layer. In some embodiments, wherein the seed layer comprises titanium (Ti), wherein the metal layer comprises aluminum (Al), copper (Cu) or aluminum copper (AlCu). In some embodiments, each of the four (4) metal pads includes a rectangular shape, a triangular shape, an annular shape or a polygonal shape. In some embodiments, the four (4) metal pads have the same size. In some embodiments, the package structure further includes: a high bandwidth memory (HBM) stack mounted on the interposer. In some embodiments, wherein the third die includes a semiconductor substrate, wherein the semiconductor substrate includes a first thickness, wherein each of the four (4) metal pads includes a second thickness, wherein a ratio of the first thickness to the second thickness is between about 20 and about 100.

[0046] Still other embodiments of the present application provide a method for forming a semiconductor package, comprising: forming a patterned mask over a die region on a wafer, the patterned mask exposing a peripheral area of ​​the die region; etching the die region using the patterned mask to form a peripheral groove; depositing a seed layer over the die region and the patterned mask; after depositing the seed layer, removing the patterned mask; after removing the patterned mask, depositing a metal layer over the seed layer; flattening the wafer to form a peripheral metal pad in the peripheral groove; dividing the die region into die; bonding the die to at least another die to form an assembly; and mounting the assembly on a packaging substrate.

[0047] In some embodiments, the package substrate includes an interposer. In some embodiments, depositing the seed layer includes depositing titanium by sputtering. In some embodiments, the seed layer includes about Peace In some embodiments, depositing the metal layer comprises using electrochemical plating.

[0048] The features of several embodiments are summarized above so that those of ordinary skill in the art can better understand the various aspects of the embodiments of the present disclosure. Those of ordinary skill in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those of ordinary skill in the art should also be aware that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A semiconductor package, comprising: Intermediary layer; as well as An assembly mounted on the interposer and comprising: a first die; and a second tube die disposed above the first tube die and including a surface away from the first tube die, wherein the second die comprises a metal pad, wherein the top surface of the metal pad is coplanar with the surface, Wherein, the metal pad is electrically floating.

2. The semiconductor package according to claim 1, further comprising: A high bandwidth memory (HBM) stack is mounted on the interposer.

3. The semiconductor package according to claim 1, wherein: The metal pad is spaced apart from the second die by a seed layer.

4. The semiconductor package according to claim 3, wherein: The seed layer includes titanium.

5. The semiconductor package according to claim 1, wherein: The metal pad includes aluminum (Al), copper (Cu) or aluminum copper (AlCu).

6. The semiconductor package according to claim 1, in, said surface of said second die being rectangular in shape, The metal pad is one of four (4) metal pads disposed at four (4) corners of the second die.

7. The semiconductor package according to claim 6, wherein: Each of the four (4) metal pads includes a rectangular shape, a triangular shape, a ring shape, or a polygonal shape.

8. The semiconductor package according to claim 1, wherein: The surface of the second die includes a semiconductor or dielectric material.

9. A packaging structure, comprising: Intermediary layer; as well as An assembly mounted on the interposer and comprising: a first tube die and a second tube die, the second tube die being arranged beside the first tube die, A third tube die is arranged above the first tube die and the second tube die, The third tube core comprises a rectangular surface away from the first tube core and the second tube core, wherein the third die comprises four (4) metal pads disposed at four (4) corners of the third die, wherein the top surfaces of the four (4) metal pads are coplanar with the rectangular surface, Wherein, the four (4) metal pads are electrically floating.

10. A method of forming a semiconductor package, comprising: forming a patterned mask over a die region on a wafer, wherein the patterned mask exposes a peripheral area of ​​the die region; etching the die region using the patterned mask to form a peripheral recess; depositing a seed layer over the die region and the patterned mask; After depositing the seed layer, removing the patterned mask; depositing a metal layer over the seed layer after removing the patterned mask; planarizing the wafer to form a peripheral metal pad in the peripheral recess; dividing the tube core area into tube cores; bonding the die to at least another die to form an assembly; as well as The components are mounted on a packaging substrate.

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