Dual feedback branch current compensated charge pump circuit

Abstract

The application discloses a double feedback branch current compensation type charge pump circuit, which comprises a core circuit, a double feedback branch and a bias circuit connected in sequence, wherein the input node of the double feedback branch is connected with the core circuit for detecting the potential change of the output voltage, the first output node of the first feedback branch in the double feedback branch is connected with the gate of the bias circuit, the second output node of the second feedback branch is connected with the bias circuit, and the up and down charging and discharging currents are carried out phased current compensation through the bias circuit according to the degree of the output voltage deviating from the center potential. The application solves the mismatching problem of the up and down charging and discharging currents when the output voltage deviates from the center potential through the double feedback branch, can convert the phase error output by the frequency discriminator into the difference between the charging and discharging currents, charges and discharges the loop filter to generate the control voltage of the voltage controlled oscillator, thereby realizing the lower charging and discharging current mismatching in the wider control voltage range, the smaller ripple on the output voltage, and the optimization of the jitter performance of the output clock of the phase-locked loop.

Description

Technical Field

[0001] This invention relates to a technology in the field of phase-locked loops, specifically a charge pump circuit with dual feedback branch current compensation. Background Technology

[0002] Due to the channel length modulation effect, the greater the deviation of the control voltage from the center potential, the greater the mismatch between the upper and lower charging and discharging current sources in a charge pump. Summary of the Invention

[0003] This invention addresses the insufficient current compensation in existing technologies when the output voltage deviates significantly from the center potential. It proposes a dual-feedback branch current-compensated charge pump circuit, which solves the mismatch problem of charging and discharging currents when the output voltage deviates significantly from the center potential. This circuit converts the phase error output by the frequency and phase detector into a difference in charging and discharging current, which charges and discharges the loop filter to generate the control voltage of the voltage-controlled oscillator. This achieves lower charging and discharging mismatch and smaller ripple on the output voltage within a wider control voltage range, thus optimizing the jitter performance of the phase-locked loop output clock.

[0004] This invention is achieved through the following technical solution:

[0005] This invention relates to a dual-feedback branch current-compensated charge pump circuit, comprising: a core circuit, dual feedback branches, and a bias circuit connected in sequence. The input node of the dual feedback branch is connected to the core circuit for detecting potential changes in the output voltage. The first output node of the first feedback branch in the dual feedback branch is connected to the gate of the bias circuit, and the second output node of the second feedback branch is connected to the bias circuit. Based on the degree to which the output voltage deviates from the center potential, the bias circuit performs staged current compensation for the upper and lower charge / discharge currents.

[0006] Technical effect

[0007] This invention employs a dual-feedback branch to compensate for the charge pump's charging and discharging current. Based on the degree to which the output voltage deviates from the center potential, the compensation process is divided into two stages, providing phased compensation for the charging and discharging current. When the output voltage deviates slightly from the center potential, part of the feedback branch is off, and compensation is only achieved through a portion of the feedback branch. When the output voltage deviates significantly from the center potential, part of the feedback branch is on, increasing the degree of compensation for the charging and discharging current. This phased compensation saves overall circuit power consumption and achieves more precise current compensation. Compared to existing technologies, this invention, under conditions of a power supply voltage of 0.9V and a charge pump current Icp of 65uA, achieves a maximum trans mismatch of less than 300nA in the range of 0.1-0.8V for the charge pump's output voltage. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of the charge pump circuit of the present invention;

[0009] In the diagram: the red line represents the first feedback branch, and the blue line represents the second feedback branch;

[0010] Figure 2 Schematic diagram of a rail-to-rail input operational amplifier;

[0011] Figure 3 This is a schematic diagram of the TRAN_mismatch simulation effect under TT_0.9V_27℃ conditions. Detailed Implementation

[0012] like Figure 1 As shown, this embodiment relates to a dual-feedback branch current-compensated charge pump circuit, including: a first feedback branch, a second feedback branch, a core circuit, and a bias circuit. The gate of the tenth PMOS transistor M10 in the bias circuit is connected to the gate of the nineteenth PMOS transistor M19 in the core circuit and the second output node of the second feedback branch. The gate of the eighth NMOS transistor M8 in the bias circuit is connected to the gate of the twentieth NMOS transistor M20 in the core circuit and the first output node of the first feedback branch. The input node of the dual-feedback branch is connected to the node of the left branch in the core circuit located between the first transmission gate TG1 and the third transmission gate TG3.

[0013] The bias circuit includes: six NMOS transistors M0-M3, M7, and M8; five PMOS transistors M4-M6, M9, and M10; and two resistors R1 and R2. The bias current input terminal i_bias is connected to one end of the first resistor R1, the gate of the zeroth NMOS transistor M0, and the gate of the seventh NMOS transistor M7. The other end of the first resistor R1 is connected to the gate of the first NMOS transistor M1, the gate of the second NMOS transistor M2, the gate of the third NMOS transistor M3, and the drain of the zeroth NMOS transistor. The source of the zeroth NMOS transistor is connected to the drain of the first NMOS transistor M1. The drain of the second NMOS transistor M2 is connected to the gate of the fourth PMOS transistor and the gate of the ninth PMOS transistor. The gate of the S-channel transistor is connected to one end of the second resistor R2. The other end of the second resistor R2 is connected to the gate of the fifth PMOS transistor M5, the gate of the sixth PMOS transistor M6, and the drain of the fourth PMOS transistor M4. The source of the fourth PMOS transistor M4 is connected to the drain of the fifth PMOS transistor M5. The drain of the sixth PMOS transistor M6 is connected to the drain of the seventh NMOS transistor and the gate of the eighth NMOS transistor M8. The drain of the third NMOS transistor M3 is connected to the drain of the ninth PMOS transistor M9 and the gate of the tenth PMOS transistor. The source of the ninth PMOS transistor M9 is connected to the drain of the tenth PMOS transistor M10. The source of the seventh NMOS transistor M7 is connected to the drain of the eighth NMOS transistor.

[0014] The core circuit includes: four transmission gates TG1, TG2, TG3, and TG4; a rail-to-rail input operational amplifier; a third rail-to-rail input operational amplifier; a twentieth NMOS transistor M20; and a nineteenth PMOS transistor M19. The drain of the nineteenth NMOS transistor is connected to one end of the first transmission gate TG1 and the second transmission gate TG2. The other end of the first transmission gate TG1 is connected to the output terminal and the inverting input terminal of the third rail-to-rail input operational amplifier OP3, as well as one end of the third transmission gate. The other end of the second transmission gate TG2 is connected to the non-inverting input terminal and the output terminal VC of the third rail-to-rail input operational amplifier, as well as one end of the fourth transmission gate TG4. The other ends of the third transmission gate TG3 and the fourth transmission gate TG4 are connected to the drain of the twentieth NMOS transistor. The positive control terminal of the first transmission gate TG1 is connected to the negative control terminal of the second transmission gate TG2 and the switch signal input terminal UPB. The positive control terminal of the third transmission gate TG3 is connected to the negative control terminal of the fourth transmission gate TG4 and the switch signal input terminal DNB. The switch signal input terminal UP is connected to the negative control terminal of the first transmission gate TG1 and the positive control terminal of the second transmission gate TG2. The switch signal input terminal DN is connected to the negative control terminal of the third transmission gate TG3 and the positive control terminal of the fourth transmission gate TG4.

[0015] The first feedback branch includes: a first rail-to-rail input operational amplifier, two PMOS transistors M14 and M16, and two NMOS transistors M12 and M13. The second output node is connected to the gate of the fourteenth PMOS transistor M14 and the drain of the sixteenth PMOS transistor M16. The input node is connected to the gate of the sixteenth PMOS transistor M16 and the positive input terminal of the first rail-to-rail input operational amplifier. The source of the fourteenth PMOS transistor M14 is connected to the inverting input terminal and the output terminal of the first rail-to-rail input operational amplifier. The drain of the fourteenth PMOS transistor M14 is connected to the gate and drain of the thirteenth NMOS transistor M13 and the gate of the twelfth NMOS transistor M12. The drain of the twelfth NMOS transistor M12 is connected to the first output node.

[0016] The second feedback branch includes: a second rail-to-rail input operational amplifier, two PMOS transistors M11 and M17, and two NMOS transistors M15 and M18. The first output node is connected to the gate of the eighteenth PMOS transistor M18 and the drain of the fifteenth NMOS transistor M15. The input node is connected to the gate of the fifteenth NMOS transistor M15 and the positive input terminal of the second rail-to-rail input operational amplifier. The source of the eighteenth NMOS transistor M18 is connected to the inverting input terminal and the output terminal of the second rail-to-rail input operational amplifier. The drain of the eighteenth NMOS transistor M18 is connected to the gate and drain of the seventeenth PMOS transistor M17 and the gate of the eleventh PMOS transistor M11. The drain of the eleventh PMOS transistor M11 is connected to the second output node.

[0017] like Figure 2 As shown, the rail-to-rail input operational amplifier includes a bias structure and a folded common-source amplifier circuit connected thereto, wherein: the gate and drain of the twenty-fifth PMOS transistor M25 in the bias structure are connected to the gates of the twenty-sixth PMOS transistor M26 and the thirty-eighth PMOS transistor M38 in the folded common-source amplifier circuit, and the gate of the twenty-fourth NMOS transistor M24 in the bias structure is connected to the gate of the thirty-first NMOS transistor M31 in the folded common-source amplifier circuit.

[0018] The bias structure includes three PMOS transistors M22, M23, and M25 and two NMOS transistors M21 and M24, wherein: the drain and gate of the twenty-first NMOS transistor M21 are connected to the gate of the twenty-fourth NMOS transistor and the drain of the twenty-second PMOS transistor; the gate of the twenty-second PMOS transistor is connected to the gate of the twenty-third PMOS transistor M23 and ground; the drain of the twenty-third PMOS transistor M23 is connected to the source of the twenty-second PMOS transistor M22; and the drain of the twenty-fourth NMOS transistor M24 is connected to the drain and gate of the twenty-fifth PMOS transistor M25.

[0019] The described folded common-source amplifier circuit includes: six NMOS transistors M29-M31, M34, M35, and M39; eight PMOS transistors M26-M28, M22, M23, and M36-M38; a zero-adjustment resistor R; and a Miller compensation capacitor C. Specifically: the drain of the twenty-sixth PMOS transistor M26 is connected to the source of the twenty-seventh PMOS transistor M27 and the twenty-eighth PMOS transistor M28; the drain of the thirty-first NMOS transistor M31 is connected to the source of the twenty-ninth PMOS transistor M29 and the thirtieth PMOS transistor M30; the positive input terminal VINP is connected to the gate of the twenty-eighth PMOS transistor M28 and the twenty-ninth NMOS transistor M29; the inverting input terminal is connected to the gate of the twenty-seventh PMOS transistor M27 and the thirtieth NMOS transistor M30; and the drain of the twenty-seventh PMOS transistor M27 is connected to the source of the thirty-second PMOS transistor M30. The drain of transistor M32 is connected to the gate and drain of the 34th NMOS transistor M34. The drain of the 28th PMOS transistor M28 is connected to the drain of the 37th PMOS transistor M37, the drain of the 35th NMOS transistor M35, one end of the zero-adjustment resistor R, and the gate of the 39th NMOS transistor M39. The drain of the 29th PMOS transistor M29 is connected to the gate of the 32nd PMOS transistor M32, the drain and gate of the 33rd PMOS transistor M33. The drain of the 30th PMOS transistor M30 is connected to the gate of the 37th PMOS transistor M37, the drain and gate of the 36th PMOS transistor M36. The other end of the zero-adjustment resistor R is connected to one end of the Miller compensation capacitor C. The other end of the Miller compensation capacitor C is connected to the drain of the 39th NMOS transistor M39, the drain of the 38th PMOS transistor M38, and the output terminal VOUT.

[0020] This embodiment uses a voltage regulation method based on the above circuit, including:

[0021] Step 1: When the power supply voltage is 0.9V and the output voltage is in the range of 0.3-0.7V, the voltage followers in the two potential detection circuits detect the potential of the second node. The potential of the second node is the first follower node, i.e., the output potential. Therefore, the potential changes of the first follower node of the third and fourth nodes. At this time, the fourteenth PMOS transistor M14 and the eighteenth PMOS transistor M18 are turned off, and the fifteenth NMOS transistor M15 and the sixteenth PMOS transistor M16 are turned on. The gate potentials of the fifteenth NMOS transistor M15 and the sixteenth PMOS transistor M16 follow the potential changes of the first follower node. The fifteenth NMOS transistor M15 and the sixteenth PMOS transistor M16 draw current from M8 and the tenth PMOS transistor M10, respectively. This is equivalent to the sixteenth PMOS transistor M16 and the fifteenth NMOS transistor M15 drawing the upper and lower charge / discharge currents, respectively. When the output voltage is lower than the center potential, due to the channel length modulation effect, the charging current is greater than the discharging current. At this time, the gate voltages of the fifteenth NMOS transistor M15 and the sixteenth PMOS transistor M16 follow the output potential. The Vgs of the fifteenth NMOS transistor M15 is less than that of the sixteenth PMOS transistor M16, resulting in a current I of the fifteenth NMOS transistor M15 being less than the current I of the sixteenth PMOS transistor M16. Therefore, the sixteenth PMOS transistor M16 draws more current from the charging current than the fifteenth NMOS transistor M15 draws from the discharging current. The difference between the current I of the sixteenth PMOS transistor M16 and the current I of the fifteenth NMOS transistor M15 is used to compensate for the charging and discharging currents. The principle is similar when the output voltage is higher than the center potential.

[0022] Step 2: When the output voltage is in the range of 0.1-0.2V or 0.7-0.8V, since the third and fourth nodes follow the first node, i.e., the output potential changes, the fifteenth NMOS transistor M15 and the sixteenth PMOS transistor M16 are turned on, and the fourteenth PMOS transistor M14 or the eighteenth PMOS transistor M18 is turned on. While the fifteenth NMOS transistor M15 and the sixteenth PMOS transistor M16 perform charge and discharge current compensation as described in Step 1, the turn-on of the fourteenth PMOS transistor M14 or the eighteenth PMOS transistor M18 causes one of the two sets of current mirrors, namely the twelfth and thirteenth NMOS transistors M13 and M12, and the seventeenth and eleventh PMOS transistors M17 and M11, to work, extracting the current of the eighth NMOS transistor M8 or the tenth PMOS transistor M10 for current compensation. When the output voltage is between 0.1 and 0.2V, due to the channel length modulation effect, the charging current is greater than the discharging current. The current drawn by the fifteenth NMOS transistor M15 and the sixteenth PMOS transistor M16 alone is insufficient to compensate for the difference between the charging and discharging currents. At this time, the fourteenth PMOS transistor M14 is turned off, and the eighteenth PMOS transistor M18 is turned on. Therefore, the current mirror pair consisting of M11 and the seventeenth PMOS transistor M17 also draws current from the tenth PMOS transistor M10 to further compensate for the difference between the charging and discharging currents. The principle is similar when the output voltage is in the range of 0.7-0.8V.

[0023] like Figure 3 As shown, through specific practical experiments, under the conditions of TT_0.9V_27℃ and charge pump current Icp of 65A, the overall circuit was simulated using TRAN, with the output voltage scanned from 0.1V to 0.8V. The magnitudes of the upper and lower charge and discharge currents were sampled, and it was found that the maximum mismatch of the charge and discharge current was less than 300nA within the range of 0.1-0.8V.

[0024] Compared with the prior art, the present invention adopts a dual-feedback branch current compensation architecture to detect the potential change of the output voltage in real time. Then, through the dual feedback branch, the upper and lower charging and discharging currents are compensated in stages according to the degree of deviation of the output voltage from the center potential, thereby achieving a small current mismatch between the upper and lower charging and discharging currents within a large output voltage range.

[0025] The above-described specific implementations can be partially adjusted by those skilled in the art in different ways without departing from the principles and purpose of the present invention. The scope of protection of the present invention is defined by the claims and is not limited to the above-described specific implementations. All implementation schemes within the scope of the claims are bound by the present invention.

Claims

1. A charge pump circuit with dual feedback branch current compensation, characterized in that, include: The core circuit, dual feedback branch, and bias circuit are connected in sequence. The input node of the dual feedback branch is connected to the core circuit to detect the potential change of the output voltage. The first output node of the first feedback branch in the dual feedback branch is connected to the gate of the bias circuit. The second output node of the second feedback branch is connected to the bias circuit. According to the degree of deviation of the output voltage from the center potential, the bias circuit performs phased current compensation for the upper and lower charging and discharging currents. The bias circuit includes six NMOS transistors, five PMOS transistors, and two resistors. The bias current input terminal i_bias is connected to one end of the first resistor, the gate of the zeroth NMOS transistor, and the gate of the seventh NMOS transistor. The other end of the first resistor is connected to the gates of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, and the drain of the zeroth NMOS transistor. The source of the zeroth NMOS transistor is connected to the drain of the first NMOS transistor. The drain of the second NMOS transistor is connected to the gates of the fourth and ninth PMOS transistors. One end of the two resistors is connected, and the other end of the second resistor is connected to the gate of the fifth PMOS transistor, the gate of the sixth PMOS transistor, and the drain of the fourth PMOS transistor. The source of the fourth PMOS transistor is connected to the drain of the fifth PMOS transistor, the drain of the sixth PMOS transistor is connected to the drain of the seventh NMOS transistor and the gate of the eighth NMOS transistor, the drain of the third NMOS transistor is connected to the drain of the ninth PMOS transistor and the gate of the tenth PMOS transistor, the source of the ninth PMOS transistor is connected to the drain of the tenth PMOS transistor, and the source of the seventh NMOS transistor is connected to the drain of the eighth NMOS transistor. The core circuit includes: four transmission gates, a rail-to-rail input operational amplifier, a third rail-to-rail input operational amplifier, a twentieth NMOS transistor, and a nineteenth PMOS transistor. The drain of the nineteenth NMOS transistor is connected to one end of the first and second transmission gates. The other end of the first transmission gate is connected to the output and inverting input of the third rail-to-rail input operational amplifier, as well as one end of the third transmission gate. The other end of the second transmission gate is connected to the non-inverting input and output (VC) of the third rail-to-rail input operational amplifier, as well as one end of the fourth transmission gate. The other ends of the third and fourth transmission gates are connected to the drain of the twentieth NMOS transistor. The positive control terminal of the first transmission gate is connected to the inverting control terminal and the switching signal input terminal of the second transmission gate. The positive control terminal of the third transmission gate is connected to the inverting control terminal and the switching signal input terminal of the fourth transmission gate. The switching signal input terminal is connected to the inverting control terminal and the positive control terminal of the first and second transmission gates, and the switching signal input terminal is connected to the inverting control terminal and the positive control terminal of the third and fourth transmission gates. The first feedback branch includes: a first rail-to-rail input operational amplifier, two PMOS transistors, and two NMOS transistors, wherein: the second output node is connected to the gate of the fourteenth PMOS transistor and the drain of the sixteenth PMOS transistor; the input node is connected to the gate of the sixteenth PMOS transistor and the positive input terminal of the first rail-to-rail input operational amplifier; the source of the fourteenth PMOS transistor is connected to the inverting input terminal and the output terminal of the first rail-to-rail input operational amplifier; the drain of the fourteenth PMOS transistor is connected to the gate and drain of the thirteenth NMOS transistor and the gate of the twelfth NMOS transistor; and the drain of the twelfth NMOS transistor is connected to the first output node. The second feedback branch includes: a second rail-to-rail input operational amplifier, two PMOS transistors, and two NMOS transistors, wherein: the first output node is connected to the gate of the eighteenth PMOS transistor and the drain of the fifteenth NMOS transistor; the input node is connected to the gate of the fifteenth NMOS transistor and the positive input terminal of the second rail-to-rail input operational amplifier; the source of the eighteenth NMOS transistor is connected to the inverting input terminal and the output terminal of the second rail-to-rail input operational amplifier; the drain of the eighteenth NMOS transistor is connected to the gate and drain of the seventeenth PMOS transistor and the gate of the eleventh PMOS transistor; and the drain of the eleventh PMOS transistor is connected to the second output node. The rail-to-rail input operational amplifier includes: a bias structure and a folded common-source amplifier circuit connected thereto, wherein: the gate and drain of the 25th PMOS transistor in the bias structure are connected to the gate of the 26th PMOS transistor and the gate of the 38th PMOS transistor in the folded common-source amplifier circuit, and the gate of the 24th NMOS transistor in the bias structure is connected to the gate of the 31st NMOS transistor in the folded common-source amplifier circuit. The bias structure includes three PMOS transistors and two NMOS transistors, wherein: the drain and gate of the twenty-first NMOS transistor are connected to the gate of the twenty-fourth NMOS transistor and the drain of the twenty-second PMOS transistor; the gate of the twenty-second PMOS transistor is connected to the gate and ground of the twenty-third PMOS transistor; the drain of the twenty-third PMOS transistor is connected to the source of the twenty-second PMOS transistor; and the drain of the twenty-fourth NMOS transistor is connected to the drain and gate of the twenty-fifth PMOS transistor. The folded common-source amplifier circuit includes: six NMOS transistors, eight PMOS transistors, zero-adjustment resistors, and Miller compensation capacitors. Specifically: the drain of the 26th PMOS transistor is connected to the source of the 27th and 28th PMOS transistors; the drain of the 31st NMOS transistor is connected to the source of the 29th and 30th PMOS transistors; the positive input terminal VINP is connected to the gate of the 28th PMOS transistor and the 29th NMOS transistor; the negative input terminal is connected to the gate of the 27th PMOS transistor and the 30th NMOS transistor; and the drain of the 27th PMOS transistor is connected to the drain of the 32nd PMOS transistor and the 34th NMOS transistor. The gate and drain of the 28th PMOS transistor are connected. The drain of the 28th PMOS transistor is connected to the drain of the 37th PMOS transistor, the drain of the 35th NMOS transistor, one end of the zero-adjustment resistor, and the gate of the 39th NMOS transistor. The drain of the 29th PMOS transistor is connected to the gate of the 32nd PMOS transistor, the drain and gate of the 33rd PMOS transistor, and the drain of the 30th PMOS transistor is connected to the gate of the 37th PMOS transistor, the drain and gate of the 36th PMOS transistor. The other end of the zero-adjustment resistor is connected to one end of the Miller compensation capacitor. The other end of the Miller compensation capacitor is connected to the drain of the 39th NMOS transistor, the drain of the 38th PMOS transistor, and the output terminal.

2. A voltage regulation method based on the dual-feedback branch current-compensated charge pump circuit of claim 1, characterized in that, include: Step 1: When the power supply voltage is 0.9V and the output voltage is in the range of 0.3-0.7V, the voltage followers in the two potential detection circuits detect the potential of the second node. The potential of the second node is the first follower node, i.e., the output potential. Therefore, when the potential of the first follower node of the third and fourth nodes changes, the fourteenth and eighteenth PMOS transistors are turned off, and the fifteenth and sixteenth NMOS transistors are turned on. The gate potential of the fifteenth NMOS transistor and the sixteenth PMOS transistor changes with the potential of the first follower node. The fifteenth NMOS transistor and the sixteenth PMOS transistor respectively draw current from the tenth PMOS transistor, which is equivalent to the sixteenth PMOS transistor and the fifteenth NMOS transistor. The charging and discharging currents are extracted separately. When the output voltage is lower than the center potential, due to the channel length modulation effect, the charging current is greater than the discharging current. At this time, the gate voltages of the fifteenth NMOS transistor and the sixteenth PMOS transistor follow the output potential. The Vgs of the fifteenth NMOS transistor is less than that of the sixteenth PMOS transistor, so the current of the fifteenth NMOS transistor is less than that of the sixteenth PMOS transistor. At this time, the sixteenth PMOS transistor extracts more charging current than the fifteenth NMOS transistor extracts discharging current. The difference between the current of the sixteenth PMOS transistor and the current of the fifteenth NMOS transistor is used to compensate for the charging and discharging current. The principle is similar when the output voltage is higher than the center potential. Step 2: When the output voltage is in the range of 0.1-0.2V or 0.7-0.8V, since the third and fourth nodes follow the first node, i.e., the output potential changes, the fifteenth NMOS transistor and the sixteenth PMOS transistor are turned on, and either the fourteenth or eighteenth PMOS transistor is turned on. While the fifteenth NMOS transistor and the sixteenth PMOS transistor are compensating for the charge and discharge current, the turning on of the fourteenth or eighteenth PMOS transistor causes one of the twelfth and thirteenth NMOS transistors, the seventeenth and eleventh PMOS transistors, and one of the two sets of current mirrors to work, affecting the eighth NMOS transistor. Alternatively, the current of the tenth PMOS transistor can be sampled for current compensation. When the output voltage is between 0.1-0.2V, due to the channel length modulation effect, the charging current is greater than the discharging current. The current sampling of the fifteenth NMOS transistor and the sixteenth PMOS transistor alone is insufficient to compensate for the difference between the charging and discharging currents. At this time, the fourteenth PMOS transistor is turned off and the eighteenth PMOS transistor is turned on. Thus, the current mirror of the fourteenth PMOS transistor and the seventeenth PMOS transistor also sample the current of the tenth PMOS transistor to further compensate for the difference between the charging and discharging currents. The principle is similar when the output voltage is in the range of 0.7-0.8V.

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