Decoding Method, Device, Electronic Device, Storage Medium and Program Product

Abstract

An embodiment of the present application provides a decoding method, apparatus, electronic device, storage medium, and program product. The method includes: receiving a decoding request, where the decoding request includes a symbol sequence and a parity check matrix; determining the number of parity check nodes corresponding to the parity check matrix according to the decoding request, and performing hierarchical processing on the symbol sequence according to the number of parity check nodes to obtain a plurality of symbol groups; determining a target parallelism according to the parity check matrix and the plurality of symbol groups; and performing iterative decoding processing on the plurality of symbol groups in sequence according to the target parallelism through the parity check matrix to obtain the original data. In the above solution, by determining the target parallelism, partial parallel decoding processing can be flexibly controlled, and full parallel decoding processing of the entire symbol sequence can be avoided, effectively reducing the computational complexity.

Description

Technical Field

[0001] This application relates to the field of communication technologies, and in particular, to a decoding method, apparatus, electronic device, storage medium, and program product. Background Art

[0002] In the field of communication technologies, channel coding and channel decoding are of great significance for improving the reliability of data transmission. At the data sending end, the original data to be sent is converted into a symbol sequence. The symbol sequence is converted into a signal form suitable for transmission over the channel by a modulator and transmitted through the channel. Redundant information can be introduced into the symbol sequence through coding and modulation techniques to enhance the anti-interference ability of the signal. At the data receiving end, the received signal is converted back into a symbol sequence through a demodulator, and the symbol sequence is decoded to obtain the original data.

[0003] At the data receiving end, through message passing between variable nodes and check nodes, the symbol sequence is gradually decoded, and the estimated value of each symbol in the symbol sequence is continuously updated and optimized to obtain the original data.

[0004] However, when the number of symbols in the symbol sequence is large, this decoding process has the problem of high computational complexity. Summary of the Invention

[0005] Embodiments of this application provide a decoding method, apparatus, electronic device, storage medium, and program product to reduce the computational complexity of the decoding process.

[0006] In a first aspect, embodiments of this application provide a decoding method, including: receiving a decoding request, where the decoding request includes a symbol sequence and a parity-check matrix; determining the number of check nodes corresponding to the parity-check matrix according to the decoding request, and performing hierarchical processing on the symbol sequence according to the number of check nodes to obtain a plurality of symbol groups; determining a target parallelism according to the parity-check matrix and the plurality of symbol groups; and performing iterative decoding processing on the plurality of symbol groups in sequence through the parity-check matrix according to the target parallelism to obtain the original data.

[0007] In a possible implementation manner, determining a target parallelism according to the parity-check matrix and the plurality of symbol groups includes: determining the amount of idle resources, the number of groups corresponding to the plurality of symbol groups, and the row weight of the parity-check matrix, where the row weight is the number of variable nodes connected to each check node; and determining the target parallelism according to the amount of idle resources, the number of groups, and the row weight.

[0008] In a possible implementation, by means of the check matrix, iterative decoding processing is sequentially performed on the multiple symbol groups according to the target parallelism to obtain the original data, including: determining a plurality of calculation tasks from the multiple symbol groups according to the target parallelism, each calculation task including a plurality of sub-symbol groups; respectively performing iterative decoding processing on the plurality of sub-symbol groups corresponding to each calculation task by means of a variable node to check node V2C message vector and a check node to variable node C2V message vector to obtain a plurality of target data corresponding to each calculation task; and determining the original data according to the plurality of target data corresponding to each calculation task.

[0009] In a possible implementation, for any one sub-symbol group under any one calculation task; iterative decoding processing is performed on the sub-symbol group by means of a variable node to check node V2C message vector and a check node to variable node C2V message vector to obtain a plurality of target data corresponding to the sub-symbol group, including: determining a channel noise eigenvalue, the check nodes corresponding to the sub-symbol group, and the variable nodes corresponding to the sub-symbol group; calculating an initial log-likelihood ratio according to the channel noise eigenvalue and the sub-symbol group, and determining the initial log-likelihood ratio as the initial V2C message vector of the variable node; determining the number of symbol values of the sub-symbol group, and determining the initial C2V message vector of the check node according to the principle of equal posterior probability and the number of symbol values; and performing iterative processing according to the initial V2C message vector and the initial C2V message vector to obtain the plurality of target data.

[0010] In a possible implementation, performing iterative processing according to the initial V2C message vector and the initial C2V message vector to obtain the plurality of target data, including: performing a preset operation until the number of times of performing the preset operation is greater than a preset number or a preset condition is satisfied, and determining target data according to a determination result; wherein the preset operation includes: determining a target element from the check matrix according to the variable node and the check node, performing a finite field multiplication calculation on the initial V2C message vector and the target element to obtain an updated V2C message vector, performing an inverse permutation process on the updated V2C message vector to obtain an inverse permutation vector, updating the check node by means of the inverse permutation vector to obtain an updated C2V message vector, and performing a determination process on the updated V2C message vector and the updated C2V message vector to obtain the determination result, the determination result being that the check passes or the check fails; wherein the preset condition is that the determination result is that the check passes.

[0011] In a possible implementation manner, determining target data according to a judgment result includes: according to the judgment result, determining a plurality of candidate posterior probabilities when the variable nodes take different symbol values; and determining the symbol value corresponding to the candidate posterior probability with the largest of the plurality of candidate posterior probabilities as the target data.

[0012] In a possible implementation manner, performing judgment processing includes: determining an index value corresponding to each symbol group; storing the updated V2C message vector and the updated C2V message vector obtained in each iteration into a cache, and updating a count value according to the index value corresponding to each symbol group; and performing judgment processing until the count value is equal to a preset value.

[0013] In a second aspect, an embodiment of the present application provides a decoding device, including: a receiving module, configured to receive a decoding request, where the decoding request includes a symbol sequence and a parity check matrix; a message initialization module, configured to determine the number of check nodes corresponding to the parity check matrix according to the decoding request, and perform hierarchical processing on the symbol sequence according to the number of check nodes to obtain a plurality of symbol groups; a determining module, configured to determine a target parallelism according to the parity check matrix and the plurality of symbol groups; and a partial parallel control module, configured to perform iterative decoding processing on the plurality of symbol groups in sequence through the parity check matrix according to the target parallelism to obtain original data.

[0014] In a possible implementation manner, the determining module is specifically configured to determine an amount of idle resources, the number of groups corresponding to the plurality of symbol groups, and the row weight corresponding to the parity check matrix, where the row weight is the number of variable nodes connected to each check node; and the determining module is further specifically configured to determine the target parallelism according to the amount of idle resources, the number of groups, and the row weight.

[0015] In a possible implementation manner, the device further includes: a processing module, configured to determine a plurality of computing tasks from the plurality of symbol groups according to the target parallelism, where each computing task includes a plurality of sub-symbol groups; the processing module is further configured to perform iterative decoding processing on the plurality of sub-symbol groups corresponding to each computing task respectively through a variable node to check node V2C message vector and a check node to variable node C2V message vector to obtain a plurality of target data corresponding to each computing task; and the processing module is further configured to determine the original data according to the plurality of target data corresponding to each computing task.

[0016] In a possible implementation, for any sub-symbol group under any computing task; the processing module is specifically configured to determine the channel noise eigenvalue, the check nodes corresponding to the sub-symbol group, and the variable nodes corresponding to the sub-symbol group; the processing module is further specifically configured to calculate an initial log-likelihood ratio according to the channel noise eigenvalue and the sub-symbol group, and determine the initial log-likelihood ratio as the initial V2C message vector of the variable node; the processing module is further specifically configured to determine the number of symbol values of the sub-symbol group, and determine the initial C2V message vector of the check node according to the principle of equal posterior probability and the number of symbol values; the processing module is further specifically configured to perform iterative processing according to the initial V2C message vector and the initial C2V message vector to obtain the multiple target data.

[0017] In a possible implementation, the processing module is further specifically configured to execute a preset operation until the number of times of executing the preset operation is greater than a preset number or a preset condition is satisfied, and determine the target data according to the judgment result; wherein, the preset operation includes: determining target elements from the parity-check matrix according to the variable node and the check node, performing a finite field multiplication calculation on the initial V2C message vector and the target elements to obtain an updated V2C message vector, performing an inverse permutation process on the updated V2C message vector to obtain an inverse permutation vector, updating the check node through the inverse permutation vector to obtain an updated C2V message vector, and performing a judgment process on the updated V2C message vector and the updated C2V message vector to obtain the judgment result, where the judgment result is that the check passes or the check fails; wherein, the preset condition is that the judgment result is that the check passes.

[0018] In a possible implementation, the processing module is specifically configured to determine multiple candidate posterior probabilities when the variable node takes different symbol values according to the judgment result; the processing module is further specifically configured to determine the symbol value corresponding to the candidate posterior probability with the largest of the multiple candidate posterior probabilities as the target data.

[0019] In a possible implementation, the device includes: a cache module, configured to determine an index value corresponding to each symbol group; the cache module is further configured to store the updated V2C message vector and the updated C2V message vector obtained in each iteration into the cache, and update a count value according to the index value corresponding to each symbol group; the cache module is further configured to perform a judgment process until the count value is equal to a preset value.

[0020] In a third aspect, an embodiment of the present application provides a decoding device, including: a memory, a processor;

[0021] The memory stores computer-executable instructions;

[0022] The processor executes the computer-executable instructions stored in the memory, such that the processor performs the above first aspect and / or various possible implementation manners of the first aspect.

[0023] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, in which computer-executable instructions are stored, and when the computer-executable instructions are executed by a processor, they are used to implement the above first aspect and / or various possible implementation manners of the first aspect.

[0024] In a fifth aspect, an embodiment of the present application provides a computer program product, including a computer program, and when the computer program is executed by a processor, it implements the above first aspect and / or various possible implementation manners of the first aspect.

[0025] The decoding method, device, electronic device, storage medium, and program product provided by the embodiments of the present application, the method includes: receiving a decoding request, where the decoding request includes a symbol sequence and a parity-check matrix; according to the decoding request, determining the number of check nodes corresponding to the parity-check matrix, and performing hierarchical processing on the symbol sequence according to the number of check nodes to obtain a plurality of symbol groups; determining a target parallelism according to the parity-check matrix and the plurality of symbol groups; and performing iterative decoding processing on the plurality of symbol groups in sequence according to the target parallelism through the parity-check matrix to obtain original data. In the above solution, by determining the target parallelism, partial parallel decoding processing can be flexibly controlled, avoiding full parallel decoding processing of the entire symbol sequence, and effectively reducing the computational complexity. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The drawings here are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application.

[0027] Figure 1 It is a schematic diagram of an application scenario of a decoding method provided by an embodiment of the present application;

[0028] Figure 2 It is a schematic flowchart of a decoding method provided by an embodiment of the present application;

[0029] Figure 3 It is a schematic flowchart of a decoding method provided by an embodiment of the present application;

[0030] Figure 4 It is a schematic diagram of a Tanner graph of a parity-check matrix provided by an embodiment of the present application;

[0031] Figure 5 It is a schematic diagram of an adder provided by an embodiment of the present application;

[0032] Figure 6 Schematic diagram of the decoder provided by the embodiment of the present application;

[0033] Figure 7 Structural schematic diagram of a decoding device provided by the embodiment of the present application;

[0034] Figure 8 Structural schematic diagram of a decoding device provided by the embodiment of the present application;

[0035] Figure 9 Structural schematic diagram of an electronic device provided by the embodiment of the present application.

[0036] Through the above-mentioned drawings, specific embodiments of the present application have been shown, and there will be more detailed descriptions hereinafter. These drawings and textual descriptions are not intended to limit the scope of the concept of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. Specific embodiments

[0037] Here, the exemplary embodiments will be described in detail, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0038] It should be noted that the decoding method, device, electronic device, storage medium, and program product of the present application can be used in the field of communication technology, and can also be used in any field other than the communication technology. The application fields of the decoding method, device, electronic device, storage medium, and program product of the present application are not limited.

[0039] Figure 1 Schematic diagram of the application scenario of a decoding method provided by the embodiment of the present application. Taking the illustrated scenario as an example: The sending end 1 sends a symbol sequence to the receiving end 2, and the receiving end 2 decodes the symbol sequence to obtain the original data.

[0040] Exemplarily, the symbol sequence refers to a series of symbols for transmission obtained by encoding and modulating the original data. Each symbol represents a certain number of information bits and is suitable for transmission over the channel. Specifically, the sending end first groups and encodes the original data (such as LDPC encoding), and then maps the encoded bits to symbols through a modulator. These symbols can be different types of signal forms, and each symbol carries a certain number of bit information, so that multiple bits can be transmitted within each symbol period, thereby improving the data transmission efficiency.

[0041] In practical applications, the receiving end decodes the compliant sequence through a decoder to obtain the original data. The decoding process involves a large amount of calculations, and the operation of the decoder will occupy the computing resources of the receiving end.

[0042] In the related art, the decoder performs a fully parallel decoding process on multiple symbols in the compliant sequence. When the number of symbols in the symbol sequence is large or the number of bits representing the symbol sequence is large, the computational complexity of the fully parallel decoding process is high. As a result, the amount of computing resources occupied by the decoder is large, affecting the operating efficiency of the receiving end.

[0043] The decoding method provided by this application aims to solve the above technical problems.

[0044] The following uses specific embodiments to elaborate in detail on the technical solution of this application and how the technical solution of this application solves the above technical problems. These several specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of this application will be described below in conjunction with the accompanying drawings.

[0045] Figure 2 It is a schematic flowchart of a decoding method provided by an embodiment of this application. The method includes the following steps:

[0046] S201. Receive a decoding request, where the decoding request includes a symbol sequence and a parity-check matrix.

[0047] Optionally, the compliant sequence can be encoded by means of a Low-Density Parity-Check Code (LDPC for short).

[0048] Optionally, the parity-check matrix of LDPC is sparse, including zero elements and non-zero elements. The sparse matrix greatly reduces the amount of calculations in the encoding and decoding processes, thereby improving the efficiency of the algorithm. The sparse structure is convenient for hardware implementation and reduces the complexity.

[0049] Exemplarily, the execution subject of this application is the receiving end, and the specific device type of the receiving end is not limited in this application.

[0050] S202. According to the decoding request, determine the number of check nodes corresponding to the parity-check matrix, and perform hierarchical processing on the symbol sequence according to the number of check nodes to obtain a plurality of symbol groups.

[0051] Optionally, the parity-check matrix is an m×n matrix, where m represents the number of parity-check nodes (i.e., parity-check equations), and n represents the number of variable nodes (i.e., symbols in the codeword). The number of rows m is read from the parity-check matrix to obtain the number of parity-check nodes. At the receiving end, the symbol sequence is verified for errors through the parity-check matrix, and if errors are present, the errors are corrected through the parity-check matrix.

[0052] Optionally, based on the number of parity-check nodes, the symbol sequence is processed in layers. Here, "processing in layers" means splitting the symbol sequence into multiple symbol groups according to certain rules or strategies to facilitate parallel processing or reduce computational complexity.

[0053] Exemplarily, the symbol sequence is data of 400×6×8 bit, the number of parity-check nodes is 100, and the symbol sequence is processed in layers according to the number of parity-check nodes to obtain 100 layers × 4×6×8 bit decoded data. Among them, 400 represents the number of symbols in the symbol sequence, 6 represents the 64-bit finite field, and 8 represents the quantization bit width.

[0054] S203. Determine the target parallelism according to the parity-check matrix and multiple symbol groups.

[0055] Optionally, according to the parity-check matrix and multiple symbol groups, determine the amount of computation required for decoding processing, and determine the target parallelism that matches it according to the amount of computation.

[0056] Illustrated with a scenario example, the higher the target parallelism, the higher the efficiency of decoding processing, and at the same time, the higher the computational complexity of decoding processing. Determine a suitable target parallelism by comprehensively considering efficiency and complexity to minimize the computational complexity on the premise that the efficiency of decoding processing meets the requirements.

[0057] S204. According to the target parallelism, perform iterative decoding processing on multiple symbol groups in sequence through the parity-check matrix to obtain the original data.

[0058] Exemplarily, perform partial parallel decoding processing according to the target parallelism.

[0059] Illustrated with a scenario example, according to the target parallelism, the number of symbol groups for simultaneous decoding processing is determined, and partial parallel decoding processing is performed according to the number of symbol groups for simultaneous processing. For example, 100 symbol groups are obtained through layer processing. If the target parallelism is 10, the number of symbol groups for simultaneous decoding processing is 10, and during partial parallel decoding processing, the other symbol groups among the 100 symbol groups are not decoded. It can be understood that compared with full parallel decoding processing, the resource consumption of partial parallel decoding processing is reduced to 1 / 10 of the original.

[0060] Optionally, the iterative process may include variable node updates and check node updates. Among them, for each variable node, calculate the messages it sends to all adjacent check nodes. These messages are based on all the messages received by the variable node from other check nodes and the received initial values. Each variable node will collect the messages from all other adjacent check nodes and update the messages it sends to the current check node based on these messages. The updated messages reflect the suggestions of the variable node to the check node after considering the opinions of all other check nodes.

[0061] Specifically, exemplarily, for each check node, calculate the messages it sends to all adjacent variable nodes. Each check node will collect the messages from all adjacent variable nodes and update the messages it sends to the current variable node based on these messages. The updated messages reflect the suggestions of the check node to the variable node after considering the opinions of all other variable nodes. These messages are based on all the messages received by the check node from other variable nodes. By exchanging information between variable nodes and check nodes, the errors in the symbol sequence transmission are gradually corrected, thereby improving the decoding accuracy.

[0062] The decoding method provided by the embodiments of this application receives a decoding request, where the decoding request includes a symbol sequence and a parity check matrix; according to the decoding request, determine the number of check nodes corresponding to the parity check matrix, and perform hierarchical processing on the symbol sequence according to the number of check nodes to obtain multiple symbol groups; determine the target parallelism according to the parity check matrix and the multiple symbol groups; and perform iterative decoding processing on the multiple symbol groups in sequence according to the target parallelism through the parity check matrix to obtain the original data. In the above solution, by determining the target parallelism, the partial parallel decoding process can be flexibly controlled, avoiding full parallel decoding of the entire symbol sequence, and effectively reducing the computational complexity.

[0063] Based on any of the above embodiments, below, in combination with Figure 3 , the detailed process of decoding will be described.

[0064] Figure 3 It is a schematic flowchart of a decoding method provided by the embodiments of this application. As Figure 3 shown, the method includes:

[0065] S301. Receive a decoding request, where the decoding request includes a symbol sequence and a parity check matrix.

[0066] It should be noted that the execution process of S301 refers to S201, which will not be elaborated here.

[0067] S302. According to the decoding request, determine the number of check nodes corresponding to the parity check matrix, and perform hierarchical processing on the symbol sequence according to the number of check nodes to obtain multiple symbol groups.

[0068] It should be noted that for the execution process of S302, refer to S202, which will not be elaborated here.

[0069] S303. Determine the amount of idle resources, the number of groups corresponding to multiple symbol groups, and the row weight corresponding to the parity-check matrix, where the row weight is the number of variable nodes connected to each parity-check node.

[0070] Optionally, the parity-check matrix can be converted into a Tanner graph.

[0071] Next, Figure 4 the Tanner graph of the parity-check matrix will be described.

[0072] Figure 4 is a schematic diagram of the Tanner graph of the parity-check matrix provided by the embodiment of the present application. As Figure 4 shown, variable nodes correspond to columns in the parity-check matrix, parity-check nodes correspond to rows in the parity-check matrix, and the edges connecting parity-check nodes and variable nodes indicate the positions of non-zero elements in the parity-check matrix. The number of variable nodes connected to each parity-check node corresponds to the row weight of the parity-check matrix, and the number of parity-check nodes connected to each variable node corresponds to the column weight of the parity-check matrix. If a certain position in the parity-check matrix is 1, there is an edge between the corresponding parity-check node and variable node. Referring to Figure 4 , it can be seen that the row weight of the parity-check matrix is 4 and the column weight is 2.

[0073] Optionally, the amount of idle resources refers to the unused computing resources available for performing decoding in the current receiving end. This includes but is not limited to the number of processor cores, memory capacity, etc. For example, in a multi-core processor environment, if there are a total of 8 cores and 4 of them have been occupied by other tasks, the amount of idle resources is 4 cores. These idle cores can be used to perform decoding processing in parallel.

[0074] Exemplarily, the number of groups corresponding to multiple symbol groups reflects the total computing amount of the decoding process.

[0075] Exemplarily, the row weight reflects the computing amount of each symbol group. A higher row weight means that more variable nodes are involved in a certain parity-check node, so more computing resources are required.

[0076] S304. Determine the target parallelism according to the amount of idle resources, the number of groups, and the row weight.

[0077] Illustrated with a scenario example, according to the amount of idle resources, determine the available computing resources, and according to the number of groups and the row weight, determine the required computing resources. Integrate the available computing resources and the required computing resources to determine the target parallelism, so as to improve the efficiency of the decoding process while avoiding performance degradation of the receiving end caused by overusing computing resources.

[0078] S305. Determine multiple computing tasks from multiple symbol groups according to the target parallelism, where each computing task includes multiple sub-symbol groups.

[0079] Illustrated with a scenario example, for instance, if the number of multiple symbol groups is 100 and the target parallelism is 10, then 10 computing tasks are determined, and each computing task includes 10 sub-symbol groups.

[0080] S306. Respectively perform iterative decoding processing on the multiple sub-symbol groups corresponding to each computing task through a variable node to check node V2C message vector and a check node to variable node C2V message vector, to obtain multiple target data corresponding to each computing task.

[0081] Exemplarily, the V2C message vector refers to the message vector sent from a variable node to a check node. Each variable node represents a bit or a symbol and updates its state according to the received external information (such as messages from other check nodes or the initial message vector). The V2C message usually contains probability estimation information about the bit corresponding to the variable node, such as the Log-Likelihood Ratio (LLR for short). The LLR value indicates whether the received bit is more likely to be 0 or 1. The V2C message vector helps the check node determine whether the current bit meets the requirements of the check equation. By collecting the message vectors from all associated variable nodes, the check node can calculate a new information vector and feedback it to the variable node.

[0082] Exemplarily, the C2V message vector is the message vector sent from a check node to a variable node. The check node is responsible for checking whether a group of variable nodes meet specific check constraint conditions. The C2V message vector contains the message vector deduced by the check node based on all the V2C message vectors received from other connected variable nodes. This is usually the result of a certain non-linear combination and is used to indicate how a variable node adjusts its probability estimation to better meet the check equation. The C2V message vector is used to update the state of the variable node, that is, to adjust the confidence estimation of the variable node about the bit it represents. This process helps correct errors and gradually approach the correct decoding result.

[0083] A feasible implementation method is applicable to any sub-symbol group under any computing task. The iterative decoding process can be carried out through the following steps: determining the channel noise eigenvalue, the check node corresponding to the sub-symbol group, and the variable node corresponding to the sub-symbol group; calculating the initial log-likelihood ratio based on the channel noise eigenvalue and the sub-symbol group, and determining the initial V2C message vector of the variable node as the initial log-likelihood ratio; determining the number of symbol values of the sub-symbol group, and determining the initial C2V message vector of the check node according to the principle of equal posterior probability and the number of symbol values; performing iterative processing based on the initial V2C message vector and the initial C2V message vector to obtain multiple target data.

[0084] Exemplarily, the formula for calculating the initial V2C message vector can be:

[0085]

[0086] Where, represents the message vector from variable node n to check node m, α is the possible symbol value, represents the log-likelihood ratio of variable node n for the value α, reflecting the confidence of variable node n in the value α in the current iteration.

[0087] Exemplarily, the formula for calculating the initial C2V message vector can be:

[0088]

[0089] Where, represents the message vector sent from check node m to variable node n, is the conditional probability, indicating the probability that check node m satisfies the check equation under the condition that the value of variable node n is α. q represents the number of symbol values.

[0090] Optionally, when initializing the C2V message vector, that is, before the check node updates the V2C vector received from the variable node, assume that the posterior probabilities of all symbol values are equal.

[0091] Optionally, according to the non-zero elements in the corresponding position of the check matrix, permute the message vector output by the variable node. The message vector output by the variable node needs to perform finite field multiplication with the finite field element corresponding to the edge. This step is called message permutation. In the check equation, the one participating in the finite field addition is the product with the variable node symbol.

[0092] Optionally, perform addition operations through an adder.

[0093] Next, Figure 5 the adder will be described.

[0094] Figure 5 Schematic diagram of the adder provided by the embodiment of the present application. As Figure 5 shown, taking 6 bits as an example, when the calculation result of the addition operation exceeds the 6-bit range, the result will be automatically truncated to ensure that the output value does not exceed the maximum value that can be represented by 6 bits (i.e., 63). This design prevents incorrect results caused by numerical overflow and maintains the closure of the finite field.

[0095] Based on the above embodiments, since the initial probability of each symbol value is set to be the same, this setting ensures that all possible symbol values are treated equally without additional information, thereby improving the accuracy of decoding.

[0096] A feasible implementation can be iteratively processed by the following method: perform a preset operation until the number of times of performing the preset operation is greater than the preset number of times or the preset condition is met, and obtain an updated V2C message vector; perform an inverse permutation process on the updated V2C message vector to obtain an inverse permutation vector; update the check node through the inverse permutation vector to obtain an updated C2V message vector; perform a decision process on the updated V2C message vector and the updated C2V message vector to obtain multiple target data; wherein, the preset operation includes: determining a target element from the parity check matrix according to the variable node and the check node, performing a finite field multiplication calculation on the initial V2C message vector and the target element to obtain an updated V2C message vector, inputting the updated V2C into the first parity check equation to obtain a first parity check result, and the first parity check result is either parity check passed or parity check failed; wherein, the preset condition is that the first parity check result is parity check passed.

[0097] Combined with the scenario example, the finite field multiplication operation helps to adjust the message vector value to reflect the state of the current parity check equation.

[0098] The first parity check equation: Input the updated V2C message into the first parity check equation to check whether it satisfies the equation. If it satisfies, it is called "parity check passed"; otherwise, it is "parity check failed".

[0099] Exemplarily, the check node is updated through the following formula:

[0100]

[0101] wherein, represents the probability that the parity check equation is satisfied under the condition that the message vector of the check node m at the variable node n is α. represents the summation process for all variable sequences V that satisfy . V represents the set of all symbol sequences that satisfy the m-th parity check relation. represents the probability that the parity check equation is satisfied given the variable sequence V. is the output of the parity-check equation, is an element in the parity-check matrix, is the value of the variable node. denotes that given the probability of the variable sequence V. denotes the product of the probabilities for all neighbor nodes except n is performed. denotes the updated V2C message vector of other variable nodes is.

[0102] Exemplarily, after obtaining the updated V2C message vector, an inverse permutation process is performed on it. The inverse permutation process refers to the process of restoring the original permutation order, and this step is to correspond the message vector output by the parity-check node with the original symbol values.

[0103] Exemplarily, the formula for the inverse permutation process can be:

[0104]

[0105] where, denotes the value of the C2V message vector after the inverse permutation process. denotes the value of the original C2V message vector output by the parity-check node.

[0106] Exemplarily, the formula for updating the parity-check node through the inverse permutation vector can be:

[0107]

[0108] where, denotes the posterior probability that the variable node n takes the value α, denotes the message vectors of all parity-check nodes associated with the variable node n except the current parity-check node m. is the signal received by the receiving end. denotes the prior probability based on the received signal. denotes that under the received signal the joint probability distribution except the message vector of the current parity-check node. denotes that under the condition that the variable node n takes the value α and the received signal the joint probability distribution of all parity-check nodes except the current parity-check node m. denotes the normalization factor, which determines that the message vector of each variable node satisfies the normalization condition, denotes the prior probability based on the received signal. denotes the message vector from other parity-check nodes k to the variable node n.

[0109] Exemplarily, according to the value of the variable node and the information of the parity-check matrix, the posterior probability of the variable node is calculated, and the variable node can update its estimation of the value of the parity-check node, thereby gradually correcting errors until all parity-check equations are satisfied.

[0110] Optionally, the posterior probability is the corrected posterior probability after introducing correlation through the parity-check matrix, where the current parity-check equation is excluded to prevent the decoding from not converging due to recycling information.

[0111] Exemplarily, the formula for decision processing can be:

[0112]

[0113] where, represents the posterior probability that the variable node n takes the value α in the case of the received signal and the parity-check node message vector associated with all variable nodes n. represents the normalization constant to ensure that the sum of the probabilities of all possible values is 1.

[0114] In this feasible implementation, errors can be gradually corrected through an iterative method, thereby improving the accuracy of decoding.

[0115] A feasible implementation can perform decision processing through the following method: determine the index value corresponding to each symbol group; store the updated V2C message vector and the updated C2V message vector obtained in each iteration in a cache, and update the count value according to the index value corresponding to each symbol group; until the count value is equal to the preset value, then perform decision processing.

[0116] Optionally, a partial parallel control module is used to control storing the message vector in the cache and control the counting process of the index value.

[0117] Optionally, each computing task corresponds to multiple sub-symbol groups, each sub-symbol group corresponds to a target data, and each target data corresponds to a unique index value.

[0118] Combined with a scenario example, taking the number of symbol groups as 100 as an example, the index values corresponding to multiple symbol groups are determined from 0 to 99. The moment when each symbol group iteratively obtains the target data is not fixed. By updating the count value, the number of currently generated target data can be determined. Until the count value is equal to 100, it means that each symbol group has completed iteration. At this time, the cache includes the iterative data corresponding to each symbol group, and decision processing will be performed on the iterative data in the cache.

[0119] In this feasible implementation, through the counter, it can be accurately determined that each symbol group has generated the target data, avoiding omission, thereby improving the accuracy of decoding.

[0120] A feasible implementation method determines target data according to a judgment result, including: determining multiple candidate posterior probabilities when variable nodes take different optional data according to the judgment result; determining the optional data corresponding to the candidate posterior probability with the largest multiple candidate posterior probabilities as the target data.

[0121] Optionally, the constraints of the current parity-check equation are used to update the posterior probability, and the constraint relationship of the current parity-check equation will be used during the final judgment. According to the calculated posterior probabilities of the message vectors of each variable node, a judgment is made, and the judgment rule is as follows:

[0122]

[0123] Among them, It means that for each variable node n, the symbol value α that maximizes the posterior probability is selected as the estimated value of the node.

[0124] Exemplarily, multiple candidate posterior probabilities (i.e., ) of the variable node under different symbol values are calculated according to the judgment result, and the symbol value corresponding to the maximum posterior probability is selected from them and determined as the target data corresponding to the variable node.

[0125] Exemplarily, after making a judgment on each element of the finite field GF(64) used by the current LDPC code, a judgment decoding sequence is obtained. If the checksum is an all-zero vector, it means that the decoding is successful, the iteration ends, and the decoding sequence is returned; otherwise, the information transfer between the variable nodes and the parity-check nodes in the next round is performed until the decoder reaches the maximum number of iterations or the decoding is successful. If the algorithm has not converged yet when the iteration proceeds to the preset maximum number of iterations, the decoding fails, the algorithm stops iterating, and the current decoding sequence is output.

[0126] In this feasible implementation method, it is ensured that, given the received signal and all relevant parity-check node message vectors, the estimated value of each variable node is the most likely correct value, thereby improving the error correction ability and accuracy of the entire system.

[0127] S307. Determine the original data according to the multiple target data corresponding to each calculation task.

[0128] Next, the decoder will be described in conjunction with Figure 6 as follows.

[0129] Figure 6 is a schematic diagram of the decoder provided by the embodiment of the present application. As shown in Figure 6As shown, the input data is initialized to initial messages, which are typically log-likelihood ratios extracted from the received signal. The initialized log-likelihood ratios are stored, and these values will be updated and used in subsequent iterations. The partially parallel control module hierarchically processes the initialized messages to obtain the index value index for each layer, and permutes the initialized messages to meet the requirements of check node updates. The permutation operation ensures the correct transmission of information between different nodes. Based on the permuted messages, the check nodes perform update calculations. This step involves updating the messages of the check nodes according to the constraints in the check matrix. The messages updated by the check nodes are inverse-permuted back to the original format so that the variable nodes can correctly process these messages. The variable nodes perform update calculations based on the inverse-permuted messages. This step involves combining the messages from multiple check nodes to update the state of the variable nodes. The partially parallel control module controls the partially parallel operation of the entire decoding process to ensure that the decoder can operate efficiently with limited hardware resources. The cache module stores the results updated by the variable nodes into the cache RES RAM, and these results will be used for subsequent decision decoding. Decision decoding is performed based on the results in the cache RES RAM to determine the final bit estimates. If the decoding is successful or the maximum number of iterations is reached, the result is output; otherwise, the iteration continues. If the decoding is successful or the maximum number of iterations is reached, the final decoding result is output, and the maximum number of iterations is determined by the index value index.

[0130] Figure 7 FIG. is a schematic structural diagram of a decoding device provided by an embodiment of the present application. As Figure 7 shown, the decoding device 70 may include: a receiving module 71, a message initialization module 72, a determination module 73, and a partially parallel control module 74, where

[0131] The receiving module 71 is configured to receive a decoding request, and the decoding request includes a symbol sequence and a check matrix.

[0132] The message initialization module 72 is configured to determine the number of check nodes corresponding to the check matrix according to the decoding request, and hierarchically process the symbol sequence according to the number of check nodes to obtain a plurality of symbol groups.

[0133] The determination module 73 is configured to determine the target parallelism according to the check matrix and the plurality of symbol groups.

[0134] The partially parallel control module 74 is configured to perform iterative decoding processing on the plurality of symbol groups in sequence through the check matrix according to the target parallelism to obtain the original data.

[0135] Optionally, the receiving module 71 may execute Figure 2 S201 in the embodiment.

[0136] Optionally, the message initialization module 72 may execute Figure 2 S202 in the embodiment.

[0137] Optionally, the determination module 73 may execute Figure 2 S203 in the embodiment.

[0138] Optionally, the partial parallel control module 74 may execute Figure 2 S204 in the embodiment.

[0139] It should be noted that the decoding device shown in the embodiment of the present application may execute the technical solutions shown in the above method embodiments, and the implementation principles and beneficial effects are similar, and will not be elaborated here.

[0140] In a possible implementation manner, the determination module 73 is specifically configured to:

[0141] Determine the amount of idle resources, the number of groups corresponding to multiple symbol groups, and the row weight corresponding to the parity-check matrix, where the row weight is the number of variable nodes connected to each check node;

[0142] Determine the target parallelism according to the amount of idle resources, the number of groups, and the row weight.

[0143] Figure 8 This is a schematic structural diagram of a decoding device provided by an embodiment of the present application. On the basis of the Figure 7 shown embodiment, as Figure 8 shown, the decoding device 80 further includes: a processing module 75 and a cache module 76, where

[0144] The processing module 75 is configured to:

[0145] Determine multiple computing tasks from multiple symbol groups according to the target parallelism, and each computing task includes multiple sub-symbol groups;

[0146] Perform iterative decoding processing on the multiple sub-symbol groups corresponding to each computing task through the variable node to check node V2C message vector and the check node to variable node C2V message vector, and obtain multiple target data corresponding to each computing task;

[0147] Determine the original data according to the multiple target data corresponding to each computing task.

[0148] In a possible implementation manner, for any sub-symbol group under any computing task; the processing module 75 is specifically configured to:

[0149] Determine the channel noise eigenvalue, the check node corresponding to the sub-symbol group, and the variable node corresponding to the sub-symbol group;

[0150] Calculate the initial log-likelihood ratio based on the channel noise eigenvalue and the sub-symbol group, and determine the initial V2C message vector of the variable node with the initial log-likelihood ratio;

[0151] Determine the number of symbol values of the sub-symbol group, and determine the initial C2V message vector of the check node according to the principle of equal posterior probability and the number of symbol values;

[0152] Perform iterative processing based on the initial V2C message vector and the initial C2V message vector to obtain multiple target data.

[0153] In a possible implementation manner, the processing module 75 is specifically configured to:

[0154] Execute a preset operation until the number of times of executing the preset operation is greater than a preset number or a preset condition is satisfied, and determine the target data according to the judgment result;

[0155] Wherein, the preset operation includes: determining a target element from the parity-check matrix according to the variable node and the check node, performing a finite field multiplication calculation on the initial V2C message vector and the target element to obtain an updated V2C message vector, performing an inverse permutation process on the updated V2C message vector to obtain an inverse permutation vector, updating the check node through the inverse permutation vector to obtain an updated C2V message vector, performing a judgment process on the updated V2C message vector and the updated C2V message vector to obtain a judgment result, and the judgment result is that the check passes or the check fails;

[0156] Wherein, the preset condition is that the judgment result is that the check passes.

[0157] In a possible implementation manner, the processing module 75 is specifically configured to:

[0158] Determine multiple candidate posterior probabilities when the variable node takes different symbol values according to the judgment result;

[0159] Determine the symbol value corresponding to the candidate posterior probability with the largest of the multiple candidate posterior probabilities as the target data.

[0160] The caching module 76 is configured to:

[0161] Determine the index value corresponding to each symbol group;

[0162] Store the updated V2C message vector and the updated C2V message vector obtained in each iteration into the cache, and update the count value according to the index value corresponding to each symbol group;

[0163] Until the count value is equal to the preset value, a judgment process is performed.

[0164] Figure 9This is a schematic structural diagram of an electronic device provided in an embodiment of the present application. As Figure 9 shown, the electronic device includes:

[0165] A processor 291, and the electronic device further includes a memory 292; it may also include a communication interface 293 and a bus 294. Among them, the processor 291, the memory 292, and the communication interface 293 can complete mutual communication through the bus 294. The communication interface 293 can be used for information transmission. The processor 291 can call the logical instructions in the memory 292 to execute the method of the above embodiment.

[0166] In addition, when the logical instructions in the above-mentioned memory 292 are implemented in the form of a software functional unit and sold or used as an independent product, they can be stored in a computer-readable storage medium.

[0167] The memory 292, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as the program instructions / modules corresponding to the methods in the embodiments of the present application. The processor 291 executes functional applications and data processing by running the software programs, instructions, and modules stored in the memory 292, that is, to implement the methods in the above method embodiments.

[0168] The memory 292 may include a program storage area and a data storage area. Among them, the program storage area can store an operating system and application programs required for at least one function; the data storage area can store data created according to the use of the terminal device, etc. In addition, the memory 292 may include a high-speed random access memory and may also include a non-volatile memory.

[0169] An embodiment of the present application provides a non-temporary computer-readable storage medium, in which computer-execution instructions are stored, and when the computer-execution instructions are executed by a processor, they are used to implement the method as described in the foregoing embodiments.

[0170] An embodiment of the present application provides a computer program product, including a computer program, and when the computer program is executed by a processor, it implements the method as described in the foregoing embodiments.

[0171] It should be noted that for the foregoing method embodiments, for the sake of simple description, they are all expressed as a series of action combinations. However, those skilled in the art should know that the present application is not limited by the described action sequence, because according to the present application, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily essential to the present application.

[0172] It should be further noted that although the steps in the flowchart are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise clearly stated in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowchart may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or sub-steps or stages of other steps.

[0173] It should be understood that the above device embodiments are illustrative only, and the devices of the present application can also be implemented in other ways. For example, the division of units / modules in the above embodiments is only a logical function division, and there can be other division methods in actual implementation. For example, multiple units, modules or components can be combined, or can be integrated into another system, or some features can be ignored or not executed.

[0174] In addition, unless otherwise specified, in each embodiment of the present application, each functional unit / module can be integrated into one unit / module, or each unit / module can exist physically alone, or two or more units / modules can be integrated together. The above integrated unit / module can be implemented in the form of hardware or in the form of a software program module.

[0175] When the integrated unit / module is implemented in the form of hardware, the hardware can be a digital circuit, an analog circuit, etc. The physical implementation of the hardware structure includes but is not limited to transistors, memristors, etc. The processor can be any suitable hardware processor, such as CPU, GPU, FPGA, DSP, and ASIC, etc. The storage unit can be any suitable magnetic storage medium or magneto-optical storage medium, such as resistive random access memory RRAM (Resistive Random Access Memory), dynamic random access memory DRAM (Dynamic Random Access Memory), static random access memory SRAM (Static Random-Access Memory), enhanced dynamic random access memory EDRAM (Enhanced Dynamic Random Access Memory), high-bandwidth memory HBM (High-Bandwidth Memory), hybrid memory cube HMC (Hybrid Memory Cube), etc.

[0176] When an integrated unit / module is implemented in the form of a software program module and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods of various embodiments of this application. And the aforementioned memory includes: various media such as USB flash drives, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), external hard drives, magnetic disks, or optical discs that can store program codes.

[0177] In the above embodiments, the descriptions of the various embodiments each have their own emphases. For the parts not detailed in a certain embodiment, reference can be made to the relevant descriptions of other embodiments. The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered to be within the scope described in this specification.

[0178] Those skilled in the art will readily think of other implementation schemes of this application after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptive changes of this application. These variations, uses, or adaptive changes follow the general principles of this application and include the common general knowledge or conventional technical means in the technical field not disclosed in this application. The specification and the embodiments are only regarded as exemplary, and the true scope and spirit of this application are pointed out by the following claims.

[0179] It should be understood that this application is not limited to the exact structure already described and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is only limited by the appended claims.

Claims

1. A decoding method, characterized in that: include: receiving a decoding request, wherein the decoding request includes a symbol sequence and a check matrix; Determine, according to the decoding request, the number of check nodes corresponding to the check matrix, and perform hierarchical processing on the symbol sequence according to the number of check nodes to obtain a plurality of symbol groups; Determining a target parallelism according to the check matrix and the plurality of symbol groups; According to the target parallelism, the multiple symbol groups are sequentially iteratively decoded by using the check matrix to obtain original data; Determining a target parallelism according to the check matrix and the plurality of symbol groups includes: Determine the amount of idle resources, the number of groups corresponding to the multiple symbol groups, and the row weight corresponding to the check matrix, where the row weight is the number of variable nodes connected to each check node; The target parallelism is determined according to the amount of idle resources, the number of groups, and the row weight.

2. The method according to claim 1, characterized in that By using the check matrix, the multiple symbol groups are iteratively decoded in sequence according to the target parallelism to obtain original data, including: Determining a plurality of computing tasks from the plurality of symbol groups according to the target parallelism, each computing task comprising a plurality of sub-symbol groups; Iteratively decode multiple sub-symbol groups corresponding to each computing task through the variable node to check node V2C message vector and the check node to variable node C2V message vector to obtain multiple target data corresponding to each computing task; The original data is determined according to a plurality of target data corresponding to each computing task.

3. The method according to claim 2, characterized in that For any sub-symbol group under any computing task; the sub-symbol group is iteratively decoded through a variable node to check node V2C message vector and a check node to variable node C2V message vector to obtain a plurality of target data corresponding to the sub-symbol group, including: Determining a channel noise characteristic value, a check node corresponding to the sub-symbol group, and a variable node corresponding to the sub-symbol group; Calculating an initial log-likelihood ratio according to the channel noise characteristic value and the sub-symbol group, and determining the initial log-likelihood ratio as an initial V2C message vector of the variable node; Determine the number of symbol values ​​of the sub-symbol group, and determine the initial C2V message vector of the check node according to the principle of equal posterior probability and the number of symbol values; Iterative processing is performed according to the initial V2C message vector and the initial C2V message vector to obtain the multiple target data.

4. The method according to claim 3, characterized in that Iterative processing is performed according to the initial V2C message vector and the initial C2V message vector to obtain the plurality of target data, including: Execute a preset operation until the number of times the preset operation is executed is greater than a preset number or a preset condition is met, and determine the target data according to the judgment result; The preset operation includes: determining a target element from the check matrix according to the variable node and the check node, performing finite field multiplication calculation on the initial V2C message vector and the target element to obtain an updated V2C message vector, performing inverse permutation processing on the updated V2C message vector to obtain an inverse permutation vector, performing update processing on the check node by using the inverse permutation vector to obtain an updated C2V message vector, performing decision processing on the updated V2C message vector and the updated C2V message vector to obtain the decision result, wherein the decision result is a check pass or a check fail; Among them, the preset condition is that the judgment result is verification passed.

5. The method according to claim 4, characterized in that Determine the target data based on the judgment result, including: According to the judgment result, determining a plurality of candidate posterior probabilities when the variable node takes different symbol values; The symbol value corresponding to the largest candidate posterior probability among the multiple candidate posterior probabilities is determined as the target data.

6. The method according to claim 4, characterized in that Conduct judgment processing, including: Determine the index value corresponding to each symbol group; The updated V2C message vector and the updated C2V message vector obtained in each iteration are stored in a cache, and the count value is updated according to the index value corresponding to each symbol group; When the count value is equal to the preset value, the decision process is performed.

7. A decoding device, characterized in that: include: A receiving module, configured to receive a decoding request, wherein the decoding request includes a symbol sequence and a check matrix; A message initialization module, configured to determine the number of check nodes corresponding to the check matrix according to the decoding request, and perform hierarchical processing on the symbol sequence according to the number of check nodes to obtain a plurality of symbol groups; A determination module, configured to determine a target parallelism according to the check matrix and the plurality of symbol groups; A partial parallel control module, configured to perform iterative decoding processing on the plurality of symbol groups in sequence through the check matrix according to the target parallelism to obtain original data; The determination module is specifically used to determine the amount of idle resources, the number of groups corresponding to the multiple symbol groups, and the row weight corresponding to the check matrix, where the row weight is the number of variable nodes connected to each check node; The target parallelism is determined according to the amount of idle resources, the number of groups, and the row weight.

8. The device according to claim 7, characterized in that The device also includes: A cache module, used for determining the index value corresponding to each symbol group; The cache module is further used to store the updated V2C message vector and the updated C2V message vector obtained in each iteration into the cache, and update the count value according to the index value corresponding to each symbol group; The cache module is also used to perform decision processing until the count value is equal to a preset value.

9. An electronic device, characterized in that: include: A processor, and a memory communicatively connected to the processor; The memory stores computer-executable instructions; The processor executes the computer-executable instructions stored in the memory to implement the method according to any one of claims 1 to 6.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, which are used to implement the method according to any one of claims 1 to 6 when executed by a processor.

11. A computer program product, characterized in that The invention comprises a computer program, which implements the method according to any one of claims 1 to 6 when being executed by a processor.

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