Radio frequency processing circuit, signal processing method and radio frequency processing equipment

Abstract

The embodiment of the invention provides a radio frequency processing circuit, a signal processing method and radio frequency processing equipment, which are applied to the technical field of communication. The radio frequency processing circuit comprises a radio frequency channel, a plurality of power dividers and a channel detection channel. And the combining ends of the plurality of power dividers are correspondingly coupled with the plurality of antenna array elements. The first branching ends of the plurality of power dividers are coupled with the input end of the radio frequency channel. And the second branching ends of the plurality of power dividers are coupled with the input end of the channel detection channel. The plurality of power dividers are used for acquiring a plurality of corresponding radio frequency signals from the plurality of antenna array elements, and performing branching processing on the plurality of radio frequency signals to obtain a plurality of first radio frequency data signals and a plurality of radio frequency reference signals. The radio frequency channel is used for inputting a plurality of first radio frequency data signals. The channel detection channel is used for inputting a plurality of radio frequency reference signals. The plurality of radio frequency reference signals are used for obtaining antenna array element level channel information. According to the embodiment of the invention, the wave beam round robin time during full-airspace coverage can be reduced, and the performance loss of a network system is reduced.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a radio frequency processing circuit, a signal processing method and a radio frequency processing device. Background Art

[0002] With the development of communication technology, the operating frequency of communication equipment has gradually increased, resulting in an increase in the spatial propagation loss of electromagnetic waves. The macro station side needs to have a higher equivalent isotropic radiated power (EIRP) to compensate for the path loss. Currently, the EIRP is increased by increasing the antenna gain through the related technologies of the hybrid beamforming (HBF) architecture. However, the technical means of increasing the antenna gain through the HBF architecture requires a single RF channel to drive more antenna elements, which will cause the beam width to become narrower. With a narrower beam width, more beams are required to perform time rotation to achieve full airspace coverage, which in turn leads to increased performance loss of the network system.

[0003] Therefore, how to reduce the beam rotation time when covering the entire airspace and reduce the performance loss of the network system has become a technical problem that needs to be solved urgently. Summary of the invention

[0004] The embodiments of the present application provide a radio frequency processing circuit, a signal processing method and a radio frequency processing device to reduce the beam rotation time during full airspace coverage and reduce network system performance loss.

[0005] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0006] In a first aspect, a radio frequency processing circuit is provided, which includes a radio frequency channel, multiple power dividers, and a channel detection channel. The combining ends of the multiple power dividers are coupled to the multiple antenna array elements; the first branching ends of the multiple power dividers are coupled to the input end of the radio frequency channel; and the second branching ends of the multiple power dividers are coupled to the input end of the channel detection channel. The multiple power dividers are used to: obtain the corresponding multiple radio frequency signals from the multiple antenna array elements, and perform branching processing on the multiple radio frequency signals to obtain multiple first radio frequency data signals and multiple radio frequency reference signals. The radio frequency channel is used to: input multiple first radio frequency data signals. The channel detection channel is used to: input multiple radio frequency reference signals; the multiple radio frequency reference signals are used to obtain antenna array element level channel information.

[0007] In an embodiment of the present application, by mapping a radio frequency channel to multiple antenna elements, the decoupling of the number of radio frequency channels and the number of antenna elements is achieved, that is, the number of radio frequency channels required for the same antenna element is reduced, and the convergence ratio between the radio frequency channel and the antenna element is improved, so that more antenna elements can be accommodated under the same physical aperture plane, thereby increasing the antenna gain and enhancing the coverage. However, under this implementation method, a single radio frequency channel drives more antenna elements, which will cause the beam width to become narrower. Under a narrower beam width, more beams are required to perform time rotation to achieve full airspace coverage, which in turn leads to increased network system performance loss. Therefore, a power divider and a dedicated channel detection channel can be set in the radio frequency processing circuit. The power divider obtains the corresponding radio frequency signal from the antenna element and performs branch processing on the radio frequency signal to obtain the first radio frequency data signal and radio frequency reference signal at the antenna element level. The dedicated channel detection channel inputs the RF reference signal at the antenna element level. Since the beam width of a single antenna element is large, it can receive channel information in the entire airspace. Therefore, the antenna element level channel information input by the channel detection channel can be used to obtain antenna element level channel information or full airspace channel information after one or a few beam rotations, thereby reducing the beam rotation time when the entire airspace is covered, shortening the channel measurement cycle, reducing time overhead, reducing network system performance loss and delaying channel aging, and improving data transmission performance. Analysis shows that the RF processing circuit provided by the present application scheme achieves the purpose of reducing the beam rotation time when the entire airspace is covered while increasing the antenna gain and reducing the performance loss of the network system.

[0008] In a possible implementation, the radio frequency processing circuit further includes a gating circuit. The second branch ends of the plurality of power dividers are coupled to the branch end of the gating circuit. The common end of the gating circuit is coupled to the input end of the channel detection channel. In this embodiment, the channel information at the level of different antenna array elements can be dynamically acquired through the cooperation between the channel detection channel and the gating circuit.

[0009] In a possible implementation, the gating circuit is a single-pole multi-throw switch.

[0010] In a possible implementation, the radio frequency processing circuit further includes a plurality of low noise amplifiers. The input ends of the plurality of low noise amplifiers are coupled to the plurality of antenna array elements, and the output ends of the plurality of low noise amplifiers are coupled to the combining ends of the plurality of power dividers. By arranging the power divider at the output end of the low noise amplifier to receive the signal processed by the low noise amplifier, the influence of the noise introduced by the antenna array element end on the radio frequency reference signal is reduced, thereby improving the quality of the signal received at the power divider side.

[0011] In a possible implementation, the RF processing circuit further includes a power amplifier. The channel detection channel is a predistortion feedback channel of the power amplifier corresponding to the power amplifier. This embodiment reduces the RF circuit hardware consumption and reduces the hardware cost by sharing the channel detection channel with the predistortion feedback channel of the power amplifier.

[0012] In the second aspect, the embodiment of the present application also provides a signal processing method, which is applied to a radio frequency processing circuit, wherein the radio frequency processing circuit includes a radio frequency channel, multiple power dividers, and a channel detection channel. The method includes: multiple power dividers obtain corresponding multiple radio frequency signals from multiple antenna array elements, and perform branching processing on the multiple radio frequency signals to obtain multiple first radio frequency data signals and multiple radio frequency reference signals. The radio frequency channel inputs multiple first radio frequency data signals. The channel detection channel inputs multiple radio frequency reference signals, and the multiple radio frequency reference signals are used to obtain antenna array element level channel information.

[0013] In a possible implementation, inputting a plurality of radio frequency reference signals includes: inputting a control signal. The control signal is used to indicate selection of one or more of the plurality of radio frequency reference signals. In response to the control signal, inputting one or more of the plurality of radio frequency reference signals.

[0014] In a possible implementation, the RF processing circuit further includes a power amplifier. The channel detection channel is a predistortion feedback channel of the power amplifier corresponding to the power amplifier. The method further includes: in a first time slot, the RF channel transmits a second RF data signal through an antenna array element. One or more of the multiple RF reference signals are input, and further includes: in a second time slot, the channel detection channel inputs one or more of the multiple RF reference signals. The first time slot and the second time slot are time slots separated.

[0015] In a third aspect, an embodiment of the present application further provides a radio frequency processing device, comprising a circuit board and any radio frequency processing circuit in the first aspect, wherein the radio frequency processing circuit is arranged on the circuit board.

[0016] In a fourth aspect, an embodiment of the present application further provides a communication system, comprising a baseband processing device and a radio frequency processing device as in the third aspect. The baseband processing device is coupled to the radio frequency processing device. The radio frequency processing device is used to: output a plurality of radio frequency reference signals to the baseband processing device, and the plurality of radio frequency reference signals are used to obtain antenna array element level channel information.

[0017] In a possible implementation, the baseband processing device is used to obtain antenna array element level channel information of the radio frequency processing circuit according to the radio frequency reference signal.

[0018] In a possible implementation, the radio frequency processing device includes a controller; the controller is configured to obtain antenna array element level channel information of the radio frequency processing circuit according to a radio frequency reference signal.

[0019] Regarding the technical principles and beneficial effects of the second, third and fourth aspects, reference may be made to the relevant description of the first aspect mentioned above and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A structural diagram of a communication system provided in an embodiment of the present application;

[0021] Figure 2 A structural diagram of a radio frequency processing device provided in an embodiment of the present application;

[0022] Figure 3 A structural diagram of an equivalent isotropic radiated power structure provided in an embodiment of the present application;

[0023] Figure 4 A comparison diagram of the number of antenna array elements and antenna gain provided in an embodiment of the present application;

[0024] Figure 5 A structure of a radio frequency processing circuit provided in an embodiment of the present application Figure 1 ;

[0025] Figure 6 A structural diagram of an active antenna unit provided in an embodiment of the present application;

[0026] Figure 7 A structure of a radio frequency processing circuit provided in an embodiment of the present application Figure 2 ;

[0027] Figure 8 A simulation relationship diagram of the number of antenna array elements and beam width provided in an embodiment of the present application;

[0028] Fig. 9 A relationship diagram between the number of antenna array elements and the beam width provided in an embodiment of the present application;

[0029] Fig.10 A beam scanning in a radio frequency processing circuit provided in an embodiment of the present application obtains a full spatial channel information diagram;

[0030] Fig.11 A structure of a radio frequency processing circuit provided in an embodiment of the present application Figure 3 ;

[0031] Fig.12 A structure of a radio frequency processing circuit provided in an embodiment of the present application Figure 4 ;

[0032] Fig.13 A structure of a radio frequency processing circuit provided in an embodiment of the present application Figure 5 ;

[0033] Fig.14 A structure of a radio frequency processing circuit provided in an embodiment of the present application Figure 6 ;

[0034] Fig.15 A structure of a radio frequency processing circuit provided in an embodiment of the present application Figure 7 ;

[0035] Fig.16 A structure of a radio frequency processing circuit provided in an embodiment of the present application Figure 8 ;

[0036] Fig.17 A structural diagram of another radio frequency processing device provided in an embodiment of the present application;

[0037] Fig.18 A flowchart of a signal processing method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0038] It should be noted that the terms "first", "second", etc. involved in the embodiments of the present application are only used to distinguish features of the same type and cannot be understood as indicating relative importance, quantity, order, etc.

[0039] The terms "exemplary" or "for example" and the like in the embodiments of the present application are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of the terms "exemplary" or "for example" is intended to present the related concepts in a specific way.

[0040] The terms "coupling" and "connection" involved in the embodiments of the present application should be understood in a broad sense. For example, they may refer to a direct physical connection, or an indirect connection achieved through electronic devices, such as a connection achieved through resistors, inductors, capacitors or other electronic devices.

[0041] First, some basic concepts involved in this application are explained:

[0042] Equivalent isotropic radiated power (EIRP): Also known as effective isotropic radiated power, it represents the relative antenna gain of the transmitting antenna relative to the antenna gain of an isotropic radiating element multiplied by the net power received by the antenna from the connected transmitter in a given direction. The power radiated by the transmitting antenna of a satellite or earth station in the axis of the center of the beam is called the effective isotropic radiated power of the transmitting device, that is, the product of the power supplied to the antenna of the radio transmitter and the absolute gain of the antenna in a given direction. It is an important indicator of the transmission capability of an earth station or repeater. An ideal omnidirectional antenna with the same unit gain in all directions is usually used as a reference antenna for wireless communication systems. EIRP is defined as: EIRP = Pt*Gt, where Pt represents the net power received from the connected transmitter and Gt represents the antenna gain of the transmitting antenna. It represents the transmission power that can be obtained by the transmitter in the direction of maximum antenna gain compared to an omnidirectional antenna.

[0043] Antenna gain: refers to the ratio of the power density of the signal generated by the actual antenna and the ideal radiating unit at the same point in space under the condition of equal input power. It quantitatively describes the degree to which an antenna radiates the input power in a concentrated manner. The gain is obviously closely related to the antenna pattern. The narrower the main lobe of the pattern and the smaller the side lobe, the higher the gain. Antenna gain is used to measure the ability of an antenna to send and receive signals in a specific direction. It is one of the most important parameters for selecting base station antennas. Generally speaking, the improvement of gain mainly relies on reducing the beam width of the vertical radiation while maintaining omnidirectional radiation performance in the horizontal plane. Antenna gain is extremely important to the operating quality of the communication system because it determines the signal level at the edge of the cell. Increasing the gain can increase the coverage of the network in a certain direction, or increase the gain margin within a certain range. Any cellular system is a two-way process. Increasing the gain of the antenna can simultaneously reduce the gain budget margin of the two-way system. Under the same conditions, the higher the gain, the farther the radio wave propagates.

[0044] Beam: refers to the shape of the electromagnetic waves emitted by the antenna on the surface of the earth. It can also be understood as the main lobe of the antenna array radiation pattern.

[0045] Beam width: refers to the angular width on both sides of the maximum radiation direction when the power density relative to the maximum radiation direction drops to half, also called 3dB beam width. The half-power beam width in the horizontal plane is called the horizontal beam width; the half-power beam width in the vertical plane is called the vertical beam width.

[0046] The present application embodiment provides a communication system 1000, such as Figure 1As shown, the baseband processing device 100 and the radio frequency processing device 200 are included. The baseband processing device 100 is coupled to the radio frequency processing device 200. The radio frequency processing device 200 is used to: output multiple radio frequency reference signals to the baseband processing device 100, and the multiple radio frequency reference signals are used to obtain antenna array element level channel information. The antenna array element level channel information may include but is not limited to the phase, amplitude and delay information of the signal.

[0047] In some possible implementations, such as Figure 2 As shown, the RF processing device 200 includes a RF processing circuit 210 and a circuit board 220 , and the RF processing circuit 210 is disposed on the circuit board 220 .

[0048] For example, as 5G communication evolves to 5.5G or 6G communication, the operating carrier frequency gradually evolves from below 6GHz (sub-6GHz) in 5G communication to higher than 6GHz (up-6GHz). As the operating frequency increases, the spatial propagation loss of electromagnetic waves increases, and a higher EIRP is required on the macro station side to compensate for the path loss. There are currently two main technical paths to increase EIRP, one is to increase the transmit power of the power amplifier 18 (power amplifier, PA), and the other is to increase the antenna gain. Figure 3 As shown in FIG. 1 , the transmit power of the PA and the antenna gain together constitute the EIRP. However, since increasing the transmit power of the PA will increase the power consumption of the RF processing circuit 210, there is a greater constraint on increasing the transmit power of the PA. Therefore, in the evolution to higher up-6GHz, the EIRP is increased by increasing the antenna gain. Increasing the antenna gain is mainly achieved by increasing the number of antenna array elements. An antenna can contain multiple antenna array elements. For example Figure 4 As shown in the figure, since the wavelength of electromagnetic waves at up-6GHz frequency is shorter than that of electromagnetic waves at sub-6GHz frequency, the size of the corresponding antenna array elements can be reduced. Therefore, under the same physical aperture, more antenna array elements can be accommodated, and the antenna gain that can be achieved is higher.

[0049] In order to increase the EIRP, in some possible implementations, the RF processing circuit 210 may be a first RF processing circuit based on a digital beamforming (DBF) architecture. Figure 5 As shown, the first RF processing circuit 210A includes a plurality of first antenna array elements 211A and a first RF channel 212A, and the first RF channel 212A is mapped one-to-one with the first antenna array element 211A. The first RF channel 212A performs functions such as filtering and amplifying RF analog signals, and the first antenna array element 211A mainly performs sending and receiving of analog signals.

[0050] The first RF processing circuit 210A can increase the EIRP by increasing the number of first antenna array elements 211A. However, as the number of first antenna array elements 211A increases, the number of first RF channels 212A matching the first antenna array elements 211A will also increase, which will greatly increase the device configuration cost. Figure 5 As shown, the main advantage of the first RF processing circuit 210A is that the first RF channel 212A is mapped one-to-one with the first antenna array element 211A. Since the beam width of a single first antenna array element 211A is large, the controller in the baseband processing circuit or RF circuit can obtain the full spatial channel information at one time without multiple beam scans, so the network performance is optimal. However, according to the mapping relationship between the first antenna array element 211A and the first RF channel 212A, it can be seen that the more the number of first antenna array elements 211A is, the more the number of first RF channels 212A corresponding to it is. As the number of first RF channels 212A increases, the hardware cost and power consumption in the first RF processing circuit 210A will increase. If the frequency evolves to up-6GHz, the first RF processing circuit 210A is still used, and as the operating frequency evolves to a higher frequency, the number of first antenna array elements 211A will increase sharply under the same physical caliber, and the hardware equipment such as the first RF channel 212A that matches it will also increase in the same proportion, which will lead to a sharp increase in the power consumption and hardware cost of the first RF processing circuit 210A.

[0051] In an example, the first RF processing circuit 210A may also be used to modulate the baseband signal to obtain an intermediate frequency signal, up-convert the intermediate frequency signal to obtain an RF signal; or directly modulate the baseband signal to an RF signal.

[0052] In an example, the first RF processing circuit 210A may be an active antenna unit (AAU) or a remote radio unit (RRU). Figure 6 As shown, the AAU includes a baseband, a digital intermediate frequency, a first radio frequency channel 212A, and a first antenna array element 211A. The baseband part mainly performs functions such as baseband signal encoding, modulation, layer mapping, and channel weighting; the digital intermediate frequency part mainly performs time domain processing functions such as frequency conversion and filtering.

[0053] In order to solve the problems existing in the first RF processing circuit 210A, in some possible implementations, the RF processing circuit 210 may be a second RF processing circuit based on a hybrid beamforming (HBF) architecture. Figure 7As shown, the second RF processing circuit 210B includes a plurality of second antenna elements 211B, a plurality of second RF channels 212B, and one second RF channel 212B is coupled to the plurality of second antenna elements 211B. The second RF processing circuit 210B can be coupled to the plurality of second antenna elements 211B via one second RF channel 212B. When the number of second antenna elements 211B is constant, the number of required second RF channels 212B is reduced compared with the first RF processing circuit 210A. Therefore, the main advantage of the second RF processing circuit 210B is that the number of second RF channels 212B is decoupled from the number of second antenna elements 211B, that is, the same number of second antenna elements 211B requires fewer second RF channels 212B, thereby reducing the power consumption and hardware cost of the second RF processing circuit 210B. However, since a single second RF channel 212B drives more second antenna elements 211B, that is, one channel maps more second antenna elements 211B, the beam of the second antenna element 211B of a single channel will be narrowed, as shown in FIG. Figure 8 shown. Figure 8 FIG. 1 is a simulation diagram showing the relationship between the number of second RF channels 212B coupled to the second antenna array element 211B, the angle (theta), and the antenna gain (ant-gain). Figure 8 The lines of the distributed triangle blocks indicate that one second RF channel 212B is coupled with four second antenna array elements 211B; the lines of the distributed circular blocks indicate that one second RF channel 212B is coupled with eight second antenna array elements 211B; and the lines of the distributed square blocks indicate that one second RF channel 212B is coupled with 16 second antenna array elements 211B. For example, Fig. 9 Figure (a) and Fig. 9 Figure (b) shows the relationship between the number of second antenna array elements 211B and the beam width. Fig. 9 (a) indicates that a second RF channel 212B is mapped to eight second antenna array elements 211B, which are eight vertical units, with a gain of 13 dBi, a horizontal beamwidth of 100°, and a vertical beamwidth of 13°; Fig. 9 (b) shows that a second RF channel 212B is mapped to 16 second antenna array elements 211B, which is a vertical sixteen-unit structure with a gain of 16 dBi, a horizontal beamwidth of 100°, and a vertical beamwidth of 6°.

[0054] In one example, to achieve full coverage, Fig.10As shown, a phase shifter 213B can be set between the second RF channel 212B and the second antenna array element 211B. Its main function is to configure different weights through the phase shifter 213B, adjust the weight value or phase value of the phase shifter 213B, so that the beam points to different directions, control the beam scanning of the second antenna array element 211B, and let the beam scan the entire airspace in a time-division manner. It can be seen that when the beam width of the second antenna array element 211B becomes narrower, more beams are required for time round-robin to cover the entire airspace, then the channel measurement cycle is lengthened, the channel ages seriously, the network performance is reduced, and the corresponding data transmission performance loss is large, thus resulting in an increase in network system performance loss.

[0055] In order to reduce the beam rotation time when the whole airspace is covered, the network system performance loss is reduced. In some possible implementations, the RF processing circuit 210 may be a third RF processing circuit based on the HBF architecture. Fig.11 As shown, the third RF processing circuit 210C includes a third RF channel 212C, a plurality of power dividers 213C and a channel detection channel 214C. The combining ends of the plurality of power dividers 213C are coupled to the plurality of third antenna array elements 211C. The first branching ends of the plurality of power dividers 213C are coupled to the input end of the third RF channel 212C. The second branching ends of the plurality of power dividers 213C are coupled to the input end of the channel detection channel 214C. The plurality of power dividers 213C are used to: obtain the corresponding plurality of RF signals from the plurality of third antenna array elements 211C, perform branching processing on the plurality of RF signals, and obtain a plurality of first RF data signals and a plurality of RF reference signals. The third RF channel 212C is used to: input a plurality of first RF data signals. The channel detection channel 214C is used to: input a plurality of RF reference signals, and the plurality of RF reference signals are used to realize the acquisition of antenna array element level channel information.

[0056] For example, Fig.12 As shown, the third RF processing circuit 210C may include a plurality of channel detection channels 214C, and one channel detection channel 214C may correspond to a plurality of third antenna array elements 211C. The first RF data signal and the RF reference signal may be the same signal.

[0057] Illustratively, the third radio frequency processing circuit 210C provided in this embodiment can be applied to, but not limited to, devices such as base stations, mobile communication terminals, and radars.

[0058] In an embodiment of the present application, by mapping a third RF channel 212C to multiple third antenna array elements 211C, the decoupling of the number of third RF channels 212C and the number of third antenna array elements 211C is achieved, that is, the number of third RF channels 212C required for the same third antenna array element 211C is reduced, and the convergence ratio between the third RF channel 212C and the third antenna array element 211C is improved, so that more third antenna array elements 211C can be accommodated under the same physical aperture plane, thereby achieving the purpose of increasing antenna gain and enhancing coverage. However, under this implementation, a single third RF channel 212C drives more third antenna array elements 211C, which will cause the beam width to become narrower. Under a narrower beam width, more beams are required to perform time rounds to achieve full airspace coverage, which in turn leads to increased network system performance loss. Therefore, a power divider 213C and a dedicated channel detection channel 214C can be set in the third RF processing circuit 210C. The power divider 213C obtains the corresponding RF signal from the third antenna array element 211C, and performs branching processing on the RF signal to obtain the first RF data signal and RF reference signal of the third antenna array element 211C level. The dedicated channel detection channel 214C inputs the RF reference signal of the third antenna array element 211C level. Since the beam width of a single third antenna array element 211C is large, channel information can be received in the entire airspace. Therefore, the third antenna array element 211C level channel information input by the channel detection channel 214C can be used to obtain antenna array element level channel information or full airspace channel information after one or a few beam rotations, thereby reducing the beam rotation time when the entire airspace is covered, shortening the channel measurement cycle, reducing time overhead, reducing network system performance loss and delaying channel aging, and improving data transmission performance. It can be seen from the analysis that the third RF processing circuit 210C provided in the present application scheme increases the antenna gain while reducing the beam rotation time during full airspace coverage, thereby reducing the performance loss of the network system.

[0059] In some possible implementations, such as Fig.13 As shown, the third RF processing circuit 210C further includes a gating circuit 215C; the second branching ends of the plurality of power dividers 213C are coupled to the branching ends of the gating circuit 215C; and the common end of the gating circuit 215C is coupled to the input end of the channel detection channel 214C.

[0060] Exemplarily, the gating circuit 215C selects the third antenna element 211C according to a preset rule. In this embodiment, the preset rule may be to select the third antenna element 211C corresponding to a signal with a larger power according to the power strength of the signal received by the third antenna element 211C.

[0061] In some possible implementations, the gating circuit 215C may be a single-pole multi-throw switch.

[0062] In some possible implementations, the third RF processing circuit 210C further includes a plurality of low noise amplifiers 216C; input ends of the plurality of low noise amplifiers 216C are correspondingly coupled to a plurality of third antenna array elements 211C, and output ends of the plurality of low noise amplifiers 216C are coupled to combining ends of a plurality of power dividers 213C.

[0063] In one example, if Fig.14 The third RF processing circuit 210C for transmitting and receiving common phase shift is shown. It includes a single pole double throw (SPDT) switch, a switch or a circulator. The SPDT switch is used to switch working time slots, such as downlink working time slots or uplink working time slots.

[0064] In one example, if Fig.15 The third RF processing circuit 210C is shown as a transmitting and receiving independent phase shift circuit, which includes a SPDT, a switch or a circulator.

[0065] In an embodiment of the present application, a power divider is arranged at the output end of a low noise amplifier to receive a signal processed by the low noise amplifier, thereby reducing the influence of noise introduced by the antenna array element end on the RF reference signal, thereby improving the quality of the signal received at the power divider side.

[0066] In some possible implementations, such as Fig.16 As shown, the third RF processing circuit 210C further includes a power amplifier 217C; the channel detection channel 214C is a power amplifier feedback channel 218C corresponding to the power amplifier 217C.

[0067] For example, Fig.16As shown, when the RF signal is output from the third RF channel 212C, it needs to be amplified by the power amplifier 217C before it can be transmitted through the third antenna array element 211C. Ideally, the power amplifier 217C receives an input signal and outputs a higher power signal proportional to its input so as to convert most of the DC power supplied to the amplifier into signal output power. However, this is not an ideal situation, and the power amplifier 217C is made of power tubes. Power tubes are active devices that only exhibit linear characteristics within a certain operating range. When the power amplifier 217C based on the power tube operates in the linear operating range, its output power is a certain amplification gain with respect to the input power. When the power amplifier 217C operates at the saturation point of the linear operating range, the maximum operating efficiency can be achieved. With the development of wireless communication technology, the modulation order of the RF signal has become more and more complex, which makes the RF signal have a higher signal peak-to-average ratio. When the signal peak-to-average ratio increases, if the power amplifier 217C operates at a higher power point in the linear working area (even the saturated power point in the linear working interval), the RF signal input by the power amplifier 217C is easy to enter the nonlinear working interval or even the saturated working interval of the power amplifier 217C, which will cause the RF signal output by the power amplifier 217C to have a large nonlinear distortion, affecting communication. In order to avoid such nonlinear distortion, a certain power backoff is usually performed, so that the saturated power point of the power amplifier 217C operating in the linear working interval is backed off by a certain amount of power point position. The disadvantage of such power backoff is that the working efficiency of the power amplifier 217C is greatly reduced, so that most of the power provided by the power supply of the power amplifier 217C is lost in the form of heat. Therefore, in order to reduce power loss, an improved method is to design a power synthesis architecture for the power amplifier 217C, and adopt a power amplifier circuit such as a Doherty architecture or other power synthesis architecture to improve the backoff amount and working efficiency of the power amplifier 217C. Another way is to set a predistortion amplifier circuit in the power amplifier 217C, and pre-assign a nonlinear distortion characteristic opposite to the nonlinear distortion characteristic of the power amplifier 217C to the RF signal input to the power amplifier 217C through the predistortion amplifier circuit, so as to compensate for the nonlinear distortion of the power amplifier 217C working in the power saturation range. The predistortion amplifier circuit can be a digital predistortion amplifier circuit and an analog predistortion amplifier circuit. In the process of using the predistortion amplifier circuit to compensate for the nonlinear distortion, it is necessary to obtain the output RF signal from the output end of the power amplifier 217C in real time. Feedback is performed based on the RF signal output by the power amplifier 217C, and the nonlinear distortion characteristic of the predistortion amplifier circuit is dynamically adjusted by the fed-back RF signal, thereby ensuring a good nonlinear compensation effect on the power amplifier 217C.In this feedback process, it is necessary to set a corresponding pre-distortion feedback (feedback, FB) channel for the power amplifier 217C to implement sampling of the RF signal output by the power amplifier 217C. The power amplifier feedback channel 218C in this embodiment can be a pre-distortion feedback channel of the power amplifier 217C. The third RF processing circuit 210C is a HBF architecture for FB channel multiplexing, that is, the original FB channel of the third RF processing circuit 210C is shared as a channel detection channel 214C, so that the channel detection channel 214C is shared with the original FB channel of the third RF processing circuit 210C to reduce hardware consumption. The FB channel is used for pre-distortion feedback of the HBF architecture power amplifier 217C, such as. Fig.16 The branch end of the gating circuit 215C shown is coupled with the coupler, and the output of the power amplifier 217C is mainly fed back to the RF channel 12 for digital pre-distortion training. The branch end of the gating circuit 215C is coupled with the power divider 213C to provide a solution for this embodiment. Through an SPDT, since the pre-distortion of the power amplifier 217C of the branch end of the gating circuit 215C and the coupling part of the coupler mainly works in the downlink time slot, and the channel detection of this embodiment is used for the uplink time slot, the FB channel can be efficiently multiplexed through the single-pole double-throw switch, thereby reducing hardware investment and reducing hardware costs.

[0068] In some possible implementations, the baseband processing device 100 is configured to obtain antenna array element-level channel information of the RF processing circuit 210 according to the RF reference signal.

[0069] For example, the RF reference signal includes channel state information, and in the communication system, the transmission strategy of the transmitter can be guided by obtaining the signal state information in the RF reference signal. For example, when the transmitter transmits information, it can avoid the propagation path with poor channel conditions or select the propagation path with good channel conditions to transmit information according to the obtained channel information, thereby improving the performance of the communication system.

[0070] In some possible implementations, such as Fig.17 As shown, the RF processing device 200 includes a controller 230, and the controller 230 is used to obtain antenna array element level channel information of the RF processing circuit 210 according to the RF reference signal.

[0071] Based on the above Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 and Fig.16 The structure shown can be implemented as follows Fig.18The signal processing method shown includes the following steps S100 to S300: the method can be applied to a radio frequency processing circuit, the radio frequency processing circuit includes a radio frequency channel, a plurality of power dividers and a channel detection channel; the specific steps include:

[0072] S100: Multiple power dividers obtain corresponding multiple radio frequency signals from multiple antenna array elements, and perform branching processing on the multiple radio frequency signals to obtain multiple first radio frequency data signals and multiple radio frequency reference signals.

[0073] For example, Fig.11 As shown, the RF processing circuit may include multiple RF channels, one RF channel may be coupled with multiple power dividers, each power divider may be coupled with one or more antenna array elements, obtain corresponding RF signals from one or more antenna array elements, and perform branching processing on the RF signals to obtain a first RF data signal and a RF reference signal. The first RF data signal contains information transmitted by the channel; the RF reference signal contains channel attribute information and channel quality information, such as the phase, amplitude, and delay of the channel.

[0074] In one example, the power divider obtains the RF signal of the corresponding channel from the antenna array element, and divides the RF signal into two to obtain a first RF data signal and a RF reference signal, which are used for RF channel input and channel detection channel input respectively.

[0075] S200: A radio frequency channel inputs a plurality of first radio frequency data signals.

[0076] S300, a channel detection channel inputs multiple radio frequency reference signals; the multiple radio frequency reference signals are used to obtain antenna array element level channel information.

[0077] In an embodiment of the present application, firstly, the effect of increasing the antenna gain is achieved by mapping a radio frequency channel to multiple antenna elements. Secondly, the power divider in the radio frequency processing circuit performs branching processing on multiple radio frequency signals obtained from multiple antenna elements to obtain multiple first radio frequency data signals and multiple radio frequency reference signals, and then the radio frequency channel inputs multiple first radio frequency data signals for obtaining channel transmission information; the channel detection channel inputs multiple radio frequency reference signals for obtaining antenna element-level channel information. By setting different channels for obtaining different information in the channel, the purpose of enhancing the channel measurement capability is achieved. This avoids the use of only one radio frequency channel in the related art, which is used to obtain channel transmission information and antenna element-level channel information, resulting in a lengthened channel measurement cycle, an increase in time overhead, an increase in network system performance loss, and accelerated channel aging.

[0078] In some possible implementations, step S300 may include the following sub-operations: step S310 to step S320:

[0079] S310. Input a control signal; the control signal is used to instruct selection of one or more of a plurality of RF reference signals.

[0080] Exemplarily, the control signal may be made according to preset information contained in the radio frequency reference signal. The preset information may include energy information, signal quality information, etc. of the radio frequency reference signal, which is not limited here.

[0081] S320: In response to the control signal, input one or more of the plurality of radio frequency reference signals.

[0082] Exemplarily, in response to the control signal, the channel sounding channel inputs one or more of the multiple RF reference signals to obtain antenna element-level channel information. In this embodiment, when multiple of the multiple RF reference signals are input, they may not be input simultaneously.

[0083] In some possible implementations, the RF processing circuit also includes a power amplifier; the channel detection channel is a power amplifier feedback channel corresponding to the power amplifier; the method also includes: in a first time slot, the RF channel transmits a second RF data signal through an antenna array element; inputs one or more of a plurality of RF reference signals, and also includes: in a second time slot, the channel detection channel inputs one or more of a plurality of RF reference signals; the first time slot and the second time slot are time slots separated.

[0084] For example, Fig.16 As shown, the power amplifier feedback channel can be used to provide feedback on the power amplifier predistortion. The first time slot and the second time slot correspond to different working states, respectively. For example, the first time slot can correspond to the downlink time slot working state, and the second time slot can correspond to the uplink time slot working state. The specific implementation process can refer to the description of the corresponding part above, which will not be repeated here.

[0085] Exemplarily, the power amplifier feedback channel may be a power amplifier predistortion feedback channel.

[0086] In the embodiment of the present application, the power amplifier feedback channel is multiplexed as a channel detection channel to reduce the RF circuit hardware consumption and lower the hardware cost.

[0087] The processor involved in the embodiments of the present application may be a chip. For example, it may be a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on chip (SoC), a central processor unit (CPU), a network processor (NP), a digital signal processor (DSP), a microcontroller unit (MCU), a programmable logic device (PLD), or other integrated chips.

[0088] The memory involved in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct RAM (DR RAM). It should be noted that the memory of the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0089] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0090] Those of ordinary skill in the art will appreciate that the modules and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0091] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and modules described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0092] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation, such as multiple modules or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

[0093] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical modules, that is, they may be located in one device or distributed on multiple devices. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0094] In addition, each functional module in each embodiment of the present application may be integrated into one device, or each module may exist physically separately, or two or more modules may be integrated into one device.

[0095] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using a software program, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (digital subscriber line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium may be any available medium that a computer can access or may contain one or more servers, data centers and other data storage devices that can be integrated with the medium. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a DVD), or a semiconductor medium (eg, a solid state disk (SSD)).

[0096] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A radio frequency processing circuit, characterized in that: It includes a radio frequency channel, a plurality of power dividers and a channel detection channel; the combining ends of the plurality of power dividers are coupled with a plurality of antenna array elements; the first branching ends of the plurality of power dividers are coupled with the input end of the radio frequency channel; The second branch ends of the plurality of power dividers are coupled to the input end of the channel detection channel; The multiple power dividers are used to: obtain corresponding multiple radio frequency signals from multiple antenna array elements, and perform branching processing on the multiple radio frequency signals to obtain multiple first radio frequency data signals and multiple radio frequency reference signals; The radio frequency channel is used to: input the multiple first radio frequency data signals; The channel detection channel is used to: input the multiple radio frequency reference signals; the multiple radio frequency reference signals are used to obtain antenna array element level channel information.

2. The radio frequency processing circuit according to claim 1, characterized in that: The radio frequency processing circuit also includes a gating circuit; The second branch terminals of the plurality of power dividers are coupled to the branch terminal of the gating circuit; The common terminal of the gating circuit is coupled to the input terminal of the channel detection channel.

3. The radio frequency processing circuit according to claim 2, characterized in that: The gating circuit is a single-pole multi-throw switch.

4. The radio frequency processing circuit according to any one of claims 1 to 3, characterized in that: The radio frequency processing circuit also includes a plurality of low noise amplifiers; The input ends of the multiple low noise amplifiers are coupled to the multiple antenna array elements accordingly, and the output ends of the multiple low noise amplifiers are coupled to the combining ends of the multiple power dividers.

5. The radio frequency processing circuit according to any one of claims 1 to 4, characterized in that: The radio frequency processing circuit also includes a power amplifier; The channel detection channel is a power amplifier feedback channel corresponding to the power amplifier.

6. A signal processing method, characterized in that: Applied to a radio frequency processing circuit, the radio frequency processing circuit includes a radio frequency channel, a plurality of power dividers and a channel detection channel; the method includes: The multiple power dividers obtain the corresponding multiple radio frequency signals from the multiple antenna array elements, and perform branching processing on the multiple radio frequency signals to obtain multiple first radio frequency data signals and multiple radio frequency reference signals; The radio frequency channel inputs the plurality of first radio frequency data signals; The channel detection channel inputs the multiple radio frequency reference signals; the multiple radio frequency reference signals are used to obtain antenna array element level channel information.

7. The signal processing method according to claim 6, characterized in that: The inputting the multiple radio frequency reference signals comprises: input a control signal; the control signal is used to indicate the selection of one or more of the multiple radio frequency reference signals; In response to the control signal, one or more of the plurality of radio frequency reference signals are input.

8. The signal processing method according to claim 6 or 7, characterized in that: The radio frequency processing circuit also includes a power amplifier; the channel detection channel is a power amplifier feedback channel corresponding to the power amplifier; The method further includes: in the first time slot, the radio frequency channel transmits a second radio frequency data signal through the antenna array element; The inputting one or more of the multiple RF reference signals also includes: in the second time slot, the channel detection channel inputs one or more of the multiple RF reference signals; the first time slot and the second time slot are interval time slots.

9. A radio frequency processing device, characterized in that: It comprises a circuit board and the radio frequency processing circuit according to any one of claims 1 to 5, wherein the radio frequency processing circuit is arranged on the circuit board.

10. A communication system, characterized in that: include: A baseband processing device and a radio frequency processing device as claimed in claim 9; The baseband processing device is coupled to the radio frequency processing device; The radio frequency processing device is used to: output a plurality of radio frequency reference signals to the baseband processing device; the plurality of radio frequency reference signals are used to obtain antenna array element level channel information.

11. The communication system according to claim 10, characterized in that: The baseband processing device is used to obtain antenna array element level channel information of the radio frequency processing circuit according to the radio frequency reference signal.

12. The communication system according to claim 10, characterized in that: The radio frequency processing device comprises a controller; the controller is used to obtain antenna array element level channel information of the radio frequency processing circuit according to the radio frequency reference signal.

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