Data processing method for optical communication and related device

Abstract

The embodiment of the invention discloses a data processing method for optical communication and a related device, which adopt inner code coding with higher gain to improve the performance of cascade coding, can be better compatible with DP-16QAM (quadrature amplitude modulation) and DP-QPSK (differential phase shift keying) modulation, and can be favorably applied to high-baud-rate long-distance transmission scenes such as 800G and 1.6 T-ZR. Specifically, firstly, a first bit set is obtained, the first bit set comprises d1 bits, d1 = 244664 * L, and L is a positive integer. Then, first FEC coding is carried out on the first bit set to obtain a second bit set, the second bit set comprises d2 bits, every 244664 bits in the first bit set are subjected to first FEC coding to obtain every 261086 bits in the second bit set, and d2 = 261086 * L; next, adding dpad filling bits to the second bit set to obtain a third bit set, dpad being an integer greater than or equal to 0; and performing second FEC coding on the third bit set to obtain a fourth bit set.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of optical communications, and in particular, to a data processing method and related devices for optical communications. Background Art

[0002] Driven by 5G, cloud computing, big data, and artificial intelligence, high-speed optical transmission networks are developing in the direction of large capacity, packetization, and intelligence. Coherent optical communication systems use the amplitude, phase, polarization, and frequency of light waves to carry information. In order to combat optical signal distortion caused by dispersion, polarization-related damage, noise, nonlinear effects, and other factors during transmission and maintain long-distance transmission, coherent optical communication systems usually need to use efficient forward error correction (FEC) codes to combat optical damage during optical transmission to keep the bit error rate low enough during long-distance transmission. In the 400G ZR scenario, the optical module uses CFEC cascade coding, in which the outer code uses staircase (SC) code and the inner code uses double-bit extended Hamming code. The cascade coding redundancy is about 14.8%, and the error correction capability is 1.25E-2 of the bit error rate before correction.

[0003] For future metropolitan telecommunication transmission and metropolitan data center interconnect (DCI) scenarios, such as the 1.6T-ZR scenario, the baud rate is about 240GB or even higher when considering the hexadecimal dual polarization 16-state quadrature amplitude modulation (DP-16QAM); for another example, the baud rate of 800G rate scenario long-distance transmission considering dual polarization quadrature phase shift keying (DP-QPSK) modulation is about 240GB or even higher. On the one hand, the existing data processing and transmission methods using CFEC coding cannot be applied to future scenarios with high baud rates. On the other hand, the existing data processing and transmission methods using CFEC coding are poorly adaptable in terms of compatibility with DP-QPSK modulation, which is a problem that needs to be solved urgently in the future. Summary of the invention

[0004] The application embodiment provides a data processing method and related devices for optical communication, which improves the performance of cascade coding by adopting an inner code with higher gain. At the same time, by designing a specific data processing method, it is better compatible with DP-16QAM and DP-QPSK modulation, which is conducive to application in future 1.6T-ZR scenarios using DP-16QAM and high baud rate long-distance transmission scenarios such as 800G using DP-QPSK.

[0005] In a first aspect, an embodiment of the present application provides a data processing method for optical communication. First, a first bit set is obtained, wherein the first bit set includes d1 bits, d1=244664×L, and L is a positive integer. Then, a first forward error correction (FEC) encoding is performed on the first bit set to obtain a second bit set, wherein the second bit set includes d2 bits, and every 244664 bits in the first bit set are encoded by the first FEC to obtain every 261086 bits in the second bit set, d2=261086×L. Next, d is added to the second bit set. pad The third bit set is obtained by adding padding bits, d pad is an integer greater than or equal to 0. Further, the third bit set is subjected to a second FEC encoding to obtain a fourth bit set.

[0006] In this implementation, the first FEC encoding (outer code encoding) is performed with 244664 bits as the granularity, and the number of bits in the first bit set d1=244664×L is also a multiple of 244664, so that it has a better implementation effect, is easy to implement in hardware, and has lower complexity. On this basis, the performance of cascade coding is improved by adopting an inner code encoding with a higher gain. At the same time, by designing a specific data processing method, it is better compatible with DP-16QAM and DP-QPSK modulation, which is conducive to the application in the future 1.6T-ZR scenario using DP-16QAM and 800G high baud rate long-distance transmission scenarios using DP-QPSK.

[0007] In some possible implementations, the d1 bits in the first bit set are distributed as r rows and 2056 columns, r=119×L, and the bits to be encoded use a bit matrix distributed in rows and columns, which has a better practical effect. Using 2056 columns is smaller than the existing 10280 columns, which is more conducive to the expansion of future solutions.

[0008] In some possible implementations, every 261086 bits in the second bit set are distributed into 119 rows and 2194 columns, and the first 2056 columns of the 2194 columns are used to carry the 244664 bits in the first bit set. Since the first 2056 columns of every 119 rows, a total of 2056×119=244664 bits, just carry the 244664 payload bits in the outer code encoding, this processing method has better data matching, making the hardware implementation simple and less complex.

[0009] In some possible implementations, each 261086 bits in the second bit set include 244664 bits in the first bit set, the 32 first type bits, the 6 second type bits and 16384 check bits of the first FEC code. In some specific applications, the 32 first type bits are obtained by performing a cyclic redundancy check (CRC) on the 244664 payload bits. Typically, the CRC uses a CRC-32 check. In other specific applications, the 32 first type bits are 32 reserved bits, referred to as RES. The 6 second type bits are a multi block alignment signal (MBAS).

[0010] In some possible implementations, d is added to the second bit set. pad After obtaining a third bit set by using the padding bits, and before performing a second FEC encoding on the third bit set to obtain a fourth bit set, the method further includes: performing a first interleaving on the third bit set. The transmission of error correlation between the inner code encoding and the outer code encoding can be reduced, and burst errors can be more effectively resisted.

[0011] In some possible implementations, performing a first interleaving on the third bit set includes: delaying bits from the third bit set according to P delay lines. P is an integer greater than 1, and each delay line includes a different number of storage units. The delay line with the smallest number of storage units includes 0 storage units, and the difference in the number of storage units between each two adjacent delay lines is Q. Each storage unit is used to store d bits, and the input bits are sequentially input into the P delay lines according to the sequence numbers of the P delay lines. Each delay line inputs d bits at a time and outputs d bits at a time. After convolution interleaving, the continuous P×d bits output include d bits output by each delay line, and Q and d are both integers greater than or equal to 1. This implementation provides a specific implementation method for the first interleaving, that is, it is implemented by convolution interleaving, which has a good practical effect.

[0012] In some possible implementations, the fourth bit set includes R codewords, each of which has a length of N bits, each of which includes K information bits, R, N, and K are all integers greater than 1, N is greater than K, and the third bit set includes R×K bits, R×K=261086×L+d pad , K is an integer multiple of d, P×d is an integer multiple of K, is an integer multiple of P. In this implementation, the length of the third bit set is an integer multiple of the information bit length K of the inner code encoding, which facilitates rapid outer code synchronization after inner code synchronization, making hardware implementation simple and less complex.

[0013] In some possible implementations, the third bit set after the first interleaving includes R rows and K columns of bits, and the K bits in each row of the third bit set after the first interleaving are K bits output by a delay line. Performing a second FEC encoding on the third bit set to obtain a fourth bit set includes: performing the second FEC encoding on the K bits in each row of the third bit set after the first interleaving to obtain N bits of each codeword in the fourth bit set. In this way, before performing convolution interleaving on the data in the third bit set, the switches of the convolution interleaver input and output are initialized to delay line 0. When all the data in the third bit set is input into the convolution interleaver, the switches of the convolution interleaver input and output are returned to delay line 0, which facilitates the synchronization of the deconvolution interleaver at the receiving end and simplifies the hardware implementation. Typically, K=d, and R is an integer multiple of P, which makes the data processing flow simpler and the hardware implementation complexity low.

[0014] In some possible implementations, the second FEC coding uses BCH coding or extended BCH coding, which improves the performance of cascade coding.

[0015] In some possible implementations, d is added to the second bit set. pad After obtaining a third bit set by using a filling bit, and before performing a second FEC encoding on the third bit set to obtain a fourth bit set, the method further includes: scrambling the third bit set, so that 0 and 1 in the scrambled bit data are more likely to be equal, so that the DC is balanced, which is conducive to reception at the receiving end.

[0016] In some possible implementations, after performing the second FEC encoding on the third bit set to obtain the fourth bit set, the method further includes: performing data processing on the fourth bit set. The data processing includes symbol mapping, second interleaving, polarization division, and framing processing.

[0017] In some possible implementations, the fourth bit set includes R codewords, each of which has a length of N bits, each of which includes K information bits, R, N and K are integers greater than 1, and N is greater than K. K = 113, N = 127, or K = 113, N = 128, or K = 112, N = 128, or K = 110, N = 126, or K = 119, N = 136, or K = 119, N = 135. The several inner code encoding schemes provided in this implementation adopt a low order of finite fields, which is convenient for hardware implementation.

[0018] In some possible implementations, K=113, N=127, r and d pad One of the following conditions is met:

[0019] r=119,d pad =1074;

[0020] r=238,d pad =340;

[0021] r=357,d pad =1414;

[0022] r=476,d pad =680;

[0023] r=595,d pad =1754;

[0024] r=714,d pad =1020;

[0025] r=833,d pad =286;

[0026] r=952,d pad =1360;

[0027] r=1071,d pad =626;

[0028] r=1190,d pad =1700;

[0029] r = 1309, d pad =966;

[0030] r = 1428, d pad =232;

[0031] r = 1547, d pad =1306;

[0032] r = 1666, d pad=572;

[0033] r = 1785, d pad =1646;

[0034] r = 1904, d pad =912;

[0035] r = 2023, d pad =178;

[0036] r = 2142, d pad =1252;

[0037] r=2261,d pad =518;

[0038] r=2380,d pad =1592.

[0039] In some possible implementations, K=113, N=128, r and d pad Satisfy one of the following conditions: r = 119, d pad =1074;

[0040] r=238,d pad =340;

[0041] r=357,d pad =1414;

[0042] r=476,d pad =680;

[0043] r=595,d pad =1754;

[0044] r=714,d pad =1020;

[0045] r=833,d pad =286;

[0046] r = 952, d pad =1360;

[0047] r=1071,d pad =626;

[0048] r=1190,d pad =1700;

[0049] r = 1309, d pad =966;

[0050] r = 1428, d pad =232;

[0051] r = 1547, d pad =1306;

[0052] r = 1666, d pad =572;

[0053] r = 1785, d pad =1646;

[0054] r = 1904, d pad =912;

[0055] r = 2023, d pad =178;

[0056] r = 2142, d pad =1252;

[0057] r=2261,d pad =518;

[0058] r=2380,d pad =1592.

[0059] In some possible implementations, K=112, N=128, r and d pad Satisfy one of the following conditions: r = 119, d pad =546;

[0060] r=238,d pad =1092;

[0061] r=357,d pad =1638;

[0062] r=476,d pad =392;

[0063] r=595,d pad =938;

[0064] r=714,d pad =1484;

[0065] r=833,d pad =238;

[0066] r=952,d pad =784;

[0067] r=1071,d pad =1330;

[0068] r=1190,d pad =84;

[0069] r = 1309, d pad =630;

[0070] r = 1428, d pad =1176;

[0071] r = 1547, d pad =1722;

[0072] r = 1666, d pad =476;

[0073] r = 1785, d pad =1022;

[0074] r = 1904, d pad =1568;

[0075] r = 2023, d pad =322;

[0076] r = 2142, d pad =868;

[0077] r=2261,d pad =1414;

[0078] r=2380,d pad =168.

[0079] In some possible implementations, K=110, N=126, r and d pad Satisfy one of the following conditions: r = 119, d pad =1154;

[0080] r=238,d pad 548;

[0081] r=357,d pad =1702;

[0082] r=476,d pad =1096;

[0083] r=595,d pad =490;

[0084] r=714,d pad =1644;

[0085] r=833,d pad =1038;

[0086] r=952,d pad =432;

[0087] r=1071,d pad =1586;

[0088] r=1190,d pad =980;

[0089] r = 1309, d pad =374;

[0090] r = 1428, d pad =1528;

[0091] r = 1547, d pad =922;

[0092] r = 1666, d pad =316;

[0093] r = 1785, d pad =1470;

[0094] r = 1904, d pad =864;

[0095] r = 2023, d pad =258;

[0096] r = 2142, d pad =1412;

[0097] r=2261,d pad =806;

[0098] r=2380,d pad =200.

[0099] In some possible implementations, K=119, N=136, r and d pad Satisfy one of the following conditions: r = 119, d pad =1666;

[0100] r=238,d pad =1428;

[0101] r=357,d pad =1190;

[0102] r=476,d pad =952;

[0103] r=595,d pad =714;

[0104] r=714,d pad =476;

[0105] r=833,dpad =238;

[0106] r=952,d pad =1904;

[0107] r=1071,d pad =1666;

[0108] r=1190,d pad =1428;

[0109] r = 1309, d pad =1190;

[0110] r = 1428, d pad =952;

[0111] r = 1547, d pad =714;

[0112] r = 1666, d pad =476;

[0113] r = 1785, d pad =238;

[0114] r = 1904, d pad =0;

[0115] r = 2023, d pad =1666;

[0116] r = 2142, d pad =1428;

[0117] r=2261,d pad =1190;

[0118] r=2380,d pad =952.

[0119] In some possible implementations, K=119, N=135, r and d pad Satisfy one of the following conditions: r = 119, d pad =1666;

[0120] r=238,d pad =1428;

[0121] r=357,d pad =1190;

[0122] r=476,d pad =952;

[0123] r=595,d pad=714;

[0124] r=714,d pad =476;

[0125] r=833,d pad =238;

[0126] r=952,d pad =1904;

[0127] r=1071,d pad =1666;

[0128] r=1190,d pad =1428;

[0129] r=1309,d pad =1190;

[0130] r=1428,d pad =952;

[0131] r=1547,d pad =714;

[0132] r=1666,d pad =476;

[0133] r=1785,d pad =238;

[0134] r=1904,d pad =0;

[0135] r=2023,d pad =1666;

[0136] r=2142,d pad =1428;

[0137] r=2261,d pad =1190;

[0138] r=2380,d pad =952。

[0139] In a second aspect, an embodiment of the present application provides a data processing device. The data processing device includes: an acquisition unit, a first encoding unit, a padding unit, and a second encoding unit. The acquisition unit is used to: acquire a first bit set, the first bit set includes d1 bits, d1=244664×L, and L is a positive integer. The first encoding unit is used to: perform a first forward error correction FEC encoding on the first bit set to obtain a second bit set, the second bit set includes d2 bits, and every 244664 bits in the first bit set are encoded by the first FEC to obtain every 261086 bits in the second bit set, d2=261086×L. The padding unit is used to: add d to the second bit set. pad The third bit set is obtained by adding padding bits, d pad is an integer greater than or equal to 0. The second encoding unit is used for: performing a second FEC encoding on the third bit set to obtain a fourth bit set.

[0140] In this implementation, the first FEC encoding (outer code encoding) is performed with 244664 bits as the granularity, and the number of bits in the first bit set d1=244664×L is also a multiple of 244664, so that it has a better implementation effect, is easy to implement in hardware, and has lower complexity. On this basis, the performance of cascade coding is improved by adopting an inner code encoding with a higher gain. At the same time, by designing a specific data processing method, it is better compatible with DP-16QAM and DP-QPSK modulation, which is conducive to the application in the future 1.6T-ZR scenario using DP-16QAM and 800G high baud rate long-distance transmission scenarios using DP-QPSK.

[0141] In some possible implementations, the d1 bits in the first bit set are distributed as r rows and 2056 columns, r=119×L, and the bits to be encoded use a bit matrix distributed in rows and columns, which has a better practical effect. Using 2056 columns is smaller than the existing 10280 columns, which is more conducive to the expansion of future solutions.

[0142] In some possible implementations, every 261086 bits in the second bit set are distributed into 119 rows and 2194 columns, and the first 2056 columns of the 2194 columns are used to carry the 244664 bits in the first bit set. Since the first 2056 columns of every 119 rows, a total of 2056×119=244664 bits, just carry the 244664 payload bits in the outer code encoding, this processing method has better data matching, making the hardware implementation simple and less complex.

[0143] In some possible implementations, each 261086 bits in the second bit set include 244664 bits in the first bit set, the 32 first type bits, the 6 second type bits, and 16384 check bits of the first FEC code. In some specific applications, the 32 first type bits are obtained by performing CRC on the 244664 payload bits. Typically, the CRC uses a CRC-32 check. In other specific applications, the 32 first type bits are 32 reserved bits, referred to as RES. The 6 second type bits are MBAS.

[0144] In some possible implementations, the data processing device further includes an interleaving unit that adds d to the second bit set. pad After the third bit set is obtained by using the filling bits, before the third bit set is subjected to the second FEC encoding to obtain the fourth bit set, the interleaving unit is used to: perform the first interleaving on the third bit set. The transmission of error correlation between the inner code encoding and the outer code encoding can be reduced, and burst errors can be more effectively resisted.

[0145] In some possible implementations, the interleaving unit is specifically used to: delay bits from the third bit set according to P delay lines. P is an integer greater than 1, and each delay line includes a different number of storage units. The delay line with the smallest number of storage units includes 0 storage units, and the difference in the number of storage units between each two adjacent delay lines is Q. Each storage unit is used to store d bits, and the input bits are sequentially input into the P delay lines according to the sequence numbers of the P delay lines. Each delay line inputs d bits at a time and outputs d bits at a time. After convolution interleaving, the continuous P×d bits output include d bits output by each delay line, and Q and d are both integers greater than or equal to 1. This implementation provides a specific implementation method of the first interleaving, that is, it is implemented by convolution interleaving, which has a good practical effect.

[0146] In some possible implementations, the fourth bit set includes R codewords, each of which has a length of N bits, each of which includes K information bits, R, N, and K are all integers greater than 1, N is greater than K, and the third bit set includes R×K bits, R×K=261086×L+d pad , K is an integer multiple of d, P×d is an integer multiple of K, is an integer multiple of P. In this implementation, the length of the third bit set is an integer multiple of the information bit length K of the inner code encoding, which facilitates rapid outer code synchronization after inner code synchronization, making hardware implementation simple and less complex.

[0147] In some possible implementations, the third bit set after the first interleaving includes R rows and K columns of bits, and the K bits in each row of the third bit set after the first interleaving are K bits output by a delay line. Performing a second FEC encoding on the third bit set to obtain a fourth bit set includes: performing the second FEC encoding on the K bits in each row of the third bit set after the first interleaving to obtain N bits of each codeword in the fourth bit set. In this way, before performing convolution interleaving on the data in the third bit set, the switches of the convolution interleaver input and output are initialized to delay line 0. When all the data in the third bit set is input into the convolution interleaver, the switches of the convolution interleaver input and output are returned to delay line 0, which facilitates the synchronization of the deconvolution interleaver at the receiving end and simplifies the hardware implementation. Typically, K=d, and R is an integer multiple of P, which makes the data processing flow simpler and the hardware implementation complexity low.

[0148] In some possible implementations, the second FEC coding uses BCH coding or extended BCH coding, which improves the performance of cascade coding.

[0149] In some possible implementations, the data processing device further includes a scrambling unit that adds d pad After a third bit set is obtained by performing a second FEC encoding on the third bit set to obtain a fourth bit set, the scrambling unit is used to scramble the third bit set so that 0 and 1 in the scrambled bit data tend to have an equal probability, so that the DC is balanced, which is conducive to reception at the receiving end.

[0150] In some possible implementations, the data processing device further includes a data processing unit, and after performing the second FEC encoding on the third bit set to obtain a fourth bit set, the data processing unit is used to perform data processing on the fourth bit set. The data processing includes symbol mapping, second interleaving, polarization division, and framing processing.

[0151] In some possible implementations, the fourth bit set includes R codewords, each of which has a length of N bits, each of which includes K information bits, R, N and K are integers greater than 1, and N is greater than K. K = 113, N = 127, or K = 113, N = 128, or K = 112, N = 128, or K = 110, N = 126, or K = 119, N = 136, or K = 119, N = 135. The several inner code encoding schemes provided in this implementation adopt a low order of finite fields, which is convenient for hardware implementation.

[0152] In some possible implementations, K=113, N=127, r and dpad One of the following conditions is met:

[0153] r=119,d pad =1074;

[0154] r=238,d pad =340;

[0155] r=357,d pad =1414;

[0156] r=476,d pad =680;

[0157] r=595,d pad =1754;

[0158] r=714,d pad =1020;

[0159] r=833,d pad =286;

[0160] r=952,d pad =1360;

[0161] r=1071,d pad =626;

[0162] r=1190,d pad =1700;

[0163] r = 1309, d pad =966;

[0164] r = 1428, d pad =232;

[0165] r = 1547, d pad =1306;

[0166] r = 1666, d pad =572;

[0167] r = 1785, d pad =1646;

[0168] r = 1904, d pad =912;

[0169] r = 2023, d pad =178;

[0170] r = 2142, d pad =1252;

[0171] r=2261,dpad =518;

[0172] r=2380,d pad =1592.

[0173] In some possible implementations, K=113, N=128, r and d pad One of the following conditions is met:

[0174] r=119,d pad =1074;

[0175] r=238,d pad =340;

[0176] r=357,d pad =1414;

[0177] r=476,d pad =680;

[0178] r=595,d pad =1754;

[0179] r=714,d pad =1020;

[0180] r=833,d pad =286;

[0181] r=952,d pad =1360;

[0182] r=1071,d pad =626;

[0183] r=1190,d pad =1700;

[0184] r = 1309, d pad =966;

[0185] r = 1428, d pad =232;

[0186] r = 1547, d pad =1306;

[0187] r = 1666, d pad =572;

[0188] r = 1785, d pad =1646;

[0189] r = 1904, d pad =912;

[0190] r = 2023, d pad =178;

[0191] r = 2142, d pad =1252;

[0192] r=2261,d pad =518;

[0193] r=2380,d pad =1592.

[0194] In some possible implementations, K=112, N=128, r and d pad Satisfy one of the following conditions: r = 119, d pad =546;

[0195] r=238,d pad =1092;

[0196] r=357,d pad =1638;

[0197] r=476,d pad =392;

[0198] r=595,d pad =938;

[0199] r=714,d pad =1484;

[0200] r=833,d pad =238;

[0201] r = 952, d pad =784;

[0202] r=1071,d pad =1330;

[0203] r=1190,d pad =84;

[0204] r = 1309, d pad =630;

[0205] r = 1428, d pad =1176;

[0206] r = 1547, d pad =1722;

[0207] r = 1666, d pad =476;

[0208] r = 1785, d pad =1022;

[0209] r = 1904, d pad =1568;

[0210] r = 2023, d pad =322;

[0211] r = 2142, d pad =868;

[0212] r=2261,d pad =1414;

[0213] r=2380,d pad =168.

[0214] In some possible implementations, K=110, N=126, r and d pad Satisfy one of the following conditions: r = 119, d pad =1154;

[0215] r=238,d pad 548;

[0216] r=357,d pad =1702;

[0217] r=476,d pad =1096;

[0218] r=595,d pad =490;

[0219] r=714,d pad =1644;

[0220] r=833,d pad =1038;

[0221] r=952,d pad =432;

[0222] r=1071,d pad =1586;

[0223] r=1190,d pad =980;

[0224] r = 1309, d pad =374;

[0225] r = 1428, d pad =1528;

[0226] r = 1547, dpad =922;

[0227] r = 1666, d pad =316;

[0228] r = 1785, d pad =1470;

[0229] r = 1904, d pad =864;

[0230] r = 2023, d pad =258;

[0231] r = 2142, d pad =1412;

[0232] r=2261,d pad =806;

[0233] r=2380,d pad =200.

[0234] In some possible implementations, K=119, N=136, r and d pad One of the following conditions is met:

[0235] r=119,d pad =1666;

[0236] r=238,d pad =1428;

[0237] r=357,d pad =1190;

[0238] r=476,d pad =952;

[0239] r=595,d pad =714;

[0240] r=714,d pad =476;

[0241] r=833,d pad =238;

[0242] r = 952, d pad =1904;

[0243] r=1071,d pad =1666;

[0244] r=1190,d pad =1428;

[0245] r = 1309, d pad =1190;

[0246] r = 1428, d pad =952;

[0247] r = 1547, d pad =714;

[0248] r = 1666, d pad =476;

[0249] r = 1785, d pad =238;

[0250] r = 1904, d pad =0;

[0251] r = 2023, d pad =1666;

[0252] r = 2142, d pad =1428;

[0253] r=2261,d pad =1190;

[0254] r=2380,d pad =952.

[0255] In some possible implementations, K=119, N=135, r and d pad One of the following conditions is met:

[0256] r=119,d pad =1666;

[0257] r=238,d pad =1428;

[0258] r=357,d pad =1190;

[0259] r=476,d pad =952;

[0260] r=595,d pad =714;

[0261] r=714,d pad =476;

[0262] r=833,d pad =238;

[0263] r = 952, d pad =1904;

[0264] r=1071,d pad =1666;

[0265] r=1190,d pad =1428;

[0266] r = 1309, d pad =1190;

[0267] r = 1428, d pad =952;

[0268] r = 1547, d pad =714;

[0269] r = 1666, d pad =476;

[0270] r = 1785, d pad =238;

[0271] r = 1904, d pad =0;

[0272] r = 2023, d pad =1666;

[0273] r = 2142, d pad =1428;

[0274] r=2261,d pad =1190;

[0275] r=2380,d pad =952.

[0276] In a third aspect, an embodiment of the present application provides a data processing device, which includes a processor. The processor is used to perform the following operations. First, obtain a first bit set, wherein the first bit set includes d1 bits, d1=244664×L, and L is a positive integer. Afterwards, perform a first forward error correction (FEC) encoding on the first bit set to obtain a second bit set, wherein the second bit set includes d2 bits, and every 244664 bits in the first bit set are encoded by the first FEC to obtain every 261086 bits in the second bit set, d2=261086×L. Next, add d to the second bit set. pad The third bit set is obtained by adding padding bits, d pad is an integer greater than or equal to 0. Further, the third bit set is subjected to a second FEC encoding to obtain a fourth bit set.

[0277] In this implementation, the first FEC encoding (outer code encoding) is performed with 244664 bits as the granularity, and the number of bits in the first bit set d1=244664×L is also a multiple of 244664, so that it has a better implementation effect, is easy to implement in hardware, and has lower complexity. On this basis, the performance of cascade coding is improved by adopting an inner code encoding with a higher gain. At the same time, by designing a specific data processing method, it is better compatible with DP-16QAM and DP-QPSK modulation, which is conducive to the application in the future 1.6T-ZR scenario using DP-16QAM and 800G high baud rate long-distance transmission scenarios using DP-QPSK.

[0278] In some possible implementations, the d1 bits in the first bit set are distributed as r rows and 2056 columns, r=119×L, and the bits to be encoded use a bit matrix distributed in rows and columns, which has a better practical effect. Using 2056 columns is smaller than the existing 10280 columns, which is more conducive to the expansion of future solutions.

[0279] In some possible implementations, every 261086 bits in the second bit set are distributed into 119 rows and 2194 columns, and the first 2056 columns of the 2194 columns are used to carry the 244664 bits in the first bit set. Since the first 2056 columns of every 119 rows, a total of 2056×119=244664 bits, just carry the 244664 payload bits in the outer code encoding, this processing method has better data matching, making the hardware implementation simple and less complex.

[0280] In some possible implementations, each 261086 bits in the second bit set include 244664 bits in the first bit set, the 32 first type bits, the 6 second type bits, and 16384 check bits of the first FEC code. In some specific applications, the 32 first type bits are obtained by performing CRC on the 244664 payload bits. Typically, the CRC uses a CRC-32 check. In other specific applications, the 32 first type bits are 32 reserved bits, referred to as RES. The 6 second type bits are MBAS.

[0281] In some possible implementations, d is added to the second bit set. pad After obtaining a third bit set by using the padding bits, and before performing the second FEC encoding on the third bit set to obtain a fourth bit set, the processor is further configured to: perform a first interleaving on the third bit set. The transmission of error correlation between the inner code encoding and the outer code encoding can be reduced, and burst errors can be more effectively resisted.

[0282] In some possible implementations, the processor is specifically used to: delay bits from the third bit set according to P delay lines. P is an integer greater than 1, and each delay line includes a different number of storage units. The delay line with the smallest number of storage units includes 0 storage units, and the difference in the number of storage units between each two adjacent delay lines is Q. Each storage unit is used to store d bits, and the input bits are sequentially input into the P delay lines according to the sequence numbers of the P delay lines. Each delay line inputs d bits at a time and outputs d bits at a time. After convolution interleaving, the continuous P×d bits output include d bits output by each delay line, and Q and d are both integers greater than or equal to 1. This implementation provides a specific implementation method for the first interleaving, that is, it is implemented by convolution interleaving, which has a good practical effect.

[0283] In some possible implementations, the fourth bit set includes R codewords, each of which has a length of N bits, each of which includes K information bits, R, N, and K are all integers greater than 1, N is greater than K, and the third bit set includes R×K bits, R×K=261086×L+d pad , K is an integer multiple of d, P×d is an integer multiple of K, is an integer multiple of P. In this implementation, the length of the third bit set is an integer multiple of the information bit length K of the inner code encoding, which facilitates rapid outer code synchronization after inner code synchronization, making hardware implementation simple and less complex.

[0284] In some possible implementations, the third bit set after the first interleaving includes R rows and K columns of bits, and the K bits in each row of the third bit set after the first interleaving are K bits output by a delay line. Performing a second FEC encoding on the third bit set to obtain a fourth bit set includes: performing the second FEC encoding on the K bits in each row of the third bit set after the first interleaving to obtain N bits of each codeword in the fourth bit set. In this way, before performing convolution interleaving on the data in the third bit set, the switches of the convolution interleaver input and output are initialized to delay line 0. When all the data in the third bit set is input into the convolution interleaver, the switches of the convolution interleaver input and output are returned to delay line 0, which facilitates the synchronization of the deconvolution interleaver at the receiving end and simplifies the hardware implementation. Typically, K=d, and R is an integer multiple of P, which makes the data processing flow simpler and the hardware implementation complexity low.

[0285] In some possible implementations, the second FEC coding uses BCH coding or extended BCH coding, which improves the performance of cascade coding.

[0286] In some possible implementations, d is added to the second bit set. pad After obtaining a third bit set by using a filling bit, and before performing a second FEC encoding on the third bit set to obtain a fourth bit set, the processor is further configured to: scramble the third bit set, so that 0 and 1 in the scrambled bit data are more likely to be equal, so that the DC is balanced, which is conducive to reception at the receiving end.

[0287] In some possible implementations, after performing the second FEC encoding on the third bit set to obtain the fourth bit set, the processor is further configured to: perform data processing on the fourth bit set. The data processing includes symbol mapping, second interleaving, polarization division, and framing processing. The data processing device further includes an interface circuit, and the interface circuit is configured to send a data frame obtained after performing data processing on the fourth bit set.

[0288] In some possible implementations, the fourth bit set includes R codewords, each of which has a length of N bits, each of which includes K information bits, R, N and K are integers greater than 1, and N is greater than K. K = 113, N = 127, or K = 113, N = 128, or K = 112, N = 128, or K = 110, N = 126, or K = 119, N = 136, or K = 119, N = 135. The several inner code encoding schemes provided in this implementation adopt a low order of finite fields, which is convenient for hardware implementation.

[0289] In some possible implementations, K=113, N=127, r and d pad One of the following conditions is met:

[0290] r=119,d pad =1074;

[0291] r=238,d pad =340;

[0292] r=357,d pad =1414;

[0293] r=476,d pad =680;

[0294] r=595,d pad =1754;

[0295] r=714,d pad =1020;

[0296] r=833,d pad =286;

[0297] r=952,dpad =1360;

[0298] r=1071,d pad =626;

[0299] r=1190,d pad =1700;

[0300] r = 1309, d pad =966;

[0301] r = 1428, d pad =232;

[0302] r = 1547, d pad =1306;

[0303] r = 1666, d pad =572;

[0304] r = 1785, d pad =1646;

[0305] r = 1904, d pad =912;

[0306] r = 2023, d pad =178;

[0307] r = 2142, d pad =1252;

[0308] r=2261,d pad =518;

[0309] r=2380,d pad =1592.

[0310] In some possible implementations, K=113, N=128, r and d pad One of the following conditions is met:

[0311] r=119,d pad =1074;

[0312] r=238,d pad =340;

[0313] r=357,d pad =1414;

[0314] r=476,d pad =680;

[0315] r=595,d pad =1754;

[0316] r=714,d pad =1020;

[0317] r=833,d pad =286;

[0318] r=952,d pad =1360;

[0319] r=1071,d pad =626;

[0320] r=1190,d pad =1700;

[0321] r = 1309, d pad =966;

[0322] r = 1428, d pad =232;

[0323] r = 1547, d pad =1306;

[0324] r = 1666, d pad =572;

[0325] r = 1785, d pad =1646;

[0326] r = 1904, d pad =912;

[0327] r = 2023, d pad =178;

[0328] r = 2142, d pad =1252;

[0329] r=2261,d pad =518;

[0330] r=2380,d pad =1592.

[0331] In some possible implementations, K=112, N=128, r and d pad Satisfy one of the following conditions: r = 119, d pad =546;

[0332] r=238,d pad =1092;

[0333] r=357,d pad =1638;

[0334] r=476,d pad =392;

[0335] r=595,d pad =938;

[0336] r=714,d pad =1484;

[0337] r=833,d pad =238;

[0338] r = 952, d pad =784;

[0339] r=1071,d pad =1330;

[0340] r=1190,d pad =84;

[0341] r = 1309, d pad =630;

[0342] r = 1428, d pad =1176;

[0343] r = 1547, d pad =1722;

[0344] r = 1666, d pad =476;

[0345] r = 1785, d pad =1022;

[0346] r = 1904, d pad =1568;

[0347] r = 2023, d pad =322;

[0348] r = 2142, d pad =868;

[0349] r=2261,d pad =1414;

[0350] r=2380,d pad =168.

[0351] In some possible implementations, K=110, N=126, r and d pad Satisfy one of the following conditions: r = 119, d pad =1154;

[0352] r=238,dpad 548;

[0353] r=357,d pad =1702;

[0354] r=476,d pad =1096;

[0355] r=595,d pad =490;

[0356] r=714,d pad =1644;

[0357] r=833,d pad =1038;

[0358] r=952,d pad =432;

[0359] r=1071,d pad =1586;

[0360] r=1190,d pad =980;

[0361] r=1309,d pad =374;

[0362] r=1428,d pad =1528;

[0363] r=1547,d pad =922;

[0364] r=1666,d pad =316;

[0365] r=1785,d pad =1470;

[0366] r=1904,d pad =864;

[0367] r=2023,d pad =258;

[0368] r=2142,d pad =1412;

[0369] r=2261,d pad =806;

[0370] r=2380,d pad =200。

[0371] In some possible implementations, K=119, N=136, r and d pad Satisfy one of the following conditions: r = 119, d pad =1666;

[0372] r=238,d pad =1428;

[0373] r=357,d pad =1190;

[0374] r=476,d pad =952;

[0375] r=595,d pad =714;

[0376] r=714,d pad =476;

[0377] r=833,d pad =238;

[0378] r=952,d pad =1904;

[0379] r=1071,d pad =1666;

[0380] r=1190,d pad =1428;

[0381] r = 1309, d pad =1190;

[0382] r = 1428, d pad =952;

[0383] r = 1547, d pad =714;

[0384] r = 1666, d pad =476;

[0385] r = 1785, d pad =238;

[0386] r = 1904, d pad =0;

[0387] r = 2023, d pad =1666;

[0388] r = 2142, d pad =1428;

[0389] r=2261,dpad =1190;

[0390] r=2380,d pad =952.

[0391] In some possible implementations, K=119, N=135, r and d pad One of the following conditions is met:

[0392] r=119,d pad =1666;

[0393] r=238,d pad =1428;

[0394] r=357,d pad =1190;

[0395] r=476,d pad =952;

[0396] r=595,d pad =714;

[0397] r=714,d pad =476;

[0398] r=833,d pad =238;

[0399] r = 952, d pad =1904;

[0400] r=1071,d pad =1666;

[0401] r=1190,d pad =1428;

[0402] r = 1309, d pad =1190;

[0403] r = 1428, d pad =952;

[0404] r = 1547, d pad =714;

[0405] r = 1666, d pad =476;

[0406] r = 1785, d pad =238;

[0407] r = 1904, d pad =0;

[0408] r = 2023, d pad =1666;

[0409] r = 2142, d pad =1428;

[0410] r=2261,d pad =1190;

[0411] r=2380,d pad =952.

[0412] In a fourth aspect, an embodiment of the present application provides an optical module, which includes a processor, and the processor is used to execute the method described in any implementation manner of the first aspect.

[0413] In some possible implementations, the optical module further includes an interface circuit, and the processor performs data processing including symbol mapping, second interleaving, polarization division, and framing processing on the fourth bit set to obtain a data frame, and then sends the data frame through the interface circuit.

[0414] In a fifth aspect, an embodiment of the present application provides a chip, which includes a processor, and the processor is used to execute the method introduced in any implementation manner of the first aspect.

[0415] In the sixth aspect, an embodiment of the present application provides a data transmission system, which includes a data sending device and a data receiving device, wherein the data sending device is used to execute the method described in any implementation mode of the first aspect and send data to the data receiving device, and the data receiving device is used to perform operations such as decoding the received data.

[0416] In the seventh aspect, an embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a computer, the method described in any implementation manner of the first aspect is implemented.

[0417] It can be seen from the above technical solutions that the embodiments of the present application have the following advantages:

[0418] In this implementation, the first FEC encoding (outer code encoding) is performed with 244664 bits as the granularity, and the number of bits in the first bit set d1=244664×L is also a multiple of 244664, so that it has a better implementation effect, is easy to implement in hardware, and has lower complexity. On this basis, the performance of cascade coding is improved by adopting an inner code encoding with a higher gain. At the same time, by designing a specific data processing method, it is better compatible with DP-16QAM and DP-QPSK modulation, which is conducive to the application in the future 1.6T-ZR scenario using DP-16QAM and 800G high baud rate long-distance transmission scenarios using DP-QPSK. BRIEF DESCRIPTION OF THE DRAWINGS

[0419] Figure 1 A schematic diagram of a communication system used in an embodiment of the present application;

[0420] Figure 2 A schematic diagram of another communication system used in an embodiment of the present application;

[0421] Figure 3 This is a schematic diagram of an implementation of a data processor at the originating end in an embodiment of the present application;

[0422] Figure 4 This is a schematic diagram of another implementation of the originating data processor in the embodiment of the present application;

[0423] Figure 5 Schematic diagram of another implementation of the originating data processor in the embodiment of the present application;

[0424] Figure 6 It is a schematic diagram of another implementation of the originating data processor in the embodiment of the present application;

[0425] Figure 7 A schematic diagram of a flow chart of a data processing method for optical communication provided in an embodiment of the present application;

[0426] Figure 8 This is a schematic diagram of the first bit set in an embodiment of the present application;

[0427] Fig. 9 A schematic diagram of bit distribution of external code encoding in an embodiment of the present application;

[0428] FIG10( a ) is a schematic diagram of a second bit set in an embodiment of the present application;

[0429] FIG10( b ) is another schematic diagram of the second bit set in an embodiment of the present application;

[0430] Fig.11 This is a schematic diagram of a third bit set in an embodiment of the present application;

[0431] Fig.12 Another schematic diagram of the third bit set in the embodiment of the present application;

[0432] FIG13( a ) is a schematic diagram of a first implementation method of convolution interleaving in an embodiment of the present application;

[0433] FIG13( b ) is a schematic diagram of a second implementation method of convolution interleaving in an embodiment of the present application;

[0434] Fig.14 Schematic diagram of an implementation method of performing inner code encoding on a fourth bit set in an embodiment of the present application;

[0435] Fig.15 This is a schematic diagram of another implementation method of the first data processing in the embodiment of the present application;

[0436] Fig.16 This is a schematic diagram of another implementation method of the first data processing in the embodiment of the present application;

[0437] Fig.17 This is a schematic diagram of another implementation method of the first data processing in the embodiment of the present application;

[0438] Fig.18 This is a schematic diagram of another implementation method of the first data processing in the embodiment of the present application;

[0439] Fig.19 This is a schematic diagram of another implementation method of the first data processing in the embodiment of the present application;

[0440] Fig. 20 A schematic diagram of the structure of a data processing device in an embodiment of the present application;

[0441] Fig.21 Another structural diagram of the data processing device in the embodiment of the present application. DETAILED DESCRIPTION

[0442] The application embodiment provides a data processing method and related devices for optical communication, which improves the performance of cascade coding by adopting an inner code with higher gain. At the same time, by designing a specific data processing method, it is better compatible with DP-16QAM and DP-QPSK modulation, which is conducive to application in future 1.6T-ZR scenarios using DP-16QAM and high baud rate long-distance transmission scenarios such as 800G using DP-QPSK.

[0443] It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, rather than to limit a specific order or precedence. It should be understood that the above terms can be interchanged where appropriate, so that the embodiments described in this application can be implemented in a sequence other than the content described in this application. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0444] Figure 1 Schematic diagram of a communication system used in the embodiment of the present application. Figure 1As shown, the communication system includes a transmitting device 01, a transmitting processing module 02, a channel transmission medium 03, a receiving processing module 04 and a receiving device 05. Taking the communication system as a data center network as an example, the transmitting device 01 and the receiving device 05 can be devices such as switches or routers, and the transmitting device 01 is also called a client-side chip (host chip) located at the transmitting end, and the receiving device 05 is also called a client-side chip located at the receiving end, and the channel transmission medium 03 can be an optical fiber. The client-side chip is sometimes also called a client-side device (host device). Among them, the transmitting device 01 and the transmitting processing module 02 can be connected through an attachment unit interface (attachment unit interface, AUI), and the receiving device 05 and the receiving processing module 04 can be connected through the AUI. The transmitting processing module 02 and the receiving processing module 04 can be optical modules (optical modules), electrical modules, connectors (connectors) or other modules that process data during data transmission. For example, the processing module can be an 800G ZR module (800G ZR module, a coherent optical module). Furthermore, the transmitting device 01, the transmitting processing module 02, the channel transmission medium 03, the receiving processing module 04 and the receiving device 05 in the communication system can support bidirectional transmission or unidirectional transmission, which is not specifically limited here.

[0445] Figure 2 FIG. 1 is a schematic diagram of another communication system used in the embodiment of the present application. Figure 2 As shown, at the transmitting end, the information source provides the data stream to be sent; the transmitting data processor receives the data stream and performs data processing including encoding, interleaving, modulation, and DSP framing to obtain a symbol data stream, which is sent to the transmitting signal processor for transmitting signal preprocessing, and reaches the receiving device after being transmitted through the channel. After the receiving device receives the distorted signal caused by noise or other damage in the channel, it is sent to the receiving signal processor for clock synchronization, dispersion compensation and other operations, and then sent to the receiving data processor for frame synchronization, demodulation, deinterleaving, and decoding processing to restore the original data and send it to the destination. Among them, Figure 2 The transmitting data processing and transmitting signal processing shown in can be applied to Figure 1 In the sending end processing module 02 shown, Figure 2 The receiving end data processing and receiving end signal processing shown in can be applied to Figure 1 In the receiving end processing module 04 shown.

[0446] Figure 3 FIG. 1 is a schematic diagram of an implementation of a data processor at the originating end in the embodiment of the present application. Figure 3As shown, the transmitting end data processor obtains the bit data to be encoded from the received data sequence, performs the first data processing including outer code encoding, inserting padding bits, first interleaving, and inner code encoding to obtain the data encoded by the outer code and inner code, and then performs the second data processing including symbol mapping, second interleaving, polarization distribution, and DSP framing. As an example, after the transmitting end data processor obtains the bit data to be encoded, it first performs the first data processing, that is, performs the outer code encoding, inserting padding bits, first interleaving, and inner code encoding in sequence to obtain the data encoded by the outer code and inner code; then, it performs the second data processing, that is, performs the symbol mapping, second interleaving, polarization distribution, and DSP framing in sequence.

[0447] Figure 4 FIG. 2 is another schematic diagram of another implementation of the data processor of the transmitting end in the embodiment of the present application. It should be understood that the operations performed by the data processor of the transmitting end in the actual application include but are not limited to: Figure 3 The operations reflected in Figure 4 As shown in FIG. 1 , before the first interleaving process is performed, the outer code coded data after outer code coding and inserting padding bits may be scrambled. Figure 3 and Figure 4 In the data processing flow introduced, the second interleaving in the second data processing is the interleaving processing performed after the modulation symbol data is obtained by symbol mapping, which is also called symbol interleaving (symbol interleave).

[0448] Figure 5 FIG. 1 is another embodiment of the data processor of the transmitting end in the embodiment of the present application. It should be understood that the execution order of each step in the second data processing can also be flexibly adjusted. Figure 5 As shown, the transmitting end data processor obtains the bit data to be encoded, and first performs the first data processing, that is, sequentially performs outer code encoding, inserts padding bits, scrambles, first interleaving, and inner code encoding to obtain data encoded by the outer code and the inner code; then, the second data processing is performed, that is, sequentially performs the second interleaving, symbol mapping, polarization distribution, and DSP framing.

[0449] Figure 6FIG. 2 is another schematic diagram of another implementation of the data processor at the originating end in the embodiment of the present application. Figure 6 As shown, the transmitting end data processor obtains the bit data to be encoded, and first performs the first data processing, that is, sequentially performs outer code encoding, inserts padding bits, scrambles, first interleaves, and inner code encoding to obtain data encoded by outer codes and inner codes; then, the second data processing is performed, that is, sequentially performs second interleaving, DSP framing, polarization distribution, and symbol mapping.

[0450] It should be noted that if Figure 3 , Figure 4 , Figure 5 The DSP framing operation in the DSP is to insert at least one preset symbol (presetsymbols) such as pilot symbols, training symbols, frame alignment symbols, and reserved symbols into the symbol data obtained after symbol mapping. The multiple pilot symbols inserted in the DSP framing are used for carrier phase recovery, the multiple training symbols are used for link training, and the multiple frame synchronization symbols are used for frame synchronization to obtain the boundary of the DPS frame. Multiple reserved symbols are reserved for other future uses, which can be randomized, or some of them can be fixed for other purposes, such as optical signal to noise ratio (OSNR) measurement and end-to-end (E2E) delay measurement. In some specific applications, the DSP frame obtained by DSP framing contains multiple subframes, and its DSP frame is also called a super-frame or multi-frame.

[0451] It should also be noted that Figure 3 , Figure 4 , Figure 5 The DSP framing operation in the DSP is performed on symbols, and can also be performed as follows Figure 6 In the manner shown, for the data after the second interleaving, DSP framing is performed before symbol mapping according to the adopted symbol mapping rule, such as inserting bits corresponding to at least one preset symbol such as pilot symbols, training symbols, frame synchronization symbols, and reserved symbols, and then performing polarization division and symbol mapping to obtain a DSP frame, which is the same symbol as the DPS frame obtained by DSP framing based on the symbol. It should be understood that other DSP framing methods are not excluded, and this application will not go into details.

[0452] It should also be noted that in some possible scenarios, the above Figure 3-Figure 6 The first interleaving operation in may not be performed (bypassed), that is, the first interleaving is an optional operation, so that the first data processing has a lower latency.

[0453] It should be understood that the "inner" in the inner code and the "outer" in the outer code are distinguished only based on the distance of the execution subject operating the data relative to the channel transmission medium. The execution subject operating the inner code is closer to the channel transmission medium, and the execution subject operating the outer code is farther away from the channel transmission medium. Figure 1 For example, since the transmitting end processing module 02 encodes the data twice before sending it to the channel transmission medium. The data encoded by the transmitting end processing module 02 first is far away from the channel transmission medium, and the data encoded by the transmitting end processing module 02 later is closer to the channel transmission medium. Therefore, the data encoded by the transmitting end processing module 02 first is called data encoded by the outer code, and the data encoded by the transmitting end processing module 02 later is called data encoded by the inner code. Correspondingly, the data decoded by the receiving end processing module 04 first is called data decoded by the inner code, and the data decoded by the receiving end processing module 04 later is called data decoded by the outer code. In a possible implementation, the above-mentioned inner code encoding and outer code encoding are both FEC encoding methods, thereby forming a cascade FEC transmission scheme. For example, the transmitting end data processing module 02 can use staircase (SC) code for outer code encoding, Hamming code for inner code encoding, or Bose-Chaudhuri-Hocquenghem (BCH) code for inner code encoding.

[0454] It should be noted that the above content is an exemplary description of the application scenario of the data processing method provided in the embodiment of the present application, and does not constitute a limitation on the application scenario of the data processing method. It is known to those skilled in the art that as business needs change, its application scenario can be adjusted according to application needs, and the embodiment of the present application does not list them one by one. The following mainly introduces the data processing method applied to the data sending end. The data processing method applied to the receiving end can be understood as the inverse operation of the data processing method of the sending end. On the basis of the determination of the data processing method of the sending end, the data processing method of the receiving end is also clear, and this application will no longer introduce the data processing method of the receiving end in detail.

[0455] Figure 7A flow chart of a data processing method for optical communication provided in an embodiment of the present application. The data processing method includes the following steps, which are described in detail below. It should be understood that, for ease of explanation, the first FEC encoding in the following text can be regarded as the outer code encoding introduced above, and the second FEC encoding in the following text can be regarded as the inner code encoding introduced above, and the following text can be understood based on this.

[0456] 101. Obtain a first bit set to be encoded.

[0457] Figure 8 Schematic diagram of the first bit set in the embodiment of the present application. The first bit set can be obtained from a received data sequence, and the received data sequence can be represented as a data stream, a matrix, or multiple data frames. As an example, Figure 8 , the first bit set is represented in the form of a matrix, the first bit set includes multiple rows of bits, and each row includes q bits, q is a positive integer. Optionally, q is an integer multiple of 257. Usually, Ethernet data frames are encoded with 257 bits as the granularity. q is an integer multiple of 257, which can better adapt to Ethernet data frames. For example, q can be 2056, 4112, 8224 or 10280. From the received data sequence, r rows are obtained each time to obtain a total of q×r bits, that is, the first bit set includes r rows and q columns of bits, that is, r×q bits, and r is a positive integer. It should be understood that the embodiment of the present application is introduced by taking q=2056 as an example, that is, the first bit set includes d1 bits, d1=r×2056, that is, d1 bits are distributed into r rows and 2056 columns, and r=119×L, L is a positive integer.

[0458] 102. Perform a first FEC encoding on the first bit set to obtain a second bit set.

[0459] The first FEC encoding is the outer code encoding introduced above. Specifically, every 244664 payload bits in the first bit set are outer-coded to obtain a total of 244664+32+6+16384=261086 coded bits. That is, every 244664 bits in the first bit set are outer-coded to obtain every 261086 bits in the second bit set, and the second bit set includes d2 bits, d2=261086×L. The 261086 coded bits include 32 first type bits, 6 second type bits, and 16384 outer code coded check bits. The payload can also be called the net load.

[0460] Fig. 9 Schematic diagram of a bit distribution of external code encoding in the embodiment of the present application. Figure 8 As shown, the bits involved in the outer code encoding and the check bits obtained by the outer code encoding can be represented by a matrix. In some specific applications, the 32 first type bits are obtained by performing a cyclic redundancy check (CRC) on 244664 payload bits. Typically, the CRC uses a CRC-32 check. In other specific applications, the 32 first type bits are 32 reserved bits, referred to as RES. The 6 second type bits are multi block alignment signals (MBAS).

[0461] More specifically, 244664 payload bits, 32 first type bits, 6 second type bits and 34 third type bits, a total of 244664+32+6+34=244736 bits, can be expressed as Fig. 9 512 rows and 478 columns in SC code. In some specific applications, 34 third-type bits are all 0 bits. 244736 bits are used as the encoding input of the SC code to obtain 16384 SC code FEC encoding check bits. It should be noted that the 16384 SC code FEC encoding check bits combined with 244736 bits total 261120 bits, which are called SC code codeword bits, which can be expressed as Fig. 9 The 512 rows and 510 columns in the SC code are also called SC code word groups (FEC blocks). The SC code is a convolutional code, and when the SC code generates 16384 FEC code check bits, in addition to using the 244736 bits, it also needs to use the 261120 SC code word bits at the previous moment.

[0462] It should be noted that the 34 third-category bits participate in the SC code encoding but are not transmitted. Therefore, the outer code encodes every 244664 payload bits in the first bit set to obtain 261120-34=261086 encoded bits, i.e., 261086 bits in the second bit set. It should also be noted that the error decorrelator (ED) operation is also performed in the SC code, making the overall FEC scheme more resistant to bursts and having better performance. The MBAS bit can be used for ED state synchronization.

[0463] In some specific applications, operations such as inserting CRC-32 bits, 6 MBAS bits, 34 all-0 bits (not transmitted), SC code, error decorrelation, etc. are also referred to as SC-FEC matching, ED and encoding (SC-FEC adapt, ED & Encoding), which is also referred to as the first FEC encoding or outer code encoding. It should be understood that the number of payload bits corresponding to the outer code encoding is 244664=2056×119. Considering that the first bit set includes r rows and 2056 columns of bits, by selecting r as an integer multiple of 119, that is, r=119×L, the first bit set containing 2056×r bits can be encoded L times by the outer code encoding to obtain a total of 261086×L encoded bits, which is called the second bit set.

[0464] Figure 10(a) is a schematic diagram of the second bit set in an embodiment of the present application. As shown in Figure 10(a), the second bit set can be represented by a multi-row matrix, wherein each row contains 2194 bits, 2056 bits in each row are used to store payload bits, and 138 bits in each row are used to store first type bits, second type bits, and FEC coding check bits of the SC code. It should be noted that the 34 third type bits contained in the SC codeword group (FEC block) are not transmitted, that is, there are no third type bits in the multi-row 2194 column matrix in Figure 10(a). As can be seen from FIG. 10( a ), each 119 rows of the multi-row 2194-column matrix, with a total of 2194×119=261086 bits, just carries 244664 payload bits, 32 first type bits, 6 second type bits and 16384 SC code FEC coding check bits, with a total of 261086 bits, and the first 2056 columns of each 119 rows, with a total of 2056×119=244664 bits, just carries 244664 payload bits in the SC code. Therefore, the processing method has better data matching, makes hardware implementation simple, and has low complexity.

[0465] It should be understood that the 244664 payload bits in one SC code word group are located in 119 rows of the matrix of multiple rows and 2194 columns, and are located in the first 2056 columns of the 119 rows and 2194 columns, that is, the 1st column to the 2056th column in FIG. 10( a ). The 16384 SC code FEC encoding check bits in one SC code word group are located in a group of 119 rows of the matrix of multiple rows and 2194 columns, and are located in the last 138 columns of the 119 rows and 2194 columns, that is, the 2057th column to the 2194th column in FIG. 10( a ).

[0466] FIG10( b ) is another schematic diagram of the second bit set in the embodiment of the present application. It should be noted that the 244664 payload bits and the 16384 SC code FEC coding check bits in an SC code codeword group are not necessarily carried in the same group of 119 rows. As shown in FIG10( b ), a group of 119 rows in a multi-row 2194-column matrix carries an SC codeword group B. j The 244664 payload bits in the SC code and the last SC codeword group (i.e., the codeword group obtained by encoding at the last moment) B j-1 For the convenience of description, it can be understood that a group of 119 rows in the multi-row 2194-column matrix carries one SC codeword block bit. In addition, FIG10( b ) also shows the specific positions of the CRC32 and MBAS bits in the multi-row 2194-column matrix.

[0467] 103. Add padding bits to the second bit set to obtain a third bit set.

[0468] Fig.11 Schematic diagram of the third bit set in the embodiment of the present application. Fig.11 As shown, d is added to the second bit set containing 261086×L bits. pad The third bit set is obtained by adding padding bits, wherein the third bit set includes d3 bits, d3=261086×L+d pad , d pad ≥ 0. Optionally, add d to the second bit set pad After the padding bits, it is necessary to add d pad 261086×L+d after padding bits pad The bits are scrambled so that the probability of 0 and 1 in the scrambled bit data is more equal, making the DC balanced and facilitating reception at the receiving end. pad The padding bits are all zero bits.

[0469] Fig.12 261086×L+d pad =R×K. It should be understood that K can be understood as the information bit length of the inner code (second FEC code). pad is an integer multiple of K, select a suitable d pad The value is selected so that the length of the third bit set is an integer multiple of the information bit length K of the inner code encoding, which facilitates rapid outer code synchronization after inner code synchronization, making hardware implementation simple and less complex.

[0470] It should be noted that for some specific application scenarios, when d pad =0, indicating that the inserting padding bit operation can be omitted (bypassed). In other words, Figure 3 , Figure 4 , Figure 5 , Figure 6 The operation of inserting stuffing bits in the data processing shown is optional.

[0471] 104. Perform a first interleaving on the third bit set to obtain a fourth bit set.

[0472] In a possible implementation, the first interleaving adopts convolution interleaving, which has a lower implementation complexity. Specifically, the third bit set is subjected to convolution interleaving to obtain a fourth bit set, the fourth bit set including d4 bits, d4=d3=261086×L+d pad The following is an introduction to possible implementations of convolutional interleaving.

[0473] FIG. 13(a) is a schematic diagram of the first implementation method of convolution interleaving in an embodiment of the present application. FIG. 13(b) is a schematic diagram of the second implementation method of convolution interleaving in an embodiment of the present application. As shown in FIG. 13(a) and FIG. 13(b), the convolution interleaver includes P delay lines, and the convolution interleaver delays the data in the input third bit set according to the P delay lines to obtain a fourth bit set. Wherein, P is an integer greater than 1, and the number of storage units included in each delay line is different. The delay line with the smallest number of storage units includes 0 storage units, and the difference in the number of storage units of each two adjacent delay lines is Q, and each storage unit is used to store d bits. The bits in the third bit set are sequentially input to the P delay lines according to the sequence numbers of the P delay lines, and each delay line inputs d bits at a time and outputs d bits at a time. The continuous P×d bits output after convolution interleaving include d bits output by each delay line. Wherein, Q is an integer greater than or equal to 1, and d is an integer greater than or equal to 1. For example, P delay lines include 0 storage units, Q storage units, 2Q storage units, ..., (P-1)Q storage units, and each storage unit is used to store d bits. Then, the P delay lines correspond to P delay values, and the delay values ​​include 0 bits, Q×d bits, 2Q×d bits, ..., (P-1)Q×d bits, which can also be understood as the interleaving depth of the convolution interleaver is P. It should be noted that the delay values ​​in this application are counted in bits. The more bits included in the delay value of the delay line, the longer the delay (also called time delay) of the delay line to the data. It should be understood that when the delay line does not include a storage unit, the delay of the delay line is 0 bits, that is, there is no delay in pass-through.

[0474] As shown in FIG13(a), the number of storage units in the P delay lines decreases in sequence according to the sequence numbers of the P delay lines. That is, delay line 0 has (P-1)Q storage units, each delay line decreases by Q storage units in sequence, and delay line P-1 has 0 storage units. As shown in FIG13(b), the number of storage units in the P delay lines increases in sequence according to the sequence numbers of the P delay lines. That is, delay line 0 has 0 storage units, each delay line increases by Q storage units in sequence, and delay line P-1 has (P-1)Q storage units.

[0475] It should be noted that at the same time, the switch of the convolution interleaver input and output is located on the same delay line. After the current delay line inputs d bits at a time and outputs d bits, the switch is switched to the next delay line to ensure that the bits in the first bit set are input to the P delay lines in sequence according to the sequence of the P delay lines. The continuous P×d bits output after convolution interleaving include the d bits output by each delay line. The specific data read and write operations are as follows: read d bits from the storage unit closest to the output port of the current delay line. Transfer the d bits stored in each storage unit in the current delay line to the next storage unit. Then write d bits to the storage unit closest to the input port in the current delay line. After that, switch to the next delay line and repeat the above operations, and so on.

[0476] It should be understood that when the same parameters P, Q and d are used, the convolution interleaving process of FIG. 13(a) and the convolution interleaving process of FIG. 13(b) are the inverse operations of each other. That is, when the transmitting end processing module adopts the convolution interleaving structure shown in FIG. 13(a), the convolution deinterleaving corresponding to the receiving end processing module adopts the structure shown in FIG. 13(b). Similarly, when the transmitting end processing module adopts the convolution interleaving structure shown in FIG. 13(b), the convolution deinterleaving corresponding to the receiving end processing module adopts the structure shown in FIG. 13(a).

[0477] The third bit set is as follows Fig.12 As shown in the example, the fourth bit set also includes R rows and K columns of bits. In a possible scenario, K is an integer multiple of d, P×d is an integer multiple of K, is an integer multiple of P. At this time, the K bits in each row of the fourth bit set are the K bits in the convolution interleaver. K bits output by a delay line. In this way, before the data in the third bit set is convolutionally interleaved, the switches of the convolution interleaver input and output are initialized to delay line 0. When all the data in the third bit set is input into the convolution interleaver, the switches of the convolution interleaver input and output are returned to delay line 0, which facilitates the synchronization of the deconvolution interleaver at the receiving end and simplifies the hardware implementation. Typically, K=d, and R is an integer multiple of P, which makes the data processing flow simpler and the hardware implementation complexity low.

[0478] In some specific embodiments, the convolution interleaver includes P=16 delay lines, two adjacent delay lines differ by Q=2 storage units, and each storage unit includes d=K bits.

[0479] 105. Perform a second FEC encoding on the fourth bit set to obtain a fifth bit set.

[0480] Fig.14 FIG. 1 is a schematic diagram of an implementation method of performing inner code encoding on the fourth bit set in an embodiment of the present application. Fig.14 As shown, the fifth bit set includes R code words encoded by inner code, each code word includes K information bits and NK check bits, a total of N bits, and a total of d5=R×N bits. Taking the fourth bit set including R rows and K columns of bits as an example, the fifth bit set obtained by performing inner code encoding on the fourth bit set includes R rows and N columns of bits. Among them, the N bits in each row of the fifth bit set can be regarded as an inner code code word.

[0481] It should be noted that by selecting an appropriate number of padding bits d pad , which allows insertion of d pad The third bit set after the padding bits is as follows Fig.12 The row and column distribution shown is 261086×L+d pad =R×K. At this time, the number of bits included in the third data set is an integer number of information bits K, which facilitates rapid outer code synchronization after inner code synchronization, making hardware implementation simple and less complex.

[0482] In a possible implementation manner, the inner code encoding in the embodiment of the present application may specifically adopt GF(2 m ) BCH coding or extended BCH coding with at least 2 bits of error correction. Typically, when the length of the inner code word remains unchanged or slightly reduced, the error correction capability of the inner code word is increased to 2 bits, which improves the performance of the cascade coding but keeps the complexity at a low level. GF refers to a finite field, also known as a Galois field, 2 m Represents the order of a finite field.

[0483] Several possible inner code encoding schemes are provided below, where N represents the length of the inner code word and K represents the length of the information bit in the inner code word. The finite field used is of a lower order, which is convenient for hardware implementation.

[0484] (1) The inner code word length is 127 bits, and the inner code information length is 113 bits, such as BCH (127, 113).

[0485] (2) The inner code word length is 128 bits, and the inner code information length is 113 bits, such as BCH (128, 113).

[0486] (3) The inner code word length is 128 bits, and the inner code information length is 112 bits, such as BCH (128, 112).

[0487] (4) The inner code word length is 126 bits, and the inner code information length is 110 bits, such as BCH (126, 110).

[0488] (5) The inner code word length is 136 bits, and the inner code information length is 119 bits, such as BCH (136, 119).

[0489] (6) The inner code word length is 135 bits, and the inner code information length is 119 bits, such as BCH (135, 119).

[0490] It should be noted that after the fifth bit set is obtained through the inner code encoding, a second data processing is performed, that is, operations including symbol mapping, second interleaving, polarization distribution, DSP framing, etc. can be referred to. Figure 3 , Figure 4 , Figure 5 , Figure 6 To understand. Among them, the symbol mapping method includes but is not limited to quadrature phase shift keying (quadrature phase shift keying, QPSK) and quadrature amplitude modulation (quadrature amplitude modulation, QAM), specifically, t bits are symbol mapped to obtain a dual-polarization (dual-polarization, DP) symbol, for example, DP-QPSK, DP-8QAM, DP-16QAM, DP-32QAM and DP-64QAM, etc. Typically, when t = 4, the dual polarization symbol is a DP-QPSK symbol. When t = 8, the dual polarization symbol is a DP-16QAM symbol. The d5 = (261086 × L + d pad) / K×N bits correspond to d5 / t dual polarization symbols. Typically, the d5 / t dual polarization symbols correspond to one DSP frame after the DSP framing. That is, a first bit set of a total of 2056×r bits of r rows is obtained from the received data sequence, and a DSP frame is obtained after the data processing, which is simple to implement and has lower complexity. Here, the d5 / t dual polarization symbols are also called symbols before DSP framing.

[0491] It should be noted that for DP-16QAM modulation, the received data sequence includes r DP-16QAM For DP-QPSK modulation, the first bit set including r is obtained from the received data sequence. DP-QPSK The first bit set of 2056 rows and 1056 columns. DP-16QAM =2×r DP-QPSK By selecting the appropriate number of padding bits d pad The value of can make the number of modulation symbols using DP-16QAM equal to the number of modulation symbols using DP-QPSK modulation, thereby ensuring that the DSP frame structure after the second data processing is the same. In other words, this data processing method can better be compatible with DP-16QAM and DP-QPSK modulation.

[0492] Several specific embodiments are provided below in combination with several different implementations of inner code encoding.

[0493] Embodiment 1: The inner code adopts (127, 113) coding, that is, the inner code codeword length is N=127 bits, and the inner code information length is K=113 bits.

[0494] For example, the inner code uses BCH (127,113), which is constructed on the finite field GF (2 7 ) can correct 2 bits of BCH (127,113) code.

[0495] The received data sequence includes multiple rows of bits, and each row includes q=2056 bits. A first bit set of r rows and q=2056 columns of bits, totaling 2056×r bits, is obtained from the received data sequence. The number of rows r is an integer multiple of 119, that is, r=119×L, where L is a positive integer.

[0496] The first bit set including 2056×r=2056×119×L=244664×L bits is subjected to L times of outer code encoding (first FEC encoding), wherein every 244664 bits in the first bit set are encoded to obtain a total of 261086 encoded bits, and a total of 261086×L encoded bits are obtained, which is called the second bit set. Here, L is also called the number of SC codeword groups.

[0497] Add d to the second bit set containing 261086×L bits pad padding bits, we get 261086×L+d pad Optionally, the third bit set of 261086×L+d pad The bits are scrambled so that the probability of 0 and 1 in the scrambled bit data is more equal, so that the DC is balanced, which is beneficial to the receiving end.

[0498] Then, the third bit set is convolutionally interleaved to obtain a length of 261086×L+d pad bits, wherein the convolution interleaver includes P=16 delay lines, two adjacent delay lines differ by Q=2 storage units, and each storage unit includes d=K bits. And 261086×L+d pad =R×K.

[0499] Then, each K=113 bit in the fourth bit set is encoded to obtain N=127 inner code word bits, and a total of d5=R×N=(261086×L+d pad ) / K×N=(261086×L+d pad ) / 113×127 bits. And perform a second data processing including symbol mapping and polarization division.

[0500] When the symbol mapping adopts DP-16QAM, d5=(261086×L+d pad ) / K×N bits, the number of DP-16QAM symbols corresponding to the fifth bit set is s DP-16QAM =d5 / 8=(261086×L+d pad ) / K×N / 8=(261086×L+d pad ) / 113×127 / 8, where L=r / 119.

[0501] When the symbol mapping adopts DP-QPSK, d5=(261086×L+d pad ) / K×N bits, the number of DP-QPSK symbols corresponding to the fifth bit set is s DP-QPSK =d5 / 4=(261086×L+dpad ) / K×N / 4=(261086×L+d pad ) / 113×127 / 4, where L=r / 119.

[0502] The following table gives some parameter combinations, including the number of rows r, the number of padding bits d pad , the number of bits in the fifth bit set d5, the number of DP-16QAM symbols corresponding to the fifth bit set s DP-16QAM The number of DP-QPSK symbols corresponding to the fifth bit set s DP-QPSK .

[0503] Table 1

[0504]

[0505]

[0506] It should be noted that, the larger the value of the row number r, the larger the number of dual-polarization symbols corresponding to the fifth bit set, and the higher the complexity; however, the larger the number of dual-polarization symbols, the smaller the framing redundancy introduced in DSP framing. The appropriate row number r can be selected according to the requirements of different scenarios to achieve an effective compromise between complexity and framing redundancy.

[0507] The number of rows of the first bit set in the DP-16QAM modulation scenario is represented as r DP-16QAM , the number of rows of the first bit set in the DP-QPSK modulation scenario is represented as r DP-QPSK In order to make the adopted data processing more compatible with DP-16QAM and DP-QPSK modulation, r DP-16QAM For r DP-QPSK 2 times, then s DP-16QAM =s DP-QPSK , so that the DSP frame structure after the second data processing is the same. The following table gives the corresponding parameter combinations.

[0508] Table 2

[0509]

[0510] As an example, in the scenario of DP-QPSK symbol mapping, the number of rows r DP-QPSK =476, the number of padding bits d pad =680, such as Figure 8 The first bit set shown includes r DP-QPSK=476 rows q = 2056 columns bits, the convolution interleaver includes P = 16 delay lines, the difference between two adjacent delay lines is Q = 2 storage units, and each storage unit includes d = K = 113 bits. After the first data processing, the number of the fifth bit set obtained is d5 = 1174496, and the fifth bit set corresponds to the number of DP-QPSK symbols

[0511] As another example, in the scenario of DP-16QAM symbol mapping, the number of rows r DP-16QAM =952, the number of padding bits d pad =1360, such as Figure 8 The first bit set shown includes r DP-16QAM =952 rows q = 2056 columns bits, the convolution interleaver includes P = 16 delay lines, the difference between two adjacent delay lines is Q = 2 storage units, and each storage unit includes d = K = 113 bits. After the first data processing, the number of the fifth bit set obtained is d5 = 2348992, and the fifth bit set corresponds to the number of DP-16QAM symbols

[0512] Embodiment 2: The inner code adopts (128, 113) coding, that is, the inner code codeword length is N=128 bits, and the inner code information length is K=113 bits.

[0513] For example, the inner code uses BCH (128,113), which is constructed on the finite field GF (2 7 ) and single-bit extension, so it can also be recorded as single-bit extended E-BCH (128, 113). It has good error correction resistance and better performance than the inner code BCH (127, 113) in Example 1.

[0514] The received data sequence includes multiple rows of bits, and each row includes q=2056 bits. A first bit set of r rows and q=2056 columns of bits, totaling 2056×r bits, is obtained from the received data sequence. r is an integer multiple of 119, that is, r=119×L, where L is a positive integer.

[0515] The first bit set including 2056×r=2056×119×L=244664×L bits is subjected to L outer code encoding (first FEC encoding), wherein every 244664 bits in the first bit set are encoded to obtain a total of 261086 encoded bits, and a total of 261086×L encoded bits are obtained, which is called the second bit set. Here, L is also called the number of SC codeword groups.

[0516] Add d to the second bit set containing 261086×L bits pad padding bits, resulting in 261086×L+d pad Optionally, 261086×L+d pad The bits are scrambled so that the probability of 0 and 1 in the scrambled bit data is more equal, so that the DC is balanced, which is beneficial to the receiving end.

[0517] Then, the third bit set is convolutionally interleaved to obtain a length of 261086×L+d pad bits, wherein the convolution interleaver includes P=16 delay lines, two adjacent delay lines differ by Q=2 storage units, and each storage unit includes d=K bits. And 261086×L+d pad =R×K.

[0518] Then, each K=113 bits in the fourth bit set are encoded with inner code to obtain N=128 inner code word bits, and a total of d5=R×N=(261086×L+d pad ) / K×N=(261086×L+d pad ) / 113×128 bits. A second data processing including symbol mapping and polarization division is performed.

[0519] When symbol mapping adopts DP-16QAM, d5=(261086×L+d pad ) / K×N bits, the number of DP-16QAM symbols corresponding to the fifth bit set is s DP-16QAM =d5 / 8=(261086×L+d pad ) / K×N / 8=(261086×L+d pad ) / 113×128 / 8=(261086×L+d pad ) / 113×16, where L=r / 119.

[0520] When the symbol mapping adopts DP-QPSK, d5=(261086×L+d pad ) / K×N bits, the number of DP-QPSK symbols corresponding to the fifth bit set is s DP-QPSK =d5 / 4=(261086×L+d pad ) / K×N / 4=(261086×L+d pad ) / 113×128 / 4=(261086×L+d pad ) / 113×32, where L=r / 119.

[0521] The following table gives some parameter combinations, including the number of rows r, the number of padding bits d pad , the number of bits in the fifth bit set d5, the number of DP-16QAM symbols corresponding to the fifth bit set s DP-16QAM The number of DP-QPSK symbols corresponding to the fifth bit set s DP-QPSK .

[0522] Table 3

[0523]

[0524]

[0525] It should be noted that, the larger the value of the row number r, the larger the number of dual-polarization symbols corresponding to the fifth bit set, and the higher the complexity; however, the larger the number of dual-polarization symbols, the smaller the framing redundancy introduced in DSP framing. The appropriate row number r can be selected according to the requirements of different scenarios to achieve an effective compromise between complexity and framing redundancy.

[0526] The number of rows of the first bit set in the DP-16QAM modulation scenario is represented as r DP-16QAM , the number of rows of the first bit set in the DP-QPSK modulation scenario is represented as r DP-QPSK In order to make the adopted data processing more compatible with DP-16QAM and DP-QPSK modulation, r DP-16QAM For r DP-QPSK 2 times, then s DP-16QAM =s DP-QPSK , so that the DSP frame structure after the second data processing is the same. The following table gives the corresponding parameter combinations.

[0527] Table 4

[0528]

[0529] As an example, in the scenario of DP-QPSK symbol mapping, the number of rows r DP-QPSK =238, the number of padding bits d pad =340, such as Figure 8 The first bit set shown includes r DP-QPSK =238 rows q =2056 columns bits, the convolution interleaver includes P = 16 delay lines, the difference between two adjacent delay lines is Q = 2 storage units, and each storage unit includes d = K = 112 bits. The number of the fifth bit set obtained after the first data processing is d5 = 591872, and the fifth bit set corresponds to the number of DP-QPSK symbols

[0530] As another example, in the scenario of DP-16QAM symbol mapping, the number of rows r DP-16QAM =476, the number of padding bits d pad =680, such as Figure 8 The first bit set shown includes r DP-QPSK =476 rows q = 2056 columns bits, the convolution interleaver includes P = 16 delay lines, the difference between two adjacent delay lines is Q = 2 storage units, and each storage unit includes d = K = 112 bits. After the first data processing, the number of the fifth bit set obtained is d5 = 1183744, and the fifth bit set corresponds to the number of DP-16QAM symbols

[0531] Embodiment 3: The inner code adopts (128, 112) coding, that is, the inner code codeword length is N=128 bits, and the inner code information length is K=112 bits.

[0532] For example, the inner code uses BCH (128,112), which is constructed on the finite field GF (2 7 ) and double-bit extension, so it can also be recorded as double-bit extended DE-BCH (128, 112). It has better anti-error correction capability and better performance than the inner code BCH (127, 113) in Example 1 and the BCH (128, 113) in Example 2. In some specific application embodiments, the inner code BCH (128, 112) can also be obtained by first shortening BCH (127, 113) by 1 bit to obtain BCH (126, 112), and then adding 2 bits of extension to obtain double-bit extended DE-BCH (128, 112). No specific limitation is made here.

[0533] The received data sequence includes multiple rows of bits, and each row includes q=2056 bits. A first bit set of r rows and q=2056 columns of bits, totaling 2056×r bits, is obtained from the received data sequence. r is an integer multiple of 119, that is, r=119×L, where L is a positive integer.

[0534] The first bit set including 2056×r=2056×119×L=244664×L bits is subjected to L outer code encoding (first FEC encoding), wherein every 244664 bits in the first bit set are encoded to obtain a total of 261086 encoded bits, and a total of 261086×L encoded bits are obtained, which is called the second bit set. Here, L is also called the number of SC codeword groups.

[0535] Add d to the second bit set containing 261086×L bits padpadding bits, we get 261086×L+d pad Optionally, 261086×L+d pad The bits are scrambled so that the probability of 0 and 1 in the scrambled bit data is more equal, so that the DC is balanced, which is beneficial to the receiving end.

[0536] Then, the third bit set is convolutionally interleaved to obtain a length of 261086×L+d pad bits, wherein the convolution interleaver includes P=16 delay lines, two adjacent delay lines differ by Q=2 storage units, and each storage unit includes d=K bits. And 261086×L+d pad =R×K.

[0537] Then, each K=112 bits in the fourth bit set are encoded with inner code to obtain N=128 inner code word bits, so that a total of d5=R×N=(261086×L+d pad ) / K×N=(261086×L+d pad ) / 112×128 bits. And perform a second data processing including symbol mapping and polarization division.

[0538] When symbol mapping adopts DP-16QAM, d5=(261086×L+d pad ) / K×N bits, the number of DP-16QAM symbols corresponding to the fifth bit set is s DP-16QAM =d5 / 8=(261086×L+d pad ) / K×N / 8=(261086×L+d pad ) / 112×128 / 8=(261086×L+d pad ) / 7, where L=r / 119.

[0539] When the symbol mapping adopts DP-QPSK, d5=(261086×L+d pad ) / K×N bits, the number of DP-QPSK symbols corresponding to the fifth bit set is s DP-QPSK =d5 / 4=(261086×L+d pad ) / K×N / 4=(261086×L+d pad ) / 112×128 / 4=(261086×L+d pad ) / 7×2, where L=r / 119.

[0540] The following table gives some parameter combinations, including the number of rows r, the number of padding bits d pad, the number of bits in the fifth bit set d5, the number of DP-16QAM symbols corresponding to the fifth bit set s DP-16QAM The number of DP-QPSK symbols corresponding to the fifth bit set s DP-QPSK .

[0541] Table 5

[0542] Serial number r <![CDATA[d pad ]]> <![CDATA[d5]]> <![CDATA[s DP-16QAM ]]> <![CDATA[s DP-QPSK ]]> 1 119 546 299008 37376 74752 2 238 1092 598016 74752 149504 3 357 1638 897024 112128 224256 4 476 392 1193984 149248 298496 5 595 938 1492992 186624 373248 6 714 1484 1792000 224000 448000 7 833 238 2088960 261120 522240 8 952 784 2387968 298496 596992 9 1071 1330 2686976 335872 671744 10 1190 84 2983936 372992 745984 11 1309 630 3282944 410368 820736 12 1428 1176 3581952 447744 895488 13 1547 1722 3880960 485120 970240 14 1666 476 4177920 522240 1044480 15 1785 1022 4476928 559616 1119232 16 1904 1568 4775936 596992 1193984 17 2023 322 5072896 634112 1268224 18 2142 868 5371904 671488 1342976 19 2261 1414 5670912 708864 1417728 20 2380 168 5967872 745984 1491968

[0543] It should be noted that, the larger the value of the row number r, the larger the number of dual-polarization symbols corresponding to the fifth bit set, and the higher the complexity; however, the larger the number of dual-polarization symbols, the smaller the framing redundancy introduced in DSP framing. The appropriate row number r can be selected according to the requirements of different scenarios to achieve an effective compromise between complexity and framing redundancy.

[0544] The number of rows of the first bit set in the DP-16QAM modulation scenario is represented as r DP-16QAM , the number of rows of the first bit set in the DP-QPSK modulation scenario is represented as r DP-QPSK In order to make the adopted data processing more compatible with DP-16QAM and DP-QPSK modulation, r DP-16QAM For r DP-QPSK 2 times, then s DP-16QAM =s DP-QPSK , so that the DSP frame structure after the second data processing is the same. The following table gives the corresponding parameter combinations.

[0545] Table 6

[0546]

[0547] As an example, in the scenario of DP-QPSK symbol mapping, the number of rows r DP-QPSK =119, the number of padding bits d pad =546, such as Figure 8 The first bit set shown includes r DP-QPSK =119 rows q = 2056 columns bits, the convolution interleaver includes P = 16 delay lines, the difference between two adjacent delay lines is Q = 2 storage units, and each storage unit includes d = K = 112 bits. After the first data processing, the number of the fifth bit set obtained is d5 = 299008, and the fifth bit set corresponds to the number of DP-QPSK symbols

[0548] As another example, in the scenario of DP-16QAM symbol mapping, the number of rows r DP-16QAM =238, the number of padding bits d pad =1092, such as Figure 8The first bit set shown includes r DP-QPSK =238 rows q =2056 columns bits, the convolution interleaver includes P = 16 delay lines, the difference between two adjacent delay lines is Q = 2 storage units, and each storage unit includes d = K = 112 bits. After the first data processing, the number of the fifth bit set obtained is d5 = 598016, and the fifth bit set corresponds to the number of DP-16QAM symbols

[0549] Embodiment 4: The inner code adopts (126, 110) coding, that is, the inner code codeword length is N=126 bits, and the inner code information length is K=110 bits.

[0550] For example, the inner code uses BCH (126,110), which is constructed on the finite field GF (2 7 ) is first shortened by 3 bits to obtain BCH(124,110), and then double-bit extended by adding odd and even parity checks, so it can also be recorded as double-bit extended DE-BCH(126,110).

[0551] The received data sequence includes multiple rows of bits, and each row includes q=2056 bits. A first bit set of r rows and q=2056 columns of bits, totaling 2056×r bits, is obtained from the received data sequence. r is an integer multiple of 119, that is, r=119×L, where L is a positive integer.

[0552] The first bit set including 2056×r=2056×119×L=244664×L bits is subjected to L outer code encoding (first FEC encoding), wherein every 244664 bits in the first bit set are encoded to obtain a total of 261086 encoded bits, and a total of 261086×L encoded bits are obtained, which is called the second bit set. Here, L is also called the number of SC codeword groups.

[0553] Add d to the second bit set containing 261086×L bits pad padding bits, we get 261086×L+d pad Optionally, 261086×L+d pad The bits are scrambled so that the probability of 0 and 1 in the scrambled bit data is more equal, so that the DC is balanced, which is beneficial to the receiving end.

[0554] Then, the third bit set is convolutionally interleaved to obtain a length of 261086×L+d padbits, wherein the convolution interleaver includes P=16 delay lines, two adjacent delay lines differ by Q=2 storage units, and each storage unit includes d=K bits. And 261086×L+d pad =R×K.

[0555] Then, each K=110 bits in the fourth bit set are encoded with inner code to obtain N=126 inner code word bits, and a total of d5=R×N=(261086×L+d pad ) / K×N=(261086×L+d pad ) / 110×126 bits. And perform a second data processing including symbol mapping and polarization division.

[0556] When symbol mapping adopts DP-16QAM, d5=(261086×L+d pad ) / K×N bits, the number of DP-16QAM symbols corresponding to the fifth bit set is s DP-16QAM =d5 / 8=(261086×L+d pad ) / K×N / 8=(261086×L+d pad ) / 110×126 / 8, where L=r / 119.

[0557] When the symbol mapping adopts DP-QPSK, d5=(261086×L+d pad ) / K×N bits, the number of DP-QPSK symbols corresponding to the fifth bit set is s DP-QPSK =d5 / 4=(261086×L+d pad ) / K×N / 4=(261086×L+d pad ) / 110×126 / 4, where L=r / 119.

[0558] The following table gives some parameter combinations, including the number of rows r, the number of padding bits d pad , the number of bits in the fifth bit set d5, the number of DP-16QAM symbols corresponding to the fifth bit set s DP-16QAM The number of DP-QPSK symbols corresponding to the fifth bit set s DP-QPSK .

[0559] Table 7

[0560] Serial number r <![CDATA[d pad ]]> <![CDATA[d5]]> <![CDATA[s DP-16QAM ]]> <![CDATA[s DP-QPSK ]]> 1 119 1154 300384 37548 75096 2 238 548 598752 74844 149688 3 357 1702 899136 112392 224784 4 476 1096 1197504 149688 299376 5 595 490 1495872 186984 373968 6 714 1644 1796256 224532 449064 7 833 1038 2094624 261828 523656 8 952 432 2392992 299124 598248 9 1071 1586 2693376 336672 673344 10 1190 980 2991744 373968 747936 11 1309 374 3290112 411264 822528 12 1428 1528 3590496 448812 897624 13 1547 922 3888864 486108 972216 14 1666 316 4187232 523404 1046808 15 1785 1470 4487616 560952 1121904 16 1904 864 4785984 598248 1196496 17 2023 258 5084352 635544 1271088 18 2142 1412 5384736 673092 1346184 19 2261 806 5683104 710388 1420776 20 2380 200 5981472 747684 1495368

[0561] It should be noted that, the larger the value of the row number r, the larger the number of dual-polarization symbols corresponding to the fifth bit set, and the higher the complexity; however, the larger the number of dual-polarization symbols, the smaller the framing redundancy introduced in DSP framing. The appropriate row number r can be selected according to the requirements of different scenarios to achieve an effective compromise between complexity and framing redundancy.

[0562] The number of rows of the first bit set in the DP-16QAM modulation scenario is represented as r DP-16QAM , the number of rows of the first bit set in the DP-QPSK modulation scenario is represented as r DP-QPSK In order to make the adopted data processing more compatible with DP-16QAM and DP-QPSK modulation, r DP-16QAM For r DP-QPSK 2 times, then s DP-16QAM =s DP-QPSK , so that the DSP frame structure after the second data processing is the same. The following table gives the corresponding parameter combinations.

[0563] Table 8

[0564]

[0565]

[0566] As an example, in the scenario of DP-QPSK symbol mapping, the number of rows r DP-QPSK =238, the number of padding bits d pad =548, such as Figure 8 The first bit set shown includes r DP-QPSK = 238 rows q = 2056 columns bits, the convolution interleaver includes P = 16 delay lines, the difference between two adjacent delay lines is Q = 2 storage units, and each storage unit includes d = K = 110 bits. After the first data processing, the number of the fifth bit set obtained is d5 = 598752, and the fifth bit set corresponds to the number of DP-QPSK symbols

[0567] As another example, in the scenario of DP-16QAM symbol mapping, the number of rows r DP-16QAM =238, the number of padding bits d pad =1092, such as Figure 8 The first bit set shown includes r DP-QPSK =476 rows q = 2056 columns bits, the convolution interleaver includes P = 16 delay lines, the difference between two adjacent delay lines is Q = 2 storage units, and each storage unit includes d = K = 110 bits. After the first data processing, the number of the fifth bit set obtained is d5 = 1197504, and the fifth bit set corresponds to the number of DP-16QAM symbols

[0568] Embodiment 5: The inner code adopts (136, 119) coding, that is, the inner code codeword length is N=136 bits, and the inner code information length is K=119 bits.

[0569] For example, the inner code uses BCH (136,119), which is constructed on the finite field GF (2 7 ) is first shortened by 120 bits to obtain BCH(135,110), and then single-bit extended, so it can also be recorded as single-bit extended E-BCH(136,119). In some specific application embodiments, the inner code BCH(136,119) can also be obtained by first adding 1 bit to BCH(255,239) to obtain E-BCH(256,239), and then shortening by 120 bits to obtain single-bit extended E-BCH(136,119). No specific limitation is made here.

[0570] The received data sequence includes multiple rows of bits, and each row includes q=2056 bits. A first bit set of r rows and q=2056 columns of bits, totaling 2056×r bits, is obtained from the received data sequence. r is an integer multiple of 119, that is, r=119×L, where L is a positive integer.

[0571] The first bit set including 2056×r=2056×119×L=244664×L bits is subjected to L outer code encoding (first FEC encoding), wherein every 244664 bits in the first bit set are encoded to obtain a total of 261086 encoded bits, and a total of 261086×L encoded bits are obtained, which is called the second bit set. Here, L is also called the number of SC codeword groups.

[0572] Add d to the second bit set containing 261086×L bits pad padding bits, we get 261086×L+d pad Optionally, 261086×L+d pad The bits are scrambled so that the probability of 0 and 1 in the scrambled bit data is more equal, so that the DC is balanced, which is beneficial to the receiving end.

[0573] Then, the third bit set is convolutionally interleaved to obtain a length of 261086×L+d pad bits, wherein the convolution interleaver includes P=16 delay lines, two adjacent delay lines differ by Q=2 storage units, and each storage unit includes d=K bits. And 261086×L+d pad =R×K.

[0574] Then, each K=119 bit in the fourth bit set is encoded with an inner code to obtain N=136 inner code word bits, and a total of d5=R×N=(261086×L+d pad ) / K×N=(261086×L+d pad ) / 119×136 bits. And perform a second data processing including symbol mapping and polarization division.

[0575] When symbol mapping adopts DP-16QAM, d5=(261086×L+d pad ) / K×N bits, the number of DP-16QAM symbols corresponding to the fifth bit set is s DP-16QAM =d5 / 8=(261086×L+d pad ) / K×N / 8=(261086×L+d pad ) / 119×136 / 8=(261086×L+d pad ) / 7, where L=r / 119.

[0576] When the symbol mapping adopts DP-QPSK, d5=(261086×L+d pad ) / K×N bits, the number of DP-QPSK symbols corresponding to the fifth bit set is s DP-QPSK =d5 / 4=(261086×L+d pad ) / K×N / 4=(261086×L+d pad ) / 119×136 / 4=(261086×L+d pad ) / 7×2, where L=r / 119.

[0577] The following table gives some parameter combinations, including the number of rows r, the number of padding bits d pad , the number of bits in the fifth bit set d5, the number of DP-16QAM symbols corresponding to the fifth bit set s DP-16QAM The number of DP-QPSK symbols corresponding to the fifth bit set s DP-QPSK .

[0578] Table 9

[0579]

[0580]

[0581] It should be noted that, the larger the value of the row number r, the larger the number of dual-polarization symbols corresponding to the fifth bit set, and the higher the complexity; however, the larger the number of dual-polarization symbols, the smaller the framing redundancy introduced in DSP framing. The appropriate row number r can be selected according to the requirements of different scenarios to achieve an effective compromise between complexity and framing redundancy.

[0582] The number of rows of the first bit set in the DP-16QAM modulation scenario is represented as r DP-16QAM , the number of rows of the first bit set in the DP-QPSK modulation scenario is represented as r DP-QPSK In order to make the adopted data processing more compatible with DP-16QAM and DP-QPSK modulation, r DP-16QAM For r DP-QPSK 2 times, then s DP-16QAM =s DP-QPSK , so that the DSP frame structure after the second data processing is the same. The following table gives the corresponding parameter combinations.

[0583] Table 10

[0584]

[0585] As an example, in the scenario of DP-QPSK symbol mapping, the number of rows r DP-QPSK =476, the number of padding bits d pad =952, such as Figure 8 The first bit set shown includes r DP-QPSK =476 rows q = 2056 columns bits, the convolution interleaver includes P = 16 delay lines, the difference between two adjacent delay lines is Q = 2 storage units, and each storage unit includes d = K = 119 bits. After the first data processing, the number of the fifth bit set obtained is d5 = 1194624, and the fifth bit set corresponds to the number of DP-QPSK symbols

[0586] As another example, in the scenario of DP-16QAM symbol mapping, the number of rows r DP-16QAM =952, the number of padding bits d pad =1904, such as Figure 8 The first bit set shown includes r DP-QPSK =476 rows q = 2056 columns bits, the convolution interleaver includes P = 16 delay lines, the difference between two adjacent delay lines is Q = 2 storage units, and each storage unit includes d = K = 119 bits. After the first data processing, the number of the fifth bit set obtained is d5 = 2389248, and the fifth bit set corresponds to the number of DP-16QAM symbols

[0587] Embodiment 6: The inner code adopts (135, 119) coding, that is, the inner code codeword length is N=135 bits, and the inner code information length is K=119 bits.

[0588] For example, the inner code uses BCH (135,119), which is constructed on the finite field GF (2 7 ) is obtained by first shortening the BCH (255, 239) code that can correct 2 bits of errors by 120 bits.

[0589] The received data sequence includes multiple rows of bits, and each row includes q=2056 bits. A first bit set of r rows and q=2056 columns of bits, totaling 2056×r bits, is obtained from the received data sequence. r is an integer multiple of 119, that is, r=119×L, where L is a positive integer.

[0590] The first bit set including 2056×r=2056×119×L=244664×L bits is subjected to L outer code encoding (first FEC encoding), wherein every 244664 bits in the first bit set are encoded to obtain a total of 261086 encoded bits, and a total of 261086×L encoded bits are obtained, which is called the second bit set. Here, L is also called the number of SC codeword groups.

[0591] Add d to the second bit set containing 261086×L bits pad padding bits, we get 261086×L+d pad Optionally, 261086×L+d pad The bits are scrambled so that the probability of 0 and 1 in the scrambled bit data is more equal, so that the DC is balanced, which is beneficial to the receiving end.

[0592] Then, the third bit set is convolutionally interleaved to obtain a length of 261086×L+d pad bits, wherein the convolution interleaver includes P=16 delay lines, two adjacent delay lines differ by Q=2 storage units, and each storage unit includes d=K bits. And 261086×L+d pad =R×K.

[0593] Then, each K=119 bit in the fourth bit set is encoded with an inner code to obtain N=135 inner code word bits, and a total of d5=R×N=(261086×L+d pad ) / K×N=(261086×L+d pad ) / 119×136 bits. And perform a second data processing including symbol mapping and polarization division.

[0594] When symbol mapping adopts DP-16QAM, d5=(261086×L+d pad ) / K×N bits, the number of DP-16QAM symbols corresponding to the fifth bit set is s DP-16QAM =d5 / 8=(261086×L+d pad ) / K×N / 8=(261086×L+d pad ) / 119×135 / 8, where L=r / 119.

[0595] When the symbol mapping adopts DP-QPSK, d5=(261086×L+d pad ) / K×N bits, the number of DP-QPSK symbols corresponding to the fifth bit set is s DP-QPSK =d5 / 4=(261086×L+d pad ) / K×N / 4=(261086×L+d pad ) / 119×135 / 4, where L=r / 119.

[0596] The following table gives some parameter combinations, including the number of rows r, the number of padding bits d pad , the number of bits in the fifth bit set d5, the number of DP-16QAM symbols corresponding to the fifth bit set s DP-16QAM The number of DP-QPSK symbols corresponding to the fifth bit set s DP-QPSK .

[0597] Table 11

[0598]

[0599]

[0600] It should be noted that, the larger the value of the row number r, the larger the number of dual-polarization symbols corresponding to the fifth bit set, and the higher the complexity; however, the larger the number of dual-polarization symbols, the smaller the framing redundancy introduced in DSP framing. The appropriate row number r can be selected according to the requirements of different scenarios to achieve an effective compromise between complexity and framing redundancy.

[0601] The number of rows of the first bit set in the DP-16QAM modulation scenario is represented as r DP-16QAM , the number of rows of the first bit set in the DP-QPSK modulation scenario is represented as r DP-QPSK In order to make the adopted data processing more compatible with DP-16QAM and DP-QPSK modulation, r DP-16QAM For r DP-QPSK 2 times, then s DP-16QAM =s DP-QPSK, so that the DSP frame structure after the second data processing is the same. The following table gives the corresponding parameter combinations.

[0602] Table 12

[0603]

[0604] As an example, in the scenario of DP-QPSK symbol mapping, the number of rows r DP-QPSK =476, the number of padding bits d pad =952, such as Figure 8 The first bit set shown includes r DP-QPSK =476 rows q = 2056 columns bits, the convolution interleaver includes P = 16 delay lines, the difference between two adjacent delay lines is Q = 2 storage units, and each storage unit includes d = K = 119 bits. After the first data processing, the number of the fifth bit set obtained is d5 = 1185840, and the fifth bit set corresponds to the number of DP-QPSK symbols

[0605] As another example, in the scenario of DP-16QAM symbol mapping, the number of rows r DP-16QAM =952, the number of padding bits d pad =1904, such as Figure 8 The first bit set shown includes r DP-QPSK =952 rows q = 2056 columns bits, the convolution interleaver includes P = 16 delay lines, the difference between two adjacent delay lines is Q = 2 storage units, and each storage unit includes d = K = 119 bits. After the first data processing, the number of the fifth bit set obtained is d5 = 2371680, and the fifth bit set corresponds to the number of DP-16QAM symbols

[0606] It should be noted that if Figure 3 , Figure 4 , Figure 5 , Figure 6 In the data processing described above, the first data processing may also be performed using multiple data streams. Several possible implementation methods are described below.

[0607] Fig.15 FIG. 2 is a schematic diagram of another implementation method of the first data processing in the embodiment of the present application. Fig.15 As shown, the received data sequence includes multiple rows of bits, and each row includes q=2056 bits. A first bit set of r rows and q=2056 columns of bits, totaling 2056×r bits, is obtained from the received data sequence. r is an integer multiple of 119, that is, r=119×L, where L is a positive integer.

[0608] The first bit set containing 2056×r=2056×119×L=244664×L bits is distributed to W paths, each path containing 244664×L / W bits, which is recorded as the first bit subset. Here, W is a positive integer greater than 1, and L is an integer multiple of W. In other words, the number of rows r is an integer multiple of W. Typically, W is 2 or 4 or 8 or 16, etc.

[0609] The first bit subset including 244664×L / W bits is encoded by L / W outer codes (first FEC encoding), wherein every 244664 bits in the first bit subset are encoded to obtain a total of 261086 encoded bits, and a total of 261086×L / W encoded bits are obtained, which are called the second bit subset. The W second bit subsets are combined to obtain a second bit set including 261086×L bits.

[0610] Add d to the second bit set containing 261086×L bits pad padding bits, we get 261086×L+d pad Optionally, 261086×L+d pad The bits are scrambled so that the probability of 0 and 1 in the scrambled bit data is more equal, so that the DC is balanced, which is beneficial to the receiving end.

[0611] Then, the third bit set is convolutionally interleaved to obtain a length of 261086×L+d pad bits, wherein the convolution interleaver includes P delay lines, two adjacent delay lines differ by Q storage units, and each storage unit includes d=K bits. And 261086×L+d pad =R×K.

[0612] Then, each K bits in the fourth bit set are encoded with inner code to obtain N inner code word bits, and the total number of d5=R×N=(261086×L+d pad A fifth bit set of ) / K×N bits is obtained. A second data processing including symbol mapping and polarization division is performed.

[0613] When symbol mapping adopts DP-16QAM, the fifth bit set of d5 bits corresponds to s DP-16QAM symbols. DP-16QAM =d5 / 8, where L=r / 119.

[0614] When symbol mapping adopts DP-QPSK, the number of DP-QPSK symbols corresponding to the fifth bit set of d5 bits is s DP-QPSK =d5 / 4, where L=r / 119.

[0615] In the above Fig.15 By appropriately modifying the first data processing flow shown in FIG. Fig.16 , Fig.17 , Fig.18 , Fig.19 The first data processing flow shown in FIG. Fig.16 The first data processing shown is used as an example for description. Fig.17 , Fig.18 , Fig.19 The first data processing flow shown can refer to the above description and combine Fig.16 Please understand and I will not elaborate on it here.

[0616] The received data sequence includes multiple rows of bits, and each row includes q=2056 bits. A first bit set of r rows and q=2056 columns of bits, totaling 2056×r bits, is obtained from the received data sequence. r is an integer multiple of 119, that is, r=119×L, where L is a positive integer.

[0617] The first bit set containing 2056×r=2056×119×L=244664×L bits is distributed to W paths, each path containing 244664×L / W bits, which is recorded as the first bit subset. Here, W is a positive integer greater than 1, and L is an integer multiple of W. In other words, the number of rows r is an integer multiple of W. Typically, W is 2 or 4 or 8 or 16, etc.

[0618] The first bit subset containing 244664×L / W bits is subjected to L / W outer code encoding (first FEC encoding), wherein every 244664 bits in the first bit subset are encoded to obtain a total of 261086 coded bits, and a total of 261086×L / W coded bits are obtained, which are called the second bit subset.

[0619] Add to the second bit subset containing 261086×L / W bits padding bits, we get The W third bit subsets are combined to obtain a third bit subset containing bits. Here That is, the third bit set contains d pad Filling bits, d pad is an integer multiple of W. Optionally, 261086×L+d pad The bits are scrambled so that the probability of 0 and 1 in the scrambled bit data is more equal, so that the DC is balanced, which is beneficial to the receiving end.

[0620] Then, the third bit set is convolutionally interleaved to obtain a length of 261086×L+dpad bits, wherein the convolution interleaver includes P delay lines, two adjacent delay lines differ by Q storage units, and each storage unit includes d=K bits. And 261086×L+d pad =R×K.

[0621] Then, each K bits in the fourth bit set are encoded with inner code to obtain N inner code word bits, and the total number of d5=R×N=(261086×L+d pad A fifth bit set of ) / K×N bits is obtained. A second data processing including symbol mapping and polarization division is performed.

[0622] When symbol mapping adopts DP-16QAM, the fifth bit set of d5 bits corresponds to s DP-16QAM symbols. DP-16QAM =d5 / 8, where L=r / 119.

[0623] When the symbol mapping adopts DP-QPSK, the number of DP-QPSK symbols corresponding to the fifth bit set of d5 bits is s DP-QPSK =d5 / 4, where L=r / 119.

[0624] It should be understood that the use of Fig.15 , Fig.16 , Fig.17 , Fig.18 , Fig.19 The first data processing flow shown in FIG. 1 is compatible with application scenarios with lower rates. For example, at a rate of 1.6T, the following Fig.15 The first data processing flow, where W=4, contains 4 external code encoding modules, each with a rate of 400G. When 2 of the 4 external code encoding modules are not executed, it can be used in the 800G rate scenario, without the need to redesign the external code encoding modules, which is convenient for hardware development; when 3 of the 4 external code encoding modules are not executed, it can be used in the 400G rate scenario, without the need to redesign the external code encoding modules, which is convenient for hardware development.

[0625] Fig. 20 FIG. 1 is a schematic diagram of a structure of a data processing device in an embodiment of the present application. Fig. 20As shown, the data processing device includes an acquisition unit 201, a first encoding unit 202, a filling unit 203, an interleaving unit 204, and a second encoding unit 205. Optionally, the data processing device also includes a scrambling unit 206. It should be understood that in some possible scenarios, the interleaving unit 204 is optional, so that the data processing device has a lower latency. The acquisition unit 201 is used to perform the operation of step 101 above, the first encoding unit 202 is used to perform the operation of step 102 above, the filling unit 203 is used to perform the operation of step 103 above, the interleaving unit 204 is used to perform the operation of step 104 above, and the second encoding unit 205 is used to perform the operation of step 105 above. It should be understood that the data processing device provided in the present application can also be implemented in other ways. For example, the unit division in the above device is only a logical function division, and there may be other division methods in actual implementation, for example, multiple units or components can be combined or integrated into another system. In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or may be each independent physical unit, or two or more functional units may be integrated into one processing unit. The above integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0626] Fig.21 FIG. 2 is another structural diagram of a data processing device in an embodiment of the present application. Fig.21 As shown, the data processing device includes a processor 301, and the processor is used to perform the operations of the above steps 101 to 105. In a possible implementation, the processor 301 may include the above Fig. 20 The acquisition unit 201, the first encoding unit 202, the filling unit 203, the interleaving unit 204, and the second encoding unit 205 shown. Optionally, the data processing device further includes an interface circuit 302, which may be a transceiver or an input / output interface, and the interface circuit 302 is used to receive a signal from another device outside the data processing device and transmit it to the processor 301 or to send a signal from the processor 301 to another device outside the data processing device. In one possible scenario, the interface circuit 302 is used to receive a data sequence and transmit the data sequence to the processor 301, and the processor obtains a first bit set to be encoded by an outer code from the data sequence. In another possible scenario, the processor 301 is also used to perform the above Figures 3 to 6 The second data processing described in any of the embodiments above obtains a data frame to be sent, and the interface circuit 302 is used to send the data frame. Optionally, the data processing device may further include a memory 303, wherein the memory 303 is used to store program instructions and data.

[0627] The embodiment of the present application also provides a chip. The chip integrates a circuit and one or more interfaces for implementing the functions of the above-mentioned processor 301. As an example, the chip integrates a memory. As another example, when the chip does not integrate a memory, it can be connected to an external memory through an interface. The chip can complete the method steps of any one or more of the above-mentioned embodiments. Alternatively, the chip implements the actions performed by the data processing device in the above-mentioned embodiment according to the program code stored in the memory.

[0628] The embodiment of the present application further provides a computer-readable storage medium, including a program or an instruction. When the program or the instruction is executed on a computer, the method executed by the processor 301 in the above method embodiment is implemented.

[0629] It should be understood that the processor mentioned in the embodiments of the present application can be implemented by hardware or by software. When implemented by hardware, the processor can be a logic circuit, an integrated circuit, etc. When implemented by software, the processor can be a general-purpose processor implemented by reading software code stored in a memory.

[0630] As an example, the processor in the embodiments of the present application may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. The general-purpose processor may be a microprocessor or any conventional processor.

[0631] In the embodiments of the present application, the memory may be a random access memory (RAM), a flash memory, a read-only memory (ROM), a programmable ROM (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a register, a hard disk, a mobile hard disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to a processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium may also be a component of the processor. The processor and the storage medium may be located in an ASIC. In addition, the ASIC may be located in a network device or a terminal device. Of course, the processor and the storage medium may also be present in a network device or a terminal device as discrete components.

[0632] In the above embodiments, all or part of them may be implemented by software, hardware, firmware or any combination thereof.

[0633] When implemented using hardware, the data processing method provided in the embodiments of the present application may be implemented without reading software codes or instructions. For example, it may be implemented by a CPU, DSP, ASIC, FPGA, other programmable logic devices, transistor logic devices, hardware components, or any combination thereof.

[0634] When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instruction is loaded and executed on a computer, the process or function described in the embodiment of the present application is performed in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, a network device, a terminal device, or other programmable device. The computer program or instruction may be stored in a computer-readable storage medium or transmitted via the computer-readable storage medium. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server that integrates one or more available media. The available medium may be a magnetic medium, such as a floppy disk, a hard disk, or a magnetic tape; it may also be an optical medium, such as a DVD; it may also be a semiconductor medium, such as a solid state disk (SSD).

[0635] Finally, it should be noted that the above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A data processing method for optical communication, characterized in that: include: Obtain a first bit set, where the first bit set includes d1 bits, where d1=244664×L, and L is a positive integer; Performing a first forward error correction (FEC) encoding on the first bit set to obtain a second bit set, where the second bit set includes d2 bits, and every 244664 bits in the first bit set are encoded by the first FEC encoding to obtain every 261086 bits in the second bit set, where d2=261086×L; Add d to the second bit set pad The third bit set is obtained by adding padding bits, d pad is an integer greater than or equal to 0; Perform a second FEC encoding on the third bit set to obtain a fourth bit set.

2. The method according to claim 1, characterized in that The d1 bits in the first bit set are distributed into r rows and 2056 columns, where r=119×L.

3. The method according to claim 1 or 2, characterized in that: Every 261086 bits in the second bit set are distributed into 119 rows and 2194 columns, and the first 2056 columns of the 2194 columns are used to carry the 244664 bits in the first bit set.

4. The method according to any one of claims 1 to 3, characterized in that Each 261086 bits in the second bit set include 244664 bits in the first bit set, the 32 first type bits, the 6 second type bits, and 16384 first FEC-coded check bits.

5. The method according to any one of claims 1 to 4, characterized in that Add d to the second bit set pad After obtaining a third bit set by performing a second FEC encoding on the third bit set and before obtaining a fourth bit set by performing a second FEC encoding on the third bit set, the method further includes: A first interleaving is performed on the third bit set.

6. The method according to claim 5, characterized in that Performing a first interleaving on the third bit set includes: The bits from the third bit set are delayed according to P delay lines, where P is an integer greater than 1, and each delay line includes a different number of storage units. The delay line with the smallest number of storage units includes 0 storage units. The difference in the number of storage units between every two adjacent delay lines is Q. Each storage unit is used to store d bits. The input bits are input into the P delay lines in sequence according to the sequence numbers of the P delay lines. Each delay line inputs d bits at a time and outputs d bits at a time. The continuous P×d bits output after convolution interleaving include d bits output by each delay line, and Q and d are both integers greater than or equal to 1.

7. The method according to claim 6, characterized in that The fourth bit set includes R codewords, each of which has a length of N bits, each of which includes K information bits, R, N and K are all integers greater than 1, N is greater than K, and the third bit set includes R×K bits, R×K=261086×L+d pad , K is an integer multiple of d, P×d is an integer multiple of K, is an integer multiple of P.

8. The method according to claim 7, characterized in that The third bit set after the first interleaving includes R rows and K columns of bits, and the K bits in each row of the third bit set after the first interleaving are The K bits output by the delay line, performing the second FEC encoding on the third bit set to obtain the fourth bit set includes: The second FEC encoding is performed on the K bits in each row of the third bit set after the first interleaving to obtain N bits of each codeword in the fourth bit set.

9. The method according to any one of claims 1 to 8, characterized in that The second FEC coding adopts BCH coding or extended BCH coding.

10. The method according to any one of claims 1 to 9, characterized in that Add d to the second bit set pad After obtaining a third bit set by performing a second FEC encoding on the third bit set and before obtaining a fourth bit set by performing a second FEC encoding on the third bit set, the method further includes: The third set of bits is scrambled.

11. The method according to any one of claims 1 to 10, characterized in that After performing a second FEC encoding on the third bit set to obtain a fourth bit set, the method further includes: Data processing is performed on the fourth bit set, where the data processing includes symbol mapping, second interleaving, polarization division, and framing processing.

12. The method according to any one of claims 2 to 11, characterized in that The fourth bit set includes R codewords, each of the codewords has a length of N bits, each of the codewords includes K information bits, R, N and K are all integers greater than 1, and N is greater than K; K = 113, N = 127, or K = 113, N = 128, or K = 112, N = 128, or K = 110, N = 126, or K = 119, N = 136, or K=119, N=135.

13. The method according to claim 12, characterized in that K = 113, N = 127, r and d pad Satisfy one of the following conditions: r = 119, d pad =1074; r＝238，d pad ＝340； r＝357，d pad ＝1414； r＝476，d pad ＝680； r＝595，d pad ＝1754； r＝714，d pad ＝1020； r＝833，d pad ＝286； r＝952，d pad ＝1360； r＝1071，d pad ＝626； r＝1190，d pad ＝1700； r＝1309，d pad ＝966； r＝1428，d pad ＝232； r＝1547，d pad ＝1306； r＝1666，d pad ＝572； r＝1785，d pad ＝1646； r＝1904，d pad ＝912； r＝2023，d pad ＝178； r＝2142，d pad ＝1252； r＝2261，d pad ＝518； r＝2380，d pad ＝1592。 14. The method according to claim 12, characterized in that K = 113, N = 128, r and d pad Satisfy one of the following conditions: r = 119, d pad =1074; r＝238，d pad ＝340； r＝357，d pad ＝1414； r＝476，d pad ＝680； r＝595，d pad ＝1754； r＝714，d pad ＝1020； r＝833，d pad ＝286； r＝952，d pad ＝1360； r＝1071，d pad ＝626； r＝1190，d pad ＝1700； r＝1309，d pad ＝966； r＝1428，d pad ＝232； r＝1547，d pad ＝1306； r＝1666，d pad ＝572； r＝1785，d pad ＝1646； r＝1904，d pad ＝912； r＝2023，d pad ＝178； r＝2142，d pad ＝1252； r＝2261，d pad ＝518； r＝2380，d pad ＝1592。 15. The method according to claim 12, characterized in that K = 112, N = 128, r and d pad Satisfy one of the following conditions: r = 119, d pad =546; r＝238，d pad ＝1092； r＝357，d pad ＝1638； r＝476，d pad ＝392； r＝595，d pad ＝938； r＝714，d pad ＝1484； r＝833，d pad ＝238； r＝952，d pad ＝784； r＝1071，d pad ＝1330； r＝1190，d pad ＝84； r＝1309，d pad ＝630； r＝1428，d pad ＝1176； r＝1547，d pad ＝1722； r＝1666，d pad ＝476； r＝1785，d pad ＝1022； r＝1904，d pad ＝1568； r＝2023，d pad ＝322； r＝2142，d pad ＝868； r＝2261，d pad ＝1414； r＝2380，d pad ＝168。 16. The method according to claim 12, characterized in that K = 110, N = 126, r and d pad Satisfy one of the following conditions: r = 119, d pad =1154; r＝238，d pad 548； r＝357，d pad ＝1702； r＝476，d pad ＝1096； r＝595，d pad ＝490； r＝714，d pad ＝1644； r＝833，d pad ＝1038； r＝952，d pad ＝432； r＝1071，d pad ＝1586； r＝1190，d pad ＝980； r＝1309，d pad ＝374； r＝1428，d pad ＝1528； r＝1547，d pad ＝922； r＝1666，d pad ＝316； r＝1785，d pad ＝1470； r＝1904，d pad ＝864； r＝2023，d pad ＝258； r＝2142，d pad ＝1412； r＝2261，d pad ＝806； r＝2380，d pad ＝200。 17. The method according to claim 12, characterized in that K = 119, N = 136, r and d pad Satisfy one of the following conditions: r = 119, d pad =1666; r＝238，d pad ＝1428； r＝357，d pad ＝1190； r＝476，d pad ＝952； r＝595，d pad ＝714； r＝714，d pad ＝476； r＝833，d pad ＝238； r＝952，d pad ＝1904； r＝1071，d pad ＝1666； r＝1190，d pad ＝1428； r＝1309，d pad ＝1190； r＝1428，d pad ＝952； r＝1547，d pad ＝714； r＝1666，d pad ＝476； r＝1785，d pad ＝238； r＝1904，d pad ＝0； r＝2023，d pad ＝1666； r＝2142，d pad ＝1428； r＝2261，d pad ＝1190； r＝2380，d pad ＝952。 18. The method according to claim 12, characterized in that K = 119, N = 135, r and d pad One of the following conditions is met: r＝119，d pad ＝1666； r＝238，d pad ＝1428； r＝357，d pad ＝1190； r＝476，d pad ＝952； r＝595，d pad ＝714； r＝714，d pad ＝476； r＝833，d pad ＝238； r＝952，d pad ＝1904； r＝1071，d pad ＝1666； r＝1190，d pad ＝1428； r＝1309，d pad ＝1190； r＝1428，d pad ＝952； r＝1547，d pad ＝714； r＝1666，d pad ＝476； r＝1785，d pad ＝238； r＝1904，d pad ＝0； r＝2023，d pad ＝1666； r＝2142，d pad ＝1428； r＝2261，d pad ＝1190； r＝2380，d pad ＝952。 19. A data processing device, characterized in that: The data processing device comprises: an acquisition unit, a first encoding unit, a filling unit, and a second encoding unit; The acquisition unit is used to: acquire a first bit set, where the first bit set includes d1 bits, d1=244664×L, and L is a positive integer; The first encoding unit is used to: perform a first forward error correction FEC encoding on the first bit set to obtain a second bit set, the second bit set includes d2 bits, and every 244664 bits in the first bit set are encoded by the first FEC to obtain every 261086 bits in the second bit set, d2=261086×L; The padding unit is used to add d to the second bit set. pad The third bit set is obtained by adding padding bits, d pad is an integer greater than or equal to 0; The second encoding unit is used for performing second FEC encoding on the third bit set to obtain a fourth bit set.

20. The data processing device according to claim 19, characterized in that The d1 bits in the first bit set are distributed into r rows and 2056 columns, where r=119×L.

21. The data processing device according to claim 19 or 20, characterized in that: Every 261086 bits in the second bit set are distributed into 119 rows and 2194 columns, and the first 2056 columns of the 2194 columns are used to carry the 244664 bits in the first bit set.

22. The data processing device according to any one of claims 19 to 21, characterized in that: The fourth bit set includes R codewords, each of the codewords has a length of N bits, each of the codewords includes K information bits, R, N and K are all integers greater than 1, and N is greater than K; K = 113, N = 127, or K = 113, N = 128, or K = 112, N = 128, or K = 110, N = 126, or K = 119, N = 136, or K=119, N=135.

23. A data processing device, characterized in that: The data processing device comprises a processor, and the processor is configured to execute the method according to any one of claims 1 to 18.

24. The data processing device according to claim 23, characterized in that: The data processing device further includes an interface circuit, the processor is further configured to perform data processing on a fourth bit set to obtain a data frame, and the interface circuit is configured to send the data frame.

25. A chip, characterized in that: The chip comprises a processor configured to execute the method according to any one of claims 1 to 18.

Images