Synchronization method and device, distributed antenna system and readable storage medium

Abstract

The invention relates to a synchronization method and device, a distributed antenna system and a computer readable storage medium. The method comprises the following steps: generating a first frame header of the distributed antenna system; the distributed antenna system is used for forwarding base station signals; according to the actual frame header position of the base station signal, performing deviation correction processing on the first frame header to obtain a second frame header of the distributed antenna system; and performing time division duplex synchronization on the distributed antenna system according to the second frame header. By adopting the method, the complexity of station opening operation of the distributed antenna system during TDD synchronization can be reduced, and time and manpower are saved.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a synchronization method, device, distributed antenna system and computer-readable storage medium. Background Art

[0002] A digital distributed antenna system (DAS) refers to a collection of antennas physically dispersed in a specific space. The system uses antennas to forward digital signals sent by base stations, thereby expanding the coverage of base stations and improving the problem of network coverage blind spots.

[0003] The reliable implementation of digital DAS requires the time division duplexing (TDD) synchronization function. The traditional 4G / 5G TDD synchronization function implementation method is to use the existing 4G / 5G module to obtain synchronization information and related configuration parameters, and then perform TDD synchronization based on the synchronization information and related configuration parameters. However, the high price of 4G / 5G modules increases the cost of network construction. Moreover, when the traditional 4G / 5G TDD synchronization system is opened, it is necessary to manually configure the relevant parameters of the base station, such as time slot ratio, special subframe ratio, SSB (Synchronization Signal Block, which can also refer to synchronization signal and physical broadcast channel block) frequency, etc. Therefore, the operation is more cumbersome when opening the station, which consumes time and human resources.

[0004] Therefore, the current TDD synchronization technology of digital DAS has the problem of complicated station opening operations. Summary of the invention

[0005] Based on this, it is necessary to provide a synchronization method, device, distributed antenna system, computer-readable storage medium and computer program product that can simplify the station opening operation in order to solve the above technical problems.

[0006] In a first aspect, the present application provides a synchronization method, comprising:

[0007] Generate a first frame header of a distributed antenna system; the distributed antenna system is used to forward base station signals;

[0008] According to the actual frame header position of the base station signal, the first frame header is subjected to a deflection correction process to obtain a second frame header of the distributed antenna system;

[0009] According to the second frame header, time division duplex synchronization is performed on the distributed antenna system.

[0010] In a second aspect, the present application further provides a synchronization device, including:

[0011] A generating module, used to generate a first frame header of a distributed antenna system; the distributed antenna system is used to forward base station signals;

[0012] A correction module, configured to perform correction processing on the first frame header according to an actual frame header position of the base station signal to obtain a second frame header of the distributed antenna system;

[0013] A synchronization module is used to perform time division duplex synchronization on the distributed antenna system according to the second frame header.

[0014] In a third aspect, the present application further provides a distributed antenna system, including an access unit and a remote unit, wherein the access unit is connected to the remote unit via an optical fiber, and the distributed antenna system is used to forward base station signals;

[0015] The access unit is configured to generate a first frame header of the distributed antenna system, perform a deflection correction process on the first frame header according to an actual frame header position of the base station signal, obtain a second frame header of the distributed antenna system, and send the second frame header;

[0016] The remote unit is used to receive the second frame header and perform time division duplex synchronization on the distributed antenna system according to the second frame header.

[0017] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the following steps are implemented:

[0018] Generate a first frame header of a distributed antenna system; the distributed antenna system is used to forward base station signals;

[0019] According to the actual frame header position of the base station signal, the first frame header is subjected to a deflection correction process to obtain a second frame header of the distributed antenna system;

[0020] According to the second frame header, time division duplex synchronization is performed on the distributed antenna system.

[0021] In a fifth aspect, the present application further provides a computer program product, including a computer program, which implements the following steps when executed by a processor:

[0022] Generate a first frame header of a distributed antenna system; the distributed antenna system is used to forward base station signals;

[0023] According to the actual frame header position of the base station signal, the first frame header is subjected to a deflection correction process to obtain a second frame header of the distributed antenna system;

[0024] According to the second frame header, time division duplex synchronization is performed on the distributed antenna system.

[0025] The above-mentioned synchronization method, device, distributed antenna system, computer-readable storage medium and computer program product generate a first frame header of the distributed antenna system, and the distributed antenna system is used to forward the base station signal. According to the actual frame header position of the base station signal, the first frame header is corrected to obtain the second frame header of the distributed antenna system, and the distributed antenna system is synchronized in time division duplex according to the second frame header; the actual frame header position of the base station signal can be used to correct the first frame header automatically generated by the DAS to obtain the TDD synchronization frame header of the DAS, that is, the second frame header, and TDD synchronization is performed directly according to the second frame header. Since no 4G / 5G module is required, the cost can be effectively reduced, and there is no need to configure parameters when opening the station, which also reduces the complexity of the station opening operation during TDD synchronization, saving time and manpower. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments of the present application or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0027] Figure 1 A schematic diagram of a synchronization method in one embodiment;

[0028] Figure 2 is a structural block diagram of a DAS in one embodiment;

[0029] Figure 3 is a structural block diagram of a DAS in another embodiment;

[0030] Figure 4 is a structural block diagram of a DAS access unit in one embodiment;

[0031] Figure 5 1. It is a flowchart of the SSB frequency point locking process of the DAS access unit in one embodiment;

[0032] Figure 6 A schematic diagram of a process flow of a TDD synchronization process of a DAS access unit in one embodiment;

[0033] Figure 7 A schematic diagram of a flow chart of a DAS remote unit TDD synchronization process in one embodiment;

[0034] Figure 8 is a flowchart of a synchronization method in another embodiment;

[0035] Fig. 9FIG. 4 is a structural block diagram of a synchronization device in an embodiment. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0037] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present disclosure described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0038] In an exemplary embodiment, Figure 1 As shown, a synchronization method is provided. This embodiment uses the method applied to DAS as an example for illustration, and includes the following steps:

[0039] Step S102, generating a first frame header of a distributed antenna system; the distributed antenna system is used to forward base station signals.

[0040] The first frame header may be a randomly generated DAS frame header, that is, a 10 ms (millisecond) frame header with a random position of the DAS. The base station signal refers to a signal sent by a base station.

[0041] In a specific implementation, a DAS may be deployed within the coverage of the base station. The DAS is used to forward the base station signal to the terminal. When executing the TDD synchronization function, the DAS may randomly generate the first frame header.

[0042] In actual applications, DAS can be provided with an access unit and a remote unit, wherein the access unit communicates with the base station to receive base station signals, and the remote unit communicates with the terminal to send base station signals to the terminal, and the access unit and the remote unit can be connected via optical fiber. In order to expand the network coverage, an extension unit (EU) can also be set between the access unit and the remote unit, and the extension unit can be connected to the access unit and the remote unit respectively via optical fiber. The access unit of DAS can be provided with a field programmable gate array (FPGA) and a central processing unit (CPU), wherein the FPGA can randomly generate a 10ms frame header.

[0043] Step S104: performing a deflection correction process on the first frame header according to the actual frame header position of the base station signal to obtain a second frame header of the distributed antenna system.

[0044] The actual frame header position may be the frame header position of the current base station signal. The second frame header may be a DAS frame header aligned with the frame header position of the current base station signal.

[0045] In a specific implementation, the DAS can receive a base station signal, determine the actual frame header position of the base station signal, correct the randomly generated first frame header according to the actual frame header position, and obtain its own second frame header aligned with the actual frame header position.

[0046] In actual applications, after the DAS access unit is powered on, it can receive the signal sent by the base station. The FPGA and CPU of the access unit determine the precise position of the 10ms frame header of the current base station based on the received base station signal, and obtain the actual frame header position of the base station signal. The FPGA can correct the randomly generated 10ms frame header according to the actual frame header position to obtain a DAS frame header aligned with the 10ms frame header of the current base station.

[0047] Step S106: performing time division duplex synchronization on the distributed antenna system according to the second frame header.

[0048] In a specific implementation, the DAS can determine the switching signal between the uplink and downlink in its own time domain according to the obtained second frame header, and implement TDD synchronization based on the switching signal.

[0049] In actual applications, the access unit of DAS can parse the time slot ratio and special subframe ratio from the base station signal, and send the DAS frame header aligned with the current base station 10ms frame header, as well as the time slot ratio and special subframe ratio to the remote unit, including directly sending them to the remote unit or forwarding them to the remote unit through an extension unit. The remote unit generates a switching signal for the power amplifier and the low noise amplifier based on the received DAS frame header, time slot ratio and special subframe ratio, and switches the power amplifier and the low noise amplifier according to the switching signal to achieve TDD synchronization of DAS.

[0050] The above-mentioned synchronization method generates a first frame header of a distributed antenna system, and the distributed antenna system is used to forward base station signals. According to the actual frame header position of the base station signal, the first frame header is corrected to obtain the second frame header of the distributed antenna system, and the distributed antenna system is synchronized in time division duplexing according to the second frame header; the actual frame header position of the base station signal can be used to correct the first frame header automatically generated by the DAS to obtain the TDD synchronization frame header of the DAS, that is, the second frame header, and TDD synchronization is performed directly according to the second frame header. Since no 4G / 5G module is required, the cost can be effectively reduced, and there is no need to configure parameters when opening the site, which also reduces the complexity of the site opening operation during TDD synchronization, saving time and manpower.

[0051] In an exemplary embodiment, the above step S102 may specifically include: determining an SSB frequency that can be synchronized with a base station signal; locking the SSB frequency, and randomly generating a first frame header corresponding to the SSB frequency.

[0052] Among them, the SSB frequency point can be a specific frequency used to transmit SSB.

[0053] In a specific implementation, the DAS may poll the SSB frequency to obtain an SSB frequency that can be synchronized with the received base station signal. The DAS may lock the SSB frequency and randomly generate a first frame header for the SSB frequency.

[0054] In actual applications, after the access unit of the DAS is powered on, it can receive the signal sent by the base station. The FPGA and CPU of the access unit jointly poll the various SSB frequencies specified by the 3GPP protocol, and perform correlation operations on the base station signal and the primary synchronization signal (PSS) sequence of each SSB frequency. According to the correlation operation results, the SSB frequency that can be synchronized with the base station signal is detected and locked. After that, the FPGA can randomly generate a 10ms frame header for the SSB frequency.

[0055] In this embodiment, by determining the SSB frequency that can be synchronized with the base station signal, locking the SSB frequency, and randomly generating the first frame header corresponding to the SSB frequency, the SSB frequency can be automatically identified without the need for a 4G / 5G module, thereby reducing costs. In addition, when opening a site, there is no need to manually configure the SSB frequency, thereby avoiding human configuration errors, improving site opening efficiency, and saving manpower.

[0056] In an exemplary embodiment, the above step S104 may specifically include: determining the deviation between the position of the first frame header and the actual frame header position of the base station signal; and aligning the first frame header with the actual frame header of the base station signal according to the deviation to obtain a second frame header.

[0057] The deviation may be a deviation between a frame header position randomly generated by the DAS and an actual frame header position of the base station.

[0058] In a specific implementation, DAS can determine the position of the first frame header and the actual frame header position of the base station signal, count the deviation between the position of the first frame header and the actual frame header position, correct the first frame header according to the deviation, and obtain a second frame header aligned with the actual frame header of the base station signal.

[0059] In actual applications, after the FPGA of the DAS access unit randomly generates a 10ms frame header, the FPGA and CPU can jointly calculate the base station signal of the currently locked SSB frequency point to determine the position of the current base station's 10ms frame header. The CPU can calculate the deviation between the position of the FPGA's self-generated 10ms frame header and the position of the base station's 10ms frame header, and transmit the deviation to the FPGA. The FPGA corrects the self-generated 10ms frame header according to the deviation to align it with the base station's 10ms frame header. The corrected self-generated 10ms frame header is the second frame header.

[0060] In this embodiment, by determining the deviation between the position of the first frame header and the actual frame header position of the base station signal, the first frame header is aligned with the actual frame header of the base station signal according to the deviation to obtain the second frame header, and the TDD synchronization frame header of the DAS can be automatically determined, thereby improving the TDD synchronization efficiency of the DAS.

[0061] In practical applications, the DAS also needs to be aligned with the base station clock. Therefore, in addition to performing TDD synchronization on the DAS according to the second frame header, the DAS can also be clock synchronized. In an exemplary embodiment, the synchronization method may further include: determining the difference between the number of points in the first frame header and the actual number of points in the frame header of the base station signal; determining the clock deviation of the distributed antenna system relative to the base station according to the difference; and performing clock synchronization on the distributed antenna system according to the clock deviation.

[0062] The number of points may be the number of sampling points. The actual number of frame header points may be the number of sampling points of the current base station frame header. The clock deviation may be the deviation between the DAS clock and the base station clock.

[0063] In the specific implementation, DAS can count the number of points in the first frame header and obtain the actual number of frame header points of the current base station signal. According to the difference between the number of points in the first frame header and the actual number of frame header points, the clock deviation between DAS and the base station is determined, and the DAS clock is adjusted and locked according to the clock deviation to synchronize the DAS clock with the base station clock.

[0064] In actual applications, the FPGA of the DAS access unit can count the points of the 10ms frame header in real time. The CPU reads the number of points of the 10ms frame header counted by the FPGA and compares the number of points with the 10ms frame header point of the current base station to obtain the difference of the 10ms frame header, and converts the difference into a clock deviation. The clock of the access unit is adjusted and locked according to the clock deviation to synchronize the clock of the access unit with the clock of the base station.

[0065] In this embodiment, by determining the difference between the number of points in the first frame header and the actual number of points in the frame header of the base station signal, the clock deviation of the distributed antenna system relative to the base station is determined based on the difference, and the clock of the distributed antenna system is synchronized based on the clock deviation. When the base station signal fades for a short time or there is no signal output, it can always maintain a stable 10ms frame header output, thereby avoiding the problem of signal cutting in the remote unit.

[0066] In an exemplary embodiment, the above step S106 may specifically include: parsing the time slot ratio and the special subframe ratio from the base station signal; determining the switching signal between the low noise amplifier and the power amplifier according to the second frame header, the time slot ratio and the special subframe ratio; and performing time division duplex synchronization on the distributed antenna system according to the switching signal.

[0067] The switching signal may be a signal instructing to switch between the low noise amplifier and the power amplifier.

[0068] In the specific implementation, DAS can parse the received base station signal to obtain the time slot ratio and special subframe ratio carried by the base station signal. According to the second frame header obtained by correction, and the time slot ratio and special subframe ratio obtained by analysis, DAS can determine its own time domain uplink and downlink switching signals. Since DAS uses a power amplifier for downlink and a low-noise amplifier for uplink, the time domain uplink and downlink switching signals can be used as switching signals between the low-noise amplifier and the power amplifier. DAS can switch between the low-noise amplifier and the power amplifier according to the switching signal to achieve TDD synchronization.

[0069] In actual applications, the FPGA of the DAS access unit transmits the base station signal to the CPU, and the CPU parses the time slot ratio and special subframe ratio from the base station signal. The access unit can send the self-generated 10ms frame header after correction, as well as the parsed time slot ratio and special subframe ratio to the remote unit. The remote unit generates a switching signal between the low noise amplifier and the power amplifier according to the corrected 10ms frame header, time slot ratio and special subframe ratio. The DAS remote unit switches to the power amplifier in the TDD downlink and to the low noise amplifier in the TDD uplink according to the switching signal.

[0070] In this embodiment, by parsing the time slot ratio and special subframe ratio from the base station signal, the switching signal between the low noise amplifier and the power amplifier is determined according to the second frame header, the time slot ratio and the special subframe ratio, and the distributed antenna system is synchronized for time division duplexing according to the switching signal. The DAS can automatically perform TDD synchronization to improve the synchronization efficiency. At the same time, there is no need to manually configure the time slot ratio and special subframe ratio, which avoids human configuration errors, improves the reliability of site opening and saves manpower.

[0071] In an exemplary embodiment, there are multiple groups of the above-mentioned second frame header, time slot ratio and special subframe ratio, which correspond to different communication standards and / or different SSB frequencies.

[0072] In the specific implementation, DAS can receive multiple groups of base station signals with different communication standards and different SSB frequencies, and determine the second frame header, time slot ratio and special subframe ratio corresponding to each group of base station signals, thereby realizing TDD synchronization of different communication standards and different SSB frequencies.

[0073] For example, the access unit of DAS can simultaneously receive signals from four base stations of different standards, namely A, B, C, and D. The access unit can then synchronize the SSB frequencies of base stations A, B, C, and D at the same time, and generate four 10ms frame headers, four time slot ratios, and four special subframe ratios aligned with base stations A, B, C, and D, respectively.

[0074] In this embodiment, by providing multiple groups of second frame headers, time slot ratios and special subframe ratios, corresponding to different communication standards and / or different SSB frequencies, TDD synchronization of multiple standards and multiple frequencies can be achieved simultaneously, further improving the synchronization efficiency.

[0075] In an exemplary embodiment, Figure 2 As shown, a distributed antenna system is provided, including an access unit 202 and a remote unit 204, the access unit 202 is connected to the remote unit 204 via an optical fiber, and the distributed antenna system is used to forward base station signals;

[0076] The access unit 202 is configured to generate a first frame header of the distributed antenna system, perform a deflection correction process on the first frame header according to an actual frame header position of a base station signal, obtain a second frame header of the distributed antenna system, and send the second frame header;

[0077] The remote unit 204 is configured to receive the second frame header, and perform time division duplex synchronization on the distributed antenna system according to the second frame header.

[0078] In a specific implementation, the access unit of the DAS can randomly generate a first frame header, determine the actual frame header position based on the received base station signal, correct the first frame header based on the actual frame header position, and obtain a second frame header aligned with the actual frame header position. The access unit can send the second frame header to the remote unit via optical fiber. It can be understood that the access unit can also send the parsed time slot ratio and special subframe ratio to the remote unit, and the remote unit can perform TDD synchronization based on the received second frame header, time slot ratio and special subframe ratio.

[0079] The above-mentioned distributed antenna system generates a first frame header of the distributed antenna system, corrects the first frame header according to the actual frame header position of the base station signal, obtains the second frame header of the distributed antenna system, and performs time division duplex synchronization on the distributed antenna system according to the second frame header; the actual frame header position of the base station signal can be used to correct the first frame header automatically generated by the DAS to obtain the TDD synchronization frame header of the DAS, that is, the second frame header, and TDD synchronization is performed directly according to the second frame header. Since no 4G / 5G module is required, the cost can be effectively reduced, and there is no need to configure parameters when opening the site, which also reduces the complexity of the site opening operation during TDD synchronization, saving time and manpower.

[0080] In an exemplary embodiment, Figure 3 As shown, the distributed antenna system may further include an extension unit 206, the access unit 202 is connected to the extension unit 206 via an optical fiber, and the extension unit 206 is connected to the remote unit 204 via an optical fiber;

[0081] The extension unit 206 is configured to receive the second frame header, and forward the second frame header to the remote unit 204 .

[0082] In a specific implementation, an extension unit can be set between the access unit and the remote unit. The extension unit and the access unit, as well as the extension unit and the remote unit, can be connected through optical fiber. The access unit can send the second frame header, time slot ratio and special subframe ratio to the extension unit through the optical fiber, and the extension unit forwards the second frame header, time slot ratio and special subframe ratio to the remote unit.

[0083] In this embodiment, the second frame header is received by the extension unit and forwarded to the remote unit, so that the communication range of the DAS can be increased and the network coverage can be further expanded.

[0084] In an exemplary embodiment, the access unit includes a first FPGA and a first processor;

[0085] A first FPGA, used to randomly generate a first frame header;

[0086] A first processor, configured to determine a deviation between a position of the first frame header and an actual frame header position of a base station signal;

[0087] The first FPGA is further used to align the first frame header with the actual frame header of the base station signal according to the deviation to obtain the second frame header and send the second frame header;

[0088] The first processor is further used to parse the time slot ratio and the special subframe ratio from the base station signal, and send the time slot ratio and the special subframe ratio.

[0089] The first FPGA may be an FPGA of an access unit, and the first processor may be a CPU of the access unit.

[0090] In the specific implementation, the FPGA of the DAS access unit randomly generates a first frame header, the FPGA and the CPU jointly determine the actual frame header position of the base station signal, the CPU calculates the deviation between the position of the first frame header and the actual frame header position, and transmits the deviation to the FPGA. The FPGA corrects the first frame header according to the deviation to align it with the actual frame header to obtain the second frame header. The FPGA sends the second frame header to the remote unit or extension unit through optical fiber. The CPU can also parse the time slot ratio and special subframe ratio from the base station signal, and send the time slot ratio and special subframe ratio to the remote unit or extension unit through optical fiber.

[0091] In this embodiment, by randomly generating a first frame header, determining the deviation between the position of the first frame header and the actual frame header position of the base station signal, aligning the first frame header with the actual frame header of the base station signal according to the deviation, obtaining a second frame header, sending the second frame header, and parsing the time slot ratio and special subframe ratio from the base station signal, sending the time slot ratio and special subframe ratio, the DAS can automatically determine the 10ms frame header, time slot ratio and special subframe ratio, thereby improving the TDD synchronization efficiency.

[0092] In an exemplary embodiment, the remote unit includes a second FPGA and a second processor;

[0093] The second processor is used to receive the time slot ratio and the special subframe ratio, and configure the time slot ratio and the special subframe ratio in the second FPGA;

[0094] The second FPGA is used to receive the second frame header, determine the switching signal between the low noise amplifier and the power amplifier according to the second frame header, time slot ratio and special subframe ratio, and perform time division duplex synchronization on the distributed antenna system according to the switching signal.

[0095] The second FPGA may be an FPGA of the remote unit, and the second processor may be a CPU of the remote unit.

[0096] In a specific implementation, the remote unit of the DAS may also be provided with an FPGA and a CPU. The CPU of the remote unit recovers the received time slot ratio and special subframe ratio, and configures the FPGA according to the recovered time slot ratio and special subframe ratio. The FPGA may also recover the received second frame header, and generate a switching signal between the low noise amplifier and the power amplifier according to the recovered second frame header and the time slot ratio and special subframe ratio configured by the CPU, and switch between the low noise amplifier and the power amplifier according to the switching signal to achieve TDD synchronization.

[0097] In this embodiment, by receiving the time slot ratio and the special subframe ratio, the time slot ratio and the special subframe ratio are configured in the second FPGA, the second frame header is received, and the switching signal between the low noise amplifier and the power amplifier is determined according to the second frame header, the time slot ratio and the special subframe ratio. The distributed antenna system is synchronized for time division duplexing according to the switching signal, so that the DAS can automatically perform TDD synchronization according to the determined 10ms frame header, time slot ratio and special subframe ratio, thereby improving the TDD synchronization efficiency.

[0098] In order to facilitate those skilled in the art to have a deeper understanding of the embodiments of the present application, a specific example will be described below.

[0099] In order to solve the problems of high cost and complicated station opening of the TDD synchronization function of the digital DAS system, this application proposes a TDD automatic synchronization method for the digital DAS system. Based on the current digital DAS system architecture, this method realizes the TDD automatic synchronization function of the digital DAS system through FPGA and processor (monitoring + algorithm), which can reduce costs, improve station opening speed and reliability, and reduce engineering manpower investment.

[0100] In an exemplary embodiment, Figure 2 As shown, a digital DAS system TDD automatic synchronization system is provided, including an access unit 202 and a remote unit 204. The digital DAS system TDD automatic synchronization system can also be as shown in FIG. Figure 3 As shown, it includes an access unit 202, an extension unit 206 and a remote unit 204.

[0101] refer to Figure 4The access unit 202 may include a radio frequency module, a processor module, an FPGA, a power module, a flash memory (FLASH), a double data rate synchronous dynamic random access memory (Double Data Rate Synchronous Dynamic Random Access Memory, which may be abbreviated as DDR), an optical interface, a network port, an indicator light, and the like.

[0102] The access unit 202 mainly implements the processing and digital-to-analog conversion of radio frequency signals, automatically scans and locks the SSB frequency of the base station, calculates the 10ms frame header of the base station, generates a 10ms frame header by itself, and aligns with the base station;

[0103] At the same time, by counting the deviation of the 10ms frame header, it is converted into a clock deviation, so as to adjust the voltage and lock the frequency of the clock of the access unit 202, so that the clock of the access unit 202 is synchronized with the clock of the base station with high precision.

[0104] Analyze the time slot ratio and special subframe ratio of the base station; broadcast the 10ms frame header, time slot ratio and special subframe ratio aligned with the base station to the extension unit 206 through the optical fiber.

[0105] The FPGA and algorithm software of the access unit 202 can simultaneously support the synchronization of multiple frequency bands, the generation of 10ms frame headers and time slot ratios, and the analysis of special subframe ratios, thereby realizing TDD automatic synchronization of digital DAS systems in multiple frequency bands.

[0106] The extension unit 206 mainly includes a processor module, a power module, an FPGA, a flash memory (FLASH), a double rate synchronous dynamic random access memory (DDR), an optical interface, a network port, an indicator light, and the like.

[0107] The extension unit 206 mainly receives the 10ms frame header, time slot ratio, and special subframe ratio parameters of the access unit 202 , and broadcasts and forwards them to the remote unit 204 .

[0108] The remote unit 204 mainly includes a processor module, an FPGA, a power module, a power amplifier and a low noise amplifier module, a flash memory (FLASH), a double rate synchronous dynamic random access memory (DDR), an optical interface, a network port, an indicator light, and the like.

[0109] The remote unit 204 mainly receives the 10ms frame header, time slot ratio, and special subframe ratio parameters of the extension unit 206, and calculates the switching points of the power amplifier and the low noise amplifier, thereby realizing the synchronization of the system's TDD receiving and transmitting signals with the base station's signals.

[0110] The TDD automatic synchronization method of the above-mentioned digital DAS system saves 4G / 5G modules, can effectively reduce system costs, and is convenient for project commissioning. It does not require knowing the parameters of the base station, nor is it necessary to configure parameters such as time slot ratio and special subframe ratio on the digital DAS system, thus reducing manpower investment.

[0111] By aligning the randomly generated 10ms frame header with the base station frame header, the synchronization process can be made more stable and reliable, while improving the site opening speed and parameter accuracy. In addition, when the base station signal fades for a short time or there is no signal output for a short time, the entire synchronization process can be kept stable without signal cutting.

[0112] In addition, since the remote unit only needs to generate a synchronous switch, the TDD synchronization complexity at the remote end is greatly reduced.

[0113] In an exemplary embodiment, referring to Figure 5 The access unit of the TDD automatic synchronization method of the digital DAS system can perform an SSB frequency point locking process, specifically including:

[0114] Step S301: After the access unit is powered on, it receives the radio frequency signal of the base station through the feeder (or antenna). After the radio frequency module processes the signal and performs analog-to-digital conversion, it forwards the digital signal to the FPGA. After the FPGA processes the signal, it forwards it to the algorithm software.

[0115] Step S302: The monitoring software calculates the SSB frequency point in the frequency band according to the 3GPP protocol, configures it to the FPGA, and performs frequency shifting. The algorithm software running in the CPU receives data from the FPGA, and the FPGA and the algorithm software jointly calculate whether they can be synchronized.

[0116] Step S303, FPGA gives a synchronization status indication;

[0117] Step S304, monitor and determine whether synchronization is achieved. If not, loop to calculate the next SSB frequency point; if synchronization is achieved, lock the current SSB frequency point.

[0118] In an exemplary embodiment, referring to Figure 6 After completing the SSB frequency point locking in the above-mentioned digital DAS system TDD automatic synchronization method, the access unit may further perform the following steps:

[0119] Step S401, FPGA randomly generates continuous 10ms frame headers (first frame header);

[0120] Step S402, FPGA and algorithm software cooperate to calculate the data of the currently locked SSB frequency point to determine the precise position (actual frame header position) of the current base station 10ms frame header;

[0121] Step S403, the algorithm software calculates the deviation between the 10ms frame header position generated by the FPGA and the 10ms frame header position of the base station;

[0122] Step S404, the FPGA corrects the self-generated 10ms frame header so that the self-generated 10ms frame header is accurately aligned with the 10ms frame header of the base station;

[0123] Step S405, FPGA outputs the 10ms frame header (second frame header) aligned with the base station in real time; at the same time, FPGA counts the number of points of the 10ms frame header in real time, and the monitoring software reads the number of points of the 10ms frame header counted by FPGA, compares it with the actual number of points of the 10ms frame header, calculates the difference of the 10ms frame header, and calculates and converts it into clock deviation, and then adjusts the voltage and locks the frequency of the clock of the access unit, so that the clock of the access unit is synchronized with the clock of the base station with high precision. Even if the signal of the base station fades for a short time or there is no signal output, FPGA can always maintain a stable output of the 10ms frame header, ensuring that the remote unit will not have a signal cutting problem during the whole process;

[0124] When there are multiple TDD carriers in a base station, even if the currently synchronized carrier loses signal, the stable 10ms frame header output will not affect the synchronization switching of other carriers. When another carrier is synchronized again, the 10ms frame header of another carrier will be aligned.

[0125] Step S406, the algorithm software receives the data from the FPGA, parses the time slot ratio and special subframe ratio of the currently locked SSB frequency point, and forwards the time slot ratio and special subframe ratio to the monitoring system through a shared memory;

[0126] Step S407, the access unit forwards the 10ms frame header (second frame header), time slot ratio and special subframe ratio aligned with the base station to the extension unit through the optical fiber.

[0127] In an exemplary embodiment, referring to Figure 7 , the remote unit of the digital DAS system TDD automatic synchronization method can perform the following steps:

[0128] Step S501, the remote unit monitors and recovers the time slot ratio and special subframe ratio from the extension unit, and configures the FPGA;

[0129] Step S502, FPGA recovers the 10ms frame header (second frame header) from the extension unit;

[0130] In step S503, the FPGA generates switch signals for the power amplifier (PA) and the low noise amplifier (LNA) respectively according to the 10ms frame header (second frame header), time slot ratio, special subframe ratio, and the maximum delay of the system, and outputs them to the switches of the PA and LNA. The remote end only needs to generate a synchronous switch, which greatly reduces the TDD synchronization complexity of the remote end.

[0131] At this point, the TDD synchronization of the entire digital DAS system is completed.

[0132] In an exemplary embodiment, the above-mentioned digital DAS system TDD automatic synchronization method and system are only for the example of a typical networked digital DAS system, such as Figure 2 As shown, it may also only include the access unit 202 and the remote unit 204. The access unit 202 directly forwards the 10ms frame header, time slot ratio, and special subframe ratio aligned with the base station to the remote unit 204 through the optical fiber.

[0133] In an exemplary embodiment, the above-mentioned digital DAS system TDD automatic synchronization method and system can be applied to any TDD system.

[0134] In an exemplary embodiment, the above-mentioned digital DAS system TDD automatic synchronization method and system, the access unit 202 supports multiple frequency bands and signal inputs of different standards, and the FPGA and algorithm software can simultaneously support the synchronization of multiple frequency bands of different standards, and output the 10ms frame header of each frequency band, different time slot ratios and special subframe ratios. For example, the access unit 202 simultaneously receives signals from four base stations of different standards, A, B, C, and D. The access unit 202 can simultaneously synchronize the SSB frequency points of the A, B, C, and D base stations, and respectively generate four 10ms frame headers aligned with the A, B, C, and D base stations, as well as four time slot ratios and special subframe ratios.

[0135] In an exemplary embodiment, Figure 8 As shown, a synchronization method is provided, and the method is applied to DAS as an example for description, including the following steps:

[0136] Step S601, determining the SSB frequency synchronized with the base station signal, locking the SSB frequency, and randomly generating a first frame header corresponding to the SSB frequency;

[0137] Step S602, determining a deviation between the position of the first frame header and the actual frame header position of the base station signal;

[0138] Step S603, performing a deviation correction process on the first frame header according to the deviation, aligning the first frame header with the actual frame header of the base station signal, and obtaining a second frame header;

[0139] Step S604, determining a switching signal between a low noise amplifier and a power amplifier according to the second frame header, and the time slot ratio and the special subframe ratio parsed from the base station signal;

[0140] Step S605: performing time division duplex synchronization on the distributed antenna system according to the switching signal.

[0141] In a specific implementation, DAS can receive base station signals, determine the SSB frequency that can synchronize the base station signals, lock the SSB frequency, and randomly generate a first frame header for the SSB frequency. DAS can also determine the actual frame header position of the base station signal, and count the deviation between the position of the first frame header and the actual frame header position, correct the first frame header according to the deviation, align the corrected first frame header with the actual frame header of the base station signal, and use the corrected first frame header as the second frame header. DAS can also parse the time slot ratio and special subframe ratio from the base station signal, determine the switching signal according to the second frame header, time slot ratio and special subframe ratio, and switch between the low noise amplifier and the power amplifier according to the switching signal to achieve TDD synchronization of DAS.

[0142] The above synchronization method determines the SSB frequency synchronized with the base station signal, locks the SSB frequency, randomly generates a first frame header corresponding to the SSB frequency, determines the deviation between the position of the first frame header and the actual frame header position of the base station signal, performs deviation correction processing on the first frame header according to the deviation, aligns the first frame header with the actual frame header of the base station signal to obtain a second frame header, determines the switching signal between the low noise amplifier and the power amplifier according to the second frame header, and the time slot ratio and special subframe ratio parsed from the base station signal, and performs time division duplex synchronization on the distributed antenna system according to the switching signal; the actual frame header position of the base station signal can be used to correct the first frame header automatically generated by the DAS to obtain the TDD synchronization frame header of the DAS, that is, the second frame header, and directly perform TDD synchronization according to the second frame header. Since no 4G / 5G module is required, the cost can be effectively reduced, and there is no need to configure parameters when opening the station, which also reduces the complexity of the station opening operation during TDD synchronization, saving time and manpower.

[0143] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0144] Based on the same inventive concept, the embodiment of the present application also provides a synchronization device for implementing the synchronization method involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in one or more synchronization device embodiments provided below can refer to the limitations on the synchronization method above, and will not be repeated here.

[0145] In an exemplary embodiment, Fig. 9 As shown, a synchronization device is provided, including: a generation module 702, a correction module 704 and a synchronization module 706, wherein:

[0146] A generating module 702 is used to generate a first frame header of a distributed antenna system; the distributed antenna system is used to forward base station signals;

[0147] A correction module 704, configured to perform correction processing on the first frame header according to an actual frame header position of the base station signal to obtain a second frame header of the distributed antenna system;

[0148] The synchronization module 706 is used to perform time division duplex synchronization on the distributed antenna system according to the second frame header.

[0149] In an exemplary embodiment, the above-mentioned generation module 702 is also used to determine the SSB frequency that can be synchronized with the base station signal; lock the SSB frequency, and randomly generate the first frame header corresponding to the SSB frequency.

[0150] In an exemplary embodiment, the above-mentioned correction module 704 is also used to determine the deviation between the position of the first frame header and the actual frame header position of the base station signal; based on the deviation, the first frame header is aligned with the actual frame header of the base station signal to obtain the second frame header.

[0151] In an exemplary embodiment, the above-mentioned synchronization device also includes a clock synchronization module, which is used to determine the difference between the number of points in the first frame header and the actual number of points in the frame header of the base station signal; based on the difference, determine the clock deviation of the distributed antenna system relative to the base station; based on the clock deviation, perform clock synchronization on the distributed antenna system.

[0152] In an exemplary embodiment, the synchronization module 706 is further used to parse the time slot ratio and the special subframe ratio from the base station signal; determine the switching signal between the low noise amplifier and the power amplifier according to the second frame header, the time slot ratio and the special subframe ratio; and perform time division duplex synchronization on the distributed antenna system according to the switching signal.

[0153] In an exemplary embodiment, there are multiple groups of the second frame header, the time slot ratio and the special subframe ratio, which correspond to different communication standards and / or different SSB frequencies.

[0154] Each module in the above synchronization device can be implemented in whole or in part by software, hardware or a combination thereof. Each module can be embedded in or independent of a processor in a communication device in the form of hardware, or can be stored in a memory in the communication device in the form of software, so that the processor can call and execute operations corresponding to each module.

[0155] In an exemplary embodiment, a communication device is provided, which may be a distributed antenna system. The communication device includes a processor, a memory, an input / output interface (I / O for short) and a communication interface. The processor, the memory and the input / output interface are connected via a system bus, and the communication interface is connected to the system bus via the input / output interface. The processor of the communication device is used to provide computing and control capabilities. The memory of the communication device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the communication device is used to store synchronization data. The input / output interface of the communication device is used to exchange information between the processor and an external device. The communication interface of the communication device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, a synchronization method is implemented.

[0156] Those skilled in the art will understand that the above structure is merely a block diagram of a partial structure related to the scheme of the present application, and does not constitute a limitation on the communication device to which the scheme of the present application is applied. The specific communication device may include more or fewer components than shown in the figure, or combine certain components, or have a different arrangement of components.

[0157] In one embodiment, a communication device is further provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the steps in the above method embodiments when executing the computer program.

[0158] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments are implemented.

[0159] In one embodiment, a computer program product is provided, including a computer program, which implements the steps in the above method embodiments when executed by a processor.

[0160] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant regulations.

[0161] A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., but are not limited to this.

[0162] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0163] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A synchronization method, characterized in that: The method comprises: Generate a first frame header of a distributed antenna system; the distributed antenna system is used to forward base station signals; According to the actual frame header position of the base station signal, the first frame header is subjected to a deflection correction process to obtain a second frame header of the distributed antenna system; According to the second frame header, time division duplex synchronization is performed on the distributed antenna system.

2. The synchronization method according to claim 1, characterized in that: The generating a first frame header of the distributed antenna system comprises: Determine a synchronization signal block SSB frequency point that can achieve synchronization with the base station signal; The SSB frequency is locked, and the first frame header corresponding to the SSB frequency is randomly generated.

3. The synchronization method according to claim 1, characterized in that: The step of performing a deflection correction process on the first frame header according to the actual frame header position of the base station signal to obtain a second frame header of the distributed antenna system includes: Determine a deviation between the position of the first frame header and an actual frame header position of the base station signal; According to the deviation, the first frame header is aligned with an actual frame header of the base station signal to obtain the second frame header.

4. The synchronization method according to claim 1, characterized in that: The method further comprises: Determine a difference between the number of points in the first frame header and the actual number of points in the frame header of the base station signal; Determining a clock deviation of the distributed antenna system relative to the base station based on the difference; The distributed antenna system is clock synchronized according to the clock deviation.

5. The synchronization method according to claim 1, characterized in that: The step of performing time division duplex synchronization on the distributed antenna system according to the second frame header includes: Parsing the time slot ratio and the special subframe ratio from the base station signal; Determining a switching signal between a low noise amplifier and a power amplifier according to the second frame header, the time slot ratio and the special subframe ratio; According to the switching signal, time division duplex synchronization is performed on the distributed antenna system.

6. The synchronization method according to claim 5, characterized in that: There are multiple groups of the second frame header, the time slot ratio and the special subframe ratio, which correspond to different communication standards and / or different SSB frequencies respectively.

7. A synchronization device, characterized in that: The device comprises: A generating module, used to generate a first frame header of a distributed antenna system; the distributed antenna system is used to forward base station signals; A correction module, configured to perform correction processing on the first frame header according to an actual frame header position of the base station signal to obtain a second frame header of the distributed antenna system; A synchronization module is used to perform time division duplex synchronization on the distributed antenna system according to the second frame header.

8. A distributed antenna system, characterized in that: The distributed antenna system comprises an access unit and a remote unit, the access unit is connected to the remote unit via an optical fiber, and the distributed antenna system is used to forward base station signals; The access unit is configured to generate a first frame header of the distributed antenna system, perform a deflection correction process on the first frame header according to an actual frame header position of the base station signal, obtain a second frame header of the distributed antenna system, and send the second frame header; The remote unit is used to receive the second frame header and perform time division duplex synchronization on the distributed antenna system according to the second frame header.

9. The distributed antenna system according to claim 8, characterized in that: The distributed antenna system further comprises an extension unit, the access unit is connected to the extension unit via an optical fiber, and the extension unit is connected to the remote unit via an optical fiber; The extension unit is used to receive the second frame header and forward the second frame header to the remote unit.

10. The distributed antenna system according to claim 8 or 9, characterized in that: The access unit includes a first field programmable gate array FPGA and a first processor; The first FPGA is used to randomly generate the first frame header; The first processor is used to determine the deviation between the position of the first frame header and the actual frame header position of the base station signal; The first FPGA is further used to align the first frame header with an actual frame header of the base station signal according to the deviation to obtain the second frame header, and send the second frame header; The first processor is further configured to parse out a time slot ratio and a special subframe ratio from the base station signal, and send the time slot ratio and the special subframe ratio.

11. The distributed antenna system according to claim 10, characterized in that: The remote unit includes a second FPGA and a second processor; The second processor is used to receive the time slot ratio and the special subframe ratio, and configure the time slot ratio and the special subframe ratio in the second FPGA; The second FPGA is used to receive the second frame header, determine the switching signal between the low noise amplifier and the power amplifier according to the second frame header, the time slot ratio and the special subframe ratio, and perform time division duplex synchronization on the distributed antenna system according to the switching signal.

12. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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