Advanced encryption standard algorithm kernel implementation method, device, equipment and medium

Abstract

The invention discloses an advanced encryption standard algorithm core implementation method and device, equipment and a medium, and relates to the technical field of computers, the advanced encryption standard algorithm core implementation device comprises a control module, an operation module and a storage module, and the method comprises the steps that a key extension enable signal is determined through the control module according to the length of an original key, determining a first operation round and a second operation round in an operation mode corresponding to the key expansion enable signal; the method comprises the following steps: performing nonlinear transformation on an original key through an operation module, performing key expansion operation of a first operation round on the key after nonlinear transformation to obtain a round key, and performing encryption and decryption operation of a second operation round on to-be-processed data according to the round key to obtain encrypted and decrypted data; and storing the round key and the encrypted and decrypted data through a storage module. According to the invention, the overall circuit area requirement is greatly reduced, the manufacturing cost of a chip is reduced, and the information security of an advanced encryption standard algorithm core is remarkably improved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to an advanced encryption standard algorithm core implementation method, device, equipment and medium. Background Art

[0002] In the field of information security in computer science, the AES (Advanced Encryption Standard) algorithm is a widely used symmetric encryption algorithm, usually implemented in hardware in the form of an AES algorithm core, which is responsible for performing functions such as encryption, decryption, and key expansion.

[0003] The AES algorithm implements encryption through a multi-round substitution-permutation network (SPN) structure. Each round of operations includes the following parts: byte replacement, row shift, column mixing and round key addition. The AES algorithm supports multiple key lengths, the most common of which are 128 bits, 192 bits and 256 bits. The longer the key length, the higher the encryption strength, but the corresponding computing resource consumption will also increase. The traditional AES algorithm core architecture has the following defects: (1) Since the existing AES algorithm core contains three types of operation units, its key expansion unit and encryption and decryption unit contain multiple round function operation units and S-box (Substitution Box) units, which will occupy a large amount of circuit area, which is a great limitation for embedded systems with limited resources. (2) Multiple round function operation units and S-box units contain a large amount of combinational logic, which requires a large number of logic gate circuits and control signals to implement, which not only increases the complexity of circuit design, but also leads to higher power consumption, thereby increasing the manufacturing cost of the chip. (3) The existing circuit directly uses the input key for calculation. Once the key information is leaked, outsiders can use the key to decrypt the ciphertext and obtain the plaintext, resulting in information theft. Therefore, the above problem needs to be solved urgently. Summary of the invention

[0004] In view of this, the purpose of the present invention is to provide an advanced encryption standard algorithm core implementation method, device, equipment and medium, which can greatly reduce the overall circuit area requirement, reduce the manufacturing cost of the chip, and significantly improve the information security of the advanced encryption standard algorithm core. The specific scheme is as follows:

[0005] In a first aspect, the present application discloses an advanced encryption standard algorithm core implementation method, which is applied to an advanced encryption standard algorithm core implementation device, the device including a control module, a computing module and a storage module, and the method includes:

[0006] Determine, by a control module, a key expansion enable signal according to the length of the original key, and determine a first operation round and a second operation round in an operation mode corresponding to the key expansion enable signal;

[0007] The original key is nonlinearly transformed by the operation module to obtain a nonlinearly transformed key, and the nonlinearly transformed key is subjected to a key expansion operation of a first operation round to obtain a round key of a corresponding round, and then encryption and decryption operations of a second operation round are performed on the data to be processed according to the round key to obtain corresponding encrypted and decrypted data; wherein the operation module realizes function adaptation under different operation modes by configuring different operation resources;

[0008] The round key and the encryption and decryption data are stored through the storage module.

[0009] Optionally, performing a key expansion operation of a first operation round on the key after the nonlinear transformation to obtain a round key of a corresponding round includes:

[0010] The number of calculated rounds is counted through a counter, and the initial value of the counter is set to 0;

[0011] Performing a key expansion operation on the current input data through the key expansion round function operation unit in the operation module, so as to output a round key corresponding to the current operation round through the key expansion round function operation unit, and adding one to the count value of the counter;

[0012] Wherein, in the first round of key expansion operation, the current input data of the key expansion round function operation unit is the key after non-linear transformation, and in the non-first round of key expansion operation, the current input data of the key expansion round function operation unit is the round key output by the key expansion round function operation unit in the previous round of operation;

[0013] Determine whether the count value of the counter reaches the first operation round;

[0014] If the count value of the counter does not reach the first operation round, jump to the step of performing key expansion operation on the current input data through the key expansion round function operation unit in the operation module until the count value of the counter reaches the first operation round to obtain the round key of the corresponding round.

[0015] Optionally, the round key and the encryption and decryption data are stored by a storage module, including:

[0016] After each round of key expansion operation is completed, the round key of the corresponding round output by the key expansion round function operation unit is stored through the corresponding register in the storage module; wherein the storage module includes multiple registers, and the multiple registers are numbered according to the first operation round.

[0017] Optionally, performing encryption and decryption operations of a second operation round on the data to be processed according to the round key to obtain corresponding encrypted and decrypted data includes:

[0018] Selecting an encryption / decryption round function operation unit for implementing the encryption / decryption operation of the second operation round from the encryption / decryption round function operation unit set in the operation module, and reading a round key of a corresponding round from a corresponding register according to the operation round of the encryption / decryption operation;

[0019] In the first round of encryption and decryption operations, the data to be processed and the round key of the corresponding round are used as the current input data of the first encryption and decryption round function operation unit to obtain the corresponding output result;

[0020] In non-first-round encryption and decryption operations, the output result of the previous round and the round key of the corresponding round are used as the current input data of the current encryption and decryption round function operation unit to obtain the corresponding output result, and the output result of the last encryption and decryption round function operation unit is used as the encryption and decryption data.

[0021] Optionally, during encryption and decryption operations, the encryption and decryption round function operation units in the encryption and decryption round function operation unit set work together in a parallel pipeline operation mode.

[0022] Optionally, a nonlinear transformation is performed on the original key through a calculation module, including:

[0023] Performing nonlinear transformation on the original key through the replacement box unit in the operation module;

[0024] Accordingly, the advanced encryption standard algorithm core implementation method also includes:

[0025] During encryption and decryption operations, the current input data of each encryption and decryption round function operation unit is byte replaced by the replacement box unit.

[0026] Optionally, the replacement box unit includes multiple replacement boxes, and the multiple replacement boxes perform non-linear transformation operations in parallel or perform byte replacement operations in parallel.

[0027] In a second aspect, the present application discloses an advanced encryption standard algorithm core implementation device, comprising:

[0028] A control module, used to determine a key extension enable signal according to the length of the original key, and determine a first operation round and a second operation round in an operation mode corresponding to the key extension enable signal;

[0029] The operation module is used to perform nonlinear transformation on the original key to obtain the nonlinear transformed key, and perform key expansion operation of the first operation round on the nonlinear transformed key to obtain the round key of the corresponding round, and then perform encryption and decryption operation of the second operation round on the data to be processed according to the round key to obtain the corresponding encrypted and decrypted data; wherein the operation module realizes function adaptation under different operation modes by configuring different operation resources;

[0030] The storage module is used to store round keys and encryption and decryption data.

[0031] In a third aspect, the present application discloses an electronic device, comprising:

[0032] Memory, used to store computer programs;

[0033] The processor is used to execute a computer program to implement the aforementioned disclosed advanced encryption standard algorithm core implementation method.

[0034] In a fourth aspect, the present application discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the aforementioned disclosed advanced encryption standard algorithm core implementation method is implemented.

[0035] It can be seen that the present application proposes an advanced encryption standard algorithm core implementation method, which is applied to an advanced encryption standard algorithm core implementation device, the device includes a control module, an operation module and a storage module, and the method includes: determining the key expansion enable signal according to the length of the original key by the control module, determining the first operation round and the second operation round under the operation mode corresponding to the key expansion enable signal; performing nonlinear transformation on the original key by the operation module, performing the key expansion operation of the first operation round on the key after the nonlinear transformation, obtaining the round key of the corresponding round, performing the encryption and decryption operation of the second operation round on the processed data according to the round key, and obtaining the encrypted and decrypted data; the operation module configures different operation resources to realize the function adaptation under different operation modes; and the storage module stores the round key and the encrypted and decrypted data. It can be seen that since the operation module in the present application can realize the function adaptation under different operation modes by configuring different operation resources, the present application does not need to construct multiple independent hardware units for the keys of various operation modes, which greatly reduces the overall circuit area requirement. Since there is no need to construct multiple independent hardware units separately, the present application no longer needs to construct a large amount of combinational logic based on complex logic gate circuits and cumbersome control signals, which significantly reduces the complexity of circuit design, effectively controls circuit power consumption, avoids high power consumption caused by a large amount of combinational logic, and reduces the manufacturing cost of the chip. Furthermore, since the key after nonlinear transformation is difficult to be directly cracked, even if the key information is leaked, it is difficult for outsiders to use it for decryption, which effectively prevents the theft of plaintext information and significantly improves the information security of the Advanced Encryption Standard algorithm core. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0037] Figure 1 This is a schematic diagram of the traditional AES algorithm core architecture;

[0038] Figure 2 A flowchart of an advanced encryption standard algorithm core implementation method disclosed in this application;

[0039] Figure 3 A schematic diagram of a specific advanced encryption standard algorithm core implementation method disclosed in this application;

[0040] Figure 4 A schematic diagram of the structure of an advanced encryption standard algorithm core implementation device disclosed in this application;

[0041] Figure 5 This is a structural diagram of an electronic device disclosed in this application. DETAILED DESCRIPTION

[0042] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0043] The traditional AES algorithm core architecture is as follows Figure 1 As shown in the figure, when the key and the data to be processed are input into the AES algorithm core, the top-level control logic determines the key length and selects the corresponding algorithm unit according to the key length. If the key length is 128 bits, the top-level control logic pulls up Enable; if the key length is 192 bits, the top-level control logic is pulled high Enable; when the key length is 256 bits, the top-level control logic is pulled high After that, the corresponding unit starts to perform key expansion after receiving the signal from the top-level control logic. After the key expansion is completed, it starts to encrypt or decrypt the data to be processed and outputs the processed ciphertext or plaintext. For example, if If the key is pulled high, the key expansion unit performs 10 rounds of round function operations; if If the enable is pulled high, the key expansion unit performs 8 rounds of round function operations; if If the enable is pulled high, the key expansion unit performs 7 rounds of round function operations. If the enable is pulled high, the encryption and decryption unit performs 10 round function operations; if If the enable is pulled high, the encryption and decryption unit performs 12 rounds of round function operations; if If the enable bit is pulled high, the encryption and decryption unit performs 14 rounds of round function operations.

[0044] The AES algorithm implements encryption through a multi-round permutation-permutation network structure. The AES algorithm has the following defects: (1) The existing AES algorithm core contains three types of operation units, and its key expansion unit and encryption and decryption unit contain multiple round function operation units and S-box units, which will occupy a large amount of circuit area, which is a great limitation for embedded systems with limited resources. (2) Multiple round function operation units and S-box units contain a large amount of combinational logic, which requires a large number of logic gate circuits and control signals to implement, which not only increases the complexity of circuit design, but also leads to higher power consumption, thereby increasing the manufacturing cost of the chip. (3) The existing circuit directly uses the input key for calculation. Once the key information is leaked, outsiders can use the key to decrypt the ciphertext to obtain the plaintext, resulting in information theft.

[0045] To this end, the embodiment of the present application proposes an advanced encryption standard algorithm core implementation solution, which can greatly reduce the overall circuit area requirement, reduce the manufacturing cost of the chip, and significantly improve the information security of the advanced encryption standard algorithm core.

[0046] The present application embodiment discloses an advanced encryption standard algorithm core implementation method, which is applied to an advanced encryption standard algorithm core implementation device, the device includes a control module, a computing module and a storage module, see Figure 2 As shown, the method includes:

[0047] Step S11: determining a key expansion enable signal according to the length of the original key through the control module, and determining a first operation round and a second operation round in an operation mode corresponding to the key expansion enable signal.

[0048] In this embodiment, the control module determines the key expansion enable signal according to the original key length, and determines the first operation round and the second operation round in the operation mode corresponding to the key expansion enable signal. For example, if the length of the original key is 128 bits, the control module pulls up the key based on the top-level control logic. Enable; if the length of the original key is 192 bits, the control module is pulled high based on the top-level control logic Enable; if the length of the original key is 256 bits, the control module is pulled high based on the top-level control logic Enable. If the key is pulled high, the key expansion unit (including a key expansion round function operation unit) performs 10 rounds of round function operations, and the first operation round is 10; if If the key is enabled, the key expansion unit performs 8 rounds of round function operations, and the first round of operations is 8; if If the enable is pulled high, the key expansion unit performs 7 rounds of round function operations, and the first round of operations is 7. If the enable is pulled high, the encryption and decryption unit (including multiple encryption and decryption round function operation units, such as 14 encryption and decryption round function operation units) performs 10 round function operations, and the second operation round is 10; if If the enable is pulled high, the encryption and decryption unit performs 12 rounds of round function operations, and the second round of operations is 12; if If the enable is pulled high, the encryption and decryption unit performs 14 rounds of round function operations, and the second operation round is 14.

[0049] Step S12: Perform a nonlinear transformation on the original key through the operation module to obtain a nonlinearly transformed key, and perform a key expansion operation on the nonlinearly transformed key in the first operation round to obtain a round key of the corresponding round, and then perform encryption and decryption operations on the processed data in the second operation round according to the round key to obtain corresponding encrypted and decrypted data; wherein the operation module configures different operation resources to achieve function adaptation under different operation modes.

[0050] In this embodiment, the original key is nonlinearly transformed by the replacement box unit in the operation module. It should be noted that the replacement box unit includes multiple replacement boxes, and the multiple replacement boxes perform nonlinear transformation operations in parallel. For example, the replacement box unit is composed of 4 parallel replacement boxes, one replacement box can only process 8 bits of data, and 4 parallel replacement boxes can process 32 bits of data each time, thereby ensuring the performance of the AES algorithm core. In this way, on the one hand, the nonlinear transformation breaks the linear relationship between input and output, making the result of the original key after transformation difficult to predict. Since the key after nonlinear transformation is difficult to be directly cracked, even if the key information is leaked, it is difficult for outsiders to use it for decryption, which effectively prevents the theft of plaintext information and significantly improves the information security of the advanced encryption standard algorithm core. On the other hand, compared with the processing of a single replacement box one by one, the nonlinear transformation operation is performed in parallel by multiple replacement boxes, which speeds up the nonlinear transformation speed of the original key, improves the nonlinear transformation efficiency of the original key, and ensures the performance of the AES algorithm core.

[0051] Further, the key expansion operation of the first operation round is performed on the key after nonlinear transformation to obtain the round key of the corresponding round. Specifically, the key expansion unit receives the enable signal of the top-level control logic and the key after nonlinear transformation through the key expansion control logic. According to the enable signal, the key expansion unit runs a corresponding number of times under the corresponding algorithm mode. Only one key expansion round function operation unit is used in the key expansion unit. After a round of operation, the generated round key is output to the encryption and decryption unit, and the operation result of the previous round is used as input data, and then the key expansion round function operation unit is used to perform the next round of operation. It can be realized that a key expansion round function operation combination logic is reused to realize the key expansion function. In this way, it is avoided to design a key expansion round function operation unit separately for each round of operation, which significantly reduces the hardware resources required for the circuit and saves the chip area.

[0052] Specifically, the number of rounds of operation is counted by a counter, and the initial value of the counter is set to 0. The key expansion operation is performed on the current input data by the key expansion round function operation unit in the operation module, so that the round key corresponding to the current operation round is output by the key expansion round function operation unit, and the count value of the counter is increased by one; wherein, in the first round of key expansion operation, the current input data of the key expansion round function operation unit is the key after nonlinear transformation, and in the non-first round of key expansion operation, the current input data of the key expansion round function operation unit is the round key output by the key expansion round function operation unit in the previous round of operation. Further, it is determined whether the count value of the counter reaches the first operation round; if the count value of the counter does not reach the first operation round, it jumps to the step of performing the key expansion operation on the current input data by the key expansion round function operation unit in the operation module until the count value of the counter reaches the first operation round, and the round key of the corresponding round is obtained.

[0053] It should be noted that after the key expansion is completed, a key expansion completion signal will be issued. When the encryption and decryption unit receives the key expansion completion signal, it starts to perform corresponding encryption and decryption operations.

[0054] In addition, each time a round of key expansion operation is completed, the round key of the corresponding round output by the key expansion round function operation unit is stored through the corresponding register in the storage module; wherein the storage module includes multiple registers, and the multiple registers are numbered according to the first operation round. That is, when the key expansion round function operation unit completes a round of key expansion operation and generates the round key of the corresponding round, these round keys are stored through the multiple registers in the storage module. Exemplarily, the first register stores the round key obtained by the first round of key expansion operation, the second register stores the round key obtained by the second round of operation, and so on. This numbering method provides convenience for accurately and quickly calling the round key of the corresponding round in the subsequent encryption and decryption operation, ensures that the system can use the round key generated in each round in an orderly manner, and improves the operation efficiency and accuracy of the entire encryption system. Exemplarily, when performing the fifth round of encryption and decryption operations, the system can directly access the fifth register to obtain the round key of the fifth round, avoiding the time cost of searching for round keys in many storage units, and improving the speed of the encryption and decryption process.

[0055] Further, a second round of encryption and decryption operations are performed on the data to be processed according to the round key to obtain corresponding encrypted and decrypted data. Specifically, the encryption and decryption unit receives an enable signal of the top-level control logic, a key expansion completion signal, and the data to be processed through the encryption and decryption control logic, and according to the enable signal, the encryption and decryption unit runs a corresponding number of times in a corresponding algorithm mode.

[0056] Specifically, from the set of encryption and decryption round function operation units in the operation module, select an encryption and decryption round function operation unit for implementing the encryption and decryption operation of the second operation round, and read the round key of the corresponding round from the corresponding register according to the operation round of the encryption and decryption operation; in the first round of encryption and decryption operation, use the data to be processed and the round key of the corresponding round as the current input data of the first encryption and decryption round function operation unit to obtain the corresponding output result; in non-first round encryption and decryption operation, use the output result of the previous round and the round key of the corresponding round as the current input data of the current encryption and decryption round function operation unit to obtain the corresponding output result, and use the output result of the last encryption and decryption round function operation unit as the encryption and decryption data. Exemplarily, the encryption and decryption round function operation unit contains 14 round function operation units. On the one hand, the round function operation unit of the corresponding round can be run according to the enable information of the encryption and decryption control logic. For example, when running in In operation mode, the encryption and decryption round function operation unit will only perform 10 rounds of operation. Round function operation unit 10 will be responsible for outputting the ciphertext or plaintext after the operation is completed. On the other hand, during encryption and decryption operations, each encryption and decryption round function operation unit in the encryption and decryption round function operation unit set works together in a parallel pipeline operation mode. That is, after the first round of round function operation of a group of data is completed, the encryption and decryption control logic can input another group of data into the encryption and decryption round function operation unit to perform the first round of round function operation, thereby realizing parallel pipeline operation of each round of round function, thus ensuring the output performance of the AES algorithm core.

[0057] In addition, during encryption and decryption operations, the current input data of each encryption and decryption round function operation unit is byte replaced by a replacement box unit. The replacement box unit is a replacement unit for performing nonlinear transformation on the original key, that is, the same replacement box unit is reused to perform nonlinear transformation of the original key and perform byte replacement of the current input data. In this way, reusing the same replacement box unit can significantly reduce the occupation of hardware resources, and can effectively reduce the area of ​​the circuit, reducing the complexity of the hardware circuit.

[0058] Step S13: storing the round key and the encryption and decryption data via a storage module.

[0059] In this embodiment, the storage module is used to store the round key obtained by each round of key expansion operation. In addition, the storage module in this embodiment also stores the corresponding encryption and decryption data for subsequent use.

[0060] Figure 3 The figure is a schematic diagram of a specific implementation method of the advanced encryption standard algorithm core. The original key is used as the key information input for encryption and decryption, and is the basis of the entire encryption process. The data to be processed is the data that needs to be encrypted or decrypted, and enters the system together with the original key. The top-level control logic receives the original key and the data to be processed, and outputs a control signal, which is used to determine the key expansion and encryption and decryption operation rounds. The key expansion unit receives the nonlinearly transformed key output by the replacement box unit, and performs a key expansion operation through the key expansion round function operation unit to obtain a round key for subsequent encryption and decryption round function operation units. In addition to performing a nonlinear transformation on the original key, the replacement box unit also performs byte replacement on the input data during the round function operation process. The encryption and decryption unit receives the data to be processed and the control signal, and uses multiple encryption and decryption round function operation units to perform encryption and decryption operations on the data to be processed according to the round key. It can be seen that in this embodiment, only one key expansion round function operation unit is used in the key expansion unit, so that the reuse of the round function operation unit can be realized. Using multiple encryption and decryption round function operation units in the encryption and decryption unit can realize parallel encryption and decryption operations.

[0061] In addition, the present embodiment can also dynamically adjust the resource allocation of the operation module according to the system load and performance indicators. For example, when the system is in a high-load state, the operation resources of certain non-critical tasks can be reduced according to the performance indicators, and more resources can be invested in important encryption and decryption operations to ensure the performance and processing speed of critical tasks. In addition, in view of the fact that the security is improved after the nonlinear transformation of the original key, the present embodiment can further design a more complete key management mechanism, for example, regularly updating the original key, and combining nonlinear transformation and key expansion operations to ensure the timeliness and security of the key. For another example, according to different users, different original keys are used, and personalized key management is achieved through the functional adaptation of the operation module, thereby improving the security protection capability of the entire system.

[0062] In summary, this application proposes a low-area AES algorithm core, which has the following beneficial effects: first, it reduces the circuit area of ​​the algorithm core. Through the analysis of the mathematical model of the AES algorithm, it can be seen that: , and The round function calculation structures of the encryption and decryption functions of the three algorithms are exactly the same, and the round function calculation structures used in each round of the key expansion function are also exactly the same. Based on this, the present application reuses an operation unit, which includes 14 parallel pipelined round function calculation units (for encryption and decryption) and one round function operation unit (for key expansion). While ensuring the performance of the AES algorithm core, it realizes the traditional technology that requires three operation units with much larger areas than the operation unit used in the present application. , and The encryption and decryption functions and key expansion functions of the three algorithms significantly reduce the area of ​​the entire system. This makes the algorithm core applicable to resource-constrained systems, allowing more embedded devices to use the AES algorithm for secure data transmission and storage, and improving the security of the device. Secondly, the present application reduces the complexity of circuit design, power consumption and manufacturing cost. In addition to reusing an operation unit, the key expansion round function operation unit and the encryption and decryption round function operation unit use the same replacement box unit, which greatly reduces the use of combinational logic in the circuit, further reduces the complexity and power consumption of the circuit design, and greatly reduces the manufacturing cost of the chip, which has important economic significance for large-scale production. Furthermore, the present application enhances the security of the algorithm core circuit. The present application sends the original key to the replacement box unit for nonlinear transformation, and uses the transformed data as the key of the algorithm core. Even if the outside world intercepts the input key, it cannot directly crack the encrypted ciphertext through the key.

[0063] It can be seen that the present application proposes an advanced encryption standard algorithm core implementation method, which is applied to an advanced encryption standard algorithm core implementation device, the device includes a control module, an operation module and a storage module, and the method includes: determining the key expansion enable signal according to the length of the original key by the control module, determining the first operation round and the second operation round under the operation mode corresponding to the key expansion enable signal; performing nonlinear transformation on the original key by the operation module, performing the key expansion operation of the first operation round on the key after the nonlinear transformation, obtaining the round key of the corresponding round, performing the encryption and decryption operation of the second operation round on the processed data according to the round key, and obtaining the encrypted and decrypted data; the operation module configures different operation resources to realize the function adaptation under different operation modes; and the storage module stores the round key and the encrypted and decrypted data. It can be seen that since the operation module in the present application can realize the function adaptation under different operation modes by configuring different operation resources, the present application does not need to construct multiple independent hardware units for the keys of various operation modes, which greatly reduces the overall circuit area requirement. Since there is no need to construct multiple independent hardware units separately, the present application no longer needs to construct a large amount of combinational logic based on complex logic gate circuits and cumbersome control signals, which significantly reduces the complexity of circuit design, effectively controls circuit power consumption, avoids high power consumption caused by a large amount of combinational logic, and reduces the manufacturing cost of the chip. Furthermore, since the key after nonlinear transformation is difficult to be directly cracked, even if the key information is leaked, it is difficult for outsiders to use it for decryption, which effectively prevents the theft of plaintext information and significantly improves the information security of the Advanced Encryption Standard algorithm core.

[0064] Correspondingly, the present application also discloses an advanced encryption standard algorithm core implementation device, see Figure 4 As shown, the device comprises:

[0065] A control module 11, configured to determine a key expansion enable signal according to the length of the original key, and determine a first operation round and a second operation round in an operation mode corresponding to the key expansion enable signal;

[0066] The operation module 12 is used to perform a nonlinear transformation on the original key to obtain a nonlinearly transformed key, and perform a key expansion operation of the first operation round on the nonlinearly transformed key to obtain a round key of a corresponding round, and then perform an encryption and decryption operation of the second operation round on the data to be processed according to the round key to obtain corresponding encrypted and decrypted data; wherein the operation module realizes function adaptation under different operation modes by configuring different operation resources;

[0067] The storage module 13 is used to store round keys and encryption and decryption data.

[0068] Among them, for more specific working processes of the above-mentioned modules, please refer to the corresponding contents disclosed in the aforementioned embodiments, which will not be repeated here.

[0069] It can be seen that the present application proposes an advanced encryption standard algorithm core implementation method, which is applied to an advanced encryption standard algorithm core implementation device, the device includes a control module, an operation module and a storage module, and the method includes: determining the key expansion enable signal according to the length of the original key by the control module, determining the first operation round and the second operation round under the operation mode corresponding to the key expansion enable signal; performing nonlinear transformation on the original key by the operation module, performing the key expansion operation of the first operation round on the key after the nonlinear transformation, obtaining the round key of the corresponding round, performing the encryption and decryption operation of the second operation round on the processed data according to the round key, and obtaining the encrypted and decrypted data; the operation module configures different operation resources to realize the function adaptation under different operation modes; and the storage module stores the round key and the encrypted and decrypted data. It can be seen that since the operation module in the present application can realize the function adaptation under different operation modes by configuring different operation resources, the present application does not need to construct multiple independent hardware units for the keys of various operation modes, which greatly reduces the overall circuit area requirement. Since there is no need to construct multiple independent hardware units separately, the present application no longer needs to construct a large amount of combinational logic based on complex logic gate circuits and cumbersome control signals, which significantly reduces the complexity of circuit design, effectively controls circuit power consumption, avoids high power consumption caused by a large amount of combinational logic, and reduces the manufacturing cost of the chip. Furthermore, since the key after nonlinear transformation is difficult to be directly cracked, even if the key information is leaked, it is difficult for outsiders to use it for decryption, which effectively prevents the theft of plaintext information and significantly improves the information security of the Advanced Encryption Standard algorithm core.

[0070] Furthermore, an embodiment of the present application also provides an electronic device. Figure 5 This is a structural diagram of an electronic device 20 according to an exemplary embodiment. The content in the diagram cannot be considered as any limitation on the scope of use of the present application.

[0071] Figure 5 The present invention provides a schematic diagram of the structure of an electronic device 20 provided in an embodiment of the present application. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a display screen 23, an input / output interface 24, a communication interface 25, a power supply 26, and a communication bus 27. The memory 22 is used to store a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the method for implementing the advanced encryption standard algorithm core disclosed in any of the aforementioned embodiments. In addition, the electronic device 20 in this embodiment may specifically be an electronic computer.

[0072] In this embodiment, the power supply 26 is used to provide working voltage for each hardware device on the electronic device 20; the communication interface 25 can create a data transmission channel between the electronic device 20 and the external device, and the communication protocol it follows is any communication protocol that can be applied to the technical solution of the present application, and is not specifically limited here; the input and output interface 24 is used to obtain external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0073] In addition, the memory 22, as a carrier for storing resources, may be a read-only memory, a random access memory, a disk or an optical disk, etc., and the resources stored thereon may include a computer program 221, and the storage method may be a temporary storage or a permanent storage. Among them, the computer program 221 includes not only a computer program that can be used to complete the advanced encryption standard algorithm core implementation method executed by the electronic device 20 disclosed in any of the aforementioned embodiments, but also a computer program that can be used to complete other specific tasks.

[0074] Furthermore, an embodiment of the present application also discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the aforementioned disclosed advanced encryption standard algorithm core implementation method is implemented.

[0075] For the specific steps of the method, reference may be made to the corresponding contents disclosed in the aforementioned embodiments, which will not be described in detail here.

[0076] The various embodiments in this application are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0077] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0078] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0079] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0080] The above is a detailed introduction to the advanced encryption standard algorithm core implementation method, device, equipment, and storage medium provided by the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for general technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, it can be seen that the content of this specification should not be understood as a limitation on the present application.

Claims

1. A method for implementing an advanced encryption standard algorithm core, characterized in that: The device is applied to the implementation of the advanced encryption standard algorithm core, the device includes a control module, a calculation module and a storage module, and the method includes: Determine, by the control module, a key expansion enable signal according to the length of the original key, and determine a first operation round and a second operation round in an operation mode corresponding to the key expansion enable signal; The operation module performs a nonlinear transformation on the original key to obtain a nonlinearly transformed key, and performs a key expansion operation of the first operation round on the nonlinearly transformed key to obtain a round key of a corresponding round, and then performs an encryption and decryption operation of the second operation round on the processed data according to the round key to obtain corresponding encrypted and decrypted data; wherein the operation module configures different operation resources to achieve function adaptation under different operation modes; The round key and the encryption and decryption data are stored by the storage module.

2. The method for implementing the Advanced Encryption Standard algorithm core according to claim 1, characterized in that: The step of performing the key expansion operation of the first operation round on the nonlinearly transformed key to obtain a round key of a corresponding round includes: Counting the number of calculated rounds by a counter, and setting the initial value of the counter to 0; Performing a key expansion operation on the current input data through the key expansion round function operation unit in the operation module, so as to output a round key corresponding to the current operation round through the key expansion round function operation unit, and adding one to the count value of the counter; Wherein, in the first round of key expansion operation, the current input data of the key expansion round function operation unit is the nonlinear transformed key, and in the non-first round of key expansion operation, the current input data of the key expansion round function operation unit is the round key output by the key expansion round function operation unit in the previous round of operation; Determining whether the count value of the counter reaches the first operation round; If the count value of the counter does not reach the first operation round, jump to the step of performing a key expansion operation on the current input data through the key expansion round function operation unit in the operation module until the count value of the counter reaches the first operation round, and obtain the round key of the corresponding round.

3. The method for implementing the Advanced Encryption Standard algorithm core according to claim 1 or 2, characterized in that: The storing the round key and the encryption and decryption data by the storage module includes: After each round of key expansion operation is completed, the round key of the corresponding round output by the key expansion round function operation unit is stored through the corresponding register in the storage module; wherein the storage module includes a plurality of the registers, and the plurality of registers are numbered according to the first operation round.

4. The method for implementing the Advanced Encryption Standard algorithm core according to claim 3, characterized in that: The performing the encryption and decryption operation of the second operation round on the data to be processed according to the round key to obtain corresponding encrypted and decrypted data includes: Selecting, from the set of encryption / decryption round function operation units in the operation module, an encryption / decryption round function operation unit for implementing the encryption / decryption operation of the second operation round, and reading the round key of the corresponding round from the corresponding register according to the operation round of the encryption / decryption operation; In the first round of encryption and decryption operations, the data to be processed and the round key of the corresponding round are used as current input data of the first encryption and decryption round function operation unit to obtain a corresponding output result; In non-first-round encryption and decryption operations, the output result of the previous round and the round key of the corresponding round are used as the current input data of the current encryption and decryption round function operation unit to obtain the corresponding output result, and the output result of the last encryption and decryption round function operation unit is used as the encryption and decryption data.

5. The method for implementing the Advanced Encryption Standard algorithm core according to claim 4, characterized in that: During encryption and decryption operations, the encryption and decryption round function operation units in the encryption and decryption round function operation unit set work together in a parallel pipeline operation mode.

6. The method for implementing the Advanced Encryption Standard algorithm core according to claim 4, characterized in that: The performing nonlinear transformation on the original key by the operation module includes: Performing nonlinear transformation on the original key by using a replacement box unit in the operation module; Accordingly, the advanced encryption standard algorithm core implementation method further includes: During encryption and decryption operations, the replacement box unit performs byte replacement on the current input data of each encryption and decryption round function operation unit.

7. The method for implementing the Advanced Encryption Standard algorithm core according to claim 6, characterized in that: The replacement box unit includes a plurality of replacement boxes, and the plurality of replacement boxes perform non-linear transformation operations in parallel or perform byte replacement operations in parallel.

8. An Advanced Encryption Standard algorithm core implementation device, characterized in that: include: A control module, configured to determine a key extension enable signal according to the length of the original key, and determine a first operation round and a second operation round in an operation mode corresponding to the key extension enable signal; A computing module, used for performing a nonlinear transformation on the original key to obtain a nonlinearly transformed key, performing a key expansion operation of the first computing round on the nonlinearly transformed key to obtain a round key of a corresponding round, and then performing an encryption and decryption operation of the second computing round on the processed data according to the round key to obtain corresponding encrypted and decrypted data; wherein the computing module realizes function adaptation under different computing modes by configuring different computing resources; A storage module is used to store the round key and the encryption and decryption data.

9. An electronic device, characterized in that: include: Memory, used to store computer programs; A processor, configured to execute the computer program to implement the advanced encryption standard algorithm core implementation method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: Used to store a computer program; wherein, when the computer program is executed by a processor, the advanced encryption standard algorithm core implementation method as claimed in any one of claims 1 to 7 is implemented.

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