Three-dimensional memory and methods of making the same, memory systems, electronic devices

Abstract

The embodiment of the present application provides a three-dimensional memory, a preparation method thereof, a storage system and electronic equipment, relates to the technical field of semiconductor chips, and aims to increase the capacity of the three-dimensional memory. The three-dimensional memory provided in the embodiment of the present application has a first side and a second side in the thickness direction of an intermediate layer, a first device layer is located on the first side of the intermediate layer, a first storage array layer is located on the side, away from the intermediate layer, of the first device layer, a second device layer is located on the second side of the intermediate layer, and a second storage array layer is located on the side, away from the intermediate layer, of the second device layer, so that a five-layer structure of the first storage array layer, the first device layer, the intermediate layer, the second device layer and the second storage array layer is arranged in a stack in the thickness direction of the intermediate layer, the first storage array layer and the second storage array layer for storage are arranged on a unit area, and the capacity of the three-dimensional memory is increased.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of semiconductor chip, and particularly relate to a three-dimensional memory, a preparation method thereof, a storage system and an electronic device. BACKGROUND

[0002] The memory internally encapsulates a plurality of chips, each of which is used for storing data, and the total amount of data that can be stored by all the chips is the maximum capacity of the memory. In the use process, the memory is affected by the size, and the number of the maximum chips that can be encapsulated in the encapsulation area is limited, thereby limiting the maximum capacity of the memory. SUMMARY

[0003] Embodiments of the present application provide a three-dimensional memory, a preparation method thereof, a storage system and an electronic device, which aims to increase the capacity of the three-dimensional memory.

[0004] To achieve the above-mentioned purpose, embodiments of the present application adopt the following technical solutions:

[0005] In one aspect, the present application provides a three-dimensional memory, comprising an intermediate layer, a first device layer, a second device layer, a first storage array layer and a second storage array layer, having a first side and a second side in the thickness direction of the intermediate layer, the first device layer comprises a plurality of first transistors, the first device layer is located on the first side of the intermediate layer, the second device layer comprises a plurality of second transistors, the second device layer is located on the second side of the intermediate layer, the first storage array layer is located on the side of the first device layer away from the intermediate layer, and the second storage array layer is located on the side of the second device layer away from the intermediate layer.

[0006] The three-dimensional memory provided by the embodiments of the present application has the first side and the second side in the thickness direction of the intermediate layer, the first device layer is located on the first side of the intermediate layer, the first storage array layer is located on the side of the first device layer away from the intermediate layer, the second device layer is located on the second side of the intermediate layer, and the second storage array layer is located on the side of the second device layer away from the intermediate layer, thereby forming a five-layer structure of the first storage array layer, the first device layer, the intermediate layer, the second device layer and the second storage array layer arranged in layers in the thickness direction of the intermediate layer, and having the first storage array layer and the second storage array layer for storage in a unit area, thereby increasing the capacity of the three-dimensional memory.

[0007] In some embodiments, the first storage array layer is connected with at least one of the plurality of first transistors, and the second storage array layer is connected with at least one of the plurality of second transistors.

[0008] Through the above arrangement, the first transistor can perform logical control on the plurality of first storage structures in the first storage array layer after being connected with the first storage array layer, so that the first storage array layer realizes the functions of storage or reading. Similarly, the second transistor can perform logical control on the plurality of second storage structures in the second storage array layer after being connected with the second storage array layer, so that the second storage array layer realizes the functions of storage or reading.

[0009] In some embodiments, the three-dimensional memory further comprises a packaging substrate, the packaging substrate is provided with a connection circuit, the packaging substrate is located on a side of the first storage array layer away from the intermediate layer, and the at least one first transistor, the first storage array layer, the at least one second transistor, and the second storage array layer are all connected with the connection circuit.

[0010] Through the above arrangement, the at least one first transistor is connected with the connection circuit, the connection of the first device layer and the connection circuit is realized, the at least one second transistor is connected with the connection circuit, the connection of the second device layer and the connection circuit is realized, and the first storage array layer and the second storage array layer are both connected with the connection circuit, so that the connection circuit realizes the connection between the first device layer, the second device layer, the first storage array layer, and the second storage array layer which are stacked along the thickness direction of the intermediate layer, and the capacity of the three-dimensional memory is increased.

[0011] In some embodiments, the first storage array layer comprises a first spacer and a second spacer which are arranged at intervals, and the first spacer and the second spacer are both located on a side of the first storage array layer away from the intermediate layer. The first spacer connects the at least one first transistor with the connection circuit, and the second spacer connects the first storage array layer with the connection circuit.

[0012] Through the above arrangement, the first spacer and the second spacer are both connected with the connection circuit, the first spacer is connected with the at least one first transistor, and the second spacer is connected with the first storage array layer, so that the first device layer and the first storage array layer can be both connected with the connection circuit.

[0013] In some embodiments, the first storage array layer comprises a first conductive pillar, one end of the first conductive pillar is connected with the first spacer, and the other end of the first conductive pillar is connected with the first transistor.

[0014] Through the above arrangement, the first conductive pillar leads the at least one first transistor out to the first spacer, so that the at least one first transistor can be connected with the connection circuit of the packaging substrate through the first spacer.

[0015] In some embodiments, the packaging substrate is provided with a first contact and a second contact on a surface close to the intermediate layer, the first contact and the second contact are both connected with the connection circuit, the first contact is connected with the first spacer, and the second contact is connected with the second spacer.

[0016] Through the above arrangement, the connection circuit of the packaging substrate is connected with the first pad through the first contact and connected with the second pad through the second contact, so that the connection circuit can be connected with the first storage array layer and the first device layer, and the connection circuit is located in the interior of the packaging substrate to avoid leakage of the connection circuit and affect the storage efficiency of the three-dimensional memory.

[0017] In some embodiments, the first contact is welded with the first pad, and the second contact is welded with the second pad.

[0018] Through the above arrangement, welding between the first contact and the first pad can realize electrical interconnection between the first contact and the first pad, and welding between the second contact and the second pad can realize electrical interconnection between the second contact and the second pad. The solder formed by welding can also play a role in stress buffering between the first storage array layer and the packaging substrate.

[0019] In some embodiments, the second storage array layer includes a third pad and a fourth pad arranged at intervals, the third pad and the fourth pad are located on a side of the second storage array layer away from the intermediate layer, the third pad is connected with at least one second transistor and the connection circuit, and the fourth pad is connected with the second storage array layer and the connection circuit.

[0020] Through the above arrangement, the third pad and the fourth pad are both connected with the connection circuit, the third pad is connected with at least one second transistor, and the fourth pad is connected with the second storage array layer, so that the second device layer and the second storage array layer can be connected with the connection circuit.

[0021] In some embodiments, the second storage array layer includes a second conductive column, one end of the second conductive column is connected with the third pad, and the other end of the second conductive column is connected with the second transistor.

[0022] Through the above arrangement, the second conductive column leads at least one second transistor to the third pad, so that at least one second transistor can be connected with the connection circuit of the packaging substrate through the third pad.

[0023] In some embodiments, the packaging substrate is provided with a third contact and a fourth contact on a surface close to the intermediate layer, the third contact and the fourth contact are both connected with the connection circuit; the three-dimensional memory further includes a first wire and a second wire, one end of the first wire is connected with the third pad, the other end of the first wire is connected with the third contact, one end of the second wire is connected with the fourth pad, and the other end of the second wire is connected with the fourth contact.

[0024] Through the above arrangement, the first wire can realize electrical interconnection between the third pad and the third contact, and the second wire can realize electrical interconnection between the fourth pad and the fourth contact.

[0025] In another aspect, the embodiments of the present application also provide a method for manufacturing a three-dimensional memory, comprising:

[0026] forming a first device layer and a second device layer on the first initial intermediate layer, and obtaining the intermediate layer; the first device layer comprises a plurality of first transistors, and the first device layer is located on a first side of the intermediate layer; the second device layer comprises a plurality of second transistors, and the second device layer is located on a second side of the intermediate layer; the first side and the second side are two opposite sides of the intermediate layer in the thickness direction;

[0027] forming a first storage array layer and a second storage array layer; the first storage array layer is located on a side of the first device layer away from the intermediate layer, and the first storage array layer is connected with at least one of the plurality of first transistors; the second storage array layer is located on a side of the second device layer away from the intermediate layer, and the second storage array layer is connected with at least one of the plurality of first transistors.

[0028] The embodiments of the present application provide a method for manufacturing a three-dimensional memory, which forms a five-layer structure of the first storage array layer, the first device layer, the intermediate layer, the second device layer, and the first storage array layer stacked in the thickness direction of the intermediate layer, and has the first storage array layer and the second storage array layer for storage in a unit area, thereby increasing the capacity of the three-dimensional memory.

[0029] In some embodiments, forming a first device layer and a second device layer on the first initial intermediate layer, and obtaining the intermediate layer comprises:

[0030] forming the second device layer on a side of the first initial intermediate layer, and obtaining a second initial intermediate layer;

[0031] forming a first protective layer on the second device layer;

[0032] turning over the second initial intermediate layer, forming the first device layer on a side of the second initial intermediate layer away from the second device layer, and obtaining the intermediate layer.

[0033] Through the above arrangement, a four-layer structure of the first device layer, the intermediate layer, the second device layer, and the first protective layer stacked in the thickness direction of the intermediate layer is formed, the first device layer and the second device layer are formed on two opposite sides of the intermediate layer in the thickness direction, the first device layer and the second device layer having a connection with a storage cell string in a unit area, the number of transistors for connection with the storage cell string, i.e., the total number of the first transistors and the second transistors, is increased, the number of storage cell strings that can be connected by the three-dimensional memory is improved, and the capacity of the three-dimensional memory is improved. In addition, the first protective layer is located on a side of the second device layer away from the second initial intermediate layer, so as to avoid that the second device layer is abraded in the process of forming the first device layer on the second initial intermediate layer.

[0034] In some embodiments, forming the first memory array layer and the second memory array layer comprises:

[0035] attaching the first memory array layer on the first device layer;

[0036] forming a second protective layer on the first memory array layer;

[0037] turning over the intermediate layer and removing the first protective layer;

[0038] attaching the second memory array layer on the second device layer;

[0039] removing the second protective layer.

[0040] With the above arrangement, the second protective layer is located on the side of the first memory array layer facing away from the first device layer, so as to avoid the first memory array layer from being damaged during the process of forming the second memory array layer on the second device layer.

[0041] In some embodiments, the preparation method further comprises:

[0042] forming a packaging substrate, the packaging substrate being provided with a connecting circuit, the packaging substrate being provided with a first contact and a second contact on the surface close to the intermediate layer, the first contact and the second contact being connected to the connecting circuit;

[0043] After the first memory array layer is formed, the first memory array layer further comprises a first pad and a second pad arranged at intervals, the first pad and the second pad being located on the side of the first memory array layer facing away from the intermediate layer, the first pad being connected to at least one first transistor;

[0044] After the first memory array layer is attached to the first device layer, the first memory array layer further comprises: connecting the first contact and the first pad by soldering; and connecting the second contact and the second pad by soldering.

[0045] With the above arrangement, soldering between the first contact and the first pad can realize electrical interconnection between the first contact and the first pad, soldering between the second contact and the second pad can realize electrical interconnection between the second contact and the second pad, and the solder formed by soldering can also play a role of stress buffering between the first memory array layer and the packaging substrate.

[0046] In some embodiments, the preparation method further comprises:

[0047] After the packaging substrate is formed, the packaging substrate is provided with a third contact and a fourth contact on the surface close to the intermediate layer, the third contact and the fourth contact being connected to the connecting circuit;

[0048] After the second memory array layer is formed, the second memory array layer further comprises a third spacer and a fourth spacer which are arranged at intervals, the third spacer and the fourth spacer are located on a side of the second memory array layer away from the intermediate layer, and the third spacer is connected with the at least one second transistor;

[0049] After the second memory array layer is attached to the second device layer, the method further comprises: forming a first conductive line and a second conductive line, connecting the third contact and the third spacer through the first conductive line, and connecting the fourth contact and the fourth spacer through the second conductive line.

[0050] Through the above arrangement, the electrical interconnection between the third spacer and the third contact can be realized through the first conductive line, and the electrical interconnection between the fourth spacer and the fourth contact can be realized through the second conductive line.

[0051] In another aspect, the embodiments of the present application further provide a storage system, comprising a three-dimensional memory and a controller, the three-dimensional memory is the three-dimensional memory as above; the controller is coupled to the three-dimensional memory to control the three-dimensional memory to store data.

[0052] In another aspect, the embodiments of the present application further provide an electronic device, comprising a host and the storage system as above, the host and the storage system are coupled.

[0053] It can be understood that the three-dimensional memory preparation method, the storage system and the electronic device provided by the above embodiments of the present application can achieve the beneficial effects as described above, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0054] In order to more clearly illustrate the technical solutions in the present application, the following will briefly introduce the drawings needed to be used in some embodiments of the present application. Obviously, the drawings in the following description are only some drawings of the embodiments of the present application, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual process, actual time sequence, etc. of the products involved in the embodiments of the present application.

[0055] Figure 1 It is a schematic diagram of the three-dimensional structure of the three-dimensional memory in some embodiments of the present application;

[0056] Figure 2 It is a sectional view of the three-dimensional memory in some embodiments of the present application;

[0057] Figure 3 It is a sectional view of the three-dimensional memory in some embodiments of the present application; Figure 1 It is a sectional view of a memory cell string in the three-dimensional memory shown in the figure along the section line AA';

[0058] Figure 4Equivalent circuit diagram for a string of memory cells in some embodiments of the application;

[0059] Figure 5 Structure diagram for a three-dimensional memory in some embodiments of the application;

[0060] Figure 6 Flow diagram for a method of fabricating a three-dimensional memory in some embodiments of the application;

[0061] Figure 7 Structure diagram for a first initial intermediate layer in some embodiments of the application;

[0062] Figure 8 Structure diagram after forming a second device layer in some embodiments of the application;

[0063] Figure 9 Structure diagram after forming a first protective layer in some embodiments of the application;

[0064] Figure 10 Structure diagram after forming a first device layer in some embodiments of the application;

[0065] Figure 11 Structure diagram after forming a first memory array layer in some embodiments of the application;

[0066] Figure 12 Structure diagram after removing a first protective layer in some embodiments of the application;

[0067] Figure 13 Structure diagram after removing a second protective layer in some embodiments of the application;

[0068] Figure 14 Structure diagram after connecting a package substrate and a first memory array layer in some embodiments of the application;

[0069] Figure 15 Structure diagram after connecting a package substrate and a second memory array layer in some embodiments of the application;

[0070] Figure 16 Block diagram of a memory system according to some embodiments;

[0071] Figure 17 Block diagram of a memory system according to some other embodiments.

[0072] BRIEF DESCRIPTION OF DRAWINGS:301, three-dimensional memory; 302, intermediate layer; 303, first device layer; 304, second device layer; 305, first transistor; 306, second transistor; 307, first memory array layer; 308, first connection portion; 309, second connection portion; 310, second memory array layer; 311, third connection portion; 312, fourth connection portion; 313, package substrate; 314, connection circuit; 315, first pad; 316, first conductive pillar; 317, second pad; 318, first contact; 319, second contact; 320, third pad; 321, second conductive pillar; 322, fourth pad; 323, third contact; 324, fourth contact; 325, first wire; 326, second wire; 327, first initial intermediate layer; 328, second initial intermediate layer; 329, first protective layer; 330, second protective layer. DETAILED DESCRIPTION

[0073] The technical solutions in some embodiments of the present application will be clearly and completely described below with reference to the drawings. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by those skilled in the art belong to the scope of protection of the present application.

[0074] In the description of the present application, it should be understood that the terms "center", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, and are only used to facilitate the description of the present application and simplify the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the present application.

[0075] Unless otherwise required by context, the term "comprises" in the specification and claims is interpreted as open, inclusive meaning, i.e. "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiment", "exemplarily" or "some examples" and the like are intended to mean that the specific features, structures, materials or characteristics related to the embodiment or example are included in at least one embodiment or example of the present application. The illustrative representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics described can be included in any one or more embodiments or examples in any appropriate manner.

[0076] The terms "first", "second", etc. are used herein only to describe one feature distinguishable from another feature, and do not signify either or imply a relative importance or an implied direction of indicated technical features. Thus, features defined with "first", "second", etc. can explicitly or implicitly include one or more of the features. In the description of embodiments of the present application, the meaning of "a plurality" is two or more, unless otherwise specified.

[0077] In describing some embodiments, "coupled" and "connected", and variations thereof, can be used. For example, the term "connected" can be used to indicate that two or more elements are in direct physical or electrical contact with each other. As another example, the term "coupled" can be used to indicate that two or more elements are in either direct physical or electrical contact with each other, or that two or more elements are not in direct contact with each other, but yet are still in cooperation or interaction with each other. The embodiments disclosed herein are not necessarily limited in scope to the terms used herein.

[0078] "A, B, and C at least one of" has the same meaning as "at least one of A, B, or C", including the following combinations of A, B, and C: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0079] "A and / or B" includes the following three combinations: only A, only B, and a combination of A and B.

[0080] As used herein, "about", "approximately", or "around" includes the recited value and the average value within an acceptable range of deviation from the particular value, as determined by one of ordinary skill in the art considering the measurement being discussed and the error (i.e., limitations of the measurement system) associated with the measurement of the particular quantity.

[0081] In the context of the present application, "on", "over", and "on top of" should be interpreted in the broadest context as meaning not only "directly on", but also including the meaning of "on" with intervening features or layers therebetween, and "over" or "on top of" not only meaning "over" or "on top of" something, but also including the meaning of "over" or "on top of" something without intervening features or layers therebetween (i.e., directly on).

[0082] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are schematic illustrations of idealized embodiments. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will, typically, have rounded or curved features. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region that would be formed in a device and are intended to be merely an aid to understanding embodiments.

[0083] As used herein, the term "substrate" refers to a material on which a subsequent layer of material can be added. The substrate itself can be patterned. The material added on the substrate can be patterned or can remain unpatterned. Further, the substrate can comprise a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0084] The term "three-dimensional memory" refers to a semiconductor device formed of strings of memory cell transistors (referred to herein as "memory cell strings", e.g., NAND memory cell strings) arranged in an array on a major surface of a substrate or source layer and extending in a direction perpendicular to the major surface of the substrate or source layer. As used herein, the term "perpendicular / perpendicularly" means nominally perpendicular to the major surface (i.e., lateral surface) of the substrate or source layer.

[0085] Reference is made to Figure 1 and Figure 2 The three-dimensional memory 10 extends in an X-Y plane, a first direction X and a second direction Y being, for example, two orthogonal directions in the plane in which the semiconductor structure 200 lies (e.g., the plane in which the source layer SL lies): the first direction X being, for example, the direction of extension of the word lines WL, and the second direction Y being, for example, the direction of extension of the bit lines BL. A third direction Z is perpendicular to the plane in which the semiconductor structure 200 lies, i.e., perpendicular to the X-Y plane.

[0086] As used herein, a component (e.g., a layer, structure, or device) is "on", "over", or "under" another component (e.g., a layer, structure, or device) of a semiconductor device (e.g., a three-dimensional memory) as determined with respect to a substrate or source layer of the semiconductor device in the third direction Z when the substrate or source layer is in the lowest plane of the semiconductor device. The same concept is applied throughout the present disclosure to describe spatial relationships.

[0087] Where, for a clearer illustration of the structure of the device, Figure 2In some embodiments, a view of the array region CA is shown, which is based on a left-handed coordinate system, i.e. the view of the array region CA shows a cross-sectional structure along the Y direction.

[0088] Referring to Figure 1 and Figure 2 Some embodiments of the present application provide a three-dimensional memory 10. The three-dimensional memory 10 can include a semiconductor structure 200. The three-dimensional memory 10 can also include a peripheral device 100 coupled to the semiconductor structure 200. The semiconductor structure 200 includes a source layer SL, and the peripheral device 100 can be disposed on a side of the semiconductor structure 200 distal to the source layer SL.

[0089] The source layer SL can include a semiconductor material, such as monocrystalline silicon, monocrystalline germanium, a III-V compound semiconductor material, a II-VI compound semiconductor material, and other suitable semiconductor materials. The source layer SL can be partially or entirely doped. Illustratively, the source layer SL can include a doped region doped with a p-type dopant. The source layer SL can also include an undoped region.

[0090] The semiconductor structure 200 can include a plurality of array- disposed strings of memory cell transistors (referred to herein as "channel structures") 40. The source layer SL can be coupled to source ends of the plurality of memory cell strings 40 (as shown). Figure 3

[0091] In some embodiments, referring to Figure 3 and Figure 4 The memory cell string 40 can include a plurality of transistors T, one transistor T (e.g. T1-T6 in Figure 4 ) can be disposed as one memory cell, and the transistors T are connected together to form the memory cell string. One transistor T (e.g. each transistor T) can be formed by a semiconductor channel 241 and a gate line G surrounding the semiconductor channel 241, wherein the gate line G is configured to control the on-off state of the transistor.

[0092] It can be understood that Figures 1-4 The number of transistors in may be illustrative only, and the memory cell string of the three-dimensional memory provided by the embodiments of the present application can also include other numbers of transistors, such as 4, 16, 32, 64.

[0093]

[0093] In some embodiments, along the third direction Z, a lowermost one of the plurality of gate lines G (e.g., a gate line closest to the source layer SL among the plurality of gate lines G) is configured as a source select gate SGS, which is configured to control the on state of the transistor T6, and in turn, the on state of the source-side pass gate in the memory cell string 40. An uppermost one of the plurality of gate lines G (e.g., a gate line farthest from the source layer SL among the plurality of gate lines G) is configured as a drain select gate SGD, which is configured to control the on state of the transistor T1, and in turn, the on state of the drain-side pass gate in the memory cell string 40. The middle ones of the plurality of gate lines G can be configured as a plurality of word lines WL, e.g., including the word line WL0, the word line WL1, the word line WL2, and the word line WL3. Data writing, reading, and erasing of a corresponding memory cell (e.g., transistor T) in the memory cell string 40 can be accomplished through the word lines WL.

[0094] With continued reference to Figure 1 and Figure 2 In some embodiments, the semiconductor structure 200 can further include an array interconnection layer 290. The array interconnection layer 290 can be coupled with the memory cell string 40. The array interconnection layer 290 can include a drain side (i.e., a bit line BL) of the memory cell string 40, which can be coupled with the semiconductor channel of each transistor T in the at least one memory cell string 40.

[0095] The array interconnection layer 290 can include one or more first interlayer insulating layers 292, and further include a plurality of contacts insulated from each other by the first interlayer insulating layers 292, e.g., including a bit line contact BL-CNT coupled with the bit line BL, and a drain select gate contact SGD-CNT coupled with the drain select gate SGD. The array interconnection layer 290 can further include one or more first interconnection conductor layers 291. The first interconnection conductor layers 291 can include a plurality of connection lines, e.g., the bit line BL, and a word line connection line WL-CL coupled with the word line WL. The materials of the first interconnection conductor layers 291 and the contacts can be electrically conductive materials, e.g., one or more of tungsten, cobalt, copper, aluminum, and metal silicide, or other suitable materials. The materials of the first interlayer insulating layers 292 can be insulating materials, e.g., one or more of silicon oxide, silicon nitride, and high dielectric constant insulating materials, or other suitable materials.

[0096] The peripheral device 100 can include peripheral circuitry. The peripheral circuitry is configured to control and sense the array device. The peripheral circuitry can be any suitable digital, analog, and / or mixed-signal control and sensing circuitry to support operation of the array device, including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components (e.g., transistors, diodes, resistors, or capacitors) of the circuitry. The peripheral circuitry can also include any other circuitry compatible with advanced logic processes, including logic circuitry (e.g., processors and Programmable Logic Devices (PLDs)) or memory circuitry (e.g., Static Random-Access Memory (SRAM)).

[0097] In some embodiments, the peripheral device 100 can include a substrate 110, transistors 120 disposed on the substrate 110, and a peripheral interconnect layer 130 disposed on the substrate 110. The peripheral circuitry can include the transistors 120.

[0098] The substrate 110 can be made of single crystalline silicon, or other suitable materials such as silicon germanium, germanium, or silicon-on-insulator film.

[0099] The peripheral interconnect layer 130 is coupled with the transistors 120 to enable transmission of electrical signals between the transistors 120 and the peripheral interconnect layer 130. The peripheral interconnect layer 130 can include one or more second interlayer insulating layers 131, and one or more second interconnect conductor layers 132. The different second interconnect conductor layers 132 can be coupled through contacts. The second interconnect conductor layers 132 and the contacts can be made of conductive materials such as one or more of tungsten, cobalt, copper, aluminum, and metal silicides, or other suitable materials. The second interlayer insulating layers 131 can be made of insulating materials such as one or more of silicon oxide, silicon nitride, and high-k insulating materials, or other suitable materials.

[0100] The peripheral interconnect layer 130 can be coupled with the array interconnect layer 290 so that the semiconductor structure 200 and the peripheral device 100 can be coupled. Specifically, because the peripheral interconnect layer 130 is coupled with the array interconnect layer 290, the peripheral circuitry in the peripheral device 100 can be coupled with the string of memory cells in the semiconductor structure 200 to enable transmission of electrical signals between the peripheral circuitry and the string of memory cells. In some possible implementations, a bonding interface 50 can be disposed between the peripheral interconnect layer 130 and the array interconnect layer 290, through which the peripheral interconnect layer 130 and the array interconnect layer 290 can be bonded and coupled with each other.

[0101] Referring to Figure 5 , the embodiment of the present application provides a three-dimensional memory 301 comprising a middle layer 302, a first device layer 303 and a second device layer 304, the middle layer 302 is arranged along a plane in which X-Y is located, the middle layer 302 has a first side and a second side arranged oppositely in a thickness direction (i.e. along the Z direction), the first device layer 303 and the second device layer 304 are both arranged along the plane in which X-Y is located, and the first device layer 303 is located at the first side of the middle layer 302, and the second device layer 304 is located at the second side of the middle layer 302. Figure 2 The middle layer 302 has a first side and a second side arranged oppositely in the thickness direction (i.e. along the Z direction), the first device layer 303 and the second device layer 304 are both arranged along the plane in which X-Y is located, and the first device layer 303 is located at the first side of the middle layer 302, and the second device layer 304 is located at the second side of the middle layer 302. Figure 2 The middle layer 302 can comprise a semiconductor material, such as silicon, germanium and the like, the first device layer 303 can comprise a plurality of first transistors 305, and the second device layer 304 can comprise a plurality of second transistors 306, the first transistors 305 and the second transistors 306 can both comprise a complementary metal oxide semiconductor (CMOS).

[0102] Continuing to refer to Figure 5 , the three-dimensional memory 301 can further comprise a first storage array layer 307, the first storage array layer 307 is arranged along the plane in which X-Y is located, and is located at a side of the first device layer 303 away from the middle layer 302, the first storage array layer 307 can comprise a plurality of first storage structures (not shown in the figure), the first storage structures are arranged along the Z direction, and the first storage structures can comprise, for example, a plurality of memory cells. Figure 2 The first storage structures are arranged along the Z direction, and the first storage structures can comprise, for example, a plurality of memory cells. Figure 2 Figure 3 ​The shown storage unit string 40, each first storage structure is connected with a first transistor 305 in the first device layer 303 corresponding to one end of the first device layer 303, and then the first storage array layer 307 is connected with at least one of the plurality of first transistors 305, wherein the first storage array layer 307 and the first device layer 303 can be formed separately, that is, the formation of the first storage array layer 307 is not subject to the existence of the first device layer 303 as a prerequisite, at the same time, the formation of the first device layer 303 is also not subject to the existence of the first storage array layer 307 as a prerequisite, the first storage array layer 307 and the first device layer 303 can be formed separately on different substrates, wherein a first connecting portion 308 is formed at one end of the first storage structure close to the first device layer 303, a second connecting portion 309 is formed at one end of the first transistor 305 close to the first storage array layer 307, and the connection mode between the first storage structure and the first transistor 305 can include wafer bonding connection, that is, the connection between the first storage structure and the first transistor 305 is realized through the bonding between the first connecting portion 308 and the second connecting portion 309, and then the connection between the first storage array layer 307 and the first device layer 303 is realized.

[0103] With reference to the foregoing Figure 5 , the three-dimensional memory 301 can further include a second storage array layer 310, the second storage array layer 310 is also arranged along the X-Y plane in the middle layer 302, and is located on the side of the second device layer 304 away from the middle layer 302. Figure 2 The second storage array layer 310 can include a plurality of second storage structures (not shown), and the second storage structures are arranged along the Z direction in the middle layer 302. Figure 2 The second storage structure can also include a plurality of second storage structures (not shown) arranged along the Z direction in the middle layer 302. Figure 3The shown storage unit string 40, each second storage structure is connected with a second transistor 306 in the second device layer 304 at one end close to the second device layer 304, so that the second storage array layer 310 is connected with at least one of the plurality of second transistors 306, wherein the second storage array layer 310 and the second device layer 304 can also be formed separately, that is, the formation of the second storage array layer 310 is not subject to the presence or absence of the second device layer 304 as a prerequisite, at the same time, the formation of the second device layer 304 is not subject to the presence or absence of the second storage array layer 310 as a prerequisite, the second storage array layer 310 and the second device layer 304 can be formed separately on different substrates, wherein a third connection part 311 is formed at one end of the second storage structure close to the second device layer 304, and a fourth connection part 312 is formed at one end of the second transistor 306 close to the second storage array layer 310, the connection mode between the second storage structure and the second transistor 306 can include wafer bonding connection, that is, the connection between the second storage structure and the second transistor 306 is realized through the bonding between the third connection part 311 and the fourth connection part 312, and then the connection between the second storage array layer 310 and the second device layer 304 is realized.

[0104] Through the above setting, after the first transistor 305 is connected with the first storage array layer 307, the plurality of first storage structures in the first storage array layer 307 can be logically controlled, so that the first storage array layer 307 realizes the functions of storage or reading. Similarly, after the second transistor 306 is connected with the second storage array layer 310, the plurality of second storage structures in the second storage array layer 310 can be logically controlled, so that the second storage array layer 310 realizes the functions of storage or reading.

[0105] Continuing to refer to Figure 5 At the same time, in the above implementation, the first storage array layer 307 and the first device layer 303 are connected by wafer bonding, and the first storage array layer 307 and the first device layer 303 can be bonded after being formed on different substrates, avoiding forming the first device layer 303 on the first storage array layer 307 or forming the first storage array layer 307 on the first device layer 303, so that the influence on the first storage array layer 307 when forming the first device layer 303 on the first storage array layer 307 or the influence on the first device layer 303 when forming the first storage array layer 307 on the first device layer 303 can be reduced, and the yield of the three-dimensional memory 301 is improved. It can be understood that the second storage array layer 310 and the second device layer 304 are also connected by wafer bonding, and the same beneficial effects can be obtained, which will not be repeated here.

[0106] Continuing to refer to Figure 5The three-dimensional memory 301 provided by the embodiment of the present application has a first side and a second side in the thickness direction of the intermediate layer 302, the first device layer 303 is located on the first side of the intermediate layer 302, the first storage array layer 307 is located on the side of the first device layer 303 away from the intermediate layer 302, the second device layer 304 is located on the second side of the intermediate layer 302, and the second storage array layer 310 is located on the side of the second device layer 304 away from the intermediate layer 302, thereby forming a five-layer structure of the first storage array layer 307, the first device layer 303, the intermediate layer 302, the second device layer 304 and the second storage array layer 310 stacked in the thickness direction of the intermediate layer 302, and increasing the capacity of the three-dimensional memory 301 by having the first storage array layer 307 and the second storage array layer 310 for storage in unit area.

[0107] With reference to the foregoing Figure 5 In the embodiment of the present application, the three-dimensional memory 301 further comprises a packaging substrate 313 located on the side of the first storage array layer 307 away from the intermediate layer 302, and the packaging substrate 313 is provided with a connecting circuit 314, the first device layer 303 and the first storage array layer 307 are connected with the connecting circuit 314, and the second device layer 304 and the second storage array layer 310 are also connected with the connecting circuit 314.

[0108] With reference to the foregoing Figure 5 In the implementation mode in which the first device layer 303 is connected with the connecting circuit 314, the first storage array layer 307 can comprise a first pad 315 and an internal first conductive column 316, wherein the first pad 315 is located on the side of the first storage array layer 307 away from the intermediate layer 302, the first pad 315 is used for connecting with the connecting circuit 314 on the packaging substrate 313, and the first conductive column 316 is arranged in the Z direction, one end of the first conductive column 316 is connected with the first pad 315, and the other end of the first conductive column 316 is located on the side of the first storage array layer 307 close to the first device layer 303. Figure 2 In the implementation mode in which the three-dimensional memory 301 comprises the first connecting part 308 and the second connecting part 309, the end of the first conductive column 316 close to the first device layer 303 is connected with at least one first connecting part 308, the first connecting part 308 is bonded with the second connecting part 309, and the second connecting part 309 is connected with the first transistor 305.

[0109] Through the above arrangement, the first conductive column 316 leads out at least one first transistor 305 to the first pad 315, so that at least one first transistor 305 can be connected with the connecting circuit 314 of the packaging substrate 313 through the first pad 315.

[0110] With reference to the foregoing Figure 5In the implementation where the first memory array layer 307 is connected with the connection circuit 314, the first memory array layer 307 can further include a second pad 317 located on the side of the first memory array layer 307 away from the intermediate layer 302, the second pad 317 is spaced apart from the first pad 315, and the second pad 317 is configured to be connected with the connection circuit 314 on the package substrate 313. In the implementation where the first memory array layer 307 includes the first memory structure, the side of the second pad 317 away from the package substrate 313 is connected with the first memory structure.

[0111] Through the above arrangement, the first memory structure is connected with the second pad 317, so that the first memory structure can be connected with the connection circuit 314 of the package substrate 313 through the second pad 317. In combination with the above implementation, the first pad 315 and the second pad 317 are both connected with the connection circuit 314, the first pad 315 is connected with the at least one first transistor 305, and the second pad 317 is connected with the first memory array layer 307, so that the first device layer 303 and the first memory array layer 307 can be connected with the connection circuit 314.

[0112] Continuing to refer to Figure 5 The package substrate 313 is provided with a first contact 318 and a second contact 319, the first contact 318 and the second contact 319 are located on the surface of the package substrate 313 close to the intermediate layer 302, and the first contact 318 and the second contact 319 are both connected with the connection circuit 314, wherein the first contact 318 is connected with the first pad 315, and the second contact 319 is connected with the second pad 317.

[0113] Through the above arrangement, the connection circuit 314 of the package substrate 313 is connected with the first pad 315 through the first contact 318 and is connected with the second pad 317 through the second contact 319, so that the connection of the package substrate 313 with the first memory array layer 307 and the first device layer 303 can be realized, and the connection circuit 314 can be located inside the package substrate 313 to avoid the leakage of the connection circuit 314 and affect the storage efficiency of the three-dimensional memory 301.

[0114] Continuing to refer to Figure 5In the above implementation, the first contact 318 is connected to the first pad 315 by welding, and the second contact 319 is connected to the second pad 317 by welding. For example, the first contact 318 and the first pad 315 can be welded by a bumping process, which can form bumps on the first contact 318. The bumps can be protrusions with metal conductive properties, such as copper, copper-tin alloy, etc. The bumps are used to connect the first contact 318 to the first pad 315. After welding, the bumps formed between the first contact 318 and the first pad 315 can be in the shape of a ball, a column, or a block, etc. Similarly, the second contact 319 and the second pad 317 can also be welded by a bumping process, which will not be described here.

[0115] Through the above arrangement, the welding between the first contact 318 and the first pad 315 can achieve electrical interconnection between the first contact 318 and the first pad 315, and the welding between the second contact 319 and the second pad 317 can achieve electrical interconnection between the second contact 319 and the second pad 317. In addition, the solder formed by welding can also act as a stress buffer between the first storage array layer 307 and the package substrate 313.

[0116] Continuing to refer to Figure 5 In the implementation in which the second device layer 304 is connected to the connection circuit 314, the second storage array layer 310 can include a third pad 320 and an internal second conductive pillar 321. The third pad 320 is located on the side of the second storage array layer 310 away from the intermediate layer 302, and is used to connect to the connection circuit 314 on the package substrate 313. The second conductive pillar 321 is arranged in the Z direction, one end of the second conductive pillar 321 is connected to the third pad 320, and the other end of the third conductive pillar is located on the side of the second storage array layer 310 close to the second device layer 304. In the implementation in which the three-dimensional memory 301 includes a third connection portion 311 and a fourth connection portion 312, the end of the second conductive pillar 321 close to the second device layer 304 is connected to at least one third connection portion 311. The third connection portion 311 is connected to the fourth connection portion 312 by bonding, and the fourth connection portion 312 is connected to the second transistor 306.

[0117] Through the above arrangement, the second conductive pillar 321 leads at least one second transistor 306 to the third pad 320, so that the at least one second transistor 306 can be connected to the connection circuit 314 of the package substrate 313 through the third pad 320.

[0118] Continuing to refer to Figure 5In the implementation where the second storage array layer 310 is connected with the connection circuit 314, the second storage array layer 310 can further include a fourth pad 322 located on a side of the second storage array layer 310 away from the intermediate layer 302, the fourth pad 322 is spaced apart from the third pad 320, and the fourth pad 322 is configured to be connected with the connection circuit 314 on the packaging substrate 313. In the implementation where the second storage array layer 310 includes the second storage structure, the fourth pad 322 is connected with the first storage structure on the side close to the intermediate layer 302.

[0119] Through the above arrangement, the second storage structure is connected with the fourth pad 322, so that the second storage structure can be connected with the connection circuit 314 on the packaging substrate 313 through the fourth pad 322. In combination with the above implementation, the third pad 320 and the fourth pad 322 are both connected with the connection circuit 314, the third pad 320 is connected with the at least one second transistor 306, and the fourth pad 322 is connected with the second storage array layer 310, so that the second device layer 304 and the second storage array layer 310 can be connected with the connection circuit 314.

[0120] Continuing to refer to Figure 5 The packaging substrate 313 is provided with a third contact 323 and a fourth contact 324, the third contact 323 and the fourth contact 324 are located on a surface of the packaging substrate 313 close to the intermediate layer 302, and the third contact 323 and the fourth contact 324 are both connected with the connection circuit 314, wherein the third contact 323 is connected with the third pad 320, and the fourth contact 324 is connected with the fourth pad 322.

[0121] Through the above arrangement, the connection circuit 314 on the packaging substrate 313 is connected with the third pad 320 through the third contact 323 and is connected with the fourth pad 322 through the fourth contact 324, so that the connection of the packaging substrate 313 with the second storage array layer 310 and the second device layer 304 can be realized, and the connection circuit 314 can be located inside the packaging substrate 313 to avoid the leakage of the connection circuit 314 and affect the storage efficiency of the three-dimensional memory 301.

[0122] Continuing to refer to Figure 5 In the implementation where the packaging substrate 313 is provided with the first contact 318 and the second contact 319, the first contact 318 and the second contact 319 are located within the projection of the first storage array layer 307 on the packaging substrate 313, and the third contact 323 and the fourth contact 324 are located outside the projection of the first storage array layer 307 on the packaging substrate 313. In order to facilitate the connection between the third contact 323 and the third pad 320 and the connection between the fourth contact 324 and the fourth pad 322.

[0123] In the above implementation, the third contact 323 and the third pad 320 can be connected by wire bonding, and the fourth contact 324 and the fourth pad 322 can also be connected by wire bonding. For example, the three-dimensional memory 301 can further include a first wire 325 and a second wire 326. One end of the first wire 325 is connected to the third pad 320, and the other end of the first wire 325 is connected to the third contact 323. One end of the second wire 326 is connected to the fourth pad 322, and the other end of the second wire 326 is connected to the fourth contact 324.

[0124] Through the above arrangement, the first wire 325 can realize the electrical interconnection between the third pad 320 and the third contact 323, and the second wire 326 can realize the electrical interconnection between the fourth pad 322 and the fourth contact 324.

[0125] Continuing to refer to Figure 5 In combination with the above embodiments, at least one first transistor 305 is connected to the connection circuit 314, realizing the connection between the first device layer 303 and the connection circuit 314. At least one second transistor 306 is connected to the connection circuit 314, realizing the connection between the second device layer 304 and the connection circuit 314. The first storage array layer 307 and the second storage array layer 310 are both connected to the connection circuit 314. The connection circuit 314 realizes the connection between the first device layer 303, the second device layer 304, the first storage array layer 307, and the second storage array layer 310 stacked along the thickness direction of the intermediate layer 302, thereby increasing the capacity of the three-dimensional memory 301.

[0126] The present application also provides a preparation method of the three-dimensional memory 301, which can be used to manufacture the three-dimensional memory in the above embodiments. Please refer to Figure 6 The preparation method can include steps S100-S200:

[0127] S100: Forming a first device layer and a second device layer on a first initial intermediate layer, and obtaining an intermediate layer; the first device layer includes a plurality of first transistors, and the first device layer is located on a first side of the intermediate layer. The second device layer includes a plurality of second transistors, and the second device layer is located on a second side of the intermediate layer. The first side and the second side are opposite sides of the intermediate layer in the thickness direction.

[0128] Please refer to Figures 7-10 In step S100, forming a first device layer 303 and a second device layer 304 on a first initial intermediate layer 327, and obtaining an intermediate layer 302 can include:

[0129] Please refer to Figure 7 and Figure 8A second device layer 304 is formed on one side of the first initial intermediate layer 327, and a second initial intermediate layer 328 is obtained. For example, a plurality of second transistors 306 are formed on one side of the first initial intermediate layer 327 to form the second device layer 304, and the remaining first initial intermediate layer 327 forms the second initial intermediate layer 328. The first initial intermediate layer 327 can include a semiconductor material, such as silicon, germanium, or the like. It can be understood that the second initial intermediate layer 328 is formed from the remaining first initial intermediate layer 327, that is, the material of the second initial intermediate layer 328 is the same as that of the first initial intermediate layer 327.

[0130] For reference Figure 9 A first protective layer 329 is formed on the second device layer 304. For example, the material of the first protective layer 329 can completely cover the surface of the second device layer 304 away from the second initial intermediate layer 328 to prevent the second transistors 306 in the second device layer 304 from being damaged. The material of the first protective layer 329 is different from that of the first initial intermediate layer 327, and there is a certain etching selectivity, such as 50:1, 100:1, or the like. Since the second transistors 306 of the second device layer 304 are formed on the first initial intermediate layer 327, in the implementation manner in which there is a high etching selectivity between the first protective layer 329 and the first initial intermediate layer 327, it can be ensured that the removal of the first protective layer 329 will not affect the second device layer 304.

[0131] For reference Figure 9 The second initial intermediate layer 328 is flipped over; in this embodiment, the relative positions of the second initial intermediate layer 328, the second device layer 304, and the first protective layer 329 remain unchanged. It can be considered that after the second initial intermediate layer 328 is flipped over, the first protective layer 329 is located at the bottom, and the second device layer 304 and the second initial intermediate layer 328 are stacked in turn upward, at this time, the first protective layer 329 can prevent the second device layer 304 from being damaged.

[0132] For reference Figure 10 After the second initial intermediate layer 328 is flipped over, a first device layer 303 is formed on the side of the second initial intermediate layer 328 away from the second device layer 304, and an intermediate layer 302 is obtained. For example, a plurality of first transistors 305 are formed on the side of the second initial intermediate layer 328 away from the second device layer 304 to form the first device layer 303, and the remaining second initial intermediate layer 328 forms the intermediate layer 302. It can be understood that the intermediate layer 302 is formed from the remaining second initial intermediate layer 328, that is, the material of the intermediate layer 302 is the same as that of the second initial intermediate layer 328.

[0133] By the above arrangement, a four-layer structure of the first device layer 303, the intermediate layer 302, the second device layer 304, and the first protective layer 329 arranged in layers in the thickness direction of the intermediate layer 302 is formed, the first device layer 303 and the second device layer 304 are formed on both sides in the thickness direction of the intermediate layer 302, the first device layer 303 and the second device layer 304 that can be connected to the memory cell string are present on a unit area, the number of transistors for connection to the memory cell string, i.e., the total number of the first transistors 305 and the second transistors 306, is increased, the number of memory cell strings that can be connected by the three-dimensional memory 301 is increased, and thus the capacity of the three-dimensional memory 301 is increased. Further, the first protective layer 329 is located on the side of the second device layer 304 away from the second initial intermediate layer 328, so that the second device layer 304 is prevented from being damaged during formation of the first device layer 303 on the second initial intermediate layer 328.

[0134] S200: Forming a first memory array layer 307 and a second memory array layer 310, the first memory array layer 307 is located on the side of the first device layer 303 away from the intermediate layer 302, and the first memory array layer 307 is connected to at least one of the plurality of first transistors 305, the second memory array layer 310 is located on the side of the second device layer 304 away from the intermediate layer 302, and the second memory array layer 310 is connected to at least one of the plurality of first transistors 305.

[0135] Please refer to Figures 11-13 In step S200, forming the first memory array layer 307 and the second memory array layer 310 includes:

[0136] Please refer to Figure 11 The first memory array layer 307 is attached to the first device layer 303. In combination with the foregoing description, it can be considered that the second initial intermediate layer 328 is a substrate on which the first device layer 303 is formed, and the first memory array layer 307 is formed on another substrate (not shown in the figure), and then the first memory array layer 307 is attached to the first device layer 303.

[0137] In the process of forming the first storage array layer 307, the first storage array layer 307 includes a plurality of first storage structures and a plurality of first connecting portions 308, the first connecting portions 308 are located at a side of the first storage array layer 307 close to the first device layer 303, and one end of the first storage structure close to the first device layer 303 is connected with the first connecting portion 308; and in the process of forming the first device layer 303 in step 100, after forming the first transistor 305, a second connecting portion 309 can also be formed at a side of the first transistor 305 away from the intermediate layer 302, and the first transistor 305 is connected with the second connecting portion 309. Then the connection between the first storage array layer 307 and the first device layer 303 can be realized through the bonding between the first connecting portion 308 and the second connecting portion 309, and the connection between the first storage array layer 307 and the first device layer 303 is further realized.

[0138] Please refer to Figure 11 and Figure 12 , a second protective layer 330 is formed on the first storage array layer 307; for example, the material of the second protective layer 330 can completely cover the surface of the first storage array layer 307 away from the first device layer 303, so as to prevent the first storage structure in the first storage array layer 307 from being abraded. The material of the second protective layer 330 is different from the material of the first storage array layer 307, and there is a certain etching selectivity, for example, 50:1, 100:1, etc. In the implementation mode in which there is a high etching selectivity between the second protective layer 330 and the first storage array layer 307, it can be ensured that the first storage array layer 307 will not be affected when the second protective layer 330 is removed.

[0139] Please refer to Figure 11 and Figure 12 , the intermediate layer 302 is flipped; in this embodiment, the relative positions of the second protective layer 330, the first storage array layer 307, the first device layer 303, the intermediate layer 302, the second device layer 304 and the first protective layer 329 do not change, and it can be considered that after the intermediate layer 302 is flipped, the second protective layer 330 is located at the bottom, the first storage array layer 307, the first device layer 303, the intermediate layer 302, the second device layer 304 and the first protective layer 329 are stacked in turn upwards, at this time, the second protective layer 330 can prevent the first storage array layer 307 from being abraded.

[0140] and the first protective layer 329 is removed; to expose the second device layer 304, so as to facilitate the subsequent connection between the second device layer 304 and the second storage array layer 310.

[0141] Please refer to Figure 13attaching the second storage array layer 310 on the second device layer 304; in combination with the foregoing description, the first initial intermediate layer 327 can be considered as a substrate on which the second device layer 304 is formed, and the second storage array layer 310 is formed on another substrate (not shown in the figure) and then attached on the second device layer 304.

[0142] In the process of forming the second storage array layer 310, the second storage array layer 310 includes a plurality of second storage structures and a plurality of third connecting parts 311, the third connecting parts 311 are located on the side of the second storage array layer 310 close to the second device layer 304, and one end of the second storage structure close to the second device layer 304 is connected with the third connecting part 311; and in the process of forming the second device layer 304 in step 100, after forming the second transistor 306, a fourth connecting part 312 can also be formed on the side of the second transistor 306 away from the intermediate layer 302, and the second transistor 306 is connected with the fourth connecting part 312. Then the connection between the second storage array layer 310 and the second device layer 304 can be realized through the bonding between the third connecting part 311 and the fourth connecting part 312, and the connection between the second storage array layer 310 and the second device layer 304 is further realized.

[0143] In combination with the foregoing description Figure 12 And Figure 13 The second protective layer 330 is removed to expose the first storage array layer 307, facilitating the subsequent connection between the first storage array layer 307 and the packaging substrate 313.

[0144] Through the above arrangement, the second protective layer 330 is located on the side of the first storage array layer 307 away from the first device layer 303, so as to avoid that the first storage array layer 307 is worn in the process of forming the second storage array layer 310 on the second device layer 304.

[0145] The preparation method of the three-dimensional memory 301 provided by the embodiment of the application forms the five-layer structure of the first storage array layer 307, the first device layer 303, the intermediate layer 302, the second device layer 304 and the first storage array layer 307 arranged in the thickness direction of the intermediate layer 302, and the first storage array layer 307 and the second storage array layer 310 for storage in a unit area, thereby increasing the capacity of the three-dimensional memory 301.

[0146] The preparation method of the three-dimensional memory 301 provided by the embodiment of the application can further include:

[0147] Please refer to Figure 14The package substrate 313 is formed, and the connection circuit 314 is arranged on the package substrate 313. The first contact 318 and the second contact 319 are arranged on the surface of the package substrate 313 close to the intermediate layer 302, and the first contact 318 and the second contact 319 are connected to the connection circuit 314.

[0148] After the first storage array layer 307 is formed, the first storage array layer 307 further includes the first pad 315 and the second pad 317 arranged at intervals. The first pad 315 and the second pad 317 are located on the side of the first storage array layer 307 away from the intermediate layer 302. The first pad 315 is connected to at least one first transistor 305.

[0149] After the first device layer 303 is attached to the first storage array layer 307, the first storage array layer 307 further includes: the first contact 318 is connected to the first pad 315 by welding; and the second contact 319 is connected to the second pad 317 by welding.

[0150] In the above implementation, the first contact 318 and the first pad 315 can be welded by using a bumping process. Similarly, the second contact 319 and the second pad 317 can also be welded by using a bumping process.

[0151] Through the above arrangement, the welding between the first contact 318 and the first pad 315 can realize the electrical interconnection between the first contact 318 and the first pad 315. The welding between the second contact 319 and the second pad 317 can realize the electrical interconnection between the second contact 319 and the second pad 317. The solder formed by welding can also play a role in stress buffering between the first storage array layer 307 and the package substrate 313.

[0152] Please refer to Figure 15 After the package substrate 313 is formed, the third contact 323 and the fourth contact 324 are arranged on the surface of the package substrate 313 close to the intermediate layer 302, and the third contact 323 and the fourth contact 324 are connected to the connection circuit 314.

[0153] After the second storage array layer 310 is formed, the second storage array layer 310 further includes the third pad 320 and the fourth pad 322 arranged at intervals. The third pad 320 and the fourth pad 322 are located on the side of the second storage array layer 310 away from the intermediate layer 302. The third pad 320 is connected to at least one second transistor 306.

[0154] After the second storage array layer 310 is attached to the second device layer 304, the first lead 325 and the second lead 326 are formed. The third contact 323 and the third pad 320 are connected by the first lead 325, and the fourth contact 324 and the fourth pad 322 are connected by the second lead 326.

[0155] In the above implementation, the third contact 323 and the third pad 320 can be connected by wire bonding, and the fourth contact 324 and the fourth pad 322 can also be connected by wire bonding.

[0156] Through the above arrangement, the electrical connection between the third pad 320 and the third contact 323 can be achieved by the first wire 325, and the electrical connection between the fourth pad 322 and the fourth contact 324 can be achieved by the second wire 326.

[0157] Please refer to Figure 16 and Figure 17 Some embodiments of the present application also provide a storage system 1000. The storage system 1000 includes a controller 20 and a three-dimensional memory 301, wherein the three-dimensional memory 301 can include the three-dimensional memory 301 as described above, and the controller 20 is coupled to the three-dimensional memory 301 to control the three-dimensional memory 301 to store data.

[0158] Among them, the storage system 1000 can be integrated into various types of storage devices, for example, included in the same package (for example, a universal flash storage (UFS) package or an embedded multi media card (eMMC) package). That is, the storage system 1000 can be applied to and packaged into different types of electronic products, such as mobile phones (for example, mobile phones), desktop computers, tablet computers, notebook computers, servers, vehicle-mounted devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device with a storage device.

[0159] In some embodiments, referring to Figure 16 The storage system 1000 includes a controller 20 and one three-dimensional memory 301, and the storage system 1000 can be integrated into a memory card.

[0160] Among them, the memory card includes any one of PC card (PCMCIA, Personal Computer Memory Card International Association), compact flash (Compact Flash, CF for short) card, smart media (Smart Media, SM for short) card, memory stick, multimedia card (Multimedia Card, MMC for short), secure digital memory card (Secure Digital Memory Card, SD for short), and UFS.

[0161] In some embodiments, the controller 20 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. Figure 17 In some embodiments, the controller 20 can be configured to manage data stored in the three-dimensional memory 301 and communicate with an external device (e.g., a host). In some embodiments, the controller 20 can also be configured to control the operation of the three-dimensional memory 301, such as read, erase, and program operations. In some embodiments, the controller 20 can also be configured to manage various functions related to data stored or to be stored in the three-dimensional memory 301, including at least one of bad block management, garbage collection, logical to physical address translation, wear leveling. In some embodiments, the controller 20 is also configured to process error correction codes related to data read from or written to the three-dimensional memory 301.

[0162] Of course, the controller 20 can also perform any other suitable functions, such as formatting the three-dimensional memory 301; for example, the controller 20 can communicate with an external device (e.g., a host) through at least one of various interface protocols.

[0163]

[0164]

[0165]

[0166] ​​​It should be noted that the interface protocol includes at least one of a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronic device (IDE) protocol, and a Firewire protocol.

[0167] Some embodiments of the present application also provide an electronic device. The electronic device can be any one of a mobile phone, a desktop computer, a tablet computer, a notebook computer, a server, a vehicle-mounted device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc.

[0168] The electronic device can include a host and the storage system 1000 described above, wherein the coupling between the host and the storage system 1000 can further include at least one of a central processing unit (CPU) and a cache.

[0169] The above merely provides a specific implementation of the present application, but the protection scope of the present application is not limited thereto, any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A three-dimensional memory, comprising: The three-dimensional memory comprises: an intermediate layer having a first side and a second side opposite in a thickness direction of the intermediate layer; a first device layer comprising a plurality of first transistors, the first device layer being located on the first side of the intermediate layer; a second device layer comprising a plurality of second transistors, the second device layer being located on the second side of the intermediate layer; a first storage array layer located on a side of the first device layer away from the intermediate layer; a second storage array layer located on a side of the second device layer away from the intermediate layer; a packaging substrate provided with a connecting circuit, the packaging substrate being located on a side of the first storage array layer away from the intermediate layer, and at least one of the first transistors, the first storage array layer, at least one of the second transistors, and the second storage array layer being connected to the connecting circuit.

2. The three-dimensional memory of claim 1, wherein, The first storage array layer is connected to at least one of the first transistors, and the second storage array layer is connected to at least one of the second transistors.

3. The three-dimensional memory of claim 1, wherein, The first storage array layer comprises a first pad and a second pad arranged at intervals, the first pad and the second pad being located on a side of the first storage array layer away from the intermediate layer, the first pad being connected to at least one of the first transistors and the connecting circuit, and the second pad being connected to the first storage array layer and the connecting circuit.

4. The three-dimensional memory of claim 3, wherein, The first storage array layer comprises a first conductive column, one end of the first conductive column being connected to the first pad, and the other end of the first conductive column being connected to the first transistor.

5. The three-dimensional memory of claim 3, wherein, The packaging substrate is provided with a first contact and a second contact on a surface close to the intermediate layer, the first contact and the second contact being connected to the connecting circuit, the first contact being connected to the first pad, and the second contact being connected to the second pad.

6. The three-dimensional memory of claim 5, wherein, The first contact is welded to the first pad, and the second contact is welded to the second pad.

7. The three-dimensional memory as claimed in any one of claims 1-6, wherein, The second storage array layer comprises a third pad and a fourth pad arranged at intervals, the third pad and the fourth pad being located on a side of the second storage array layer away from the intermediate layer, the third pad being connected to at least one of the second transistors and the connecting circuit, and the fourth pad being connected to the second storage array layer and the connecting circuit.

8. The three-dimensional memory as recited in claim 7, further comprising, The second storage array layer comprises a second conductive column, one end of the second conductive column being connected to the third pad, and the other end of the second conductive column being connected to the second transistor.

9. The three-dimensional memory as recited in claim 7, further comprising, The packaging substrate is provided with a third contact and a fourth contact on a surface close to the intermediate layer, the third contact and the fourth contact being connected to the connecting circuit; the three-dimensional memory further comprises a first lead and a second lead, one end of the first lead being connected to the third pad, the other end of the first lead being connected to the third contact, one end of the second lead being connected to the fourth pad, and the other end of the second lead being connected to the fourth contact.

10. A method of making a three-dimensional memory, comprising: The three-dimensional memory comprises: forming a first device layer and a second device layer on a first initial intermediate layer, and obtaining an intermediate layer; The first device layer comprises a plurality of first transistors, the first device layer is located on a first side of the intermediate layer, the second device layer comprises a plurality of second transistors, the second device layer is located on a second side of the intermediate layer, the first side and the second side are opposite sides of the intermediate layer in a thickness direction; The forming of the first device layer and the second device layer on the first initial intermediate layer comprises: forming the second device layer on one side of the first initial intermediate layer, and obtaining a second initial intermediate layer; forming a first protective layer on the second device layer; turning over the second initial intermediate layer, forming the first device layer on a side of the second initial intermediate layer away from the second device layer, and obtaining an intermediate layer; forming a first storage array layer and a second storage array layer, the first storage array layer is located on a side of the first device layer away from the intermediate layer, the first storage array layer is connected with at least one of the plurality of first transistors, the second storage array layer is located on a side of the second device layer away from the intermediate layer, and the second storage array layer is connected with at least one of the plurality of first transistors; forming a packaging substrate, the packaging substrate is provided with a connecting circuit, the packaging substrate is provided with a first contact and a second contact on a surface close to the intermediate layer, and the first contact and the second contact are connected with the connecting circuit; after the forming of the first storage array layer, the first storage array layer further comprises a first pad and a second pad arranged at intervals, the first pad and the second pad are located on a side of the first storage array layer away from the intermediate layer, and the first pad is connected with at least one of the first transistors; after the first storage array layer is attached to the first device layer, the first storage array layer further comprises that the first contact and the first pad are connected by welding, and the second contact and the second pad are connected by welding.

11. The method of claim 10, wherein, The forming of the first storage array layer and the second storage array layer comprises: attaching the first storage array layer to the first device layer; forming a second protective layer on the first storage array layer; turning over the intermediate layer and removing the first protective layer; attaching the second storage array layer to the second device layer; removing the second protective layer.

12. The method of claim 10, wherein, The preparation method further comprises: after the forming of the packaging substrate, the packaging substrate is provided with a third contact and a fourth contact on a surface close to the intermediate layer, and the third contact and the fourth contact are connected with the connecting circuit; after the forming of the second storage array layer, the second storage array layer further comprises a third pad and a fourth pad arranged at intervals, the third pad and the fourth pad are located on a side of the second storage array layer away from the intermediate layer, and the third pad is connected with at least one of the second transistors; after the second storage array layer is attached to the second device layer, the second storage array layer further comprises that a first lead wire and a second lead wire are formed, the third contact and the third pad are connected through the first lead wire, and the fourth contact and the fourth pad are connected through the second lead wire.

13. A storage system, characterized by comprises: the three-dimensional memory of any one of claims 1-9; a controller coupled to the three-dimensional memory to control the three-dimensional memory to store data.

14. An electronic device, comprising: a host coupled to the memory system.

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