Planar silicon carbide MOSFET device and preparation method thereof

Abstract

The invention provides a planar silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device and a preparation method thereof, and the planar silicon carbide MOSFET device is provided with a first N-type doped region which has an overlapping region with a first P-type well region in a first source electrode structure and a second P-type well region in a second source electrode structure, and the N-type doped region and the P-type well region in the overlapping region are neutralized with each other. Therefore, the channel length of the device is shortened, the channel resistance of the device is reduced, and the resistance of an accumulation region near a channel can be optimized. Second N-type doped regions with different widths and ion concentrations are arranged below the first N-type doped region, so that the JFET region resistance is optimized. Moreover, the width and concentration of the first N-type doped region and the second N-type doped region are regulated and controlled at the same time, so that the surface electric field of the JFET region can be regulated and controlled, and the performance of the device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a planar silicon carbide MOSFET device and a preparation method thereof. Background Art

[0002] Planar SiC MOSFET devices are one of the most widely used SiC MOSFET structures in the market. Their main features include relatively simple process, good cell consistency and high avalanche energy. Among them, optimizing resistance is an important direction for optimizing planar SiC MOSFET devices.

[0003] In the planar silicon carbide MOSFET device structure, the channel resistance and the JFET (Junction Field Effect Transistor) regional resistance account for a particularly large proportion, so by optimizing the channel resistance and the JFET regional resistance, the device performance can be effectively improved. Among them, reducing the channel length is an important way to optimize the channel resistance, but the channel length formed in the existing technology is only about 0.5 microns, and there is still a lot of room for optimization. And as the size of existing planar silicon carbide MOSFET devices continues to shrink, the proportion of JFET regional resistance increases significantly. At the same time, as the size of the JFET area decreases, the overcurrent density increases, and the difficulty of regulating the electric field distribution increases. Therefore, optimizing the JFET regional resistance cannot be optimized simply by increasing the ion concentration in the JFET area.

[0004] Therefore, as the feature size continues to shrink, how to optimize the resistance in planar silicon carbide MOSFET devices has become a technical problem that the industry urgently needs to solve. Summary of the invention

[0005] The present invention provides a planar silicon carbide MOSFET device and a manufacturing method thereof, so as to optimize the resistance in the planar silicon carbide MOSFET device.

[0006] According to a first aspect of the present invention, there is provided a planar silicon carbide MOSFET device, comprising:

[0007] substrate;

[0008] an epitaxial layer, the epitaxial layer being located on the first surface of the substrate;

[0009] a device layer, the device layer comprising a drain structure, a first source structure, a second source structure and a gate structure; the drain structure is located on the second surface of the substrate, and the first surface and the second surface of the substrate are opposite; the first source structure and the second source structure are both located in the epitaxial layer, and the first source structure comprises a first P-type well region, and the second source structure comprises a second P-type well region; the gate structure is located on the surface of the epitaxial layer;

[0010] A first N-type doped region, wherein the first N-type doped region is located in the epitaxial layer and has an overlapping region with both the first P-type well region and the second P-type well region;

[0011] a second N-type doping region, the second N-type doping region being located below the first N-type doping region and between the first P-type well region and the second P-type well region; wherein the ion concentration of the second N-type doping region is greater than the ion concentration of the first N-type doping region;

[0012] a dielectric layer, the dielectric layer covering the upper surface and four sides of the gate structure;

[0013] A metal connection layer covers a surface of the epitaxial layer and a surface of the dielectric layer and is electrically connected to the first source structure and the second source structure.

[0014] Optionally, the width of the overlapping region is between 0.1 micrometer and 0.2 micrometer.

[0015] Optionally, the depth of the first N-type doping region is between 0.1 micrometer and 0.4 micrometer.

[0016] According to a second aspect of the present invention, there is provided a method for preparing a planar silicon carbide MOSFET device, comprising:

[0017] providing a substrate;

[0018] forming an epitaxial layer on the first surface of the substrate;

[0019] forming a first source structure and a second source structure in the epitaxial layer, wherein the first source structure includes a first P-type well region and the second source structure includes a second P-type well region; forming a drain structure on the second surface of the substrate;

[0020] forming a first N-type doped region in the epitaxial layer, wherein the first N-type doped region is located in the epitaxial layer and has an overlapping region with both the first P-type well region and the second P-type well region;

[0021] forming a second N-type doping region in the epitaxial layer, wherein the second N-type doping region is located below the first N-type doping region and between the first P-type well region and the second P-type well region; wherein the ion concentration of the second N-type doping region is greater than the ion concentration of the first N-type doping region;

[0022] A gate structure, a dielectric layer and a metal connection layer are sequentially formed on the surface of the epitaxial layer to form the planar silicon carbide MOSFET device.

[0023] Optionally, forming the first N-type doping region specifically includes:

[0024] forming a first patterned mask layer on the surface of the epitaxial layer, wherein the first patterned mask layer includes a first N-type doping region pattern and a barrier region, wherein the first N-type doping region pattern is located between the first P-type well region and the second P-type well region, and has an overlapping region with the first P-type well region and the second P-type well region;

[0025] Using the first patterned mask layer as a mask, N-type ions are implanted into the epitaxial layer to form a first N-type doped region.

[0026] Optionally, forming the second N-type doping region specifically includes:

[0027] forming a mask layer of a second N-type doping region pattern in the first N-type doping region pattern in the first patterned mask layer;

[0028] Using the mask layer of the second N-type doping region pattern as a mask, N-type ions are implanted into the epitaxial layer to form a second N-type doping region below the first N-type doping region.

[0029] Optionally, forming a mask layer of a second N-type doping region pattern in the first N-type doping region pattern in the first patterned mask layer specifically includes:

[0030] depositing a mask layer material in the first N-type doping region pattern in the first patterned mask layer;

[0031] Part of the mask layer material is removed by etching, and only the mask layer material on the two side walls of the first N-type doping region pattern is retained to form a mask layer of the second N-type doping region pattern as a second patterned mask layer.

[0032] Optionally, forming the gate structure specifically includes:

[0033] forming a gate oxide layer on the surface of the epitaxial layer;

[0034] A polysilicon layer is formed on the gate oxide layer to form a gate structure.

[0035] Optionally, after forming the gate oxide layer on the surface of the epitaxial layer, the method further comprises: performing annealing in a nitrogen-containing environment.

[0036] Optionally, the thickness of the gate oxide layer is between 40 nanometers and 80 nanometers.

[0037] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0038] In the planar silicon carbide MOSFET device provided in the first aspect of the present invention, a first N-type doped region having an overlapping region with the first P-type well region in the first source structure and the second P-type well region in the second source structure is provided, and the N-type doped region and the P-type well region in the overlapping region are neutralized with each other, so that the channel length of the device is shortened, thereby reducing the channel resistance of the device, and the resistance of the accumulation region near the channel can be optimized. A second N-type doped region with different widths and ion concentrations is also provided below the first N-type doped region to optimize the resistance of the JFET region. Moreover, by simultaneously regulating the widths and ion concentrations of the first N-type doped region and the second N-type doped region, the surface electric field of the JFET region can be regulated, thereby improving device performance.

[0039] In the preparation method of the planar silicon carbide MOSFET device provided in the second aspect of the present invention, the first N-type doping region and the second N-type doping region are formed in the epitaxial layer by ion implantation, wherein the first N-type doping region and the first P-type well region and the second P-type well region have overlapping regions, so that the channel length is shortened, thereby reducing the channel resistance, and by adjusting the concentration and width of the second N-type doping region, the JFET region resistance can be optimized.

[0040] Furthermore, the method for preparing the planar silicon carbide MOSFET device forms a mask layer of the second N-type doping region pattern by a self-alignment process, that is, a mask layer of the second N-type doping region pattern is formed in the first N-type doping region pattern in the first patterned mask layer. Compared with the traditional photolithography process, the self-alignment process can simplify the manufacturing process, improve the alignment accuracy and reduce the manufacturing cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 is a schematic cross-sectional structure diagram of a planar silicon carbide MOSFET device provided by an embodiment of the present invention;

[0042] Figure 2 It is a schematic flow chart of a method for preparing a planar silicon carbide MOSFET device provided in one embodiment of the present invention;

[0043] Figure 3a-3f is based on Figure 2The device cross-sectional structure schematic diagram corresponding to different process stages of the preparation method of the planar silicon carbide MOSFET device shown.

[0044] Reference numerals:

[0045] 1- substrate;

[0046] 2- epitaxial layer;

[0047] 3-Drain structure;

[0048] 4- first source structure;

[0049] 5- second source structure;

[0050] 6-a first N-type doping region;

[0051] 7-a second N-type doping region;

[0052] 8-gate oxide layer;

[0053] 9-polysilicon layer;

[0054] 10- dielectric layer;

[0055] 11-metal connection layer;

[0056] 401-first P-type well region;

[0057] 501 - second P-type well region. DETAILED DESCRIPTION

[0058] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the embodiments in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present invention. The terms "first", "second", "third", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0059] As described in the background art, it is difficult to effectively optimize the resistance in the planar silicon carbide MOSFET device in the prior art.

[0060] Generally, when a forward voltage is applied to the gate of a planar silicon carbide MOS tube, an electric field is formed in the device, causing the carriers (electrons or holes) in the channel to move, thereby forming a conductive path between the source and the drain. The resistance in the conductive path mainly includes the channel resistance, the JFET region resistance, the drift region resistance and the highly doped substrate resistance.

[0061] The following takes the channel resistance and JFET region resistance as examples to analyze in detail the problems existing in the resistance optimization of the existing planar silicon carbide MOS tube.

[0062] First, defects in the silicon carbide / silicon dioxide interface can cause low channel mobility, which in turn leads to a large channel on-resistance of the device. Existing technologies usually use nitrogen or nitric oxide to treat the silicon carbide / silicon dioxide interface to improve channel mobility, but this method can only improve channel mobility to a limited extent, so optimizing channel resistance by further reducing the channel length has become a key direction. The channel length currently formed by the self-aligned process can only be about 0.5 microns, and there is still much room for improvement.

[0063] Secondly, as the size of the device decreases, the width of the JFET region is further reduced, resulting in an increase in the proportion of resistance in the JFET region, which increases the resistance in the planar silicon carbide MOS device. The prior art usually optimizes the JFET region resistance by adjusting the width and ion concentration of the JFET region. However, as the size of the device decreases, the proportion of resistance in the JFET region increases significantly, and the width of the JFET region also decreases, resulting in an increase in the overcurrent density and a sharp increase in the electric field in the JFET region, which increases the difficulty of regulating the electric field distribution. Therefore, if the ion concentration of the JFET region is simply increased to reduce the resistance, this cannot solve the problem of electric field distribution. Therefore, the JFET region resistance cannot be optimized only by adjusting the width and ion concentration of the JFET region.

[0064] The JFET regional resistance, that is, in a planar silicon carbide MOS tube, when the current is confined to flow in a narrow N region close to the P body region, a JFET effect will be generated, thereby generating a JFET regional resistance.

[0065] In view of this, the present invention creatively proposes a planar silicon carbide MOSFET device.

[0066] in, Figure 1 It is a schematic diagram of the cross-sectional structure of a planar silicon carbide MOSFET device provided in one embodiment of the present invention.

[0067] Please refer to Figure 1 According to an embodiment of the present invention, a planar silicon carbide MOSFET device is provided, comprising:

[0068] Substrate 1;

[0069] An epitaxial layer 2, wherein the epitaxial layer 2 is located on the first surface of the substrate 1;

[0070] A device layer, the device layer comprising a drain structure 3, a first source structure 4, a second source structure 5 and a gate structure; the drain structure 3 is located on the second surface of the substrate 1, and the first surface and the second surface of the substrate 1 are opposite; the first source structure 4 and the second source structure 5 are both located in the epitaxial layer 2, and the first source structure 4 includes a first P-type well region 401, and the second source structure 5 includes a second P-type well region 501; the gate structure is located on the surface of the epitaxial layer 2;

[0071] A first N-type doping region 6, wherein the first N-type doping region 6 is located in the epitaxial layer 2 and has an overlapping region with both the first P-type well region 401 and the second P-type well region 501;

[0072] a second N-type doping region 7, wherein the second N-type doping region 7 is located below the first N-type doping region 6 and between the first P-type well region 401 and the second P-type well region 501; wherein the ion concentration of the second N-type doping region 7 is greater than the ion concentration of the first N-type doping region 6;

[0073] A dielectric layer 10, wherein the dielectric layer 10 covers the upper surface and four sides of the gate structure;

[0074] A metal connection layer 11 , wherein the metal connection layer 11 covers the surface of the epitaxial layer 2 and the surface of the dielectric layer 10 , and is electrically connected to the first source structure 4 and the second source structure 5 .

[0075] Through the above technical means, the embodiment of the present invention can provide a planar silicon carbide MOSFET device that optimizes the resistance in the device. The specific principle is as follows:

[0076] The planar silicon carbide MOSFET device provided by the present invention includes a first N-type doping region 6 and a second N-type doping region 7. The first N-type doping region 6 is located between the first P-type well region 401 and the second P-type well region 501, and there is an overlapping region with both the first P-type well region 401 and the second P-type well region 501, and the P-type ions and the N-type ions in the overlapping region are neutralized with each other, so that the overlapping region is N-type or weak P-type, resulting in a shortened channel length, thereby reducing the channel resistance, and also reducing the resistance of the accumulation region near the channel, so that the current distribution during the device opening and closing process can be effectively adjusted, and the failure caused by overshoot current can be reduced. The second N-type doping region 7 is located below the first N-type doping region 6 and between the first P-type well region 401 and the second P-type well region 501. By adjusting the concentration and width of the second N-type doping region 7, the JFET region resistance in the device can be optimized.

[0077] And by adjusting the ion concentration of the second N-type doping region 7 and cooperating with the setting of the first N-type doping region 6, the JFET region resistance optimization and the JFET surface electric field distribution problem can be balanced. Among them, increasing the ion concentration of the second N-type doping region 7 can reduce the JFET region resistance, but increasing the second N-type doping region 7 will cause the JFET region surface electric field to increase, and because the width of the first N-type doping region 6 is greater than the width of the second N-type doping region 7, the JFET region surface electric field strength can be reduced, thereby achieving a good balance between the JFET region resistance optimization and the JFET surface electric field distribution problem.

[0078] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0079] As an implementation method, the width of the overlapping region is between 0.1 micrometers and 0.2 micrometers, and the ion concentration of the first N-type doping region 6 is relatively small. If the ion concentration in the first N-type doping region 6 is relatively large, the ions in the first N-type doping region 6 will diffuse into the first P-type well region 401 and the second P-type well region 501, causing device leakage.

[0080] Specifically, if the overlapping region is N-type or weak P-type, the accumulation region near the channel is also N-type or weak P-type, so that the resistance of the accumulation region near the channel is reduced, which can effectively adjust the current distribution during the device startup and shutdown process and reduce failures caused by overshoot current.

[0081] As a specific implementation manner, the depth of the first N-type doping region 6 is between 0.1 micrometer and 0.4 micrometer.

[0082] In summary, in the planar silicon carbide MOSFET device provided by the present invention, a first N-type doped region having an overlapping region with the first P-type well region in the first source structure and the second P-type well region in the second source structure is provided, and the N-type doped region and the P-type well region in the overlapping region are neutralized with each other, so that the channel length of the device is shortened, thereby reducing the channel resistance of the device, and the resistance of the accumulation region near the channel can be optimized. A second N-type doped region with different widths and ion concentrations is also provided below the first N-type doped region to optimize the resistance of the JFET. Moreover, by simultaneously regulating the widths and ion concentrations of the first N-type doped region and the second N-type doped region, the surface electric field of the JFET region can be regulated, thereby improving the device performance.

[0083] in, Figure 2 It is a schematic flow chart of a method for preparing a planar silicon carbide MOSFET device provided in one embodiment of the present invention; Figure 3a-3f is based on Figure 2 The device cross-sectional structure schematic diagram corresponding to different process stages of the preparation method of the planar silicon carbide MOSFET device shown.

[0084] like Figure 2 Combination Figure 3a-3f As shown, an embodiment of the present invention further provides a method for preparing a planar silicon carbide MOSFET device, the method comprising:

[0085] S1: Provide a substrate 1; Figure 3a shown.

[0086] Specifically, the substrate 1 is an N-type highly doped silicon carbide substrate.

[0087] S2: forming an epitaxial layer 2 on the first surface of the substrate 1; Figure 3b shown.

[0088] Specifically, the epitaxial layer 2 is an N-type low-doped silicon carbide epitaxial layer 2 .

[0089] S3: forming a first source structure 4 and a second source structure 5 in the epitaxial layer 2, wherein the first source structure 4 includes a first P-type well region 401, and the second source structure 5 includes a second P-type well region 501; forming a drain structure 3 on the second surface of the substrate 1; Figure 3c shown.

[0090] Specifically, the drain structure 3 may be, for example, a drain metal electrode, the material of which includes titanium, nickel, silver, etc. Those skilled in the art may select the drain metal electrode according to actual conditions, and the present invention is not limited thereto.

[0091] The first source structure 4 includes a first P-type well region 401, a first N region and a first P region, and the second source structure 5 includes a second P-type well region 501, a second N region and a second P region. Step S3 specifically includes the following steps:

[0092] S31: forming a third patterned mask layer on the epitaxial layer 2; wherein the third patterned mask layer includes a first P-type well region pattern and a second P-type well region pattern;

[0093] S32: performing P-type ion implantation using the third patterned mask layer as a mask to form the first P-type well region 401 and the second P-type well region 501;

[0094] S33: removing the third patterned mask layer;

[0095] S34: forming a fourth patterned mask layer on the epitaxial layer 2; wherein the fourth patterned mask layer includes a first N region pattern and a second N region pattern;

[0096] S35: performing high-concentration N-type ion implantation using the fourth patterned mask layer as a mask to form the first N region and the second N region;

[0097] S36: forming a fourth patterned mask layer on the epitaxial layer 2; wherein the fourth patterned mask layer includes a first P region pattern and a second P region pattern;

[0098] S37: performing high-concentration P-type ion implantation using the fourth patterned mask layer as a mask to form the first P region and the second P region.

[0099] As an example, the material of the third patterned mask layer and the fourth patterned mask layer may be photoresist. Of course, there are many other options for the material of the third patterned mask layer and the fourth patterned mask layer, and the present invention is not limited thereto.

[0100] The above is a description of step S1 to step S3. The remaining steps of the method for preparing a planar silicon carbide MOSFET device provided in this embodiment are described below:

[0101] S4: forming a first N-type doping region 6 in the epitaxial layer 2, wherein the first N-type doping region 6 is located in the epitaxial layer 2 and has an overlapping region with both the first P-type well region 401 and the second P-type well region 501; Figure 3d shown.

[0102] Wherein, step S4 specifically includes the following steps:

[0103] S41: forming a first patterned mask layer on the surface of the epitaxial layer 2, wherein the first patterned mask layer includes a first N-type doping region pattern and a barrier region, wherein the first N-type doping region pattern is located between the first P-type well region 401 and the second P-type well region 501, and has an overlapping region with the first P-type well region 401 and the second P-type well region 501, which overlaps with each other in the upper and lower directions;

[0104] S42 : using the first patterned mask layer as a mask, injecting N-type ions into the epitaxial layer 2 to form a first N-type doped region 6 .

[0105] As a specific implementation, the first patterned mask layer may be, for example, a hard mask layer, and step S41 specifically includes the following steps:

[0106] S411: depositing a hard mask layer on the epitaxial layer 2;

[0107] S412: spin coating a first photoresist layer on the hard mask layer;

[0108] S413: using a first photomask to expose and develop the first photoresist layer to form a first patterned photoresist layer;

[0109] S414: using the first patterned photoresist layer as a mask, etching the hard mask layer to form a first patterned hard mask layer as a first patterned mask layer.

[0110] S5: forming a second N-type doping region 7 in the epitaxial layer 2, wherein the second N-type doping region 7 is located below the first N-type doping region 6 and between the first P-type well region 401 and the second P-type well region 501; wherein the ion concentration of the second N-type doping region 7 is greater than the ion concentration of the first N-type doping region 6; Figure 3e shown.

[0111] Wherein, step S5 specifically includes the following steps:

[0112] S51: forming a mask layer of a second N-type doping region pattern in the first N-type doping region pattern in the first patterned mask layer;

[0113] S52 : using the mask layer of the second N-type doping region pattern as a mask, injecting N-type ions into the epitaxial layer 2 to form a second N-type doping region 7 below the first N-type doping region 6 .

[0114] As a specific implementation, step S51 specifically includes the following steps:

[0115] S511: depositing a mask layer material in the first N-type doping region pattern in the first patterned mask layer;

[0116] S512: etching and removing part of the mask layer material, leaving only the mask layer material on both side walls of the first N-type doping region pattern, to form a mask layer of the second N-type doping region pattern as a second patterned mask layer.

[0117] Of course, after forming the second N-type doping region 7 in the epitaxial layer 2 , the method further includes: removing the second patterned mask layer on the surface of the epitaxial layer 2 , and performing high temperature annealing to activate ions in the first source structure 4 and the second source structure 5 .

[0118] The mask layer material may be, for example, silicon dioxide. Of course, those skilled in the art should be aware that there are many other mask layer materials, and the present invention does not limit this.

[0119] The etching method in S512 may be, for example, reactive ion etching, which can achieve steep sidewall etching. Of course, there are many other etching methods, and the present invention is not limited thereto.

[0120] S6: forming a gate structure, a dielectric layer 10 and a metal connection layer 11 on the surface of the epitaxial layer 2 in sequence to form the planar silicon carbide MOSFET device; Figure 3f shown.

[0121] Wherein, step S6 specifically includes the following steps:

[0122] S61 : forming a gate oxide layer 8 on the surface of the epitaxial layer 2 , wherein the gate oxide layer 8 covers the first N-type doping region 6 , a portion of the first source structure 4 and a portion of the second source structure 5 .

[0123] Specifically, the thickness of the gate oxide layer 8 is between 40 nanometers and 80 nanometers.

[0124] Preferably, after S61, the step may further include: annealing in a nitrogen-containing environment, which can further eliminate the interface defects of silicon dioxide / silicon carbide, thereby further improving the channel mobility. The nitrogen-containing environment may include nitrogen monoxide or nitrogen dioxide.

[0125] S62: forming a polysilicon layer 9 on the gate oxide layer 8 to form a gate structure.

[0126] S63: forming a dielectric layer 10, wherein the dielectric layer 10 covers the upper surface and four sides of the gate structure.

[0127] S64: forming a metal connection layer 11, wherein the metal connection layer 11 covers the surface of the epitaxial layer 2 and the surface of the dielectric layer 10, and is electrically connected to the first source structure 4 and the second source structure 5 to form the planar silicon carbide MOSFET device.

[0128] In summary, in the preparation method of the planar silicon carbide MOSFET device provided by the present invention, the first N-type doping region and the second N-type doping region are formed in the epitaxial layer by ion implantation, wherein the first N-type doping region and the first P-type well region and the second P-type well region have overlapping regions, so that the channel length is shortened, thereby reducing the channel resistance, and by adjusting the concentration and width of the second N-type doping region, the JFET region resistance can be optimized.

[0129] Furthermore, the method for preparing the planar silicon carbide MOSFET device forms a mask layer of the second N-type doping region pattern by a self-alignment process, that is, a mask layer of the second N-type doping region pattern is formed in the first N-type doping region pattern in the first patterned mask layer. Compared with the traditional photolithography process, the self-alignment process can simplify the manufacturing process, improve the alignment accuracy and reduce the manufacturing cost.

[0130] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A planar silicon carbide MOSFET device, characterized in that: include: substrate; an epitaxial layer, the epitaxial layer being located on the first surface of the substrate; a device layer, the device layer comprising a drain structure, a first source structure, a second source structure and a gate structure; the drain structure is located on the second surface of the substrate, and the first surface and the second surface of the substrate are opposite; the first source structure and the second source structure are both located in the epitaxial layer, and the first source structure comprises a first P-type well region, and the second source structure comprises a second P-type well region; the gate structure is located on the surface of the epitaxial layer; A first N-type doped region, wherein the first N-type doped region is located in the epitaxial layer and has an overlapping region with both the first P-type well region and the second P-type well region; a second N-type doping region, the second N-type doping region being located below the first N-type doping region and between the first P-type well region and the second P-type well region; wherein the ion concentration of the second N-type doping region is greater than the ion concentration of the first N-type doping region; a dielectric layer, the dielectric layer covering the upper surface and four sides of the gate structure; A metal connection layer covers a surface of the epitaxial layer and a surface of the dielectric layer and is electrically connected to the first source structure and the second source structure.

2. The planar silicon carbide MOSFET device according to claim 1, characterized in that: The width of the overlapping area is between 0.1 micrometer and 0.2 micrometer.

3. The planar silicon carbide MOSFET device according to claim 1, characterized in that: The depth of the first N-type doping region is between 0.1 micrometer and 0.4 micrometer.

4. A method for preparing a planar silicon carbide MOSFET device, characterized in that: The method includes: providing a substrate; forming an epitaxial layer on the first surface of the substrate; forming a first source structure and a second source structure in the epitaxial layer, wherein the first source structure includes a first P-type well region and the second source structure includes a second P-type well region; forming a drain structure on the second surface of the substrate; forming a first N-type doped region in the epitaxial layer, wherein the first N-type doped region is located in the epitaxial layer and has an overlapping region with both the first P-type well region and the second P-type well region; forming a second N-type doping region in the epitaxial layer, wherein the second N-type doping region is located below the first N-type doping region and between the first P-type well region and the second P-type well region; wherein the ion concentration of the second N-type doping region is greater than the ion concentration of the first N-type doping region; A gate structure, a dielectric layer and a metal connection layer are sequentially formed on the surface of the epitaxial layer to form the planar silicon carbide MOSFET device.

5. The method for preparing a planar silicon carbide MOSFET device according to claim 4, characterized in that: Forming the first N-type doping region specifically includes: forming a first patterned mask layer on the surface of the epitaxial layer, wherein the first patterned mask layer includes a first N-type doping region pattern and a barrier region, wherein the first N-type doping region pattern is located between the first P-type well region and the second P-type well region, and has an overlapping region with the first P-type well region and the second P-type well region; Using the first patterned mask layer as a mask, N-type ions are implanted into the epitaxial layer to form a first N-type doped region.

6. The method for preparing a planar silicon carbide MOSFET device according to claim 5, characterized in that: Forming the second N-type doping region specifically includes: forming a mask layer of a second N-type doping region pattern in the first N-type doping region pattern in the first patterned mask layer; Using the mask layer of the second N-type doping region pattern as a mask, N-type ions are implanted into the epitaxial layer to form a second N-type doping region below the first N-type doping region.

7. The method for preparing a planar silicon carbide MOSFET device according to claim 6, characterized in that: The step of forming a mask layer of a second N-type doping region pattern in the first N-type doping region pattern in the first patterned mask layer specifically includes: depositing a mask layer material in the first N-type doping region pattern in the first patterned mask layer; Part of the mask layer material is removed by etching, and only the mask layer material on the two side walls of the first N-type doping region pattern is retained to form a mask layer of the second N-type doping region pattern as a second patterned mask layer.

8. The method for preparing a planar silicon carbide MOSFET device according to claim 4, characterized in that: Forming the gate structure specifically includes: forming a gate oxide layer on the surface of the epitaxial layer; A polysilicon layer is formed on the gate oxide layer to form a gate structure.

9. The method for preparing a planar silicon carbide MOSFET device according to claim 8, characterized in that: After forming the gate oxide layer on the surface of the epitaxial layer, the method further comprises: performing annealing in a nitrogen-containing environment.

10. The method for preparing a planar silicon carbide MOSFET device according to claim 8, characterized in that: The thickness of the gate oxide layer is between 40 nanometers and 80 nanometers.

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