High-density SiC MOSFET structure and preparation process thereof

Abstract

The invention relates to the technical field of MOS (metal oxide semiconductor), and discloses a high-density SiC MOSFET (metal oxide semiconductor field effect transistor) structure and a preparation process thereof, the high-density SiC MOSFET structure comprises a plurality of parallel MOS cells, each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a grid electrode and a source electrode, each semiconductor epitaxial layer comprises an N substrate layer, an N diffusion layer, a P well layer, an N well layer and a P-layer, the profile of the cross section of the grid electrode is T-shaped, and the width of the cross section of the P well layer and the width of the cross section of the N well layer do not exceed the width of the cross section of the grid electrode. The polycrystalline silicon is introduced to be in direct contact with the source electrode, so that the electric field effect of the drain electrode and the source electrode can be amplified, charges of the drain electrode mainly flow into the N diffusion layer from the metal deposition layer, and under the simultaneous action of a grid electrode electric field and an original electrode electric field, the charges mainly flow towards a charge channel and a charge channel in a concentrated manner; thus, diffusion of charges to adjacent MOS cells can be reduced.

Description

Technical Field

[0001] The present invention relates to the field of MOS semiconductor technology, and in particular to a high-density SiC MOSFET structure and a preparation process thereof. Background Art

[0002] The high-density SiC (silicon carbide) MOSFET structure aims to achieve higher current density, lower on-resistance and faster switching speed by optimizing device design and manufacturing process, while maintaining the high voltage resistance, high temperature and high frequency advantages of SiC materials.

[0003] The existing patent discloses a SiC MOSFET cell structure and its manufacturing method (publication number CN117976712A). The cell structure includes: source metal region source, source OHM region, source ohmic contact region N+, channel N-type doping region NC, channel P-type doping region PC, vertical conductive channel JFET region, Pwell region, drift layer N-, substrate N+, drain OHM region, gate electrode region gate, and gate-source isolation dielectric SiO2. In the technology disclosed in the patent, due to the electric field effect of the drain and source, the charge of the drain will drift to the diffusion layer of the adjacent MOS cell under the intervention of the gate electric field of the adjacent MOS cell. Summary of the invention

[0004] The main technical problem solved by the present invention is to provide a high-density SiC MOSFET structure and a preparation process thereof, which solves the problems in the above-mentioned background technology.

[0005] To solve the above technical problems, according to one aspect of the present invention, more specifically, a high-density SiCMOSFET structure is provided, comprising a plurality of mutually parallel MOS cells, wherein a single MOS cell comprises a drain, a semiconductor epitaxial layer, a gate and a source, wherein the semiconductor epitaxial layer comprises an N substrate layer, an N diffusion layer, a P well layer, an N well layer and a P-layer, wherein the cross-sectional profile of the gate is in a "T" shape, and the cross-sectional widths of the P well layer and the N well layer do not exceed the cross-sectional width of the gate, wherein the cross-sectional profile of the P well layer is in a "Z" shape, and the cross-sectional profile of the N well layer is in an "L" shape, wherein the P well layer and the N well layer fit each other; The left and right sides of the single MOS cell are formed with a P-layer by ion implantation, and polysilicon is etched and deposited inside the P-layer; Two metal deposition layers are arranged in the N substrate layer of a single MOS cell. The metal deposition layers are in ohmic contact with the drain electrode and are located below the connection between the P well layer and the P-layer.

[0006] Furthermore, a P-doped layer is formed on the left and right sides of the bottom of a single MOS cell by ion implantation, wherein the P-doped layer is in ohmic contact with the metal deposition layer and the drain.

[0007] Furthermore, an N+ doping layer is formed inside the N diffusion layer and directly above the metal deposition layer by ion implantation.

[0008] Furthermore, an oxide field plate is provided inside a single MOS cell and between two metal deposition layers, wherein the oxide field plate is in contact with the metal deposition layer and the drain.

[0009] A preparation process of a high-density SiC MOSFET structure comprises the following steps: S1, etching the upper surface and the lower surface of the semiconductor epitaxial layer forming the source region to form a rectangular groove; S2, the rectangular grooves on the upper surface are filled to form polysilicon, and the rectangular grooves on the lower surface are formed into a metal deposition layer by vapor deposition; S3, after cleaning the surface of the semiconductor epitaxial layer, a drain electrode and a source electrode are deposited; S4. Measure the performance improvement of SiC MOSFET structure.

[0010] Furthermore, in step S, the metal deposition layer in the rectangular groove on the lower surface includes TiSi 、CoSi and NiSi materials.

[0011] Furthermore, in the step S, the device having the drain and the source formed thereon is passivated.

[0012] Furthermore, in step S, the performance of the measured structure is determined according to the failure time of electromigration in the SiC MOSFET structure, the threshold voltage, and the time when the SiC MOSFET structure is turned on, then: In the formula, represents the stability performance factor of the measured SiC MOSFET structure, represents the current density, represents the threshold voltage of the measured structure, Indicates the turn-on time of the measured structure.

[0013] The present invention provides a high-density SiC MOSFET structure and a preparation process thereof. Compared with the prior art, the method has the following effects: 1. The present invention introduces polysilicon in direct contact with the source, which can amplify the electric field effect of the drain and the source, and the charge of the drain mainly flows from the metal deposition layer into the N diffusion layer. Under the simultaneous action of the gate electric field and the source electric field, the charge is mainly concentrated in the charge channel and the charge channel, which can reduce the diffusion of charge to adjacent MOS cells.

[0014] 2. The present invention can alleviate the electric field concentration phenomenon near the drain through the P-doped layer, thereby increasing the breakdown voltage of the device. The P-doped layer can also improve the distribution of current in the device and reduce the on-resistance. Moreover, the ohmic contact between the P-doped layer and the drain can improve the heat conduction path and reduce the thermal resistance of the device.

[0015] 3. The present invention allows charges to flow into the charge channel and the charge channel mainly in the vertical direction by arranging an N+ doped layer just above the metal deposition layer, thereby blocking the conduction path of the parasitic bipolar transistor and suppressing the latch-up effect. In high-voltage or high-current applications, the enhancement of the anti-latch-up capability can significantly improve the reliability of the device.

[0016] 4. The present invention can directly block the shortest route between the gate and the drain by means of the oxide field plate, thereby improving the anti-breakdown capability of the SiC MOSFET structure without reducing the gate electric field effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a structural schematic diagram of Embodiment 1 of the present invention; Figure 2 It is a structural schematic diagram of Embodiment 2 of the present invention; Figure 3 This is a schematic diagram of the structure of Embodiment 3 of the present invention; Figure 4 This is a schematic diagram of the structure of Embodiment 4 of the present invention; Figure 5 A schematic diagram of the electric field direction after the SiC MOSFET structure in the present invention is connected to the gate voltage; Figure 6 It is a schematic diagram of the arrangement of MOS cells in the present invention.

[0018] In the figure: 1, drain; 2, N substrate layer; 3, N diffusion layer; 4, P well layer; 5, N well layer; 6, gate; 7, source; 8, polysilicon; 9, P- layer; 10, metal deposition layer; 11, P- doped layer; 12, N+ doped layer; 13, oxide field plate. DETAILED DESCRIPTION

[0019] In order to make the technical solution of the present invention clearer, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0020] A preparation process of a high-density SiC MOSFET structure comprises the following steps: Step 1, etching the upper surface and the lower surface of the semiconductor epitaxial layer forming the source region to form a rectangular groove; Step 2: The rectangular grooves on the upper surface are filled with polysilicon 8, and the rectangular grooves on the lower surface are formed into a metal deposition layer 10 by vapor deposition; the metal deposition layer 10 in the rectangular grooves on the lower surface includes TiSi 、CoSi and NiSi materials.

[0021] Step 3: After cleaning the surface of the semiconductor epitaxial layer, the drain electrode 1 and the source electrode 7 are deposited; and the device formed with the drain electrode 1 and the source electrode 7 is passivated.

[0022] Step 4: Measure the performance improvement of the SiC MOSFET structure. The performance of the measured structure is determined based on the failure time of electromigration in the SiC MOSFET structure, the threshold voltage, and the time when the SiC MOSFET structure is turned on. Then: Where g represents the overall stability performance of the measured SiC MOSFET structure and is a dimensionless coefficient used to quantify the performance improvement of the device under parameters such as current density, threshold voltage and switching speed.

[0023] m represents the current intensity passing through a unit area, reflecting the current carrying capacity of the device. The greater the current density, the stronger the device's conduction capacity, but it may lead to an increase in thermal effects.

[0024] u represents the minimum gate voltage required for MOSFET to start conducting, which determines the turn-on characteristics of the device. The lower the threshold voltage, the easier it is for the device to turn on, but it may affect the turn-off stability.

[0025] t represents the time required for the device to switch from the off state to the fully turned on state, reflecting the switching speed. The shorter the turn-on time, the better the high-frequency performance of the device.

[0026] Among them, when calculating the stability performance coefficient of the measured SiC MOSFET structure, the current density of the measured SiC MOSFET structure is taken as (MA / cm²), the threshold voltage of the measured SiC MOSFET structure is (V), the measured turn-on time of the SiCMOSFET structure is (ns), then we have: From the above calculation, we can know that the stability performance coefficient of the SiC MOSFET structure measured this time is If the stability coefficient of the SiC MOSFET structure under the traditional process is calculated, , the stability performance of the SiC MOSFET structure measured this time is improved by 7.2%.

[0027] Example 1 like Figure 1 , 5 As shown in Figure 6, according to one aspect of the present invention, a high-density SiC MOSFET structure is provided, which is composed of a plurality of mutually parallel MOS cells, wherein a single MOS cell comprises a drain 1, a semiconductor epitaxial layer, a gate 6 and a source 7, wherein the semiconductor epitaxial layer comprises an N substrate layer 2, an N diffusion layer 3, a P well layer 4, an N well layer 5 and a P- layer 9, characterized in that: the cross-sectional profile of the gate 6 is in a "T" shape, and the cross-sectional widths of the P well layer 4 and the N well layer 5 do not exceed the cross-sectional width of the gate 6, the cross-sectional profile of the P well layer 4 is in a "Z" shape, and the cross-sectional profile of the N well layer 5 is in an "L" shape, wherein the P well layer 4 and the N well layer 5 fit each other. The left and right sides of the single MOS cell are formed with a P- layer 9 by ion implantation, and polysilicon 8 is etched and deposited inside the P- layer 9; two metal deposition layers 10 are arranged in the N substrate layer 2 of the single MOS cell, the metal deposition layers 10 are in ohmic contact with the drain 1, and the metal deposition layers 10 are located below the connection between the P well layer 4 and the P- layer 9. After the gate 6 is connected to the gate voltage, a charge channel 1 (such as Figure 6 As shown in FIG. 1 ), a path can be formed between the drain 1 and the source 7. Under the action of the T-shaped gate 6, a weak charge channel 2 is formed between the P-well layer 4 and the P-layer 9 to connect the N-well layer 5 and the N-diffusion layer 3.

[0028] At this time, an electric field is also directly formed between the drain 1 and the source 7, but the electric field strength is weaker than the electric field formed between the gate 6 and the drain 1. At this time, polysilicon 8 is introduced to directly contact the source 7, which can amplify the electric field effect of the drain 1 and the source 7 (the principle is to increase the electric field effect by reducing the distance between the drain 1 and the source 7), and the charge of the drain 1 mainly flows from the metal deposition layer 10 into the N diffusion layer 3. In this way, under the simultaneous action of the gate electric field and the source electric field, the charge is mainly concentrated in the charge channel 1 and the charge channel 2, which can reduce the diffusion of charge to adjacent MOS cells.

[0029] Example 2 like Figure 2As shown, a P-doped layer 11 is formed on the left and right sides of the bottom of a single MOS cell by ion implantation, wherein the P-doped layer 11 is in ohmic contact with the metal deposition layer 10 and the drain 1. The P-doped layer 11 can alleviate the electric field concentration phenomenon near the drain, increase the breakdown voltage of the device, and the P-doped layer 11 can improve the distribution of current in the device and reduce the on-resistance, and the ohmic contact between the P-doped layer 11 and the drain 1 can improve the heat conduction path and reduce the thermal resistance of the device.

[0030] Example 3 like Figure 3 As shown, an N+ doped layer 12 is formed by ion implantation inside the N diffusion layer 3 and directly above the metal deposition layer 10. Providing the N+ doped layer 12 directly above the metal deposition layer 10 allows the charges to flow mainly into the charge channel 1 and the charge channel 2 along the vertical direction, thereby blocking the conduction path of the parasitic bipolar transistor, thereby suppressing the latch-up effect. In high voltage or high current applications, the enhancement of the anti-latch-up capability can significantly improve the reliability of the device.

[0031] Example 4 like Figure 4 As shown, an oxide field plate 13 is provided inside a single MOS cell and between two metal deposition layers 10, wherein the oxide field plate 13 is in contact with the metal deposition layer 10 and the drain 1. The oxide field plate 13 can directly block the closest route between the gate 7 and the drain 1, thereby improving the anti-breakdown capability of the SiC MOSFET structure without reducing the gate electric field effect.

[0032] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A high-density SiC MOSFET structure, comprising a plurality of mutually parallel MOS cells, wherein each of the MOS cells comprises a drain (1), a semiconductor epitaxial layer, a gate (6) and a source (7), wherein the semiconductor epitaxial layer comprises an N substrate layer (2), an N diffusion layer (3), a P well layer (4), an N well layer (5) and a P-layer (9), characterized in that: The cross-sectional profile of the gate (6) is in a "T" shape, and the cross-sectional widths of the P-well layer (4) and the N-well layer (5) do not exceed the cross-sectional width of the gate (6), the cross-sectional profile of the P-well layer (4) is in a "Z" shape, and the cross-sectional profile of the N-well layer (5) is in an "L" shape, wherein the P-well layer (4) and the N-well layer (5) fit each other; A P-layer (9) is formed on the left and right sides of a single MOS cell by ion implantation, and polysilicon (8) is etched and deposited inside the P-layer (9); Two metal deposition layers (10) are provided in the N substrate layer (2) of a single MOS cell, the metal deposition layers (10) are in ohmic contact with the drain (1), and the metal deposition layers (10) are located below the connection between the P well layer (4) and the P-layer (9).

2. The high-density SiC MOSFET structure according to claim 1, characterized in that: A P-doped layer (11) is formed on the left and right sides of the bottom of a single MOS cell by ion implantation, wherein the P-doped layer (11) is in ohmic contact with the metal deposition layer (10) and the drain (1).

3. The high-density SiC MOSFET structure according to claim 1, characterized in that: An N+ doping layer (12) is formed by ion implantation inside the N diffusion layer (3) and directly above the metal deposition layer (10).

4. The high-density SiC MOSFET structure according to claim 1, characterized in that: An oxidation field plate (13) is provided inside a single MOS cell and between two metal deposition layers (10), wherein the oxidation field plate (13) is in contact with the metal deposition layer (10) and the drain electrode (1).

5. A process for preparing a high-density SiC MOSFET structure, characterized in that: Applied to the SiC MOSFET structure according to any one of claims 1 to 4, the preparation process of the high-density SiC MOSFET structure comprises the following steps: S1, etching the upper surface and the lower surface of the semiconductor epitaxial layer forming the source region to form a rectangular groove; S2, the rectangular grooves on the upper surface are filled to form polysilicon (8), and the rectangular grooves on the lower surface are formed into a metal deposition layer (10) by vapor deposition; S3, after cleaning the surface of the semiconductor epitaxial layer, a drain electrode (1) and a source electrode (7) are deposited; S4. Measure the performance improvement of SiC MOSFET structure.

6. The process for preparing a high-density SiC MOSFET structure according to claim 5, characterized in that: In step S2, the metal deposition layer (10) in the rectangular groove on the lower surface includes TiSi 、CoSi and NiSi materials.

7. The process for preparing a high-density SiC MOSFET structure according to claim 5, characterized in that: In the step S3, a passivation treatment is performed on the device formed with the drain (1) and the source (7).

8. The process for preparing a high-density SiC MOSFET structure according to claim 5, characterized in that: In step S4, the performance of the measured structure is determined according to the failure time of electromigration in the SiC MOSFET structure, the threshold voltage, and the time when the SiC MOSFET structure is turned on. Then: In the formula, represents the stability performance factor of the measured SiC MOSFET structure, represents the current density, represents the threshold voltage of the measured structure, Indicates the turn-on time of the measured structure.

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