Manufacturing method of BCD semiconductor device

Abstract

The invention provides a manufacturing method of a BCD semiconductor device, and the method comprises the steps: depositing a gate polysilicon layer on a substrate, forming a patterned photoresist to define a P-type body region, carrying out the baking of the substrate, carrying out the hardening of the photoresist, carrying out the etching and low-temperature UVC irradiation of the gate polysilicon layer, and carrying out the ion implantation to form the P-type body region. According to the method, the photoresist for defining the P-type body region is formed and then baked, the original high-temperature UVC irradiation is changed into low-temperature UVC irradiation, the photoresist is changed into the required morphology through high-temperature baking, and the morphology of the photoresist is cured through low-temperature UVC irradiation after the grid polycrystalline silicon layer is etched, so that the problem that the morphology of the photoresist is asymmetric due to different irradiation angles of a point light source is solved; during P-body ion implantation, the photoresistor is symmetrical in morphology and uniform in ion implantation, so that the threshold voltage Vt of the device keeps relatively high consistency at different positions of a wafer, and the reliability of the device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a BCD semiconductor device. Background Art

[0002] BCD is a monolithic integration process technology that can produce bipolar junction transistors (BJT), complementary metal oxide semiconductor (CMOS) and diffused metal oxide semiconductor (DMOS) devices on the same chip. The BCD process not only combines the advantages of high transconductance and strong load driving capability of bipolar devices and high integration and low power consumption of CMOS, but also integrates DMOS power devices with fast switching speed. Since DMOS has the characteristics of high speed and high current capability, the withstand voltage is usually high. Therefore, the power management chip manufactured by the BCD process can work under high frequency, high voltage and high current, which is an ideal process for manufacturing high-performance power chips.

[0003] LDMOS device is a power device with double diffusion structure, which is widely used because it is more compatible with CMOS process. In the process of manufacturing lateral double diffused metal oxide semiconductor (LDMOS) device by BCD process, the self-aligned injection channel process can effectively reduce the channel resistance and improve the reliability of the device. The self-aligned injection channel process uses the method of first etching the gate polysilicon (Poly) and then performing P-body region injection (P-body IMP) to form a channel, which can avoid the reliability problems caused by La' / Lb' asymmetry, such as Figure 1 As shown in the figure, the channel length can be adjusted by the P-body IMP injection angle, which can effectively and simply reduce the channel resistance and improve the device performance.

[0004] However, after etching the gate polysilicon, there are polymer particles (Polymer) remaining, which affects the subsequent P-type body region doping morphology and makes the device prone to leakage. Summary of the invention

[0005] The purpose of the present invention is to provide a method for manufacturing a BCD semiconductor device, improve the problem of asymmetric photoresist morphology caused by different irradiation angles of a point light source, improve the doping morphology of the P-type body region, maintain a high consistency of the threshold voltage Vt of the device at different positions on the wafer, and improve the reliability of the device.

[0006] To achieve the above object, a method for manufacturing a BCD semiconductor device comprises:

[0007] Providing a substrate, and depositing a gate polysilicon layer on the substrate;

[0008] forming a patterned photoresist on the gate polysilicon layer to define a P-type body region;

[0009] baking the substrate;

[0010] Etching the gate polysilicon layer;

[0011] irradiating the substrate with UVC; and,

[0012] Ion implantation is performed to form a P-type body region in the substrate.

[0013] Optionally, forming a patterned photoresist on the gate polysilicon layer includes: baking the formed patterned photoresist to perform a hardening process.

[0014] Optionally, baking the substrate is performed after the film hardening treatment, and the temperature of baking the substrate is the same as the temperature of the film hardening treatment.

[0015] Optionally, the temperature at which the substrate is baked is greater than the temperature at which the substrate is irradiated with UVC.

[0016] Optionally, a gate oxide layer is formed between the substrate and the gate polysilicon layer.

[0017] Optionally, etching the gate polysilicon layer includes:

[0018] Performing main etching on the gate polysilicon layer using the patterned photoresist as a mask to expose the gate oxide layer;

[0019] The gate polysilicon layer is lightly etched using the patterned photoresist as a mask to remove polymer residues generated by the main etching.

[0020] Optionally, when ion implantation is performed after UVC irradiation, the photoresist morphology is symmetrical about the formed P-type body region.

[0021] Optionally, during ion implantation, the implanted ions are implanted at a certain tilt angle.

[0022] Optionally, the method further includes: removing the patterned photoresist.

[0023] Optionally, after removing the patterned photoresist, the method further includes: defining a gate region to form a polysilicon gate.

[0024] Optionally, the method is applied to a self-aligned channel implantation process of LDMOS.

[0025] In summary, the manufacturing method of the BCD semiconductor device provided by the present invention deposits a gate polysilicon layer on a substrate, bakes the photoresist after forming the P-type body region, and replaces the original high-temperature UVC irradiation with low-temperature UVC irradiation. The photoresist is first changed to the desired morphology by high-temperature baking, and the gate polysilicon layer is etched and then the photoresist morphology is solidified by low-temperature UVC irradiation. The problem of asymmetric photoresist morphology caused by different irradiation angles of point light sources is improved. During P-body ion implantation, the photoresist morphology is symmetrical and the implanted ions are uniform, so that the threshold voltage Vt of the device maintains a high consistency at different positions of the wafer, thereby improving the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a partial structural diagram of a BCD device;

[0027] Figure 2A and Figure 2B SEM image of the photoresist morphology forming the P-body;

[0028] Figure 3 A schematic flow chart of a method for manufacturing a BCD semiconductor device provided by an embodiment of the present invention;

[0029] 4A to 4H The present invention is a schematic structural diagram of the corresponding steps in the method for manufacturing a BCD semiconductor device provided by an embodiment of the present invention.

[0030] The reference numerals are described as follows:

[0031] 100-substrate; 110-groove; 120-P-type body region;

[0032] 101 - gate oxide layer; 102 - gate polysilicon layer; 103 - photoresist. DETAILED DESCRIPTION

[0033] To make the content of the present invention more clear and understandable, the content of the present invention is further described below in conjunction with the accompanying drawings. Of course, the present invention is not limited to this specific embodiment, and general replacements known to those skilled in the art are also covered within the protection scope of the present invention.

[0034] Secondly, the present invention is described in detail using schematic diagrams. When describing the examples of the present invention in detail, for the sake of convenience, the schematic diagrams are not partially enlarged according to general proportions, and this should not be used as a limitation of the present invention.

[0035] For ease of description, some embodiments of the present invention may use spatially relative terms such as "above", "below", "top", "below", etc. to describe the relationship between one element or component and another (or other) elements or components as shown in the various figures of the embodiments. It should be understood that in addition to the orientations described in the drawings, the spatially relative terms are also intended to include different orientations of the device in use or operation. For example, if the device in the drawings is turned over, the elements or components described as being "below" or "beneath" other elements or components will subsequently be positioned as being "above" or "above" the other elements or components. The terms "first", "second", etc., hereinafter, are used to distinguish between similar elements and are not necessarily used to describe a specific order or time sequence.

[0036] In the manufacturing process of LDMOS devices, there are polymer particles (Polymer) residues after the gate polysilicon is etched in the self-aligned channel injection process, which affects the subsequent P-type body region doping morphology and causes the device to leak easily. Therefore, in order to ensure the P-type body region doping morphology, light etching (SLIGHT ET) and ultraviolet baking (UVC) processes are added after the gate polysilicon is etched to improve it.

[0037] The UVC machine uses a bulb as the light source. After the point light source irradiates at high temperature, the photoresist morphology at different positions of the wafer is inconsistent due to inconsistent irradiation angles, especially the asymmetry of the photoresist at the edge of the wafer. Figure 2A As shown in the figure, the photoresist on the side irradiated by UVC is straight, while the photoresist on the backlight side is more deformed.

[0038] P-body IMP and photoresist after UVC act as barriers to implanted ions. The photoresist morphology is asymmetric and the implanted ions are uneven, resulting in large differences in the LDMOS threshold voltage Vt at different locations on the wafer.

[0039] In order to solve the above problems, the present invention provides a method for manufacturing a BCD semiconductor device, depositing a gate polysilicon layer on a substrate to form a patterned photoresist to define a P-type body region, baking the substrate, hardening the photoresist, and then etching and low-temperature UVC irradiating the gate polysilicon layer, and then performing ion implantation to form a P-type body region. The present invention bakes the photoresist after forming the P-type body region, and replaces the original high-temperature UVC irradiation with low-temperature UVC irradiation. The photoresist is first changed to the desired morphology by high-temperature baking, and the gate polysilicon layer is etched and then low-temperature UVC irradiation is used to solidify the photoresist morphology, thereby improving the problem of asymmetric photoresist morphology caused by different irradiation angles of point light sources. During P-body ion implantation, the photoresist morphology is symmetrical and the implanted ions are uniform, so that the threshold voltage Vt of the device maintains a high consistency at different positions of the wafer, thereby improving the reliability of the device.

[0040] Figure 3A schematic flow chart of a method for manufacturing a BCD semiconductor device provided by an embodiment of the present invention is shown as follows: Figure 3 As shown, the manufacturing method of the BCD semiconductor device provided in this embodiment includes the following steps:

[0041] Step S01: providing a substrate, and depositing a gate polysilicon layer on the substrate;

[0042] Step S02: forming a patterned photoresist on the gate polysilicon layer to define a P-type body region;

[0043] Step S03: baking the substrate;

[0044] Step S04: etching the gate polysilicon layer;

[0045] Step S05: irradiating the substrate with UVC; and,

[0046] Step S06: performing ion implantation to form a P-type body region in the substrate.

[0047] 4A to 4H This is a schematic diagram of the structure of each step in the method for manufacturing a BCD semiconductor device according to an embodiment of the present invention. Figure 3 As shown, combined with 4A to 4H , a method for manufacturing the BCD semiconductor device provided by the present invention is described in detail.

[0048] First, refer to Figure 4A As shown, step S01 is performed to provide a substrate 100 and deposit a gate polysilicon layer 102 on the substrate.

[0049] Specifically, a substrate 100 is provided, and the substrate 200 may be single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi) or silicon carbide (SiC), or may be silicon on insulator (SOI) or germanium on insulator (GOI); or may be other materials, such as III-V compounds such as gallium arsenide. The substrate 100 described in this embodiment is only an example of a silicon substrate, which is only an example, and the present invention is not limited thereto.

[0050] A gate oxide layer 101 is formed between the substrate 100 and the gate polysilicon layer 102 .

[0051] Next, refer to FIG. 4B to FIG. 4CAs shown, step S02 and step S03 are performed to form a patterned photoresist 103 on the gate polysilicon layer 102 to define the P-body region, and the substrate 100 is baked. The formation of the patterned photoresist 103 includes: using a P-body mask to define the place where the P-body needs to be injected with a photoresist, forming a patterned photoresist 103, defining the P-body region, and then baking the formed patterned photoresist 103 for hardening. Baking the substrate is performed after the hardening process, which can be a continuation of the photoresist hardening process. After Hard bake, bake is added for a certain time, and the temperature of the substrate baking is the same as the temperature of the hardening process. The temperature T1 of baking the substrate 100 ranges from 80°C to 180°C, for example, 150°C. In other embodiments of the present invention, the substrate baking can also be performed separately from the photoresist hardening process, and the baking temperature can also be different from the hardening process temperature.

[0052] Next, refer to FIG. 4D to FIG. 4E As shown, step S04 is executed to etch the gate polysilicon layer 102. The places where the P-body needs to be injected are defined by using a photoresist through the P-body mask, forming a patterned photoresist 103, defining the P-body area, and then removing the gate polysilicon layer 102 in the defined area by dry etching. The etching process for the gate polysilicon layer 103 includes: using the baked patterned photoresist 103 as a mask to perform main etching on the gate polysilicon layer 102 to expose the gate oxide layer 101; using the baked patterned photoresist 103 as a mask to perform light etching on the gate polysilicon layer 103 to remove the polymer residue generated by the main etching, such as Figure 4C shown.

[0053] like Figure 4DAs shown, after the main etching of the gate polysilicon layer 102, the inner wall of the groove 110 formed by the etching is attached with polymer residues produced by the main etching. If it is not removed, it will affect the subsequent P-body region doping morphology, causing the device to leak easily. Therefore, light etching (SLIGHT ET) is performed after the main etching of the gate polysilicon layer 102. The implementation method of light etching is: using a dry etcher, selecting an etching gas containing F elements, and then in the power setting, selecting only the upper electrode that can generate plasma, and the power of the lower electrode is set to the minimum, or not using the lower electrode. In this way, the free radicals containing F in the plasma will diffuse to the surface of the silicon wafer, react isotropically with the inside of the groove, form a smooth groove surface, and take away some damaged layers on the groove surface. In the selection of etching gas, a gas containing F can be selected to react with the silicon surface. Such as CF4, CHF3, C4F8 and other gases. Through isotropic light etching, the etching byproducts adhering to the inner wall of the etching groove can be reduced, thereby reducing the deposition of polymers in the etching groove and improving the condition of particles in the etching groove.

[0054] Next, refer to Figure 4F As shown, step S05 is executed to irradiate the substrate with UVC (short-wave ultraviolet rays). The temperature T2 at which the substrate is irradiated with UVC is lower than the temperature T1 at which the substrate is baked, for example, T1-T2≧50°C, and the temperature T1 at which the substrate is baked is in the range of 80°C to 180°C, for example, 150°C.

[0055] Temperature has a great influence on the morphology of the photoresist. In this embodiment, the patterned photoresist 103 is first changed to the desired morphology at high temperature, and the gate polysilicon layer 103 is etched and then cured by low-temperature UVC irradiation to stabilize the morphology of the photoresist 103. The morphology of the photoresist on the left and right sides of the P-type body region formed subsequently is symmetrical. Figure 2B As shown, when ion implantation is performed using the photoresist 103 as a barrier, the implanted ions are uniform, and thus the threshold voltage Vt of the LDMOS device maintains a high consistency at different locations on the wafer.

[0056] Next, refer to Figures 4G to 4H As shown, step S06 is performed to perform ion implantation to form a P-type body region 120 on the substrate 100. When performing ion implantation, the implanted ions are implanted at a certain tilt angle, such as Figure 4F As shown. Before ion implantation, the photoresist 103 undergoes a light etching process and is first baked at high temperature and then treated with low temperature UVC, so that the morphology of the photoresist 103 is symmetrical about the formed P-body region. When the P-body ions are implanted, the ion implantation at an inclined angle does not affect the doping morphology of the P-body region.

[0057] Furthermore, the manufacturing method of the BCD semiconductor device provided in this embodiment further includes: removing the patterned photoresist, defining the gate region, and forming a polysilicon gate. Exemplarily, the photoresist 103 can be removed by an ashing process, and then the gate region is defined on the substrate 100 by a photolithography and etching process to form a polysilicon gate.

[0058] The manufacturing method of the BCD semiconductor device provided in this embodiment can be applied to the self-aligned channel injection process of LDMOS. In other embodiments of the present invention, the manufacturing method can also be applied to other related etching processes.

[0059] In summary, the present invention provides a method for manufacturing a BCD semiconductor device, depositing a gate polysilicon layer on a substrate, forming a patterned photoresist to define a P-type body region, and baking the substrate to harden the photoresist, then etching and low-temperature UVC irradiating the gate polysilicon layer, and then performing ion implantation to form a P-type body region. The present invention bakes the photoresist after forming the P-type body region, and replaces the original high-temperature UVC irradiation with low-temperature UVC irradiation, first high-temperature baking to change the photoresist to the desired morphology, and then low-temperature UVC irradiation to solidify the photoresist morphology after etching the gate polysilicon layer, thereby improving the problem of asymmetric photoresist morphology caused by different irradiation angles of point light sources. During P-body ion implantation, the photoresist morphology is symmetrical and the implanted ions are uniform, so that the threshold voltage Vt of the device maintains a high consistency at different positions on the wafer, thereby improving the reliability of the device.

[0060] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for manufacturing a BCD semiconductor device, characterized in that: include: Providing a substrate, and depositing a gate polysilicon layer on the substrate; forming a patterned photoresist on the gate polysilicon layer to define a P-type body region; baking the substrate; Etching the gate polysilicon layer; irradiating the substrate with UVC; as well as, Ion implantation is performed to form a P-type body region in the substrate.

2. The method for manufacturing a BCD semiconductor device according to claim 1, characterized in that: Forming a patterned photoresist on the gate polysilicon layer includes: baking the formed patterned photoresist to perform a hardening process.

3. The method for manufacturing a BCD semiconductor device according to claim 2, characterized in that: The substrate is baked after the hardening treatment, and the temperature of the substrate is the same as the temperature of the hardening treatment.

4. The method for manufacturing a BCD semiconductor device according to claim 3, characterized in that: The temperature at which the substrate is baked is greater than the temperature at which the substrate is irradiated with UVC.

5. The method for manufacturing a BCD semiconductor device according to claim 1, wherein: A gate oxide layer is also formed between the substrate and the gate polysilicon layer.

6. The method for manufacturing a BCD semiconductor device according to claim 1, characterized in that: Etching the gate polysilicon layer includes: Performing main etching on the gate polysilicon layer using the patterned photoresist as a mask to expose the gate oxide layer; The gate polysilicon layer is lightly etched using the patterned photoresist as a mask to remove polymer residues generated by the main etching.

7. The method for manufacturing a BCD semiconductor device according to claim 1, wherein: When ion implantation is performed after UVC irradiation, the photoresist morphology is symmetrical about the formed P-type body region.

8. The method for manufacturing a BCD semiconductor device according to claim 7, characterized in that: When ion implantation is performed, the implanted ions are implanted at a certain tilt angle.

9. The method for manufacturing a BCD semiconductor device according to claim 1, characterized in that: Also includes: The patterned photoresist is removed.

10. The method for manufacturing a BCD semiconductor device according to claim 9, characterized in that: After removing the patterned photoresist, the following steps further include: defining a gate region to form a polysilicon gate.

11. The method for manufacturing a BCD semiconductor device according to claim 1, wherein: The method is applied to the self-aligned injection channel process of LDMOS.

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