Solar cell, photovoltaic module and preparation method of solar cell

Abstract

The invention relates to a solar cell, a photovoltaic module and a preparation method of the solar cell. The solar cell comprises a semiconductor substrate, and a first doped semiconductor layer is arranged on a first surface and located in a first sub-region and a second sub-region; the dielectric layer is arranged on the side, away from the semiconductor substrate, of the first doped semiconductor layer and located in the second sub-region; the second doped semiconductor layer is arranged on the first surface and located in the second region and the second sub-region; a part of the second doped semiconductor layer of the second sub-region is arranged on one side, deviating from the semiconductor substrate, of the dielectric layer; the orthographic projection of the dielectric layer on the semiconductor substrate is a first orthographic projection, the orthographic projection of the first doped semiconductor layer on the semiconductor substrate is a second orthographic projection, a first distance is formed between the edge, close to one side of the second area, of the first orthographic projection and the outer contour of the second orthographic projection in the first direction, and the first orthographic projection is located in the second orthographic projection. Therefore, according to the solar cell, the photovoltaic module and the preparation method of the solar cell provided by the invention, the conversion efficiency of the solar cell can be improved.

Description

Technical Field

[0001] The present application relates to the field of photovoltaic technology, and in particular to a solar cell, a photovoltaic module and a method for preparing a solar cell. Background Art

[0002] Solar cells, also known as photovoltaic cells, are semiconductor devices that convert sunlight directly into electrical energy. As they are green and environmentally friendly products that do not cause environmental pollution, and solar energy is a renewable resource, solar cells are a new type of battery with broad development prospects.

[0003] In the related art, a heterojunction back contact cell (HBC) is a cell in which a metal electrode is disposed on the backlight side of the cell, so that the light-facing side of the cell is not blocked by the metal electrode, thereby increasing the light absorption area. However, the conversion efficiency of the above HBC cell needs to be improved. Summary of the invention

[0004] Based on this, it is necessary to provide a solar cell, a photovoltaic module and a method for preparing a solar cell, which can improve the conversion efficiency of the solar cell.

[0005] In a first aspect, an embodiment of the present application provides a solar cell, comprising a plurality of first regions and a plurality of second regions, wherein the first regions and the second regions are alternately arranged along a first direction, wherein the first region comprises a first sub-region and a second sub-region, and the second sub-region is located between the first sub-region and the second region; the solar cell comprises:

[0006] A semiconductor substrate having a first surface and a second surface arranged opposite to each other;

[0007] A first doped semiconductor layer is disposed on the first surface and located in the first sub-region and the second sub-region;

[0008] The dielectric layer is disposed on a side of the first doped semiconductor layer away from the semiconductor substrate and is located in the second sub-region;

[0009] A second doped semiconductor layer is disposed on the first surface and is located in the second region and the second sub-region; a portion of the second doped semiconductor layer located in the second sub-region is disposed on a side of the dielectric layer away from the semiconductor substrate;

[0010] Among them, in the same first region, the orthographic projection of the dielectric layer on the semiconductor substrate is a first orthographic projection, the orthographic projection of the first doped semiconductor layer on the semiconductor substrate is a second orthographic projection, the first orthographic projection is located within the second orthographic projection, and there is a first spacing between the contour edge of the first orthographic projection close to the second region and the contour edge of the second orthographic projection close to the second region.

[0011] In the solar cell of the embodiment of the present application, the first doped semiconductor layer protrudes from the side wall of the dielectric layer, and the non-dielectric layer protrudes from the side wall of the first doped semiconductor layer, so that the dielectric layer has no cantilever structure relative to the side wall of the first doped semiconductor layer, and the cantilever structure of the dielectric layer can be avoided to affect the preparation of subsequent film layers. For example, it can avoid affecting the preparation and passivation effect of the subsequent second passivation layer, thereby improving the open circuit voltage and conversion efficiency of the solar cell.

[0012] In one embodiment, the dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer, and the first sub-dielectric layer is disposed between the second sub-dielectric layer and the first doped semiconductor layer;

[0013] Under preset acid etching conditions, the etching rate of the first sub-dielectric layer is greater than the etching rate of the second sub-dielectric layer.

[0014] In one embodiment, under preset acidic etching conditions, the ratio of the etching rate of the first sub-dielectric layer to the etching rate of the second sub-dielectric layer is in the range of 1.1-1000; the etching agent of the preset acidic etching conditions includes a hydrofluoric acid solution.

[0015] In one of the embodiments, under preset alkaline etching conditions, the etching rates of the first sub-dielectric layer and the second sub-dielectric layer are both lower than the etching rates of the semiconductor substrate and the first doped semiconductor layer; and / or, under preset acidic etching conditions, the etching rate of the first sub-dielectric layer is higher than the etching rates of the semiconductor substrate and the first doped semiconductor layer.

[0016] In one embodiment, under preset alkaline etching conditions, the etching rate of any one of the first sub-dielectric layer and the second sub-dielectric layer is A, and the etching rate of any one of the semiconductor substrate and the first doped semiconductor layer is B, and A and B satisfy the following condition: 0.001≤A / B≤0.9.

[0017] In one embodiment, the solar cell includes a first passivation layer, the first passivation layer is disposed between the first doped semiconductor layer and the semiconductor substrate and is located in the first region;

[0018] Under preset alkaline etching conditions, the etching rates of the first sub-dielectric layer and the second sub-dielectric layer are both lower than the etching rate of the first passivation layer; and / or, under preset acidic etching conditions, the etching rate of the first sub-dielectric layer is higher than the etching rate of the first passivation layer.

[0019] In one embodiment, under preset alkaline etching conditions, the etching rate of any one of the first sub-dielectric layer and the second sub-dielectric layer is C, the etching rate of the first passivation layer is D, and C and D satisfy the following condition: 0.001≤C / D≤0.9.

[0020] In one embodiment, the material of the first sub-dielectric layer includes at least one of silicon dioxide, silicon nitride, and silicon oxynitride;

[0021] And / or, the material of the second sub-dielectric layer includes at least one of silicon dioxide, silicon nitride, and silicon oxynitride.

[0022] In one embodiment, the solar cell includes a first conductive layer, which is disposed on a side of a portion of the first doped semiconductor layer and a portion of the second doped semiconductor layer away from the semiconductor substrate and is located in a first sub-region and a second sub-region, and an orthographic projection of side walls of the first conductive layer on both sides along a first direction on the semiconductor substrate is located within an orthographic projection of the dielectric layer on the semiconductor substrate;

[0023] And / or, the solar cell includes a second conductive layer, which is arranged on a side of the second doped semiconductor layer facing away from the semiconductor substrate and is at least located in the second region; the distance along the first direction between the orthographic projection of the second conductive layer on the semiconductor substrate and the orthographic projection of the first doped semiconductor layer on the semiconductor substrate is greater than or equal to 0.

[0024] In one embodiment, the first surface includes a first sub-surface, a second sub-surface and a third sub-surface, the first sub-surface is located in the first area, the second sub-surface and the third sub-surface are located in the second area, the second sub-surface is located between the third sub-surface and the first sub-surface, and the distance between the first sub-surface and the second surface is greater than the distance between the third sub-surface and the second surface;

[0025] The second sub-surface is an inclined surface. In the same second region, the end of the second sub-surface away from the second surface is inclined relative to the end close to the second surface toward a direction away from the center of the third sub-surface; the angle between the second sub-surface and the plane where the third sub-surface is located ranges from 10° to 90°.

[0026] In one embodiment, the first spacing ranges from 0.001 μm to 30 μm;

[0027] And / or, in the same first region, a second distance is provided between the first doped semiconductor layer and an outer contour of the first region along the first direction, and the second distance ranges from 0.001 μm to 5 μm;

[0028] And / or, the ratio of the thickness of the first sub-dielectric layer to the thickness of the second sub-dielectric layer is in a range of 1.1-10.

[0029] In a second aspect, an embodiment of the present application provides a photovoltaic module, comprising the solar cell in the above-mentioned first aspect.

[0030] The photovoltaic module of the embodiment of the present application includes a solar cell, in which the first doped semiconductor layer protrudes from the side wall of the dielectric layer, and the non-dielectric layer protrudes from the side wall of the first doped semiconductor layer, so that the dielectric layer has no cantilever structure relative to the side wall of the first doped semiconductor layer, and the cantilever structure of the dielectric layer can be avoided from affecting the preparation of subsequent film layers. For example, it can avoid affecting the preparation and passivation effect of the subsequent second passivation layer, thereby improving the open circuit voltage and conversion efficiency of the solar cell.

[0031] In a third aspect, an embodiment of the present application provides a method for preparing a solar cell, wherein the solar cell includes a plurality of first regions and a plurality of second regions, the first regions and the second regions are alternately arranged along a first direction, the first region includes a first sub-region and a second sub-region, and the second sub-region is located between the first sub-region and the second region; the method for preparing the solar cell includes:

[0032] Providing a semiconductor substrate; the semiconductor substrate has a first surface and a second surface arranged opposite to each other;

[0033] A first doped semiconductor layer, a dielectric layer, and a second doped semiconductor layer are formed on the first surface; the first doped semiconductor layer is arranged in the first sub-region and the second sub-region; the dielectric layer is arranged on the side of the first doped semiconductor layer away from the semiconductor substrate and is located in the second sub-region; the second doped semiconductor layer is arranged in the second region and the second sub-region, and the part of the second doped semiconductor layer located in the second sub-region is arranged on the side of the dielectric layer away from the semiconductor substrate;

[0034] Among them, in the same first region, the orthographic projection of the dielectric layer on the semiconductor substrate is a first orthographic projection, the orthographic projection of the first doped semiconductor layer on the semiconductor substrate is a second orthographic projection, the first orthographic projection is located within the second orthographic projection, and there is a first spacing between the contour edge of the first orthographic projection close to the second region and the contour edge of the second orthographic projection close to the second region.

[0035] In the method for preparing a solar cell according to an embodiment of the present application, the first doped semiconductor layer protrudes from the side wall of the dielectric layer, and the non-dielectric layer protrudes from the side wall of the first doped semiconductor layer, so that the dielectric layer has no cantilever structure relative to the side wall of the first doped semiconductor layer, and the cantilever structure of the dielectric layer can be avoided from affecting the preparation of subsequent film layers. For example, it can avoid affecting the preparation and passivation effect of the subsequent second passivation layer, thereby improving the open circuit voltage and conversion efficiency of the solar cell.

[0036] In one embodiment, forming a first doped semiconductor layer, a dielectric layer, and a second doped semiconductor layer on a first surface includes:

[0037] Sequentially forming a first doped semiconductor material layer, a first sub-dielectric material layer, and a second sub-dielectric material layer on the first surface, wherein the first doped semiconductor material layer, the first sub-dielectric material layer, and the second sub-dielectric material layer are both located in the first region and the second region;

[0038] The first sub-dielectric material layer and the second sub-dielectric material layer are subjected to a first patterning process to remove the first sub-dielectric material layer and the second sub-dielectric material layer located in the second region and retain the first sub-dielectric material layer and the second sub-dielectric material layer located in the first region.

[0039] In one embodiment, after performing a first patterning process on the first sub-dielectric material layer and the second sub-dielectric material layer, the method includes:

[0040] Under preset alkaline etching conditions, the semiconductor substrate is subjected to a second patterning process using the first sub-dielectric material layer and the second sub-dielectric material layer as masks to remove a portion of the semiconductor substrate in the second region and expose the second sub-surface and the third sub-surface.

[0041] In one embodiment, the process of performing the second patterning process on the semiconductor substrate further includes:

[0042] The first doped semiconductor material layer located at the edge of the first region is removed to expose the edge of the first sub-surface, and the first doped semiconductor material layer located at the remaining portion of the first region is retained to form a first doped semiconductor layer; the first sub-dielectric material layer and the second sub-dielectric material layer include a cantilever structure, and the cantilever structure protrudes from the side wall of the first doped semiconductor layer;

[0043] Wherein, under the preset alkaline etching conditions, the etching rates of the first sub-dielectric material layer and the second sub-dielectric material layer are both lower than the etching rates of the semiconductor substrate and the first doped semiconductor material layer.

[0044] In one embodiment, after performing a second patterning process on the semiconductor substrate, the method includes:

[0045] Under preset acid etching conditions, etching and removing the first sub-dielectric material layer of the cantilever structure, and stripping and removing the second sub-dielectric material layer of the cantilever structure;

[0046] Wherein, under the preset acid etching conditions, the etching rate of the first sub-dielectric material layer is greater than the etching rate of the second sub-dielectric material layer.

[0047] In one embodiment, the process of etching and removing the first sub-dielectric material layer of the cantilever structure further includes:

[0048] Etching and removing the first sub-dielectric material layer located at the edge of the first doped semiconductor layer;

[0049] The process of stripping and removing the second sub-medium material layer of the cantilever structure also includes:

[0050] The second sub-dielectric material layer located at the edge of the first doped semiconductor layer is removed by stripping to expose the edge of the first doped semiconductor layer.

[0051] In one embodiment, after etching away the first sub-dielectric material layer of the cantilever structure, the method includes:

[0052] forming a second doped semiconductor material layer on the first surface, wherein the second doped semiconductor material layer is located in the first region and the second region;

[0053] The second doped semiconductor material layer, the first sub-dielectric material layer, and the second sub-dielectric material layer located in the first sub-region are removed to expose the first doped semiconductor layer located in the first sub-region, the second doped semiconductor material layer located in the second sub-region and the second region is retained, and a second doped semiconductor layer is formed, the first sub-dielectric material layer and the second sub-dielectric material layer located in the second sub-region are retained, and a dielectric layer is formed.

[0054] In one embodiment, before sequentially forming the first doped semiconductor material layer, the first sub-dielectric material layer and the second sub-dielectric material layer on the first surface, the method further includes: forming a first passivation material layer on the first surface, the first passivation material layer being located in the first region and the second region;

[0055] The process of performing the first patterning process on the first sub-dielectric material layer and the second sub-dielectric material layer also includes: exposing the first doped semiconductor material layer;

[0056] The process of performing the second patterning process on the semiconductor substrate also includes: removing the first doped semiconductor material layer and the first passivation material layer located in the second region;

[0057] Alternatively, the process of performing the first patterning process on the first sub-dielectric material layer and the second sub-dielectric material layer further includes: removing the first doped semiconductor material layer located in the second region to expose the first passivation material layer;

[0058] The process of performing the second patterning process on the semiconductor substrate further includes: removing the first passivation material layer located in the second region;

[0059] Alternatively, the process of performing the first patterning process on the first sub-dielectric material layer and the second sub-dielectric material layer further includes: removing the first doped semiconductor material layer and the first passivation material layer located in the second region to expose the semiconductor substrate.

[0060] In one embodiment, the process of performing the second patterning process on the semiconductor substrate further includes:

[0061] removing the first passivation material layer located at the edge of the first region, retaining the first passivation material layer located at the remaining portion of the first region, and forming a first passivation layer;

[0062] Wherein, under the preset alkaline etching conditions, the etching rates of the first sub-dielectric material layer and the second sub-dielectric material layer are both lower than the etching rate of the first passivation material layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] Figure 1 A cross-sectional view of a solar cell provided in an embodiment of the present application.

[0064] Figure 2 Another cross-sectional view of a solar cell provided in an embodiment of the present application.

[0065] Figure 3 A schematic diagram of the structure after forming the second dielectric material layer provided in an embodiment of the present application.

[0066] Figure 4 This is a schematic diagram of the structure after the first patterning process provided in an embodiment of the present application.

[0067] Figure 5 Another structural schematic diagram after the first patterning process provided in an embodiment of the present application.

[0068] Figure 6 Another structural schematic diagram after the first patterning process provided in an embodiment of the present application.

[0069] Figure 7 This is a schematic diagram of the structure after the second patterning process provided in an embodiment of the present application.

[0070] Figure 8 for Figure 7 Schematic diagram of the local enlarged structure.

[0071] Fig. 9 This is a schematic diagram of the structure after the cantilever structure is removed according to an embodiment of the present application.

[0072] Fig.10 for Fig. 9 Schematic diagram of the local enlarged structure.

[0073] Fig.11 A schematic diagram of the structure for forming a second doped semiconductor material layer provided in an embodiment of the present application.

[0074] Fig.12 This is a schematic diagram of the structure after the dielectric layer is formed according to an embodiment of the present application.

[0075] Fig.13 A schematic diagram of the process of preparing a solar cell provided in an embodiment of the present application.

[0076] Description of reference numerals:

[0077] 100, solar cell; 100a, first region; 101a, first sub-region; 102a, second sub-region; 100b, second region; 110, semiconductor substrate; 111, first surface; 1111, first sub-surface; 1112, second sub-surface; 1113, third sub-surface; 112, second surface; 121, first doped semiconductor layer; 121c, first doped semiconductor material layer; 122, second doped semiconductor layer; 122c, second doped semiconductor material layer; 130 , dielectric layer; 130a, cantilever structure; 131, first sub-dielectric layer; 131c, first sub-dielectric material layer; 132, second sub-dielectric layer; 132c, second sub-dielectric material layer; 141, first conductive layer; 142, second conductive layer; 151, first passivation layer; 151c, first passivation material layer; 152, second passivation layer; 152c, second passivation material layer; 153, third passivation layer; 161, first electrode; 162, second electrode; 170, anti-reflection layer. DETAILED DESCRIPTION

[0078] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present application, so the present application is not limited by the specific embodiments disclosed below.

[0079] In the description of the present application, it should be understood that if the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. appear, the orientation or position relationship indicated by these terms is based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.

[0080] In addition, if the terms "first" or "second" appear, these terms are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, if the term "plurality" appears, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0081] In the related art, the HBC battery includes a first region and a second region alternately arranged along a first direction, the first region includes a first sub-region and a second sub-region, and the second sub-region is arranged on both sides of the first sub-region along the first direction. The HBC battery includes a semiconductor substrate, a first doping layer, a second doping layer and an insulating layer, the semiconductor substrate includes a first surface and a second surface arranged oppositely, the first doping layer, the second doping layer and the insulating layer are all arranged on the first surface, the first doping layer is arranged in the first region, and the second doping layer is arranged in the second region and the second sub-region. In the second sub-region, the second doping layer is located on the side of the first doping layer away from the semiconductor substrate, and the insulating layer is arranged between the first doping layer and the second doping layer.

[0082] In the preparation process of the HBC battery, a first doping layer and an insulating layer are sequentially formed on the first surface of the semiconductor substrate, the insulating layer of the second region is removed, and the insulating layer of the first region is retained, and then the first doping layer of the second region is removed by wet etching, and the first doping layer of the first region is retained. Then, a passivation layer and a second doping layer are formed in the second region and the second sub-region.

[0083] However, in the process of wet etching to remove the first doped layer, at the junction of the first region and the second region, due to the different etching rates of the etching solution on the insulating layer and the first doped layer, the insulating layer is not easily etched, while the first doped layer is easily etched laterally, resulting in over-etching of the first doped layer, which will cause the insulating layer at the edge of the first region to protrude relative to the first doped layer to form a cantilever. The cantilever will affect the preparation of subsequently formed film layers, for example, it will affect the preparation and passivation effect of the passivation layer subsequently formed on the insulating layer, resulting in low open circuit voltage and low conversion efficiency of the HBC battery.

[0084] To solve the above problems, the embodiments of the present application provide a solar cell, a photovoltaic module and a method for preparing a solar cell, which can improve the conversion efficiency of the solar cell.

[0085] The following will be combined Figure 1-Figure 13 The solar cell 100, the photovoltaic module and the method for preparing the solar cell 100 provided in the embodiments of the present application are described.

[0086] The embodiment of the present application further provides a photovoltaic module, which may include a solar cell 100. There may be at least one solar cell 100 in the photovoltaic module. The embodiment of the present application takes the case where there are multiple solar cells 100 in the photovoltaic module as an example, and the multiple solar cells 100 together constitute a battery string layer.

[0087] In some embodiments, the photovoltaic module may include a first encapsulation member and a second encapsulation member located on both sides of the battery string layer, and the first encapsulation member and the second encapsulation member encapsulate the battery string layer to protect the battery string layer. The first encapsulation member and the second encapsulation member may include an encapsulation adhesive layer and a cover plate, the encapsulation adhesive layer is located on the side of the cover plate facing the battery string layer, the cover plate can protect the battery string layer, and the encapsulation adhesive layer can be used to connect the cover plate and the battery string layer.

[0088] Exemplarily, the solar cell 100 may include a heterojunction solar cell (HJT for short), a back contact cell (BC for short), a tunnel oxide passivating contact cell (TOPCON for short), a heterojunction back contact cell (HBC for short), or a hybrid full passivation back contact cell (HBC for short). The present application embodiment is described by taking a heterojunction back contact cell as an example.

[0089] The solar cell 100 provided in the embodiment of the present application is described below.

[0090] See also Figure 1 , the solar cell 100 may have a first direction A, a second direction and a third direction C, and the first direction A, the second direction and the third direction C are all different. The first direction A, the second direction and the third direction C may be perpendicular to each other. For example, the third direction C may be the thickness direction of the solar cell 100, and the first direction A and the second direction may be any two different directions perpendicular to the thickness direction of the semiconductor substrate 110. The first direction A may be the length direction of the solar cell 100, and the second direction may be the width direction of the solar cell 100. The length, width and thickness in the embodiments of the present application are merely for the convenience of description and do not imply any limitation on the size. For example, the width may be greater than, equal to or less than the length. The direction of the solar cell 100 may be consistent with the direction of the film layer such as the semiconductor substrate 110.

[0091] See also Figure 1The embodiment of the present application provides a solar cell 100, which includes a plurality of first regions 100a and a plurality of second regions 100b, wherein the first regions 100a and the second regions 100b are alternately arranged along a first direction A. The first region 100a includes a first sub-region 101a and a second sub-region 102a, wherein the second sub-region 102a may be located at both sides of the first sub-region 101a along the first direction A, and the second sub-region 102a is located between the first sub-region 101a and the second region 100b.

[0092] See also Figure 1 The solar cell 100 includes a semiconductor substrate 110, which can provide support for the film layers to be formed subsequently. The semiconductor substrate 110 can be used to receive incident light and generate photogenerated carriers.

[0093] For example, see Figure 1 The semiconductor substrate 110 may have a first surface 111 and a second surface 112 that are arranged opposite to each other along the thickness direction (i.e., the third direction C) of the semiconductor substrate 110, and at least one of the first surface 111 and the second surface 112 may be used to receive sunlight. The embodiment of the present application is described by taking the second surface 112 being used to receive sunlight as an example, that is, the second surface 112 is close to the light-facing surface of the solar cell 100, and the first surface 111 is close to the backlight surface of the solar cell 100.

[0094] For example, the semiconductor substrate 110 may be a silicon substrate, and the material of the silicon substrate may include at least one of single crystal silicon and polycrystalline silicon. The present application embodiment is described by taking single crystal silicon as an example.

[0095] Exemplarily, the doping type of the semiconductor substrate 110 may be N-type doping, which may be achieved by doping N-type ions, and the N-type ions may include at least one of phosphorus, arsenic, and antimony. Alternatively, the doping type of the semiconductor substrate 110 may be P-type doping, which may be achieved by doping P-type ions, and the P-type ions may include at least one of aluminum and boron. The embodiment of the present application is described by taking the doping type of the semiconductor substrate 110 as N-type doping as an example.

[0096] In some embodiments, at least one of the first surface 111 and the second surface 112 may have a velvet structure. The velvet structure may be a pyramid velvet, an etched pit velvet, etc. The velvet structure has a low reflectivity to incident light, and thus has a high absorption rate of incident light, so that the photoelectric conversion efficiency of the solar cell 100 is high. In other embodiments, at least one of the first surface 111 and the second surface 112 may not have a velvet structure.

[0097] See also Figure 1The solar cell 100 includes a first doped semiconductor layer 121, which is disposed on the first surface 111 and located in the first sub-region 101a and the second sub-region 102a. The first doped semiconductor layer 121 has a relatively low resistance, which can effectively reduce current loss and increase conductivity.

[0098] See also Figure 1 The solar cell 100 includes a dielectric layer 130 and a second doped semiconductor layer 122. The dielectric layer 130 is disposed on the side of the first doped semiconductor layer 121 away from the semiconductor substrate 110, and the dielectric layer 130 is located in the second sub-region 102a. The second doped semiconductor layer 122 is disposed on the first surface 111. The second doped semiconductor layer 122 has a lower resistance, which can effectively reduce the loss of current and increase conductivity. The second doped semiconductor layer 122 is located in the second region 100b and the second sub-region 102a, and the part of the second doped semiconductor layer 122 located in the second sub-region 102a is disposed on the side of the dielectric layer 130 away from the semiconductor substrate 110. In this way, in the second sub-region 102a, by disposing the dielectric layer 130 between the first doped semiconductor layer 121 and the second doped semiconductor layer 122, the dielectric layer 130 acts as an insulating layer, which can reduce the leakage between the first doped semiconductor layer 121 and the second doped semiconductor layer 122, reduce carrier recombination, and improve the efficiency of the solar cell 100.

[0099] See also Figure 1 In the same first region 100a, the orthographic projection of the dielectric layer 130 on the semiconductor substrate 110 is the first orthographic projection, and the orthographic projection of the first doped semiconductor layer 121 on the semiconductor substrate 110 is the second orthographic projection, the first orthographic projection is located within the second orthographic projection, and a first spacing L1 is provided between the contour edge of the first orthographic projection close to the second region 100b and the outer contour of the second orthographic projection along the first direction A. In this way, the first doped semiconductor layer 121 protrudes from the side wall of the dielectric layer 130, and the non-dielectric layer 130 protrudes from the side wall of the first doped semiconductor layer 121, so that the dielectric layer 130 has no cantilever structure relative to the side wall of the first doped semiconductor layer 121, and the cantilever structure of the dielectric layer 130 can be avoided from affecting the preparation of subsequent film layers, for example, it can avoid affecting the preparation and passivation effect of the subsequent second passivation layer 152, thereby improving the open circuit voltage and conversion efficiency of the solar cell 100.

[0100] Exemplarily, the doping type of the second doped semiconductor layer 122 is opposite to the doping type of the first doped semiconductor layer 121. The doping type of one of the first doped semiconductor layer 121 and the second doped semiconductor layer 122 may be N-type doping, and the doping type of the other may be P-type doping.

[0101] Exemplarily, the material of the first doped semiconductor layer 121 includes doped polycrystalline silicon, doped amorphous silicon, or doped microcrystalline silicon.

[0102] For example, the first doped semiconductor layer 121 may be formed by patterning the first doped semiconductor material layer 121 c.

[0103] Exemplarily, the second doped semiconductor layer 122 includes a doped amorphous silicon layer or a doped microcrystalline silicon layer.

[0104] Exemplarily, the thickness of the second doped semiconductor layer 122 ranges from 5 nm to 50 nm. For example, the thickness of the second doped semiconductor layer 122 may be 5 nm, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, or any value between 5 nm and 50 nm.

[0105] Exemplarily, the first spacing L1 ranges from 0.001 μm to 30 μm, thereby preventing the first spacing L1 from being too small, which is beneficial to reducing the difficulty of preparing the first spacing L1. In addition, the first spacing L1 can be prevented from being too large, which is beneficial to reducing the area occupied by the first spacing L1, thereby increasing the coverage area of ​​the dielectric layer 130, which is beneficial to improving the insulation effect of the dielectric layer 130. For example, the first spacing L1 can be 0.001 μm, 0.1 μm, 1 μm, 3 μm, 5 μm, 7 μm, 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, or any value between 0.001 μm and 30 μm.

[0106] For example, see Figure 1 In the same first region 100a, the first doped semiconductor layer 121 has a second spacing L2 with the outer contour of the first region 100a along the first direction A, and the second spacing L2 ranges from 0.001 μm to 5 μm. For example, the second spacing L2 may be 0.001 μm, 0.1 μm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, or any value between 0.001 μm and 5 μm.

[0107] The dielectric layer 130 provided in the embodiment of the present application is described below.

[0108] In some embodiments, the dielectric layer 130 includes a first sub-dielectric layer 131 and a second sub-dielectric layer 132, and the first sub-dielectric layer 131 is disposed between the second sub-dielectric layer 132 and the first doped semiconductor layer 121. Under preset etching conditions, the etching rate of the first sub-dielectric layer 131 is greater than the etching rate of the second sub-dielectric layer 132, the first sub-dielectric layer 131 is an etching layer, and the second sub-dielectric layer 132 is an anti-etching layer. In this way, during the preparation of the first doped semiconductor layer 121, if the first sub-dielectric layer 131 and the second sub-dielectric layer 132 form a cantilever structure 130a ( Figure 7 ), the first sub-dielectric layer 131 can be etched under the preset etching conditions to remove the first sub-dielectric layer 131 at the cantilever structure 130a, and the second sub-dielectric layer 132 above the first sub-dielectric layer 131 at the cantilever structure 130a can be peeled off, so that the cantilever structure 130a can be removed, so that the dielectric layer 130 in the final solar cell 100 product has no cantilever structure 130a relative to the first doped semiconductor layer 121, so that the cantilever structure 130a of the dielectric layer 130 can be avoided to affect the preparation of subsequent film layers, for example, it can be avoided to affect the preparation and passivation effect of the subsequent second passivation layer 152, so as to improve the open circuit voltage and conversion efficiency of the solar cell 100.

[0109] Exemplarily, the material of the first sub-dielectric layer 131 includes at least one of silicon dioxide (eg, silicon dioxide without impurities doped with impurities, silicon dioxide doped with impurities), silicon nitride, and silicon oxynitride.

[0110] Exemplarily, the material of the second sub-dielectric layer 132 includes at least one of silicon dioxide (eg, silicon dioxide without doping impurities), silicon nitride, and silicon oxynitride.

[0111] Exemplarily, the preset etching conditions may include preset acidic etching conditions and / or preset alkaline etching conditions. Under the preset acidic etching conditions, the etching rate of the first sub-dielectric layer 131 is greater than the etching rate of the second sub-dielectric layer 132. And / or, under the preset alkaline etching conditions, the etching rate of the first sub-dielectric layer 131 is greater than the etching rate of the second sub-dielectric layer 132.

[0112] Exemplarily, the etching agent of the preset acidic etching condition includes a hydrofluoric acid solution.

[0113] Exemplarily, under the preset acid etching conditions, the ratio of the etching rate of the first sub-dielectric layer 131 to the etching rate of the second sub-dielectric layer 132 is in the range of 1.1 to 1000. For example, the ratio of the etching rate of the first sub-dielectric layer 131 to the etching rate of the second sub-dielectric layer 132 can be 1.1, 10, 50, 100, 300, 500, 700, 1000 or any value between 1.1 and 1000.

[0114] In some embodiments, under the preset alkaline etching conditions, the etching rates of the first sub-dielectric layer 131 and the second sub-dielectric layer 132 are both lower than the etching rates of the semiconductor substrate 110 and the first doped semiconductor layer 121. Thus, under the preset alkaline etching conditions, when patterning is performed on any one of the semiconductor substrate 110 and the first doped semiconductor layer 121, the first sub-dielectric layer 131 and the second sub-dielectric layer 132 can play a good protective role on the covered semiconductor substrate 110 and the first doped semiconductor layer 121. In addition, the first sub-dielectric layer 131 and the second sub-dielectric layer 132 can be used as masks for the patterning process, so that there is no need to set a mask separately, which is conducive to simplifying the preparation process of the solar cell 100 and reducing the production cost.

[0115] Exemplarily, under preset alkaline etching conditions, the etching rates of the first sub-dielectric layer 131 and the second sub-dielectric layer 132 are both lower than the etching rate of semiconductor silicon, and semiconductor silicon includes amorphous silicon, microcrystalline silicon, polycrystalline silicon, single crystal silicon, etc. The embodiment of the present application is described by taking the example that the materials of the first passivation layer 151, the first doped semiconductor layer 121 and the semiconductor substrate 110 can all include semiconductor silicon.

[0116] Exemplarily, under preset alkaline etching conditions, the etching rate of any one of the first sub-dielectric layer 131 and the second sub-dielectric layer 132 is A, the etching rate of any one of the semiconductor substrate 110 and the first doped semiconductor layer 121 is B, and A and B satisfy the following conditions: 0.001≤A / B≤0.9, the ratio of A to B is A / B, for example, the ratio of A to B can be 0.001, 0.01, 0.1, 0.2, 0.5, 0.7, 0.9 or any value between 0.001-0.9.

[0117] In an embodiment where the etching rate of the first sub-dielectric layer 131 is greater than the etching rate of the second sub-dielectric layer 132 under the preset acid etching conditions, during the preparation of the first doped semiconductor layer 121, if the dielectric layer 130 forms a cantilever structure 130a ( Figure 7), the first sub-dielectric layer 131 can be etched under the preset acidic etching conditions to remove the first sub-dielectric layer 131 at the cantilever structure 130a, and the second sub-dielectric layer 132 above the first sub-dielectric layer 131 at the cantilever structure 130a can be peeled off, so that the cantilever structure 130a can be removed, so that the dielectric layer 130 in the final solar cell 100 product has no cantilever structure 130a relative to the first doped semiconductor layer 121, so that the influence of the cantilever structure 130a on the passivation effect of the second passivation layer 152 can be avoided, and the passivation effect of the second passivation layer 152 can be improved, so as to improve the open circuit voltage and conversion efficiency of the solar cell 100. For example, under the preset acidic etching conditions, the etching rate of the first sub-dielectric layer 131 is greater than the etching rate of the semiconductor substrate 110 and the first doped semiconductor layer 121. In this way, in the process of removing the cantilever structure 130a, the damage to the semiconductor substrate 110 and the first doped semiconductor layer 121 can be reduced.

[0118] Exemplarily, the ratio of the thickness of the first sub-dielectric layer 131 to the thickness of the second sub-dielectric layer 132 is in the range of 1.1-10, so that the ratio of the thickness of the first sub-dielectric layer 131 to the thickness of the second sub-dielectric layer 132 can be avoided from being too small, which is conducive to preventing the second sub-dielectric layer 132 from being too thick and difficult to peel off. In addition, the ratio of the thickness of the first sub-dielectric layer 131 to the thickness of the second sub-dielectric layer 132 can be avoided from being too large, which is conducive to preventing the second sub-dielectric layer 132 from being too thin and difficult to prepare, and can also prevent the second sub-dielectric layer 132 from being too thin and having a poor protective effect on the film layer below. For example, the ratio of the thickness of the first sub-dielectric layer 131 to the thickness of the second sub-dielectric layer 132 can be 1.1, 2, 3, 5, 7, 9, 10 or any value between 1.1-10.

[0119] In some embodiments, the solar cell 100 includes a first passivation layer 151, which is disposed between the first doped semiconductor layer 121 and the semiconductor substrate 110, and is located in the first region 100a. The first passivation layer 151 can improve the photoelectric conversion efficiency by reducing the surface recombination rate, thereby improving the open circuit voltage and conversion efficiency of the solar cell 100. The region where the first passivation layer 151 contacts the first surface 111 may be a first polarity region.

[0120] Exemplarily, under preset alkaline etching conditions, the etching rates of the first sub-dielectric layer 131 and the second sub-dielectric layer 132 are both lower than the etching rate of the first passivation layer 151. Thus, under the preset alkaline etching conditions, when the first passivation layer 151 is patterned, the first sub-dielectric layer 131 and the second sub-dielectric layer 132 can provide better protection for the covered first passivation layer 151. In addition, the first sub-dielectric layer 131 and the second sub-dielectric layer 132 can be used as masks for the patterning process, thereby eliminating the need to set up a separate mask, which is beneficial for simplifying the preparation process of the solar cell 100 and reducing production costs.

[0121] Exemplarily, during the preparation of the first doped semiconductor layer 121, if the dielectric layer 130 forms a cantilever structure 130a relative to the first doped semiconductor layer 121, the first sub-dielectric layer 131 can be etched under preset acidic etching conditions to remove the first sub-dielectric layer 131 at the cantilever structure 130a, and the second sub-dielectric layer 132 above the first sub-dielectric layer 131 at the cantilever structure 130a can be peeled off, so that the cantilever structure 130a can be removed, so that the dielectric layer 130 in the final solar cell 100 product has no cantilever structure 130a relative to the first doped semiconductor layer 121, thereby improving the open circuit voltage and conversion efficiency of the solar cell 100. Under the preset acidic etching conditions, the etching rate of the first sub-dielectric layer 131 is greater than the etching rate of the first passivation layer 151, so that in the process of removing the cantilever structure 130a, the damage to the first passivation layer 151 can be reduced.

[0122] Exemplarily, the first passivation layer 151 may include tunnel oxide or intrinsic amorphous silicon.

[0123] For example, the first passivation layer 151 may include a tunneling oxide, and the first doped semiconductor layer 121 may include doped polysilicon.

[0124] For example, the first passivation layer 151 may include intrinsic amorphous silicon, and the first doped semiconductor layer 121 may include a doped amorphous silicon layer or doped microcrystalline silicon.

[0125] Exemplarily, under preset alkaline etching conditions, the etching rate of any one of the first sub-dielectric layer 131 and the second sub-dielectric layer 132 is C, the etching rate of the first passivation layer 151 is D, and C and D satisfy the following conditions: 0.001≤C / D≤0.9, and the ratio of C to D is C / D. For example, the ratio of C to D can be 0.001, 0.01, 0.1, 0.2, 0.5, 0.7, 0.9 or any value between 0.001-0.9.

[0126] In some embodiments, the solar cell 100 includes a second passivation layer 152, the second passivation layer 152 is located in the second region 100b and the second sub-region 102a, the portion of the second passivation layer 152 located in the second sub-region 102a is disposed on a side of the dielectric layer 130 away from the semiconductor substrate 110, and the second doped semiconductor layer 122 is located on a side of the second passivation layer 152 away from the semiconductor substrate 110. The region where the second passivation layer 152 contacts the first surface 111 is a second polarity region.

[0127] Exemplarily, the material of the second passivation layer 152 includes intrinsic amorphous silicon.

[0128] Exemplarily, the thickness of the second passivation layer 152 may be in the range of 3 nm-15 nm. For example, the thickness of the second passivation layer 152 may be 3 nm, 5 nm, 7 nm, 10 nm, 12 nm, 15 nm or any value between 3 nm and 15 nm.

[0129] In some embodiments, the solar cell 100 includes a first conductive layer 141, which can collect the current generated by the cell and transmit it to the first electrode 161. In addition, the first conductive layer 141 can also have an anti-reflection effect. The first conductive layer 141 is disposed on a side of a portion of the first doped semiconductor layer 121 and a portion of the second doped semiconductor layer 122 away from the semiconductor substrate 110, and the first conductive layer 141 is located in the first sub-region 101a and the second sub-region 102a. In this way, by extending the first conductive layer 141 from the first sub-region 101a to the second sub-region 102a, the first conductive layer 141 can be disposed in a larger area, and can better cover the first doped semiconductor layer 121, which is conducive to improving the conduction of the first conductive layer 141 to carriers.

[0130] Exemplarily, the orthographic projections of the side walls of the first conductive layer 141 on both sides along the first direction A on the semiconductor substrate 110 are located within the orthographic projections of the dielectric layer 130 on the semiconductor substrate 110. For example, the first conductive layer 141 can be formed by patterning a conductive material layer. During the patterning process of the conductive material layer, the removed conductive material layer is at least partially located above the dielectric layer 130, so that the dielectric layer 130 can protect the underlying film layer, which is beneficial to avoid damage to the first doped semiconductor layer 121 and the first passivation layer 151 during the patterning process of the conductive material layer.

[0131] Exemplarily, there may be a first distance D1 along the first direction A between the orthographic projection of the first conductive layer 141 on the semiconductor substrate 110 and the orthographic projection of the first doped semiconductor layer 121 on the semiconductor substrate 110, and the size range of the first distance D1 is 10μm-150μm. For example, the size of the first distance D1 may be 10μm, 30μm, 50μm, 80μm, 100μm, 120μm, 150μm or any value between 10μm-150μm.

[0132] Exemplarily, the orthographic projection of the first passivation layer 151 on the semiconductor substrate 110 and the orthographic projection of the first doped semiconductor layer 121 on the semiconductor substrate 110 may at least partially overlap. For example, the orthographic projection of the first passivation layer 151 on the semiconductor substrate 110 and the orthographic projection of the first doped semiconductor layer 121 on the semiconductor substrate 110 may overlap.

[0133] In some embodiments, the solar cell 100 includes a second conductive layer 142, which can collect the current generated by the cell and transmit it to the second electrode 162. In addition, the second conductive layer 142 can also have an anti-reflection effect. The second conductive layer 142 is disposed on the side of the second doped semiconductor layer 122 away from the semiconductor substrate 110, and the second conductive layer 142 is at least located in the second region 100b. The first conductive layer 141 and the second conductive layer 142 are spaced apart along the first direction A, so that the first conductive layer 141 and the second conductive layer 142 can be prevented from short-circuiting.

[0134] For example, see Figure 1 The second conductive layer 142 may be located only in the second region 100b without extending to the first region 100a, so that the distance between the first conductive layer 141 and the second conductive layer 142 is relatively far, which is beneficial to prevent the first conductive layer 141 and the second conductive layer 142 from short-circuiting.

[0135] For other examples, see Figure 2 The second conductive layer 142 may extend from the second region 100b to the second sub-region 102a, so that the area of ​​the second conductive layer 142 is larger, which is beneficial to improving the transmission of carriers by the second conductive layer 142.

[0136] Exemplarily, the distance along the first direction A between the orthographic projection of the second conductive layer 142 on the semiconductor substrate 110 and the orthographic projection of the first doped semiconductor layer 121 on the semiconductor substrate 110 is a second distance D2, and the size range of the second distance D2 is 0 μm-120 μm. For example, the size of the second distance D2 can be 0 μm, 10 μm, 30 μm, 50 μm, 80 μm, 100 μm, 120 μm or any value between 0 μm and 120 μm.

[0137] Exemplarily, the orthographic projections of the side walls of the second conductive layer 142 on both sides along the first direction A on the semiconductor substrate 110 are located within the orthographic projections of the dielectric layer 130 on the semiconductor substrate 110. For example, the second conductive layer 142 can be formed by patterning a conductive material layer. During the patterning process of the conductive material layer, the removed conductive material layer is completely located above the dielectric layer 130, so that the dielectric layer 130 can better protect the film layer below, which is beneficial to better avoid damage to the first doped semiconductor layer 121 and the first passivation layer 151 during the patterning process of the conductive material layer.

[0138] Exemplarily, the material of at least one of the first conductive layer 141 and the second conductive layer 142 includes a transparent conductive oxide, for example, one or more of zinc oxide, indium oxide, and tin oxide, and the doping elements include one or more of gallium (Ga), tin (Sn), titanium (Ti), zirconium (Zr), molybdenum (Mo), cerium (Ce), fluorine (F), tungsten (W), and aluminum (Al).

[0139] Exemplarily, the thickness of at least one of the first conductive layer 141 and the second conductive layer 142 ranges from 10 nm to 150 nm. For example, the thickness may be 10 nm, 20 nm, 50 nm, 70 nm, 100 nm, 120 nm, 150 nm or any value between 10 nm and 150 nm.

[0140] In some embodiments, see Figure 1 The first surface 111 includes a first sub-surface 1111, a second sub-surface 1112, and a third sub-surface 1113. The first sub-surface 1111 is located in the first region 100a, the second sub-surface 1112 and the third sub-surface 1113 are located in the second region 100b, the second sub-surface 1112 is located between the third sub-surface 1113 and the first sub-surface 1111, and the second sub-surface 1112 may be located on both sides of the third sub-surface 1113 along the first direction A. The distance between the first sub-surface 1111 and the second surface 112 is greater than the distance between the third sub-surface 1113 and the second surface 112, that is, the second sub-surface 1112 and the third sub-surface 1113 jointly form a groove, so that the total area of ​​the second sub-surface 1112 and the third sub-surface 1113 can be increased without occupying an additional area of ​​the semiconductor substrate 110 along the first direction A, which is beneficial to improving the coverage area of ​​the second doped semiconductor layer 122, thereby facilitating improving the performance of the solar cell 100.

[0141] Exemplarily, the difference D3 between the distance between the first sub-surface 1111 and the second surface 112 and the distance between the third sub-surface 1113 and the second surface 112 ranges from 0.5μm to 10μm. For example, the difference D3 can be 0.5μm, 1μm, 2μm, 5μm, 7μm, 10μm or any value between 0.5μm and 10μm.

[0142] In the example, the second sub-surface 1112 is an inclined surface. In the same second area 100b, the end of the second sub-surface 1112 away from the second surface 112 is inclined relative to the end close to the second surface 112 in a direction away from the center of the third sub-surface 1113. At this time, the opening size of the groove formed by the second sub-surface 1112 and the third sub-surface 1113 gradually increases along the direction from the second surface 112 to the first surface 111, which is beneficial to reduce the difficulty of subsequently covering other film layers on the second sub-surface 1112.

[0143] Exemplarily, the angle θ between the plane where the second sub-surface 1112 and the third sub-surface 1113 are located is in the range of 10°-90°, so that the angle θ can be prevented from being too small, which is beneficial to increasing the total area of ​​the second sub-surface 1112 and the third sub-surface 1113. In addition, the angle θ can be prevented from being too large, which is beneficial to reducing the difficulty of subsequently covering other film layers on the second sub-surface 1112. For example, the angle θ between the plane where the second sub-surface 1112 and the third sub-surface 1113 are located can be 10°, 30°, 50°, 70°, 90°, or any value between 10°-90°.

[0144] The first electrode 161 and the second electrode 162 provided in the embodiment of the present application are described below.

[0145] In some embodiments, see Figure 1 The solar cell 100 includes a first electrode 161, which is located on a side of the first conductive layer 141 away from the semiconductor substrate 110. The first electrode 161 can collect and transmit carriers, thereby realizing solar energy conversion. The first electrode 161 can be located in the first sub-region 101a.

[0146] In some embodiments, see Figure 1 The solar cell 100 includes a second electrode 162, which is located on the side of the second conductive layer 142 away from the semiconductor substrate 110. The second electrode 162 can collect and transmit carriers, thereby realizing the conversion of solar energy into electric energy. The second electrode 162 can be located in the second region 100b. The first electrode 161 and the second electrode 162 are arranged in a first direction A at intervals.

[0147] Exemplarily, the material of at least one of the first electrode 161 and the second electrode 162 includes a conductive metal such as silver, copper, or tin.

[0148] In some embodiments, see Figure 1 The solar cell 100 includes a third passivation layer 153 , and the third passivation layer 153 is located on the second surface 112 .

[0149] Exemplarily, the third passivation layer 153 includes one or more of intrinsic amorphous silicon, a composite layer of intrinsic amorphous silicon and doped microcrystalline silicon or doped amorphous silicon, a composite layer of tunneling oxide and doped polysilicon, silicon oxide, aluminum oxide, silicon nitride, and silicon oxynitride.

[0150] In some embodiments, see Figure 1 The solar cell 100 includes an anti-reflection layer 170 . The anti-reflection layer 170 is located on a side of the third passivation layer 153 facing away from the semiconductor substrate 110 .

[0151] Exemplarily, the anti-reflection layer 170 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, magnesium fluoride, and transparent conductive oxide.

[0152] The following is an explanation of a method for preparing the solar cell 100 provided in an embodiment of the present application.

[0153] The embodiment of the present application provides a method for preparing a solar cell 100, which can be used to prepare the solar cell 100 in the above embodiment. The solar cell 100 includes a plurality of first regions 100a and a plurality of second regions 100b, the first regions 100a and the second regions 100b are alternately arranged along a first direction A, the first region 100a includes a first sub-region 101a and a second sub-region 102a, and the second sub-region 102a is located between the first sub-region 101a and the second region 100b.

[0154] See also Fig.13 , the method for preparing the solar cell 100 may include:

[0155] S100: providing a semiconductor substrate; the semiconductor substrate having a first surface and a second surface arranged opposite to each other;

[0156] First, see Figure 3 , a semiconductor substrate 110 is provided, wherein the semiconductor substrate 110 has a first surface 111 and a second surface 112 which are opposite to each other.

[0157] Exemplarily, at least one of the first surface 111 and the second surface 112 of the semiconductor substrate 110 may be textured so that at least one of the first surface 111 and the second surface 112 forms a texture structure.

[0158] For example, the velvet structure can be prepared by wet chemical etching, for example, an alkaline solution can be used for velvet preparation, such as a NaOH solution, or chemical etching, laser etching, mechanical method, plasma etching, etc. can be used to prepare the velvet structure.

[0159] S200: forming a first doped semiconductor layer, a dielectric layer, and a second doped semiconductor layer on the first surface; the first doped semiconductor layer is arranged in the first sub-region and the second sub-region; the dielectric layer is arranged on the side of the first doped semiconductor layer away from the semiconductor substrate, and is located in the second sub-region; the second doped semiconductor layer is arranged in the second region and the second sub-region, and the part of the second doped semiconductor layer located in the second sub-region is arranged on the side of the dielectric layer away from the semiconductor substrate; wherein, in the same first region, the orthographic projection of the dielectric layer on the semiconductor substrate is the first orthographic projection, the orthographic projection of the first doped semiconductor layer on the semiconductor substrate is the second orthographic projection, the first orthographic projection is located in the second orthographic projection, and a first spacing exists between the contour edge of the first orthographic projection close to the second region and the contour edge of the second orthographic projection close to the second region.

[0160] In some embodiments, see Figure 1 After providing the semiconductor substrate 110, the method may include forming a first doped semiconductor layer 121, a dielectric layer 130, and a second doped semiconductor layer 122 on the first surface 111. The first doped semiconductor layer 121 is disposed in the first sub-region 101a and the second sub-region 102a. The dielectric layer 130 is disposed on a side of the first doped semiconductor layer 121 away from the semiconductor substrate 110, and the dielectric layer 130 is located in the second sub-region 102a. The second doped semiconductor layer 122 is disposed in the second region 100b and the second sub-region 102a, and a portion of the second doped semiconductor layer 122 located in the second sub-region 102a is disposed on a side of the dielectric layer 130 away from the semiconductor substrate 110. In the same first region 100a, the orthographic projection of the dielectric layer 130 on the semiconductor substrate 110 is the first orthographic projection, the orthographic projection of the first doped semiconductor layer 121 on the semiconductor substrate 110 is the second orthographic projection, the first orthographic projection is located within the second orthographic projection, and a first spacing L1 is provided between the contour edge of the first orthographic projection close to the second region 100b and the outer contour of the second orthographic projection along the first direction A. In this way, the first doped semiconductor layer 121 protrudes from the side wall of the dielectric layer 130, and the non-dielectric layer 130 protrudes from the side wall of the first doped semiconductor layer 121, so that the dielectric layer 130 has no cantilever structure relative to the side wall of the first doped semiconductor layer 121, and the cantilever structure of the dielectric layer 130 can be avoided from affecting the preparation of subsequent film layers, for example, it can avoid affecting the preparation and passivation effect of the subsequent second passivation layer 152, thereby improving the open circuit voltage and conversion efficiency of the solar cell 100.

[0161] For example, at least one of the first doped semiconductor layer 121 , the dielectric layer 130 , and the second doped semiconductor layer 122 may be formed by a deposition process.

[0162] Exemplarily, the deposition process may include atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), or reactive plasma deposition (RPD). Other structural layers in the embodiments of the present disclosure may also be formed by deposition, which will not be described in detail.

[0163] Exemplarily, the patterning process of at least one of the first doped semiconductor layer 121, the dielectric layer 130 and the second doped semiconductor layer 122 may be wet etching, dry etching or laser etching. The patterning process of other structural layers in the embodiment of the present disclosure is similar and will not be described in detail.

[0164] In some embodiments, see Figure 3 , forming a first doped semiconductor layer 121, a dielectric layer 130 and a second doped semiconductor layer 122 on the first surface 111, may include: sequentially forming a first doped semiconductor material layer 121c, a first sub-dielectric material layer 131c and a second sub-dielectric material layer 132c on the first surface 111, wherein the first doped semiconductor material layer 121c, the first sub-dielectric material layer 131c and the second sub-dielectric material layer 132c are all located in the first region 100a and the second region 100b. Then, referring to Figure 4 , the first sub-dielectric material layer 131c and the second sub-dielectric material layer 132c are subjected to a first patterning process to remove the first sub-dielectric material layer 131c and the second sub-dielectric material layer 132c located in the second region 100b, and retain the first sub-dielectric material layer 131c and the second sub-dielectric material layer 132c located in the first region 100a. The retained first sub-dielectric material layer 131c and the second sub-dielectric material layer 132c located in the first region 100a can be used as a mask for a subsequent second patterning process, so that a mask does not need to be separately provided for the second patterning process, which is conducive to simplifying the preparation process of the solar cell 100 and reducing the production cost.

[0165] In some embodiments, see Figure 3Before sequentially forming the first doped semiconductor material layer 121c, the first sub-dielectric material layer 131c, and the second sub-dielectric material layer 132c on the first surface 111, the method may further include forming a first passivation material layer 151c on the first surface 111, wherein the first passivation material layer 151c is located in the first region 100a and the second region 100b. The first passivation material layer 151c is located between the semiconductor substrate 110 and the first doped semiconductor material layer 121c.

[0166] For example, the first patterning process may be performed by laser etching. Since the laser energy of laser etching is relatively large, it is easy to cause over-etching. Therefore, when the first sub-dielectric material layer 131c and the second sub-dielectric material layer 132c are subjected to the first patterning process, the first doped semiconductor material layer 121c and the first passivation material layer 151c are easily etched.

[0167] For example, see Figure 4 In the process of performing the first patterning process on the first sub-dielectric material layer 131c and the second sub-dielectric material layer 132c, only the first sub-dielectric material layer 131c and the second sub-dielectric material layer 132c may be subjected to the first patterning process, that is, only the first sub-dielectric material layer 131c and the second sub-dielectric material layer 132c of the second region 100b are removed to expose the first doped semiconductor material layer 121c. Alternatively, see Figure 5 In the process of performing the first patterning process on the first sub-dielectric material layer 131c and the second sub-dielectric material layer 132c, the first sub-dielectric material layer 131c, the second sub-dielectric material layer 132c and the first doped semiconductor material layer 121c may be simultaneously patterned, that is, the first sub-dielectric material layer 131c, the second sub-dielectric material layer 132c and the first doped semiconductor material layer 121c in the second region 100b are removed to expose the first passivation material layer 151c. Alternatively, see Figure 6 In the process of performing the first patterning process on the first sub-dielectric material layer 131c and the second sub-dielectric material layer 132c, the first sub-dielectric material layer 131c, the second sub-dielectric material layer 132c, the first doped semiconductor material layer 121c and the first passivation material layer 151c may be simultaneously subjected to the first patterning process, that is, the first sub-dielectric material layer 131c, the second sub-dielectric material layer 132c, the first doped semiconductor material layer 121c and the first passivation material layer 151c of the second region 100b are removed to expose the semiconductor substrate 110.

[0168] In some embodiments, see Figure 7After the first sub-dielectric material layer 131c and the second sub-dielectric material layer 132c are subjected to the first patterning treatment, the method may include, under a preset alkaline etching condition, using the first sub-dielectric material layer 131c and the second sub-dielectric material layer 132c as a mask, performing a second patterning treatment on the semiconductor substrate 110 to remove a portion of the thickness of the semiconductor substrate 110 located in the second region 100b, exposing the second sub-surface 1112 and the third sub-surface 1113. The first sub-dielectric material layer 131c and the second sub-dielectric material layer 132c retained in the first region 100a may be used as a mask for the second patterning treatment process, thereby eliminating the need to set a separate mask for the second patterning treatment, which is beneficial to simplifying the preparation process of the solar cell 100 and reducing the production cost.

[0169] See also Figure 4 and Figure 7 In an embodiment in which the first sub-dielectric material layer 131c and the second sub-dielectric material layer 132c are subjected to a first patterning process to expose the first doped semiconductor material layer 121c, the process of performing a second patterning process on the semiconductor substrate 110 also includes removing the first doped semiconductor material layer 121c and the first passivation material layer 151c located in the second region 100b to expose the second sub-surface 1112 and the third sub-surface 1113.

[0170] See also Figure 5 and Figure 7 In an embodiment in which the first sub-dielectric material layer 131c, the second sub-dielectric material layer 132c and the first doped semiconductor material layer 121c are subjected to a first patterning process to expose the first passivation material layer 151c, the process of performing a second patterning process on the semiconductor substrate 110 further includes removing the first passivation material layer 151c located in the second region 100b to expose the second sub-surface 1112 and the third sub-surface 1113.

[0171] See also Figure 6 and Figure 7 In an embodiment where the first sub-dielectric material layer 131c, the second sub-dielectric material layer 132c, the first doped semiconductor material layer 121c and the first passivation material layer 151c are subjected to a first patterning process and the semiconductor substrate 110 is exposed, when the semiconductor substrate 110 is subjected to a second patterning process, a portion of the thickness of the semiconductor substrate 110 may be removed to facilitate removal of the semiconductor substrate 110 damaged by laser etching.

[0172] In some embodiments, see Figure 7 and Figure 8Under the preset alkaline etching conditions, the etching rates of the first sub-dielectric material layer 131c and the second sub-dielectric material layer 132c are both lower than the etching rates of the semiconductor substrate 110 and the first doped semiconductor material layer 121c, so that the first sub-dielectric material layer 131c and the second sub-dielectric material layer 132c can be used as alkali-resistant masks to better protect the underlying first doped semiconductor layer 121 during etching. In the process of performing the second patterning process on the semiconductor substrate 110, the first doped semiconductor material layer 121c is easily over-etched and the first doped semiconductor material layer 121c at the edge of the first region 100a is removed, exposing the edge of the first sub-surface 1111 (for example, see Fig.10 , the width of the edge of the exposed first sub-surface 1111 is the size of the second spacing L2 along the first direction A), the first doped semiconductor material layer 121c located at the rest of the first region 100a is retained and the first doped semiconductor layer 121 is formed. At this time, since the first doped semiconductor material layer 121c at the edge of the first region 100a is removed by overetching, the first sub-dielectric material layer 131c and the second sub-dielectric material layer 132c located at the edge of the first region 100a are suspended to form a cantilever structure 130a, that is, the first sub-dielectric material layer 131c and the second sub-dielectric material layer 132c include a cantilever structure 130a, and the cantilever structure 130a protrudes from the side wall of the first doped semiconductor layer 121. The cantilever structure 130a will affect the subsequent production and passivation effect of the second passivation layer 152, resulting in a low open circuit voltage and low conversion efficiency of the solar cell 100.

[0173] In the embodiment in which the first passivation material layer 151c is formed, under the preset alkaline etching conditions, the etching rates of the first sub-dielectric material layer 131c and the second sub-dielectric material layer 132c are both lower than the etching rate of the first passivation material layer 151c. In the process of performing the second patterning process on the semiconductor substrate 110, the first passivation material layer 151c is easily over-etched and the first passivation material layer 151c located at the edge of the first region 100a is removed to expose the edge of the first sub-surface 1111, and the first passivation material layer 151c located at the rest of the first region 100a is retained to form the first passivation layer 151. At this time, since the first doped semiconductor material layer 121c and the first passivation material layer 151c at the edge of the first region 100a are both removed, the first sub-dielectric material layer 131c and the second sub-dielectric material layer 132c located at the edge of the first region 100a are suspended to form a cantilever structure 130a.

[0174] In some embodiments, see Fig. 9 and Fig.10, under the preset acid etching conditions, the etching rate of the first sub-dielectric material layer 131c is greater than the etching rate of the second sub-dielectric material layer 132c. After the semiconductor substrate 110 is subjected to the second patterning process, the first sub-dielectric layer 131 may be etched under the preset acid etching conditions, the first sub-dielectric layer 131 at the cantilever structure 130a is easily etched by acid and is removed first, and at the same time, the second sub-dielectric layer 132 located above the first sub-dielectric layer 131 at the cantilever structure 130a is peeled off to achieve the effect of removing the cantilever structure 130a. That is, the first sub-dielectric material layer 131c of the cantilever structure 130a is etched off, and the second sub-dielectric material layer 132c of the cantilever structure 130a is peeled off. In this way, the cantilever structure 130a can be removed, so that the dielectric layer 130 in the final solar cell 100 product does not have the cantilever structure 130a relative to the first doped semiconductor layer 121, so that the open circuit voltage and conversion efficiency of the solar cell 100 can be improved.

[0175] For example, see Fig. 9 and Fig.10 The process of etching and removing the first sub-dielectric material layer 131c of the cantilever structure 130a may further include etching and removing the first sub-dielectric material layer 131c located at the edge of the first doped semiconductor layer 121, thereby facilitating the reduction of the difficulty of completely removing the first sub-dielectric material layer 131c at the cantilever structure 130a. The process of stripping and removing the second sub-dielectric material layer 132c of the cantilever structure 130a may further include stripping and removing the second sub-dielectric material layer 132c located at the edge of the first doped semiconductor layer 121, and exposing the edge of the first doped semiconductor layer 121 (for example, the width of the exposed edge of the first doped semiconductor layer 121 is the size of the first spacing L1 along the first direction A), thereby facilitating the reduction of the difficulty of completely removing the second sub-dielectric material layer 132c at the cantilever structure 130a.

[0176] In summary, the second patterning process is performed under the preset alkaline etching conditions, the first sub-dielectric material layer 131c and the second sub-dielectric material layer 132c are used as masks for the second patterning process, and the etching-resistant second sub-dielectric material layer 132c is arranged on the side away from the first doped semiconductor layer 121, which can play a good protective role for the first doped semiconductor layer 121 during etching. During the second patterning process, due to different etching rates, the first sub-dielectric material layer 131c and the second sub-dielectric material layer 132c are not easily etched, while the first doped semiconductor material layer 121c and the first passivation material layer 151c below are easily etched laterally, resulting in the first sub-dielectric material layer 131c and the second sub-dielectric material layer 132c protruding at the edge to form a cantilever structure 130a, affecting the subsequent production and passivation effect of the second passivation layer 152. The first sub-dielectric material layer 131c, which is easily etched, is arranged on a side close to the first doped semiconductor material layer 121c. After the second patterning process, under the preset acid etching conditions, the first sub-dielectric material layer 131c at the cantilever structure 130a can be removed, and the second sub-dielectric material layer 132c located above the first sub-dielectric material layer 131c at the cantilever structure 130a can be peeled off, so as to achieve the effect of removing the cantilever structure 130a, avoid affecting the subsequent preparation and passivation effect of the second passivation layer 152, and improve the open circuit voltage of the solar cell 100.

[0177] In some embodiments, see Fig.11 After etching away the first sub-dielectric material layer 131c of the cantilever structure 130a, the method may include sequentially forming a second passivation material layer 152c and a second doped semiconductor material layer 122c on the first surface 111, wherein the second passivation material layer 152c and the second doped semiconductor material layer 122c are located in the first region 100a and the second region 100b. Fig.12 , remove the second doped semiconductor material layer 122c, the second passivation material layer 152c, the first sub-dielectric material layer 131c and the second sub-dielectric material layer 132c located in the first sub-region 101a, expose the first doped semiconductor layer 121 located in the first sub-region 101a, retain the second doped semiconductor material layer 122c located in the second sub-region 102a and the second region 100b, and form the second doped semiconductor layer 122, retain the second passivation material layer 152c located in the second sub-region 102a and the second region 100b, and form the second passivation layer 152, retain the first sub-dielectric material layer 131c and the second sub-dielectric material layer 132c located in the second sub-region 102a, and form the dielectric layer 130.

[0178] In some embodiments, see Figure 1After forming the dielectric layer 130, the method may include forming a first conductive layer 141 and a second conductive layer 142. The first conductive layer 141 is disposed on a side of a portion of the first doped semiconductor layer 121 and a portion of the second doped semiconductor layer 122 away from the semiconductor substrate 110, and the first conductive layer 141 is located in the first sub-region 101a and the second sub-region 102a. The second conductive layer 142 is disposed on a side of the second doped semiconductor layer 122 away from the semiconductor substrate 110, and the second conductive layer 142 is at least located in the second region 100b. The first conductive layer 141 and the second conductive layer 142 are spaced apart along the first direction A, so as to prevent the first conductive layer 141 and the second conductive layer 142 from short-circuiting.

[0179] In some embodiments, see Figure 1 After forming the first conductive layer 141 and the second conductive layer 142, the first electrode 161 and the second electrode 162 may be formed. The first electrode 161 is located on a side of the first conductive layer 141 away from the semiconductor substrate 110, and the first electrode 161 may be located in the first sub-region 101a. The second electrode 162 is located on a side of the second conductive layer 142 away from the semiconductor substrate 110, and the second electrode 162 may be located in the second region 100b. The first electrode 161 and the second electrode 162 are spaced apart along the first direction A.

[0180] Exemplarily, at least one of the first electrode 161 and the second electrode 162 can be formed by screen printing, electroplating, laser transfer, inkjet printing, or the like.

[0181] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0182] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application.

Claims

1. A solar cell, characterized in that: The solar cell comprises a plurality of first regions and a plurality of second regions, wherein the first regions and the second regions are alternately arranged along a first direction, the first region comprises a first sub-region and a second sub-region, and the second sub-region is located between the first sub-region and the second region; the solar cell comprises: A semiconductor substrate having a first surface and a second surface arranged opposite to each other; A first doped semiconductor layer, disposed on the first surface and located in the first sub-region and the second sub-region; a dielectric layer, disposed on a side of the first doped semiconductor layer away from the semiconductor substrate and located in the second sub-region; A second doped semiconductor layer is disposed on the first surface and is located in the second region and the second sub-region; a portion of the second doped semiconductor layer located in the second sub-region is disposed on a side of the dielectric layer away from the semiconductor substrate; Among them, in the same first region, the orthographic projection of the dielectric layer on the semiconductor substrate is a first orthographic projection, the orthographic projection of the first doped semiconductor layer on the semiconductor substrate is a second orthographic projection, the first orthographic projection is located within the second orthographic projection, and there is a first distance between the contour edge of the first orthographic projection close to the second region and the contour edge of the second orthographic projection close to the second region.

2. The solar cell according to claim 1, characterized in that The dielectric layer comprises a first sub-dielectric layer and a second sub-dielectric layer, wherein the first sub-dielectric layer is arranged between the second sub-dielectric layer and the first doped semiconductor layer; Under preset acid etching conditions, the etching rate of the first sub-dielectric layer is greater than the etching rate of the second sub-dielectric layer.

3. The solar cell according to claim 2, characterized in that: Under the preset acid etching conditions, the ratio of the etching rate of the first sub-dielectric layer to the etching rate of the second sub-dielectric layer is in the range of 1.1-1000; the etching agent of the preset acid etching conditions includes a hydrofluoric acid solution.

4. The solar cell according to claim 2, characterized in that: Under preset alkaline etching conditions, the etching rates of the first sub-dielectric layer and the second sub-dielectric layer are both lower than the etching rates of the semiconductor substrate and the first doped semiconductor layer; And / or, under preset acid etching conditions, an etching rate of the first sub-dielectric layer is greater than etching rates of the semiconductor substrate and the first doped semiconductor layer.

5. The solar cell according to claim 2, characterized in that: Under preset alkaline etching conditions, the etching rate of any one of the first sub-dielectric layer and the second sub-dielectric layer is A, and the etching rate of any one of the semiconductor substrate and the first doped semiconductor layer is B, and A and B satisfy the following condition: 0.001≤A / B≤0.

9.

6. The solar cell according to any one of claims 2 to 5, characterized in that: The solar cell comprises a first passivation layer, wherein the first passivation layer is disposed between the first doped semiconductor layer and the semiconductor substrate and is located in the first region; Under preset alkaline etching conditions, the etching rates of the first sub-dielectric layer and the second sub-dielectric layer are both lower than the etching rate of the first passivation layer; And / or, under preset acid etching conditions, an etching rate of the first sub-dielectric layer is greater than an etching rate of the first passivation layer.

7. The solar cell according to claim 6, characterized in that: Under preset alkaline etching conditions, the etching rate of any one of the first sub-dielectric layer and the second sub-dielectric layer is C, the etching rate of the first passivation layer is D, and C and D satisfy the following condition: 0.001≤C / D≤0.

9.

8. The solar cell according to any one of claims 2 to 5, characterized in that: The material of the first sub-dielectric layer includes at least one of silicon dioxide, silicon nitride, and silicon oxynitride; And / or, the material of the second sub-dielectric layer includes at least one of silicon dioxide, silicon nitride, and silicon oxynitride.

9. The solar cell according to any one of claims 1 to 5, characterized in that: The solar cell comprises a first conductive layer, the first conductive layer is arranged on a side of a portion of the first doped semiconductor layer and a portion of the second doped semiconductor layer away from the semiconductor substrate, and is located in the first sub-region and the second sub-region, and the orthographic projection of the sidewalls of the first conductive layer on both sides along the first direction on the semiconductor substrate is located within the orthographic projection of the dielectric layer on the semiconductor substrate; And / or, the solar cell comprises a second conductive layer, the second conductive layer is arranged on a side of the second doped semiconductor layer away from the semiconductor substrate and is at least located in the second region; A distance along the first direction between an orthographic projection of the second conductive layer on the semiconductor substrate and an orthographic projection of the first doped semiconductor layer on the semiconductor substrate is greater than or equal to 0.

10. The solar cell according to any one of claims 1 to 5, characterized in that: The first surface includes a first sub-surface, a second sub-surface and a third sub-surface, the first sub-surface is located in the first area, the second sub-surface and the third sub-surface are located in the second area, the second sub-surface is located between the third sub-surface and the first sub-surface, and the distance between the first sub-surface and the second surface is greater than the distance between the third sub-surface and the second surface; The second sub-surface is an inclined surface. In the same second region, the end of the second sub-surface away from the second surface is inclined relative to the end close to the second surface in a direction away from the center of the third sub-surface; the angle between the second sub-surface and the plane where the third sub-surface is located ranges from 10° to 90°.

11. The solar cell according to any one of claims 2 to 5, characterized in that: The first spacing ranges from 0.001 μm to 30 μm; And / or, in the same first region, a second distance between the first doped semiconductor layer and an outer contour of the first region is provided along the first direction, and the second distance is in a range of 0.001 μm-5 μm; And / or, the ratio of the thickness of the first sub-dielectric layer to the thickness of the second sub-dielectric layer is in a range of 1.1-10.

12. A photovoltaic module, characterized in that: A solar cell comprising any one of claims 1-11.

13. A method for preparing a solar cell, characterized in that: The solar cell includes a plurality of first regions and a plurality of second regions, the first regions and the second regions are alternately arranged along a first direction, the first region includes a first sub-region and a second sub-region, and the second sub-region is located between the first sub-region and the second region; The method for preparing the solar cell comprises: Providing a semiconductor substrate; the semiconductor substrate has a first surface and a second surface arranged opposite to each other; A first doped semiconductor layer, a dielectric layer, and a second doped semiconductor layer are formed on the first surface; the first doped semiconductor layer is arranged in the first sub-region and the second sub-region; the dielectric layer is arranged on a side of the first doped semiconductor layer away from the semiconductor substrate and is located in the second sub-region; the second doped semiconductor layer is arranged in the second region and the second sub-region, and a portion of the second doped semiconductor layer located in the second sub-region is arranged on a side of the dielectric layer away from the semiconductor substrate; Among them, in the same first region, the orthographic projection of the dielectric layer on the semiconductor substrate is a first orthographic projection, the orthographic projection of the first doped semiconductor layer on the semiconductor substrate is a second orthographic projection, the first orthographic projection is located within the second orthographic projection, and there is a first distance between the contour edge of the first orthographic projection close to the second region and the contour edge of the second orthographic projection close to the second region.

14. The method for preparing a solar cell according to claim 13, characterized in that: The forming of a first doped semiconductor layer, a dielectric layer and a second doped semiconductor layer on the first surface includes: Forming a first doped semiconductor material layer, a first sub-dielectric material layer, and a second sub-dielectric material layer in sequence on the first surface, wherein the first doped semiconductor material layer, the first sub-dielectric material layer, and the second sub-dielectric material layer are all located in the first region and the second region; The first sub-dielectric material layer and the second sub-dielectric material layer are subjected to a first patterning process to remove the first sub-dielectric material layer and the second sub-dielectric material layer located in the second region and retain the first sub-dielectric material layer and the second sub-dielectric material layer located in the first region.

15. The method for preparing a solar cell according to claim 14, characterized in that: After the first sub-dielectric material layer and the second sub-dielectric material layer are subjected to the first patterning process, the method further comprises: Under preset alkaline etching conditions, the semiconductor substrate is subjected to a second patterning process using the first sub-dielectric material layer and the second sub-dielectric material layer as masks to remove a portion of the semiconductor substrate located in the second region and expose the second sub-surface and the third sub-surface.

16. The method for preparing a solar cell according to claim 15, characterized in that: The process of performing the second patterning process on the semiconductor substrate further includes: The first doped semiconductor material layer located at the edge of the first region is removed to expose the edge of the first sub-surface, and the first doped semiconductor material layer located at the remaining portion of the first region is retained to form the first doped semiconductor layer; the first sub-dielectric material layer and the second sub-dielectric material layer include a cantilever structure, and the cantilever structure protrudes from the side wall of the first doped semiconductor layer; Wherein, under the preset alkaline etching conditions, the etching rates of the first sub-dielectric material layer and the second sub-dielectric material layer are both lower than the etching rates of the semiconductor substrate and the first doped semiconductor material layer.

17. The method for preparing a solar cell according to claim 16, characterized in that: After the semiconductor substrate is subjected to a second patterning process, the method further comprises: Under preset acid etching conditions, etching and removing the first sub-dielectric material layer of the cantilever structure, and stripping and removing the second sub-dielectric material layer of the cantilever structure; Wherein, under the preset acid etching condition, the etching rate of the first sub-dielectric material layer is greater than the etching rate of the second sub-dielectric material layer.

18. The method for preparing a solar cell according to claim 17, characterized in that: The process of etching and removing the first sub-dielectric material layer of the cantilever structure also includes: Etching and removing the first sub-dielectric material layer located at the edge of the first doped semiconductor layer; The process of stripping and removing the second sub-dielectric material layer of the cantilever structure also includes: The second sub-dielectric material layer located at the edge of the first doped semiconductor layer is stripped and removed to expose the edge of the first doped semiconductor layer.

19. The method for preparing a solar cell according to claim 17, characterized in that: After the etching removes the first sub-dielectric material layer of the cantilever structure, the method includes: forming a second doped semiconductor material layer on the first surface, wherein the second doped semiconductor material layer is located in the first region and the second region; The second doped semiconductor material layer, the first sub-dielectric material layer and the second sub-dielectric material layer located in the first sub-region are removed to expose the first doped semiconductor layer located in the first sub-region, the second doped semiconductor material layer located in the second sub-region and the second region is retained to form the second doped semiconductor layer, the first sub-dielectric material layer and the second sub-dielectric material layer located in the second sub-region are retained to form the dielectric layer.

20. The method for preparing a solar cell according to claim 15, characterized in that: Before sequentially forming the first doped semiconductor material layer, the first sub-dielectric material layer and the second sub-dielectric material layer on the first surface, the method further includes: forming a first passivation material layer on the first surface, wherein the first passivation material layer is located in the first region and the second region; The process of performing the first patterning process on the first sub-dielectric material layer and the second sub-dielectric material layer further includes: exposing the first doped semiconductor material layer; The process of performing the second patterning process on the semiconductor substrate further includes: removing the first doped semiconductor material layer and the first passivation material layer located in the second region; Alternatively, the process of performing the first patterning process on the first sub-dielectric material layer and the second sub-dielectric material layer further includes: removing the first doped semiconductor material layer located in the second region to expose the first passivation material layer; The process of performing the second patterning process on the semiconductor substrate further includes: removing the first passivation material layer located in the second area; Alternatively, the process of performing the first patterning process on the first sub-dielectric material layer and the second sub-dielectric material layer further includes: removing the first doped semiconductor material layer and the first passivation material layer located in the second region to expose the semiconductor substrate.

21. The method for preparing a solar cell according to claim 20, characterized in that: The process of performing the second patterning process on the semiconductor substrate further includes: removing the first passivation material layer located at the edge of the first region, retaining the first passivation material layer located at the remaining portion of the first region, and forming a first passivation layer; Wherein, under the preset alkaline etching conditions, the etching rates of the first sub-dielectric material layer and the second sub-dielectric material layer are both lower than the etching rate of the first passivation material layer.

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