Back contact battery and manufacturing method thereof

Abstract

The invention discloses a back contact cell and a manufacturing method thereof, relates to the technical field of photovoltaics, and aims to prevent electric leakage between doped semiconductor layers with opposite conduction types in the back contact cell. The back contact cell includes a semiconductor substrate, a first doped semiconductor layer, an intrinsic semiconductor layer, a second doped semiconductor layer, and an insulating mask layer. The part, located on the first region, of the first doped semiconductor layer is a first doped part, and the other part is a second doped part. The doping concentration of impurities in the second doping part is smaller than that of the impurities in the first doping part. The intrinsic semiconductor layer is formed on a portion of the isolation region outside the second doped portion, and is integrally formed with the first doped semiconductor layer. And the second doped semiconductor layer covers the second region, at least part of the intrinsic semiconductor layer and at least part of the second doped part. The conduction types of the second doped semiconductor layer and the first doped semiconductor layer are opposite, and at least one of the second doped semiconductor layer and the first doped semiconductor layer is a doped crystalline silicon layer.

Description

Technical Field

[0001] The present invention relates to the field of photovoltaic technology, and in particular to a back contact battery and a manufacturing method thereof. Background Art

[0002] Back-contact cells refer to solar cells with both the positive and negative electrodes on the back of the cell and no metal electrode blocking the front. Compared with solar cells with blocked fronts, back-contact cells have higher short-circuit current and photoelectric conversion efficiency, and are one of the current technical directions for achieving high-efficiency crystalline silicon cells.

[0003] However, in the existing back contact cell, there is a leakage problem between the two doped semiconductor layers with opposite conductivity types located on the backlight side, resulting in a decrease in the photoelectric conversion efficiency of the back contact cell. Summary of the invention

[0004] The object of the present invention is to provide a back contact cell and a method for manufacturing the same, which are used to prevent leakage between a first doped semiconductor layer and a second doped semiconductor layer of opposite conductivity types, thereby improving the photoelectric conversion efficiency of the back contact cell.

[0005] In order to achieve the above-mentioned object, in a first aspect, the present invention provides a back contact battery, which includes: a semiconductor substrate, a first doped semiconductor layer, an intrinsic semiconductor layer, a second doped semiconductor layer and an insulating mask layer. The semiconductor substrate has a first surface and a second surface opposite to each other. The second surface has a first region and a second region that are alternately distributed, and an isolation region between each first region and a second region adjacent to itself. The first doped semiconductor layer is formed on the first region and part of the isolation region. The portion of the first doped semiconductor layer located on the first region is the first doped portion, and the remaining portion is the second doped portion. The doping concentration of impurities in the second doped portion is less than the doping concentration of impurities in the first doped portion. The intrinsic semiconductor layer is formed on the portion other than the second doped portion of the isolation region and is integrally formed with the first doped semiconductor layer. The second doped semiconductor layer covers the second region, at least part of the intrinsic semiconductor layer and at least part of the second doped portion. The conductivity type of the second doped semiconductor layer is opposite to that of the first doped semiconductor layer, and at least one of the second doped semiconductor layer and the first doped semiconductor layer is a doped crystalline silicon layer. The intrinsic semiconductor layer is used to electrically isolate the first doped semiconductor layer and the second doped semiconductor layer in a direction parallel to the second surface. The insulating mask layer is located between the second doped semiconductor layer and the intrinsic semiconductor layer and the second doped portion.

[0006] In the case of adopting the above technical solution, the above-mentioned first doped semiconductor layer and the second doped semiconductor layer are both formed on one side of the second surface of the semiconductor substrate, and the conductivity types of the two are opposite. Based on this, when the back contact battery is in a working state, the electrons and holes generated by the semiconductor substrate after absorbing photons move toward the first doped semiconductor layer and the second doped semiconductor layer respectively, and are collected and guided by the two respectively to form a photocurrent. Among them, along the thickness direction of the semiconductor substrate, the second doped semiconductor layer is not only formed on the second region of the second surface of the semiconductor substrate, but also covers at least part of the intrinsic semiconductor layer and at least part of the second doped part included in the first doped semiconductor layer. In addition, the insulating mask layer is located between the second doped semiconductor layer and the intrinsic semiconductor layer and the second doped part respectively. Because the insulating mask layer is a non-conductive film layer, the existence of the insulating mask layer can electrically isolate the second doped semiconductor layer and the second doped part of opposite conductivity types along the thickness direction of the semiconductor substrate, preventing the two from leaking electricity along the thickness direction of the semiconductor substrate.

[0007] Secondly, along the direction parallel to the second surface of the semiconductor substrate, an intrinsic semiconductor layer is formed between the first doped semiconductor layer and the second doped semiconductor layer, and the intrinsic semiconductor layer is used to electrically isolate the first doped semiconductor layer and the second doped semiconductor layer along the direction parallel to the second surface, so as to prevent leakage between the two in the direction parallel to the second surface, further reduce the carrier recombination rate on the second surface side of the semiconductor substrate, and help improve the photoelectric conversion efficiency of the back contact battery. In addition, in the actual manufacturing process, due to the accuracy of the machine and / or for the purpose of preventing leakage, the width of the isolation area between the first area and the adjacent second area is large. Based on this, the first doped semiconductor layer not only includes a first doped portion located on the first area, but also includes a second doped portion located on a partial isolation area. At this time, when the back contact battery is in a working state, the first doped semiconductor layer can not only collect and guide the electrons or holes corresponding to the first area in time, but also collect and guide the electrons or holes corresponding to the partial isolation area in time. Therefore, while preventing the first doped semiconductor layer and the second doped semiconductor layer from lateral leakage through the intrinsic semiconductor layer, the carrier recombination rate at the isolation area with a larger width can be reduced, further improving the photoelectric conversion efficiency of the back contact battery.

[0008] In addition, because the second doped portion is located between the first doped portion and the intrinsic semiconductor layer, when the doping concentration of impurities in the second doped portion located on the partial isolation area is less than the doping concentration of impurities in the first doped portion located on the first area, the conductivity of the second doped portion can be reduced, and the electrical breakdown penetrating the intrinsic semiconductor layer can be reduced. At the same time, the diffusion of impurities in the second doped portion into the intrinsic semiconductor layer can be suppressed or even eliminated, thereby ensuring that the intrinsic semiconductor layer has a good electrical isolation effect and ensuring that the back contact battery has good electrical performance.

[0009] As a possible implementation solution, the first doped semiconductor layer is a doped crystalline silicon layer.

[0010] When the above technical solution is adopted, the doped crystalline silicon layer has a higher lateral carrier transport characteristic than the doped amorphous silicon layer. In addition, part of the insulating mask layer and part of the second doped semiconductor layer cover the second doped portion. Therefore, when the first doped semiconductor layer is a doped crystalline silicon layer, the second doped portion has a good lateral carrier transport characteristic, which is conducive to the second doped portion to laterally transport more electrons or holes collected by itself to the first doped portion, and to guide them out through the first doped portion exposed to the outside, further reducing the carrier recombination efficiency at the isolation region. At the same time, it can also make the first doped portion have a higher carrier collection characteristic, reducing the carrier recombination efficiency at the first region.

[0011] As a possible implementation solution, along the direction from the second doping portion to the intrinsic semiconductor layer, the ratio of the width of the second doping portion to the width of the isolation region is greater than or equal to 0.8 and less than 1.

[0012] In the case of adopting the above technical solution, along the direction from the second doping part to the intrinsic semiconductor layer, when the ratio of the width of the second doping part to the width of the isolation region is within the above range, the width of the second doping part is greater than the width of the intrinsic semiconductor layer, which can prevent the second doping part from reducing the carrier recombination rate at the isolation region by the second doping part due to the small width of the second doping part. The degree is not obvious, ensuring that the back contact battery has a high photoelectric conversion efficiency. In addition, because the second doping part and the intrinsic semiconductor layer are co-located on the isolation region, when the width of the isolation region is a constant value, the width of the second doping part is inversely proportional to the width of the intrinsic semiconductor layer. Moreover, within a certain range, the electrical isolation effect of the intrinsic semiconductor layer in the direction parallel to the second surface is proportional to its own width. Based on this, when the ratio is within the above range, it can also prevent the electrical isolation effect of the intrinsic semiconductor layer from being poor due to the small width of the second doping part, ensuring that the first doped semiconductor layer and the second doped semiconductor layer can be prevented from leaking along the direction parallel to the second surface through the intrinsic semiconductor layer.

[0013] As a possible implementation solution, along the direction from the second doping portion to the intrinsic semiconductor layer, the width of the intrinsic semiconductor layer is greater than or equal to 6 μm and less than or equal to 120 μm.

[0014] When the above technical solution is adopted, the width of the intrinsic semiconductor layer is within the above range, which can prevent the intrinsic semiconductor layer from affecting its electrical isolation effect along the second direction due to its small width, and ensure that the first doped semiconductor layer and the second doped semiconductor layer can be prevented from leaking electricity along the second surface through the intrinsic semiconductor layer. In addition, it can also prevent the second doped portion from having a small width due to the large width of the intrinsic semiconductor layer, which leads to a low carrier collection capacity, and further improve the degree of reducing the carrier recombination rate at the isolation region through the second doped portion.

[0015] As a possible implementation solution, along the direction from the second doping portion to the intrinsic semiconductor layer, the width of the isolation region is greater than or equal to 30 μm and less than or equal to 200 μm.

[0016] In the case of adopting the above technical solution, the width of the isolation region is within the above range, which can prevent the difficulty of setting the second doped portion and the intrinsic semiconductor layer with a reasonable width within a smaller width range due to the smaller range of the isolation region, and ensure that the second doped portion and the intrinsic semiconductor layer have the functions described above. In addition, it can also prevent the first doped semiconductor layer and / or the second doped semiconductor layer from having a smaller width due to the larger width of the intrinsic semiconductor layer, thereby ensuring that the first doped semiconductor layer and the second doped semiconductor layer can collect and export the carriers corresponding to the first region and the second region in time, and further reduce the carrier recombination rate on the second side.

[0017] As a possible implementation solution, the doping concentration of the impurities in the second doping portion is greater than or equal to 1E18 cm -3 , and less than or equal to 5E20cm -3 .

[0018] When the above technical solution is adopted, the doping concentration of the impurities in the second doping part is within the above range, which can prevent the poor carrier collection ability of the second doping part due to the low doping concentration of the impurities in the second doping part, and further improve the degree of reducing the carrier recombination rate in the isolation region by the second doping part. In addition, it can also prevent the carriers in the second doping part from easily diffusing into the intrinsic semiconductor layer due to the high doping concentration of the impurities in the second doping part, ensuring that the intrinsic semiconductor layer has a good electrical isolation effect.

[0019] As a possible implementation scheme, the doping concentration of impurities in the first doping part is 10 to 100 times the doping concentration of impurities in the second doping part. In this case, the doping concentration of impurities in the first doping part is relatively high, which can make the first doping part have a higher carrier collection ability. In addition, the manufacturing difficulty of obtaining a first doping part with an excessively high doping concentration can also be reduced.

[0020] As a possible implementation scheme, the doping concentration of impurities in the second doping part gradually decreases along the direction from the second doping part to the intrinsic semiconductor layer. In this case, while the impurities in the second doping part have a certain doping concentration, and thus the second doping part has a certain carrier lateral collection ability, the part with the lowest impurity doping concentration in the second doping part can also be made to contact with the intrinsic semiconductor layer, reducing the carrier concentration gradient at the contact point between the two, further inhibiting or even eliminating the diffusion of impurities in the second doping part into the intrinsic semiconductor layer, and ensuring that the intrinsic semiconductor layer has a good electrical isolation effect.

[0021] As a possible implementation scheme, the above-mentioned back contact battery further includes a first passivation layer, and the first passivation layer is located between the semiconductor substrate and the first doped semiconductor layer and the intrinsic semiconductor layer respectively.

[0022] When the above technical solution is adopted, the selective contact structure composed of the first passivation layer and the first doped semiconductor layer has an excellent interface passivation effect, and can realize the selective collection of carriers, reduce the carrier recombination rate in the first area and partial isolation area of ​​the backlight surface of the semiconductor substrate, and further improve the photoelectric conversion efficiency of the back contact battery.

[0023] As a possible implementation scheme, the above-mentioned back contact battery further includes a second passivation layer, and the second passivation layer is located between the second doped semiconductor layer and the semiconductor substrate, the intrinsic semiconductor layer and the second doped portion respectively.

[0024] In the case of adopting the above technical solution, the selective contact structure composed of the second passivation layer and the second doped semiconductor layer can realize the selective collection of carriers and reduce the carrier recombination rate of the second region of the backlight surface of the semiconductor substrate. At the same time, the second passivation layer and the intrinsic semiconductor layer are also located between the portion of the second doped semiconductor layer located on the second region and the second doped portion. At this time, both can suppress the carrier recombination rate at the interface of the second doped semiconductor layer and the first doped semiconductor layer corresponding to the isolation region, further improving the photoelectric conversion efficiency of the back contact battery.

[0025] As a possible implementation scheme, when the back contact cell further includes a first passivation layer, and the first passivation layer is a tunnel passivation layer, the material of the first doped semiconductor layer is doped polysilicon, and the conductivity type is N-type.

[0026] In the case of adopting the above technical solution, when the back contact battery also includes a first passivation layer, and the first passivation layer is a tunnel passivation layer, the selective contact structure formed by the first passivation layer and the first doped semiconductor layer is a tunnel passivation contact structure. At this time, the material of the first doped semiconductor layer is doped polysilicon. Based on this, because the contact resistance between the P-type doped polysilicon layer and the electrode is high and the field passivation effect is poor, when the first passivation layer included in the back contact battery is a tunnel passivation layer and the first doped semiconductor layer is a doped polysilicon layer, when the conductivity type of the first doped semiconductor layer is N-type, the field passivation effect of the first doped semiconductor layer can be further improved, and the contact resistance between the first doped portion and the electrode can be reduced, which is conducive to improving the electrical performance of the back contact battery. In addition, the intrinsic semiconductor layer and the first doped semiconductor layer are integrally formed, and the second doped semiconductor layer is also located on at least part of the intrinsic semiconductor layer and at least part of the second doped portion included in the first doped semiconductor layer, so the formation order of the first doped semiconductor layer is before the formation order of the second doped semiconductor layer. In addition, compared with amorphous silicon, polycrystalline silicon has better heat resistance. Based on this, when the back contact battery also includes a first passivation layer, and the first passivation layer is a tunnel passivation layer and the material of the first doped semiconductor layer is doped polysilicon, if a laser etching process is used to remove the portion of the material layer corresponding to the first region for manufacturing the second doped semiconductor layer, the first doped semiconductor whose material is doped polysilicon is less affected by the high temperature laser or even not affected by the high temperature laser, which is beneficial to improve the yield of the back contact battery. Furthermore, in the actual manufacturing process, the manufacturing cost of the heterogeneous contact structure is higher than that of the tunnel passivation contact structure, and the tunnel passivation contact structure can be realized by a variety of processes such as low pressure chemical vapor deposition, plasma chemical vapor deposition, physical chemical vapor deposition or plasma enhanced atomic layer deposition, which is more compatible with the back contact battery process, while the heterogeneous contact structure needs to be manufactured by a plate plasma chemical vapor deposition device that supports a lower formation temperature. Based on this, when the first passivation layer of the back contact battery is a tunnel passivation layer and the material of the first doped semiconductor layer is doped polysilicon, it is beneficial to reduce the manufacturing cost, reduce the investment in plate plasma chemical vapor deposition equipment, and save production site area.

[0027] As a possible implementation scheme, when the back contact battery also includes a second passivation layer, and the material of the second passivation layer includes intrinsic amorphous silicon and / or intrinsic microcrystalline silicon, the material of the second doped semiconductor layer is doped amorphous silicon and / or doped microcrystalline silicon, and the conductivity type is P type.

[0028] In the case of adopting the above technical solution, when the back contact battery also includes a second passivation layer, and the material of the second passivation layer includes intrinsic amorphous silicon and / or intrinsic microcrystalline silicon, the second passivation layer and the second doped semiconductor layer selective contact structure are heterogeneous contact structures. At this time, the material of the second doped semiconductor layer is doped amorphous silicon and / or doped microcrystalline silicon. Based on this, compared with the P-type doped amorphous silicon and / or doped microcrystalline silicon layer, the P-type doped polycrystalline silicon layer has a higher contact resistance with the electrode and a poorer field passivation effect. Therefore, in the above case, the conductivity type of the second doped semiconductor layer is set to P-type, instead of setting the conductivity type of the tunnel passivation contact structure to P-type, which can further improve the field passivation effect of the first doped semiconductor layer, and at the same time can reduce the contact resistance between the first doped part and the electrode, which is conducive to improving the electrical performance of the back contact battery.

[0029] As a possible implementation scheme, the first surface of the semiconductor substrate and the surface of the second region of the semiconductor substrate are both velvet. In this case, the refractive index of light transmitted from the first surface and the surface of the second region to the semiconductor substrate can be increased, further improving the photoelectric conversion efficiency of the back contact battery. In addition, when the surface of the second region is velvet, the backlight side of the second doped semiconductor layer formed on the second region also has corresponding undulating features. Compared with a plane, a surface with undulating features has a larger specific surface area. Therefore, when the backlight side of the second doped semiconductor layer on the second region has undulating features, it is beneficial to increase the contact area between the second doped semiconductor layer and the electrode, reduce the contact resistance between the two, and further improve the electrical performance of the back contact battery.

[0030] In a second aspect, the present invention also provides a method for manufacturing a back-contact battery, which comprises: first, providing a semiconductor substrate. The semiconductor substrate has a first surface and a second surface opposite to each other. The second surface has a first region and a second region that are alternately distributed, and an isolation region between each first region and the second region adjacent to itself. Next, a layer of an intrinsic semiconductor material layer arranged in a whole layer is formed on the second surface. Next, a first mask layer is formed; the first mask layer covers the portion of the intrinsic semiconductor material layer corresponding to the second region and the isolation region. Under the masking action of the first mask layer, the portion of the intrinsic semiconductor material layer located on the first region is selectively doped, so that the portion of the intrinsic semiconductor material layer located on the first region and part of the isolation region forms a first doped semiconductor layer, and the portion of the intrinsic semiconductor material layer located on the remaining isolation region forms an intrinsic semiconductor layer. The portion of the first doped semiconductor layer located on the first region is a first doped portion, and the remaining portion is a second doped portion, and the doping concentration of impurities in the second doped portion is less than the doping concentration of impurities in the first doped semiconductor layer. Then, the first mask layer is removed. Next, at least an insulating mask layer is formed to cover the first doped semiconductor layer and the intrinsic semiconductor layer; and at least under the masking effect of the insulating mask layer, the portion of the intrinsic semiconductor material layer remaining on the second region is selectively removed. Next, a second doped semiconductor layer is formed on the insulating mask layer and the second region. The second doped semiconductor layer and the first doped semiconductor layer have opposite conductivity types, and at least one of the second doped semiconductor layer and the first doped semiconductor layer is a doped crystalline silicon layer. The intrinsic semiconductor layer is used to electrically isolate the second doped semiconductor layer from the first doped semiconductor layer. Then, the portion of the insulating mask layer located on the first doped portion is removed.

[0031] As a possible implementation scheme, when the width of the second doped portion is greater than or equal to 6um and less than or equal to 120um along the direction from the second doped portion to the intrinsic semiconductor layer, after selectively doping the portion of the intrinsic semiconductor material layer located on the first region and before removing the first mask layer, the method for manufacturing a back contact battery also includes: annealing the first doped semiconductor layer and the intrinsic semiconductor layer to make the width of the second doped portion reach a target width.

[0032] In the case of adopting the above technical solution, the second doped portion is formed by diffusion when the portion of the intrinsic semiconductor material layer located on the first region is selectively doped under the masking action of the first mask layer. Based on this, along the direction from the second doped portion to the intrinsic semiconductor layer, when the width of the second doped portion is greater than or equal to 6μm and less than or equal to 120μm, the width of the second doped portion is relatively large. At this time, the first doped semiconductor layer and the intrinsic semiconductor layer after selective doping are annealed, so that the second doped portion, or the impurities in the first doped portion and the second doped portion can diffuse a longer distance in the direction parallel to the second surface after being heated, thereby obtaining a second doped portion whose actual width reaches the target width.

[0033] As a possible implementation scheme, after the above-mentioned removal of the first mask layer and before forming the second doped semiconductor layer on the insulating mask layer and the second region, the manufacturing method of the back contact battery includes: forming a mask material layer arranged in an entirety on the first doped semiconductor layer, the intrinsic semiconductor layer and the portion of the intrinsic semiconductor material layer remaining on the second region. Next, the portion of the mask material layer located above the second region is removed, and the remaining portion of the mask material layer forms the second mask layer. Next, under the masking action of the second mask layer, the portion of the intrinsic semiconductor material layer remaining on the second region is selectively removed. Next, under the masking action of at least a portion of the second mask layer, the first surface of the semiconductor substrate and the surface of the semiconductor substrate corresponding to the second region are subjected to a texturing treatment. After the texturing treatment, at least a portion of the second mask layer forms an insulating mask layer.

[0034] When the above technical solution is adopted, the presence of the second mask layer can prevent the portion of the intrinsic semiconductor material layer remaining on the second region from being affected by the etching operation and the subsequent texturing process during the process of selectively removing the portion.

[0035] As a possible implementation scheme, a laser etching process is used to sequentially remove the portion of the mask material layer located above the second region and the portion of the intrinsic semiconductor material layer remaining on the second region.

[0036] When the above technical solution is adopted, since the laser etching process has a high etching accuracy, the laser etching process is used to sequentially remove the portion of the mask material layer located above the second area and the portion of the intrinsic semiconductor material layer remaining on the second area, thereby improving the yield of the manufactured back-contact battery.

[0037] As a possible implementation scheme, the second mask layer includes a first silicon nitride layer and a second silicon nitride layer spaced apart in the thickness direction of the semiconductor substrate, and an intrinsic silicon layer located between the first silicon nitride layer and the second silicon nitride layer. In the above case, after the first surface of the semiconductor substrate and the surface of the semiconductor substrate corresponding to the second region are textured, before the second doped semiconductor layer is formed on the insulating mask layer and the second region, the manufacturing method of the back contact battery further includes: removing the second silicon nitride layer and the intrinsic silicon layer in sequence.

[0038] In the case of adopting the above technical solution, when other factors are the same, compared with the second mask layer being a single-layer film, when the second mask layer includes the first silicon nitride layer, the intrinsic silicon layer and the second silicon nitride layer, the mask characteristics of the second mask layer can be improved to ensure that the first doped semiconductor layer and the intrinsic semiconductor layer located below it can be protected by the second mask layer. In addition, when a laser etching process is used to remove the portion of the mask material layer located above the second region and the portion of the intrinsic semiconductor material layer remaining on the second region, because the laser spot is a Gaussian spot, the energy at the center is higher and the energy at the edge is lower, so in order to completely remove the portion of the mask material layer located above the second region and the portion of the intrinsic semiconductor material layer remaining on the second region, the edge of the laser spot pattern may cover part of the second mask layer. The film properties of the silicon nitride material change after being heated, thereby enhancing its corrosion resistance. Based on this, in the subsequent texturing process, when the texturing solution corrodes to the boundary between the second region and the isolation region, it is easy to corrode the surface of the semiconductor substrate and the intrinsic semiconductor layer corresponding to the boundary between the isolation region and the second region. When the second mask layer is only a single-layer silicon nitride layer, the edge of the second mask layer has strong corrosion resistance, so an air gap is formed between this part of the isolation region and the edge of the second mask layer. Because the size of the air gap is small, the second doped semiconductor layer formed subsequently is difficult to fill in the air gap, and the carrier recombination rate of the area below the air gap is large. In the above case, when the second mask layer includes a first silicon nitride layer, an intrinsic silicon layer, and a second silicon nitride layer, even if the second silicon nitride layer located on the outside is affected by the heat of the laser spot so that its edge is heated and the corrosion resistance of its edge is enhanced, it can be removed by appropriately extending the etching time. Although the first silicon nitride layer located inside also protrudes on the velvet area after the texturing treatment, its edge has not been irradiated with laser, which causes changes in the film properties. In addition, after etching away the second silicon nitride layer, the etching time is appropriately extended to completely remove the intrinsic silicon layer covering the first silicon nitride layer, and the portion of the first silicon nitride layer located on the velvet area is also removed, so that the above-mentioned air gap will not be formed, thereby reducing the carrier recombination rate at the junction of the isolation area and the second area, and further improving the photoelectric conversion efficiency of the back contact battery.

[0039] As a possible implementation scheme, forming a second doped semiconductor layer on the insulating mask layer and the second region includes: forming a second doped semiconductor material layer disposed entirely on the second region and the second mask layer. Next, selectively removing a portion of the second doped semiconductor material layer corresponding to the first region, so that the remaining portion of the second doped semiconductor material layer forms the second doped semiconductor layer.

[0040] As a possible implementation scheme, after providing a semiconductor substrate, before forming a whole layer of an intrinsic semiconductor material layer on the second surface, the manufacturing method of the back contact battery further includes: forming a whole layer of a first passivation material layer on the second surface. And after selectively removing the remaining portion of the intrinsic semiconductor material layer on the second region, before forming a second doped semiconductor layer on the second region and the insulating mask layer, the manufacturing method of the back contact battery further includes: selectively removing the portion of the first passivation material layer located on the second region, so that the remaining portion of the first passivation material layer forms a first passivation layer.

[0041] As a possible implementation scheme, after selectively removing the portion of the intrinsic semiconductor material layer remaining on the second region, before forming a second doped semiconductor layer on the insulating mask layer and the second region, the method for manufacturing a back contact battery also includes: forming a second passivation layer on the insulating mask layer.

[0042] The beneficial effects of the second aspect of the present invention and its various implementations can be analyzed by referring to the beneficial effects of the first aspect and its various implementations, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0044] Figure 1 A schematic longitudinal cross-sectional view of a first structure of a back contact battery provided by an embodiment of the present invention;

[0045] Figure 2 A schematic longitudinal cross-sectional view of a second structure of a back contact battery provided by an embodiment of the present invention;

[0046] Figure 3 A schematic longitudinal cross-sectional view of a third structure of a back contact battery provided by an embodiment of the present invention;

[0047] Figure 4 Schematic diagram of the structure of the back contact battery provided in the embodiment of the present invention during the manufacturing process Figure 1 ;

[0048] Figure 5Schematic diagram of the structure of the back contact battery provided in the embodiment of the present invention during the manufacturing process Figure 2 ;

[0049] Figure 6 Schematic diagram of the structure of the back contact battery provided in the embodiment of the present invention during the manufacturing process Figure 3 ;

[0050] Figure 7 Schematic diagram of the structure of the back contact battery provided in the embodiment of the present invention during the manufacturing process Figure 4 ;

[0051] Figure 8 Schematic diagram of the structure of the back contact battery provided in the embodiment of the present invention during the manufacturing process Figure 5 ;

[0052] Fig. 9 Schematic diagram of the structure of the back contact battery provided in the embodiment of the present invention during the manufacturing process Figure 6 ;

[0053] Fig.10 Schematic diagram of the structure of the back contact battery provided in the embodiment of the present invention during the manufacturing process Figure 7 ;

[0054] Fig.11 Schematic diagram of the structure of the back contact battery provided in the embodiment of the present invention during the manufacturing process Figure 8 ;

[0055] Fig.12 Schematic diagram of the structure of the back contact battery provided in the embodiment of the present invention during the manufacturing process Figure 9 ;

[0056] Fig.13 Schematic diagram of the structure of the back contact battery provided in the embodiment of the present invention during the manufacturing process Figure 10 ;

[0057] Fig.14 Schematic diagram of the structure of the back contact battery provided in the embodiment of the present invention during the manufacturing process Figure 10 one;

[0058] Fig.15 Schematic diagram of the structure of the back contact battery provided in the embodiment of the present invention during the manufacturing process Figure 10 two;

[0059] Fig.16 Schematic diagram of the structure of the back contact battery provided in the embodiment of the present invention during the manufacturing process Figure 10 three;

[0060] Fig.17 Schematic diagram of the structure of the back contact battery provided in the embodiment of the present invention during the manufacturing process Figure 10 Four. DETAILED DESCRIPTION

[0061] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0062] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for the purpose of clear expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may further design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0063] In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. In addition, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "under" the other layer / element. In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0064] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. The meaning of "several" is one or more, unless otherwise clearly and specifically defined.

[0065] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0066] Solar cells are now being used more and more widely as a new energy alternative. Among them, photovoltaic solar cells are devices that convert sunlight into electrical energy. Specifically, solar cells use the photovoltaic principle to generate carriers, and then use electrodes to lead the carriers out, thereby facilitating the effective use of electrical energy.

[0067] When the positive and negative electrodes of a solar cell are both located on the back of the solar cell, the solar cell is a back-contact cell. The biggest feature of a back-contact cell is that there is no metal electrode blocking the front, so it has a higher short-circuit current Isc, which makes the back-contact cell one of the current technical directions for achieving high-efficiency crystalline silicon cells.

[0068] Specifically, the above-mentioned back contact battery generally includes a semiconductor substrate, a first doped semiconductor layer, a second doped semiconductor layer and an isolation layer. Among them, along the direction parallel to the surface of the semiconductor substrate, the first doped semiconductor layer and the second doped semiconductor layer are alternately formed on the same side of the semiconductor substrate. In addition, the conductivity type of the second doped semiconductor layer is opposite to that of the first doped semiconductor layer, and the second doped semiconductor layer covers a partial area of ​​the first doped semiconductor layer. The isolation layer is only located between the first doped semiconductor layer and the second doped semiconductor layer, and is used to isolate the first doped semiconductor layer from the second doped semiconductor layer. In addition, in the actual application process, compared with the doped amorphous silicon layer, the doped crystalline silicon layer has a higher carrier transport layer capacity. Based on this, when at least one of the above-mentioned first doped semiconductor layer and the second doped semiconductor layer is a doped crystalline silicon layer, it is beneficial to improve its own carrier collection efficiency, reduce the carrier recombination rate on the backlight side, and help improve the photoelectric conversion efficiency of the back contact battery.

[0069] However, the isolation layer in the above-mentioned back contact battery can only electrically isolate the first doped semiconductor layer and the second doped semiconductor layer along the thickness direction of the semiconductor substrate. When at least one of the first doped semiconductor layer and the second doped semiconductor layer is a doped crystalline silicon layer, the doped crystalline silicon layer has good carrier lateral transport characteristics. Therefore, when the back contact battery is in a working state, the first doped semiconductor layer and the second doped semiconductor layer will be in electrical contact along a direction parallel to the semiconductor substrate to generate leakage, resulting in a decrease in the photoelectric conversion efficiency of the back contact battery. In the prior art, an intrinsic amorphous silicon passivation layer or a tunneling silicon dioxide layer is also provided between the first doped semiconductor layer and the second doped semiconductor layer. Since the intrinsic amorphous silicon passivation layer or the tunneling silicon dioxide layer has a tunneling effect, when the doped polycrystalline silicon with strong conductivity is used as the semiconductor doping layer, it is easy to break through the intrinsic amorphous silicon passivation layer or the tunneling silicon dioxide layer, thereby generating a large leakage.

[0070] In order to solve the above technical problems, in the first aspect, an embodiment of the present invention provides a back contact battery. Figure 1As shown, the back contact battery includes: a semiconductor substrate 11, a first doped semiconductor layer 17, an intrinsic semiconductor layer 20, a second doped semiconductor layer 21 and an insulating mask layer 22. The semiconductor substrate 11 has a first surface and a second surface opposite to each other. The second surface has first regions 14 and second regions 15 that are alternately distributed, and an isolation region 16 located between each first region 14 and the second region 15 adjacent to itself. The first doped semiconductor layer 17 is formed on the first region 14 and part of the isolation region 16. The portion of the first doped semiconductor layer 17 located on the first region 14 is the first doped portion 18, and the remaining portion is the second doped portion 19. The doping concentration of impurities in the second doped portion 19 is less than the doping concentration of impurities in the first doped portion 18. The intrinsic semiconductor layer 20 is formed on the portion other than the second doped portion 19 of the isolation region 16, and is integrally formed with the first doped semiconductor layer 17. The second doped semiconductor layer 21 covers the second region 15, at least part of the intrinsic semiconductor layer 20 and at least part of the second doped portion 19. The second doped semiconductor layer 21 and the first doped semiconductor layer 17 have opposite conductivity types, and at least one of the second doped semiconductor layer 21 and the first doped semiconductor layer 17 is a doped crystalline silicon layer. The intrinsic semiconductor layer 20 is used to electrically isolate the first doped semiconductor layer 17 and the second doped semiconductor layer 21 along a direction parallel to the second surface. The insulating mask layer 22 is located between the second doped semiconductor layer 21 and the intrinsic semiconductor layer 20 and the second doped portion 19, respectively.

[0071] When the above technical solution is adopted, Figure 1As shown, the first doped semiconductor layer 17 and the second doped semiconductor layer 21 are both formed on one side of the second surface of the semiconductor substrate 11, and the conductivity types of the two are opposite. Based on this, when the back contact battery is in a working state, the electrons and holes generated after the semiconductor substrate 11 absorbs photons move toward the first doped semiconductor layer 17 and the second doped semiconductor layer 21 respectively, and are collected and guided by the two respectively to form a photocurrent. Among them, along the thickness direction of the semiconductor substrate 11, the second doped semiconductor layer 21 is not only formed on the second region 15 of the second surface of the semiconductor substrate 11, but also covers at least part of the intrinsic semiconductor layer 20 and at least part of the second doped portion 19 included in the first doped semiconductor layer 17. In addition, the insulating mask layer 22 is located between the second doped semiconductor layer 21 and the intrinsic semiconductor layer 20 and the second doped portion 19 respectively. Because the insulating mask layer 22 is a non-conductive film layer, the existence of the insulating mask layer 22 can electrically isolate the second doped semiconductor layer 21 and the second doped portion 19 of opposite conductivity types along the thickness direction of the semiconductor substrate 11, and prevent the two from leaking along the thickness direction of the semiconductor substrate 11. Secondly, along the direction parallel to the second surface of the semiconductor substrate 11, an intrinsic semiconductor layer 20 is formed between the first doped semiconductor layer 17 and the second doped semiconductor layer 21, and the intrinsic semiconductor layer 20 is used to electrically isolate the first doped semiconductor layer 17 and the second doped semiconductor layer 21 along the direction parallel to the second surface, so as to prevent leakage between the two along the direction parallel to the second surface, further reduce the carrier recombination rate on the second surface side of the semiconductor substrate 11, and help improve the photoelectric conversion efficiency of the back contact battery. In addition, in the actual manufacturing process, due to the machine accuracy and / or for the purpose of preventing leakage, the width of the isolation region 16 located between the first region 14 and the adjacent second region 15 is relatively large. Based on this, the first doped semiconductor layer 17 includes not only a first doped portion 18 located on the first region 14, but also a second doped portion 19 located on the partial isolation region 16. At this time, when the back contact battery is in a working state, the first doped semiconductor layer 17 can not only collect and export the electrons or holes corresponding to the first region 14 in a timely manner, but also collect and export the electrons or holes corresponding to the partial isolation region 16 in a timely manner. Therefore, while preventing the first doped semiconductor layer 17 and the second doped semiconductor layer 21 from lateral leakage through the intrinsic semiconductor layer 20, it can also reduce the carrier recombination rate at the isolation region 16 with a larger width, thereby further improving the photoelectric conversion efficiency of the back contact battery.In addition, since the second doped portion 19 is located between the first doped portion 18 and the intrinsic semiconductor layer 20, when the doping concentration of impurities in the second doped portion 19 located on the partial isolation region 16 is less than the doping concentration of impurities in the first doped portion 18 located on the first region 14, the conductivity of the second doped portion 19 can be reduced, and the electrical breakdown penetrating the intrinsic semiconductor layer 20 can be reduced. At the same time, the diffusion of impurities in the second doped portion 19 into the intrinsic semiconductor layer 20 can be suppressed or even eliminated, thereby ensuring that the intrinsic semiconductor layer 20 has a good electrical isolation effect and ensuring that the back contact battery has good electrical performance.

[0072] In actual application, from the material aspect, the semiconductor substrate can be a substrate made of semiconductor materials such as a silicon substrate, a germanium silicon substrate or a germanium substrate. From the conductivity type aspect, the semiconductor substrate can be an N-type semiconductor substrate or a P-type semiconductor substrate. From the structural aspect, the first side of the semiconductor substrate corresponds to the light-facing side of the back contact battery, and the second side of the semiconductor substrate corresponds to the back-light-facing side of the back contact battery. Based on this, Figure 1 and Figure 2 As shown, the light-facing surface and the backlight surface of the semiconductor substrate 11 can both be polished surfaces, that is, relatively flat surfaces. Figure 3 As shown, the light-facing surface of the semiconductor substrate 11 and the surface of the semiconductor substrate 11 corresponding to the second region 15 are both velvet. In this case, the refractive index of light transmitted from the first surface and the surface of the second region 15 to the semiconductor substrate 11 can be increased, further improving the photoelectric conversion efficiency of the back contact battery. In addition, when the surface of the second region 15 is velvet, the backlight side of the second doped semiconductor layer 21 formed on the second region 15 also has corresponding undulating features. Compared with a plane, a surface with undulating features has a larger specific surface area. Therefore, when the backlight side of the second doped semiconductor layer 21 on the second region 15 has undulating features, it is beneficial to increase the contact area between the second doped semiconductor layer 21 and the electrode 36, reduce the contact resistance between the two, and further improve the electrical performance of the back contact battery.

[0073] In addition, if Figure 1As shown, the semiconductor substrate 11 has first regions 14 and second regions 15 arranged alternately and spaced apart, and an isolation region 16 located between each first region 14 and the second region 15 adjacent to itself. It should be understood that the boundaries between the first region 14, the second region 15 and the isolation region 16 are virtual boundaries. In addition, since the portion (first doped portion 18) of the first doped semiconductor layer 17 not covered by the insulating mask layer 22 is formed on the first region 14, the position, quantity and specification of the first region 14 on the backlight surface of the semiconductor substrate 11 affect the position, quantity and specification of the first doped portion 18 included in the first doped semiconductor layer 17 formed subsequently. Correspondingly, since the second doped semiconductor layer 21 is formed in the second region 15 and covers at least part of the second doped portion 19 and at least part of the intrinsic semiconductor layer 20, the position, quantity and specification of the second region 15 on the semiconductor substrate 11 affect the position, quantity and specification of the portion of the second doped semiconductor layer 21 formed subsequently that is in direct contact with the semiconductor substrate 11. As for the position of the isolation region 16, after the range of the first region 14 and the second region 15 is determined, the remaining area of ​​the second surface is the isolation region 16. Based on this, the specific position, quantity and specification of the first region 14, the second region 15 and the isolation region 16 on the semiconductor substrate 11 can be set according to the requirements of the position of the corresponding parts of the first doped semiconductor layer 17 and the second doped semiconductor layer 21 in the actual application scenario, and no specific limitation is made here.

[0074] For the above-mentioned first doped semiconductor layer, in terms of conductivity type, the first doped portion and the second doped portion included in the first doped semiconductor layer have the same conductivity type; wherein the conductivity type of the first doped semiconductor layer can be N-type or P-type; the specific conductivity type of the first doped semiconductor layer can be based on the actual application scenario and is not specifically limited here. In terms of materials, the first doped semiconductor layer can be a doped amorphous silicon layer or a doped crystalline silicon layer; wherein, when the first doped semiconductor layer is a doped crystalline silicon layer, the material of the first doped semiconductor layer can include microcrystalline silicon, single crystal silicon, polycrystalline silicon and nanocrystalline silicon, etc.

[0075] It is worth noting that compared with the doped amorphous silicon layer, the doped crystalline silicon layer has a higher carrier lateral transport characteristic. Figure 1As shown, part of the insulating mask layer 22 and part of the second doped semiconductor layer 21 cover the second doped portion 19. Therefore, when the first doped semiconductor layer 17 is a doped crystalline silicon layer, the second doped portion 19 has good lateral carrier transport characteristics, which is conducive to the second doped portion 19 to laterally transport more electrons or holes collected by itself to the first doped portion 18, and lead them out through the exposed first doped portion 18, further reducing the carrier recombination efficiency at the isolation region 16. At the same time, it can also make the first doped portion 18 have a higher carrier collection characteristic, reducing the carrier recombination efficiency at the first region 14.

[0076] As for the first doped portion and the second doped portion included in the first doped semiconductor layer, in terms of impurity doping concentration, the specific doping concentration of impurities in the first doped portion and the second doped portion can be determined according to the actual application scenario, as long as the doping concentration of impurities in the second doped portion is less than the doping concentration of impurities in the first doped portion.

[0077] Exemplarily, the doping concentration of the impurities in the second doping portion is greater than or equal to 1E18 cm -3 , and less than or equal to 5E20cm -3 For example, the doping concentration of the impurities in the second doping part can be 1E18 cm -3 、5E18 cm -3 、1E19 cm -3 、5E19cm -3 、1E20cm -3 or 5E20cm -3 In this case, the doping concentration of the impurities in the second doping part is within the above range, which can prevent the poor carrier collection ability of the second doping part due to the low doping concentration of the impurities in the second doping part, and further improve the degree of reducing the carrier recombination rate in the isolation region by the second doping part. In addition, it can also prevent the carriers in the second doping part from easily diffusing into the intrinsic semiconductor layer due to the high doping concentration of the impurities in the second doping part, ensuring that the intrinsic semiconductor layer has a good electrical isolation effect.

[0078] Exemplarily, the doping concentration of impurities in the second doping part gradually decreases along the direction from the second doping part to the intrinsic semiconductor layer. In this case, while the impurities in the second doping part have a certain doping concentration, and thus the second doping part has a certain carrier lateral collection capability, the part with the lowest impurity doping concentration in the second doping part can also be made to contact the intrinsic semiconductor layer, reducing the carrier concentration gradient at the contact point between the two, further inhibiting or even eliminating the diffusion of impurities in the second doping part into the intrinsic semiconductor layer, and ensuring that the intrinsic semiconductor layer has a good electrical isolation effect.

[0079] Among them, along the direction from the second doping part to the intrinsic semiconductor layer, the extent to which the doping concentration of impurities in the second doping part gradually decreases can be determined according to the actual application scenario, and is not specifically limited here.

[0080] Exemplarily, the doping concentration of the impurities in the first doping portion is 10 to 100 times the doping concentration of the impurities in the second doping portion. For example, when the doping concentration of the impurities in the second doping portion is 1E18 cm -3 When the doping concentration of the impurities in the first doping part is 1E19 cm -3 、3E19 cm -3 、5E19 cm -3 、7E19cm -3 or 1E20cm -3 In this case, the doping concentration of impurities in the first doping portion is relatively high, so that the first doping portion has a relatively high carrier collection capability. In addition, the manufacturing difficulty of obtaining the first doping portion with an excessively high doping concentration can be reduced.

[0081] In terms of size, since the second doped portion and the intrinsic semiconductor layer are located together on the isolation region, and the width of the intrinsic semiconductor layer along the direction from the first region to the second region will affect its own isolation effect, the width of the intrinsic semiconductor layer and the width of the isolation region can be determined according to the requirement of electrically isolating the first doped semiconductor layer and the second doped semiconductor layer along the direction parallel to the second surface in the actual application scenario through the intrinsic semiconductor layer, and then the width of the second doped portion can be determined according to the width of the intrinsic semiconductor layer and the width of the isolation region. The embodiment of the present invention does not specifically limit the width of the second doped portion, the intrinsic semiconductor layer and the isolation region.

[0082] Exemplarily, along the direction from the second doped portion to the intrinsic semiconductor layer, the width of the isolation region may be greater than or equal to 30 μm and less than or equal to 200 μm. For example, the width of the isolation region may be 30 μm, 50 μm, 80 μm, 100 μm, 150 μm or 200 μm, etc. In this case, the width of the isolation region is within the above range, which can prevent the difficulty of setting a second doped portion and an intrinsic semiconductor layer with a reasonable width within a smaller width range due to the smaller range of the isolation region, and ensure that the second doped portion and the intrinsic semiconductor layer have the functions described above. In addition, it can also prevent the first doped semiconductor layer and / or the second doped semiconductor layer from having a smaller width due to the larger width of the intrinsic semiconductor layer, thereby ensuring that the first doped semiconductor layer and the second doped semiconductor layer can collect and export the carriers corresponding to the first region and the second region in a timely manner, and further reduce the carrier recombination rate on one side of the second surface.

[0083] Exemplarily, along the direction from the second doped portion to the intrinsic semiconductor layer, the width of the intrinsic semiconductor layer may be greater than or equal to 6 μm and less than or equal to 120 μm. For example, the width of the intrinsic semiconductor layer may be 6 μm, 10 μm, 20 μm, 50 μm, 80 μm, 100 μm, 110 μm or 120 μm, etc. In this case, the width of the intrinsic semiconductor layer is within the above range, which can prevent the electrical isolation effect of the intrinsic semiconductor layer from being affected by the small width of the intrinsic semiconductor layer in the direction parallel to the second direction, and ensure that the first doped semiconductor layer and the second doped semiconductor layer can be prevented from leaking electricity in the direction parallel to the second surface through the intrinsic semiconductor layer. In addition, it can also prevent the second doped portion from having a small width due to the large width of the intrinsic semiconductor layer, which leads to a low carrier collection capacity, and further improve the degree of reducing the carrier recombination rate at the isolation region by the second doped portion.

[0084] Exemplarily, along the direction from the second doping part to the intrinsic semiconductor layer, the ratio of the width of the second doping part to the width of the isolation region may be greater than or equal to 0.8 and less than 1. For example, the ratio of the width of the second doping part to the width of the isolation region may be 0.8, 0.82, 0.84, 0.86, 0.88, 0.9 or 0.92, etc. In this case, when the ratio of the width of the second doping part to the width of the isolation region along the direction from the second doping part to the intrinsic semiconductor layer is within the above range, the width of the second doping part is greater than the width of the intrinsic semiconductor layer, which can prevent the extent of reducing the carrier recombination rate at the isolation region by the second doping part due to the small width of the second doping part from being obvious, thereby ensuring that the back contact battery has a higher photoelectric conversion efficiency. In addition, since the second doping part and the intrinsic semiconductor layer are located together on the isolation region, when the width of the isolation region is a constant value, the width of the second doping part is inversely proportional to the width of the intrinsic semiconductor layer. Moreover, within a certain range, the electrical isolation effect of the intrinsic semiconductor layer in the direction parallel to the second surface is proportional to its own width. Based on this, when the ratio is within the above range, it can also prevent the electrical isolation effect of the intrinsic semiconductor layer from being poor due to the small width of the second doped part, and ensure that the first doped semiconductor layer and the second doped semiconductor layer can be prevented from leaking electricity along the direction parallel to the second surface through the intrinsic semiconductor layer.

[0085] As for the specific width of the second doping portion, it can be determined according to the width of the isolation region and the ratio of the width of the second doping portion to the width of the isolation region. For example, when the width of the isolation region is greater than or equal to 30 μm and less than or equal to 200 μm, and the ratio of the width of the second doping portion to the width of the isolation region is equal to 0.8, the width of the second doping portion can be 24 μm, 50 μm, 80 μm, 100 μm, 150 μm or 160 μm, etc.

[0086] As for the above-mentioned intrinsic semiconductor layer, the integral formation of the intrinsic semiconductor layer and the first doped semiconductor layer means that the intrinsic semiconductor layer and the first doped semiconductor layer are based on the same intrinsic semiconductor material layer and are formed at the same time. Based on this, the thickness of the intrinsic semiconductor layer is equal to the thickness of the first doped semiconductor layer, and the material of the intrinsic semiconductor layer can refer to the material of the first doped semiconductor layer. For example: when the material of the first doped semiconductor layer is doped polysilicon, the material of the intrinsic semiconductor layer is intrinsic polysilicon.

[0087] For the above-mentioned second doped semiconductor layer, in terms of conductivity type, when the conductivity type of the first doped semiconductor layer is N-type, the conductivity type of the second doped semiconductor layer is P-type. When the conductivity type of the first doped semiconductor layer is P-type, the conductivity type of the second doped semiconductor layer is N-type. In terms of materials, when the first doped semiconductor layer is a doped amorphous silicon layer, the second doped semiconductor layer is a doped crystalline silicon layer; the specific material of the doped crystalline silicon layer can refer to the above. When the first doped semiconductor layer is a doped crystalline silicon layer, the second doped semiconductor layer can be a doped amorphous silicon layer or a doped crystalline silicon layer. The specific material of the second doped semiconductor layer can be determined according to the material of the first doped semiconductor layer and the actual application scenario, and is not specifically limited here.

[0088] It should be noted that when the material of one of the first doped semiconductor layer and the second doped semiconductor layer is doped amorphous silicon and / or doped microcrystalline silicon, Figure 2 and Figure 3 As shown, the back contact cell may further include a transparent conductive layer 35 covering the first doped portion 18 and the second doped semiconductor layer 21 to improve the carrier collection rate. In addition, the transparent conductive layer 35 is formed with a penetrating insulating groove corresponding to the isolation region 16 to prevent the first doped semiconductor layer 17 and the second doped semiconductor layer 21 from leaking electricity through the transparent conductive layer 35. Specifically, the insulating groove may only penetrate the transparent conductive layer 35, or may penetrate the transparent conductive layer 35 and the second doped semiconductor layer 21. In addition, the embodiment of the present invention does not specifically limit the material and thickness of the transparent conductive layer 35.

[0089] As for the formation range of the second doped semiconductor layer, it can be determined according to the specific structure of the back contact battery. Figure 1 As shown, in the case where the back contact cell does not include a transparent conductive layer, the second doped semiconductor layer 21 may cover the second region 15, the entire intrinsic semiconductor layer 20 and the entire second doped portion 19. Figure 2 and Figure 3 As shown, when the back contact battery includes the above-mentioned transparent conductive layer 35 and the insulating groove penetrates the transparent conductive layer 35 and the second doped semiconductor layer 21, the second doped semiconductor layer 21 covers the second region 15, part of the intrinsic semiconductor layer 20 and part of the second doped part 19.

[0090] For the above-mentioned insulating mask layer, the material of the above-mentioned insulating mask layer can be any insulating material with a masking function, as long as it can be applied to the back contact battery provided in the embodiment of the present invention. For example: the material of the insulating mask layer can be silicon nitride, silicon oxynitride or silicon oxycarbide. As for the thickness of the insulating mask layer, it can also be determined according to actual needs. For example: the thickness of the insulating mask layer can be greater than or equal to 10nm and less than or equal to 200nm.

[0091] As a possible implementation, Figure 3 As shown, the back contact cell may further include a first passivation layer 23, and the first passivation layer 23 is located between the semiconductor substrate 11 and the first doped semiconductor layer 17 and the intrinsic semiconductor layer 20. In this case, the selective contact structure composed of the first passivation layer 23 and the first doped semiconductor layer 17 has an excellent interface passivation effect, and can achieve selective collection of carriers, reduce the carrier recombination rate of the first region 14 and the partial isolation region 16 of the backlight surface of the semiconductor substrate 11, and further improve the photoelectric conversion efficiency of the back contact cell.

[0092] Specifically, the material of the above-mentioned first passivation layer can be determined according to the requirements for the type of selective contact structure composed of the first passivation layer and the first doped semiconductor layer in the actual application scenario, and is not specifically limited here. For example: when the actual application scenario requires that the selective contact structure composed of the first passivation layer and the first doped semiconductor layer is a tunneling passivation contact structure, the first passivation layer is a tunneling passivation layer (the material of the tunneling passivation layer can be silicon oxide, titanium oxide or aluminum oxide and other materials), and the first doped semiconductor layer is a doped polycrystalline silicon layer. For another example: when the actual application scenario requires that the selective contact structure composed of the first passivation layer and the first doped semiconductor layer is a heterogeneous contact structure, the material of the first passivation layer includes intrinsic amorphous silicon and / or intrinsic microcrystalline silicon, and the material of the first doped semiconductor layer is doped amorphous silicon and / or doped microcrystalline silicon.

[0093] Preferably, when the back contact battery further includes a first passivation layer, and the first passivation layer is a tunneling passivation layer, the material of the first doped semiconductor layer is doped polysilicon, and the conductivity type is N-type. In this case, because the contact resistance between the P-type doped polysilicon layer and the electrode is relatively high, and the field passivation effect is relatively poor, when the first passivation layer included in the back contact battery is a tunneling passivation layer, and the first doped semiconductor layer is a doped polysilicon layer, when the conductivity type of the first doped semiconductor layer is N-type, the field passivation effect of the first doped semiconductor layer can be further improved, and at the same time, the contact resistance between the first doped portion and the electrode can be reduced, which is beneficial to improving the electrical performance of the back contact battery. In addition, if Figures 5 to 15As shown, the intrinsic semiconductor layer 20 is integrally formed with the first doped semiconductor layer 17, and the second doped semiconductor layer 21 is also located on at least part of the intrinsic semiconductor layer 20 and at least part of the second doped portion 19 included in the first doped semiconductor layer 17, so the formation order of the first doped semiconductor layer 17 is before the formation order of the second doped semiconductor layer 21. In addition, compared with amorphous silicon, polycrystalline silicon has better heat resistance. Based on this, when the back contact battery also includes a first passivation layer 23, and the first passivation layer 23 is a tunneling passivation layer and the material of the first doped semiconductor layer 17 is doped polycrystalline silicon, if a laser etching process is used to remove the portion of the material layer corresponding to the first region 14 for manufacturing the second doped semiconductor layer 21, the first doped semiconductor whose material is doped polycrystalline silicon is less affected by the high temperature laser or even not affected by the high temperature laser, which is conducive to improving the yield of the back contact battery. Furthermore, in the actual manufacturing process, the manufacturing cost of the heterogeneous contact structure is higher than that of the tunnel passivation contact structure, and the tunnel passivation contact structure can be realized by a variety of processes such as low-pressure chemical vapor deposition, plasma chemical vapor deposition, physical chemical vapor deposition or plasma enhanced atomic layer deposition, which is more compatible with the back contact battery process, while the heterogeneous contact structure needs to be manufactured by a plate-type plasma chemical vapor deposition equipment that supports a lower formation temperature. Based on this, when the first passivation layer of the back contact battery is a tunnel passivation layer and the material of the first doped semiconductor layer is doped polysilicon, it is beneficial to reduce the manufacturing cost, reduce the investment in the plate-type plasma chemical vapor deposition equipment, and save the production site area.

[0094] Specifically, the embodiment of the present invention does not specifically limit the thickness of the tunnel passivation layer and the first doped semiconductor layer. For example, the thickness of the tunnel passivation layer may be greater than or equal to 1 nm and less than or equal to 4 nm. The thickness of the first doped semiconductor layer may be greater than or equal to 30 nm and less than or equal to 250 nm.

[0095] As a possible implementation, Figure 3 As shown, the above-mentioned back contact battery can also include a second passivation layer 24, and the second passivation layer 24 is located between the second doped semiconductor layer 21 and the semiconductor substrate 11, the intrinsic semiconductor layer 20, and the second doped portion 19 respectively. In this case, the selective contact structure composed of the second passivation layer 24 and the second doped semiconductor layer 21 can realize the selective collection of carriers and reduce the carrier recombination rate of the second region 15 of the backlight surface of the semiconductor substrate 11. At the same time, the second passivation layer 24 and the intrinsic semiconductor layer 20 are also located between the portion of the second doped semiconductor layer 21 located on the second region 15 and the second doped portion 19. At this time, both can suppress the carrier recombination rate at the interface between the second doped semiconductor layer 21 and the first doped semiconductor layer 17 corresponding to the isolation region 16, further improving the photoelectric conversion efficiency of the back contact battery.

[0096] Specifically, the material of the second passivation layer can be determined according to the requirements for the type of selective contact structure composed of the second passivation layer and the second doped semiconductor layer in the actual application scenario, and is not specifically limited here. For example: when the actual application scenario requires that the selective contact structure composed of the second passivation layer and the second doped semiconductor layer is a tunneling passivation contact structure, the second passivation layer is a tunneling passivation layer, and the second doped semiconductor layer is a doped polycrystalline silicon layer. For another example: when the actual application scenario requires that the selective contact structure composed of the second passivation layer and the second doped semiconductor layer is a heterogeneous contact structure, the material of the second passivation layer includes intrinsic amorphous silicon and / or intrinsic microcrystalline silicon, and the material of the second doped semiconductor layer is doped amorphous silicon and / or doped microcrystalline silicon.

[0097] Preferably, when the back contact battery further includes a second passivation layer, and the material of the second passivation layer includes intrinsic amorphous silicon and / or intrinsic microcrystalline silicon, the material of the second doped semiconductor layer is doped amorphous silicon and / or doped microcrystalline silicon, and the conductivity type is P type.

[0098] Specifically, the embodiment of the present invention does not specifically limit the thickness of the above-mentioned passivation layer and the second doped semiconductor layer. For example, when the material of the second passivation layer includes intrinsic amorphous silicon and / or intrinsic microcrystalline silicon, the thickness of the second passivation layer can be greater than or equal to 2nm and less than or equal to 10nm. The thickness of the second doped semiconductor layer can be greater than or equal to 5nm and less than or equal to 30nm.

[0099] When the above technical solution is adopted, as mentioned above, compared with the P-type doped amorphous silicon and / or doped microcrystalline silicon layer, the contact resistance between the P-type doped polycrystalline silicon layer and the electrode is higher and the field passivation effect is poor. Therefore, in the above case, the conductivity type of the second doped semiconductor layer is set to P-type instead of setting the conductivity type of the tunneling passivation contact structure to P-type. This can further improve the field passivation effect of the first doped semiconductor layer and reduce the contact resistance between the first doped portion and the electrode, which is beneficial to improving the electrical performance of the back contact battery.

[0100] In some cases, such as Figure 2 and Figure 3 As shown, the back contact cell provided by the embodiment of the present invention may further include an electrode 36 electrically coupled to the first doped portion 18 and the second doped semiconductor layer 21, respectively, to conduct carriers of corresponding conductive types. Specifically, the material of the electrode 36 may be a conductive material such as silver, aluminum, copper, nickel or titanium.

[0101] In some cases, such as Figure 3As shown, the back contact cell provided by the embodiment of the present invention may also include an interface passivation layer 37 and an anti-reflection layer 38 stacked in sequence on the first surface to reduce the carrier recombination rate on one side of the first surface and increase the refractive index of the first surface to light. Specifically, the material and thickness of the interface passivation layer 37 and the anti-reflection layer 38 can be determined according to the actual application scenario and are not specifically limited here.

[0102] For example, the material of the interface passivation layer may be intrinsic amorphous silicon, and the material of the anti-reflection layer may be silicon nitride.

[0103] In a second aspect, an embodiment of the present invention provides a method for manufacturing a back-contact battery. Figures 4 to 17 The manufacturing process is described by a cross-sectional view of the operation shown. Specifically, the manufacturing method of the back contact battery includes the following manufacturing steps:

[0104] First, if Figure 4 As shown, a semiconductor substrate 11 is provided. The semiconductor substrate 11 has an opposite first surface 12 and a second surface 13. The second surface 13 has first regions 14 and second regions 15 alternately distributed, and an isolation region 16 between each first region 14 and the second region 15 adjacent to it.

[0105] Specifically, information such as the material and conductivity type of the semiconductor substrate can be found in the previous text and will not be repeated here.

[0106] Next, if Figure 5 As shown, an integrally formed intrinsic semiconductor material layer 25 is formed on the second surface.

[0107] In the actual manufacturing process, the intrinsic semiconductor material layer is used to manufacture the first doped semiconductor layer and the intrinsic semiconductor layer mentioned above. Therefore, the material, thickness and formation process of the intrinsic semiconductor material layer can be determined according to the material and thickness of the first doped semiconductor layer and the intrinsic semiconductor layer.

[0108] For example, when the material of the first doped semiconductor layer and the intrinsic semiconductor layer is polycrystalline silicon, they can be formed by low-pressure chemical vapor deposition, plasma chemical vapor deposition, plasma enhanced atomic layer deposition, etc. For another example, when the material of the first doped semiconductor layer and the intrinsic microcrystalline silicon layer is amorphous silicon, they can be formed by plasma chemical vapor deposition, etc.

[0109] In addition, when the manufactured back contact cell further includes a first passivation layer located between the semiconductor substrate and the first doped semiconductor layer and the intrinsic semiconductor layer, as Figure 5As shown, after providing a semiconductor substrate 11 and before forming a whole layer of intrinsic semiconductor material layer 25 on the second surface, the method for manufacturing a back contact battery further includes the step of forming a whole layer of first passivation material layer 33 on the second surface.

[0110] Specifically, the formation process of the first passivation material layer can be determined according to the material type of the first passivation material layer. For example, when the material of the first passivation material layer includes silicon oxide and the semiconductor substrate is a silicon substrate, the first passivation material layer can be formed by a high-temperature reaction of oxygen and the semiconductor substrate, or by a wet chemical method (such as a reaction of the semiconductor substrate with ozone or an oxidation reaction of the semiconductor substrate with nitric acid).

[0111] Then, if Figure 6 and Figure 7 As shown, a first mask layer 26 is formed; the first mask layer 26 covers the portion of the intrinsic semiconductor material layer 25 corresponding to the second region 15 and the isolation region 16. Under the masking action of the first mask layer 26, the portion of the intrinsic semiconductor material layer 25 located on the first region 14 is selectively doped, so that the portion of the intrinsic semiconductor material layer 25 located on the first region 14 and part of the isolation region 16 forms the first doped semiconductor layer 17, and the portion of the intrinsic semiconductor material layer 25 located on the remaining isolation region 16 forms the intrinsic semiconductor layer 20. The portion of the first doped semiconductor layer 17 located on the first region 14 is the first doped portion 18, and the remaining portion is the second doped portion 19, and the doping concentration of impurities in the second doped portion 19 is less than the doping concentration of impurities in the first doped semiconductor layer 17.

[0112] In the actual manufacturing process, Figure 5 As shown, after forming the intrinsic semiconductor material layer 25, a process such as chemical vapor deposition can be used to form a first mask material layer that is entirely disposed on the intrinsic semiconductor material layer 25. Then, as shown in FIG. Figure 6 As shown, laser etching or other processes can be used to remove the portion of the first mask material layer corresponding to the first region 14 to form a first mask layer 26. The material of the first mask layer 26 can be any material having a masking function, as long as it can be applied to the manufacturing method of the back contact battery provided in the embodiment of the present invention. For example, the material of the first mask layer 26 can be silicon oxide or silicon nitride. Then, as Figure 7 As shown, diffusion, ion implantation or doping source coating and pushing processes may be used to selectively dope the portion of the intrinsic semiconductor material layer 25 located on the first region 14 to form the first doped semiconductor layer 17 and the intrinsic semiconductor layer 20 .

[0113] It can be understood that, since the second doped portion included in the first doped semiconductor layer is located below the first mask layer, and the impurities are transferred from the first doped portion to the second doped portion under the action of diffusion, when the width of the second doped portion is small, it can be directly formed by the above-mentioned selective doping. When the width of the second doped portion is greater than or equal to 6 μm and less than or equal to 120 μm along the direction from the second doped portion to the intrinsic semiconductor layer, after the portion of the intrinsic semiconductor material layer located on the first region is selectively doped and before subsequent operations are performed, such as Figure 8 As shown, the first doped semiconductor layer 17 and the intrinsic semiconductor layer 20 are annealed to make the width of the second doped portion 19 reach the target width. In this case, the second doped portion 19 is formed by diffusion when the portion of the intrinsic semiconductor material layer 25 located on the first region 14 is selectively doped under the masking action of the first mask layer 26. Based on this, along the direction from the second doped portion 19 to the intrinsic semiconductor layer 20, when the width of the second doped portion 19 is greater than or equal to 6μm and less than or equal to 120μm, the width of the second doped portion 19 is relatively large. At this time, the first doped semiconductor layer 17 and the intrinsic semiconductor layer 20 after selective doping are annealed, so that the impurities in the second doped portion 19, or the first doped portion 18 and the second doped portion 19 diffuse longer distances in the direction parallel to the second surface after being heated, thereby obtaining a second doped portion 19 whose actual width reaches the target width.

[0114] For example: when the width of the second doped portion is 6μm, 10μm, 20μm, 50μm, 80μm, 100μm, 110μm or 120μm along the direction from the second doped portion to the intrinsic semiconductor layer, the above-mentioned annealing treatment can be performed on the first doped semiconductor layer and the intrinsic semiconductor layer after selectively doping the portion of the intrinsic semiconductor material layer located on the first region and before performing subsequent operations.

[0115] The processing conditions of the annealing treatment may be determined according to the specific width of the second doping portion and the actual application scenario, and are not specifically limited here.

[0116] Then, if Fig. 9 As shown, the first mask layer is removed. Specifically, the process and conditions used to remove the first mask layer can be determined according to the material of the first mask layer and the actual application scenario, and are not specifically limited here. For example, when the material of the first mask layer is silicon oxide, a wet etching process can be used, and the first mask layer can be removed by a hydrogen fluoride solution.

[0117] Then, if Fig.11 and Fig.12As shown, at least an insulating mask layer 22 covering the first doped semiconductor layer 17 and the intrinsic semiconductor layer 20 is formed; and at least under the masking effect of the insulating mask layer 22, the portion of the intrinsic semiconductor material layer 25 remaining on the second region 15 is selectively removed.

[0118] Specifically, the material and thickness of the insulating mask layer may be referred to above and will not be described in detail here.

[0119] In the actual manufacturing process, a process such as chemical vapor deposition can be used to form only a whole insulating mask material layer on the first doped semiconductor layer, the intrinsic semiconductor layer, and the portion of the intrinsic semiconductor material layer remaining on the second region. Then, a process such as laser etching can be used to remove the portion of the insulating mask material layer located above the second region to form an insulating mask layer. Then, a process such as laser etching can be used to selectively remove the portion of the intrinsic semiconductor material layer remaining on the second region only under the masking effect of the insulating mask layer.

[0120] Alternatively, after removing the first mask layer and before forming the second doped semiconductor layer 21 on the insulating mask layer and the second region, the method for manufacturing a back contact cell may include the following steps: Fig.10 As shown, a mask material layer 27 is formed on the first doped semiconductor layer 17, the intrinsic semiconductor layer 20 and the remaining portion of the intrinsic semiconductor material layer 25 on the second region 15. Then, as shown in FIG. Fig.11 As shown in FIG. 1 , the portion of the mask material layer located above the second region 15 is removed, and the remaining portion of the mask material layer forms a second mask layer 28. Next, as shown in FIG. Fig.12 As shown, under the masking effect of the second mask layer 28, the portion of the intrinsic semiconductor material layer 25 remaining on the second region 15 is selectively removed. Fig.13 As shown, under the masking effect of at least a portion of the second mask layer, the first surface of the semiconductor substrate 11 and the surface of the second region 15 corresponding to the semiconductor substrate 11 are subjected to texturing treatment. After the texturing treatment, at least a portion of the second mask layer forms an insulating mask layer 22. In this case, the presence of the above-mentioned second mask layer 28 can prevent the selective removal of the portion of the intrinsic semiconductor material layer 25 remaining on the second region 15 from being affected by the etching operation and the subsequent texturing treatment. At the same time, texturing the surface of the first surface of the semiconductor substrate 11 and the second region 15 can increase the refractive index of light on the surface of the first surface and the second region 15, thereby improving the photoelectric conversion efficiency of the manufactured back contact battery.

[0121] Specifically, the embodiment of the present invention does not specifically limit the manufacturing process of the mask material layer and the material of the second mask layer formed based on the mask material layer, as long as the insulating mask layer can be manufactured through the second mask layer and has a masking effect during the texturing process. In addition, laser etching and other processes can be used to sequentially remove the portion of the mask material layer located above the second area and the portion of the intrinsic semiconductor material layer remaining on the second area. In this case, since the laser etching process has a high etching accuracy, the laser etching process is used to sequentially remove the portion of the mask material layer located above the second area and the portion of the intrinsic semiconductor material layer remaining on the second area, which can improve the yield of the manufactured back contact battery.

[0122] In actual application, the second mask layer can be made of the same material as the insulating mask layer. At this time, the remaining part of the second mask layer after the texturing process forms the insulating mask layer.

[0123] Or, if Fig.12 As shown, the second mask layer 28 may also include a first silicon nitride layer 29 and a second silicon nitride layer 30 spaced apart in the thickness direction of the semiconductor substrate 11, and an intrinsic silicon layer 31 between the first silicon nitride layer 29 and the second silicon nitride layer 30. In the above case, after the first surface of the semiconductor substrate 11 and the surface of the semiconductor substrate 11 corresponding to the second region 15 are textured, and before the second doped semiconductor layer is formed on the insulating mask layer and the second region, the method for manufacturing the back contact battery further includes the steps of: removing the second silicon nitride layer 30 and the intrinsic silicon layer 31 in sequence.

[0124] In the case of adopting the above technical solution, when other factors are the same, compared with the second mask layer being a single-layer film, when the second mask layer includes the first silicon nitride layer, the intrinsic silicon layer and the second silicon nitride layer, the mask characteristics of the second mask layer can be improved to ensure that the first doped semiconductor layer and the intrinsic semiconductor layer located below it can be protected by the second mask layer. In addition, when a laser etching process is used to remove the portion of the mask material layer located above the second region and the portion of the intrinsic semiconductor material layer remaining on the second region 15, because the laser spot is a Gaussian spot, the energy at the center is higher and the energy at the edge is lower, so in order to completely remove the portion of the mask material layer located above the second region and the portion of the intrinsic semiconductor material layer remaining on the second region, the edge of the laser spot pattern may cover part of the second mask layer. The film properties of the silicon nitride material change after being heated, thereby enhancing its corrosion resistance. Based on this, in the subsequent texturing process, when the texturing solution corrodes to the boundary between the second region and the isolation region, it is easy to corrode the surface of the semiconductor substrate and the intrinsic semiconductor layer corresponding to the boundary between the isolation region and the second region. When the second mask layer is only a single-layer silicon nitride layer, the edge of the second mask layer has strong corrosion resistance, so an air gap is formed between this part of the isolation region and the edge of the second mask layer. Because the size of the air gap is small, the second doped semiconductor layer formed subsequently is difficult to fill in the air gap, and the carrier recombination rate of the area below the air gap is large. In the above case, when the second mask layer includes a first silicon nitride layer, an intrinsic silicon layer, and a second silicon nitride layer, even if the second silicon nitride layer located on the outside is affected by the heat of the laser spot so that its edge is heated and the corrosion resistance of its edge is enhanced, it can be removed by appropriately extending the etching time. Although the first silicon nitride layer located inside also protrudes on the velvet area after the texturing treatment, its edge has not been irradiated with laser, which causes changes in the film properties. In addition, after etching away the second silicon nitride layer, the etching time is appropriately extended to completely remove the intrinsic silicon layer covering the first silicon nitride layer, and the portion of the first silicon nitride layer located on the velvet area is also removed, so that the above-mentioned air gap will not be formed, thereby reducing the carrier recombination rate at the junction of the isolation area and the second area, and further improving the photoelectric conversion efficiency of the back contact battery.

[0125] In the actual manufacturing process, it can be seen from the above content that the insulating mask layer is the portion of the first silicon nitride layer remaining on the isolation area, so the thickness of the first silicon nitride layer can refer to the thickness of the insulating mask layer. The intrinsic silicon layer can be an intrinsic amorphous silicon layer or an intrinsic crystalline silicon layer. The crystalline state of the intrinsic amorphous silicon layer can be microcrystalline, single crystal, polycrystalline or nanocrystalline, etc. As for the thickness of the intrinsic silicon layer and the second silicon nitride layer, it can be determined according to the actual application scenario, and no specific limitation is made here.

[0126] Exemplarily, the thickness of the second silicon nitride layer may be greater than or equal to 10 nm and less than or equal to 200 nm. For example, the thickness of the second silicon nitride layer may be 10 nm, 30 nm, 60 nm, 100 nm, 150 nm or 200 nm.

[0127] Exemplarily, the thickness of the intrinsic silicon layer may be greater than or equal to 10 nm and less than or equal to 100 nm. For example, the thickness of the intrinsic silicon layer may be 10 nm, 20 nm, 40 nm, 60 nm, 80 nm or 100 nm.

[0128] Secondly, when the second mask layer includes a first silicon nitride layer, an intrinsic silicon layer, and a second silicon nitride layer, the intrinsic silicon layer can be formed by a process such as low-pressure chemical vapor deposition or plasma enhanced chemical vapor deposition. The first silicon nitride layer and the second silicon nitride layer can be formed by a process such as plasma enhanced chemical vapor deposition. As for the etchant for removing the intrinsic silicon layer and the second silicon nitride layer, it can be determined according to the actual application scenario. For example, it can be a hydrogen fluoride solution.

[0129] It should be noted that if the manufactured back-contact battery includes a first passivation layer located between the semiconductor substrate and the first doped semiconductor layer and the intrinsic semiconductor layer, and the first passivation material layer is formed as a whole layer before the intrinsic semiconductor material layer is formed, then after selectively removing the portion of the intrinsic semiconductor material layer remaining on the second region, before forming the second doped semiconductor layer on the second region and the insulating mask layer, the manufacturing method of the back-contact battery further includes the steps of: Fig.12 As shown, the portion of the first passivation material layer located on the second region 15 is selectively removed, so that the remaining portion of the first passivation material layer forms the first passivation layer 23. Specifically, the selective removal process may be implemented by laser etching or other processes.

[0130] Then, if Fig.14 and Fig.15 As shown, a second doped semiconductor layer 21 is formed on the insulating mask layer 22 and the second region 15. The second doped semiconductor layer 21 and the first doped semiconductor layer 17 have opposite conductivity types, and at least one of the second doped semiconductor layer 21 and the first doped semiconductor layer 17 is a doped crystalline silicon layer. The intrinsic semiconductor layer 20 is used to electrically isolate the second doped semiconductor layer 21 from the first doped semiconductor layer 17.

[0131] In actual application, a plasma chemical vapor deposition process or the like can be used to form a second doped semiconductor material layer disposed entirely on the second region and the second mask layer. Next, a laser etching process or the like can be used to selectively remove a portion of the second doped semiconductor material layer corresponding to the first region, so that the remaining portion of the second doped semiconductor material layer forms a second doped semiconductor layer.

[0132] It should be noted that, when the manufactured back-contact battery also includes the second passivation layer mentioned above, after selectively removing the portion of the intrinsic semiconductor material layer remaining on the second region, and before forming the second doped semiconductor layer on the insulating mask layer and the second region, the manufacturing method of the back-contact battery also includes: forming a second passivation layer on the insulating mask layer.

[0133] Specifically, before forming the second doped semiconductor material layer, the second passivation layer may be formed by using a corresponding deposition process and etching. Fig.14 As shown, a second passivation material layer 34 may be formed as a whole layer before forming the second doped semiconductor material layer 32. Then, as shown in FIG. Fig.15 As shown, after forming the second doped semiconductor material layer 32, laser etching or other processes are used to sequentially remove the second doped semiconductor layer 21 and the second passivation material layer 34 corresponding to the first region 14. At this time, the manufacturing process of the back contact battery can be simplified and the manufacturing efficiency can be improved.

[0134] Then, if Fig.15 As shown, the portion of the insulating mask layer 22 located on the first doped portion 18 is removed. Specifically, the portion of the insulating mask layer 22 located on the first doped portion 18 may be removed by a process such as wet etching.

[0135] In some cases, such as Fig.16 As shown, after removing the portion of the insulating mask layer 22 located on the first doped portion 18, a chemical vapor deposition process or the like can be used to form an interface passivation layer 37 and an anti-reflection layer 38 on the first surface. Specifically, the material and thickness of the interface passivation layer 37 and the anti-reflection layer 38 can be referred to above and will not be described again here.

[0136] In some cases, after removing the portion of the insulating mask layer located on the first doped portion, a process such as physical vapor deposition can be used to form a transparent conductive layer disposed entirely on the first doped portion and the second doped semiconductor layer. Fig.17 As shown, laser etching or other processes are used to form an insulating groove that at least penetrates the transparent conductive layer 35. Then, screen printing, inkjet printing or laser transfer can be used to form electrodes 36 that are electrically coupled to the first doped portion 18 and the second doped semiconductor layer 21. The material and thickness of the transparent conductive layer 35 and the material of the electrode 36 can be referred to above and will not be repeated here.

[0137] The beneficial effects of the second aspect and its various implementations in the embodiments of the present invention can be analyzed with reference to the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0138] The present invention also provides three embodiments to illustrate the manufacturing method and performance of the back contact battery provided by the embodiments of the present invention.

[0139] Embodiment 1:

[0140] The first step is to put the silicon wafer into a tank-type polishing and cleaning machine for polishing and cleaning to remove the cutting damage layer on the first and second sides of the silicon wafer, and to control the polishing morphology of both sides by controlling the polishing and cleaning temperature, time and liquid concentration.

[0141] The second step is to use a chemical vapor deposition process to sequentially form a first passivation material layer (made of silicon oxide), an intrinsic semiconductor material layer (made of polycrystalline silicon) and a first mask material layer (made of silicon oxide) on the second side of the silicon wafer. Specifically, the first passivation material layer and the intrinsic semiconductor material layer are formed using a low-pressure chemical vapor deposition furnace (LPCVD). The thickness of the first passivation material layer is 1.4 nm, and the thickness of the intrinsic semiconductor material layer is 50 nm. The first mask material layer is grown by LPCVD, and its thickness is 40 nm.

[0142] Step 3: Use a laser etching process to selectively remove the first mask material layer corresponding to the first area, and the remaining part of the first mask material layer forms a first mask layer. The laser uses a 355nm picosecond laser.

[0143] In the fourth step, under the masking effect of the first mask layer, the portion of the intrinsic semiconductor material layer corresponding to the first area is selectively doped with phosphorus by high-temperature diffusion, so that the portion of the intrinsic semiconductor material layer corresponding to the first area forms a first doped portion, and the portion of the intrinsic semiconductor material located in the partial isolation area and close to the first doped portion forms a second doped portion.

[0144] The fifth step is to use a wet etching process and remove the phosphosilicate glass layer formed on the first doping part after phosphorus diffusion through an HF solution, and remove the first mask layer at the same time.

[0145] Step 6: Using a chemical vapor deposition process, a first silicon nitride material layer, an intrinsic amorphous silicon material layer, and a second silicon nitride material layer are stacked in sequence. Among them, the intrinsic non-polycrystalline silicon material layer is formed by a plasma chemical vapor deposition process, and its thickness is 20nm. The first silicon nitride material layer and the second silicon nitride material layer are formed by a plasma chemical vapor deposition process, and the thickness of the first silicon nitride material layer and the second silicon nitride material layer are both 60nm.

[0146] Step 7: Use a laser etching process to selectively remove the stacked first silicon nitride material layer, the intrinsic amorphous silicon material layer, and the second silicon nitride material layer corresponding to the second region to form a second mask layer. Under the masking effect of the second mask layer, use a laser etching process to selectively remove the remaining portion of the intrinsic semiconductor material layer on the second region. The laser uses a 532nm nanosecond laser.

[0147] Step 8: Under the masking effect of at least part of the second mask layer, the surfaces of the first surface and the second area of ​​the second surface of the silicon wafer are textured. The first function of the texture treatment is to remove the damaged layer on the surface of the second area after the laser treatment and perform interface cleaning treatment; the second function is to form a texture surface on the surface of the first surface and the second area. Next, the intrinsic crystalline silicon layer and the second silicon nitride layer included in the second mask layer are removed using a hydrogen fluoride solution.

[0148] Step 9: Using chemical vapor deposition process, a whole layer of intrinsic amorphous silicon layer and P-type amorphous silicon layer is formed, wherein the thickness of the intrinsic amorphous silicon layer is 5 nm, and the thickness of the P-type amorphous silicon layer is 15 nm.

[0149] Step 10: Use a laser etching process to remove the corresponding intrinsic amorphous silicon layer and the P-type amorphous silicon layer on the first region, wherein the laser is a 532nm picosecond laser.

[0150] Step 11: Use a wet etching process to remove the first silicon nitride layer in the second mask layer corresponding to the first region. The main functional liquid used in the wet etching process is HF solution.

[0151] Step 12: deposit an interface passivation layer of intrinsic amorphous silicon material and an anti-reflection layer of silicon nitride material on the first surface.

[0152] Step 13: deposit a transparent conductive layer (TCO) on the first doped part and the second doped semiconductor layer, using an ITO film layer.

[0153] Step 14: Use laser etching technology to form an insulating groove that at least penetrates the transparent conductive layer, so that the two polarity regions can achieve complete structural insulation. The laser uses a 355nm picosecond laser.

[0154] Step 15: Print low-temperature silver paste on the TCO of both electrodes by screen printing, and then anneal at 200°C for 30 minutes.

[0155] Example 2

[0156] The operation steps of Example 2 are the same as those of Example 1 except for the second step. The second step of Example 2 changes the deposition method and thickness of the first mask material layer to reduce the preparation time of the first mask material layer. Specifically, the first mask material layer is formed by a plasma chemical vapor deposition process and has a thickness of 60 nm.

[0157] Example 3

[0158] The operation steps of Example 3 are the same as those of Example 1 except for the ninth step. In the ninth step of Example 3, the intrinsic amorphous silicon layer and the P-type amorphous silicon layer are replaced with the intrinsic amorphous silicon layer and the P-type microcrystalline silicon to improve the contact of the P region. Specifically, the thickness of the P-type microcrystalline silicon layer is 25 nm.

[0159] Table 1 tests the back contact cells corresponding to Examples 1 to 3 and compares the parameters of the three back contact cells.

[0160]

[0161] It can be seen from the data in Table 1 that the back contact cell formed by the manufacturing method provided by the embodiment of the present invention has a higher efficiency. Moreover, in Example 2, only the deposition method and deposition thickness of the first mask material layer are changed, and the final structure of the back contact cell is not changed, and the corresponding data of Example 1 and Example 2 are roughly the same. In Example 3, after the P-type amorphous silicon layer is replaced with a P-type microcrystalline silicon layer with a better conductivity type, the efficiency and fill factor of the back contact cell are improved, and the bypass resistance and series resistance are reduced.

[0162] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

[0163] The embodiments of the present disclosure are described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, a person skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A back contact battery, characterized in that: include: A semiconductor substrate having a first surface and a second surface opposite to each other; The second surface has first areas and second areas that are alternately spaced and an isolation area between each first area and the second area adjacent to the first area; A first doped semiconductor layer is formed on the first region and a portion of the isolation region; the portion of the first doped semiconductor layer located on the first region is a first doped portion, and the remaining portion is a second doped portion; the doping concentration of impurities in the second doped portion is less than the doping concentration of impurities in the first doped portion; An intrinsic semiconductor layer is formed on a portion of the isolation region other than the second doped portion and is integrally formed with the first doped semiconductor layer; a second doped semiconductor layer covering the second region, at least a portion of the intrinsic semiconductor layer and at least a portion of the second doped portion; The conductivity types of the second doped semiconductor layer and the first doped semiconductor layer are opposite, and at least one of the second doped semiconductor layer and the first doped semiconductor layer is a doped crystalline silicon layer; The intrinsic semiconductor layer is used to electrically isolate the first doped semiconductor layer from the second doped semiconductor layer along a direction parallel to the second surface; and an insulating mask layer, located between the second doped semiconductor layer and the intrinsic semiconductor layer and the second doped portion respectively.

2. The back contact cell according to claim 1, characterized in that: The first doped semiconductor layer is the doped crystalline silicon layer.

3. The back contact cell according to claim 1, characterized in that: Along the direction from the second doped portion to the intrinsic semiconductor layer, a ratio of a width of the second doped portion to a width of the isolation region is greater than or equal to 0.8 and less than 1; and / or, Along the direction from the second doping portion to the intrinsic semiconductor layer, the width of the intrinsic semiconductor layer is greater than or equal to 6 μm and less than or equal to 120 μm; and / or, Along a direction from the second doping portion to the intrinsic semiconductor layer, a width of the isolation region is greater than or equal to 30 μm and less than or equal to 200 μm.

4. The back contact cell according to claim 1, characterized in that: The doping concentration of the impurities in the second doping part is greater than or equal to 1E18 cm -3 , and less than or equal to 5E20cm -3 and / or, The doping concentration of impurities in the first doping portion is 10 to 100 times the doping concentration of impurities in the second doping portion; and / or, Along a direction from the second doping portion to the intrinsic semiconductor layer, a doping concentration of impurities in the second doping portion gradually decreases.

5. The back contact battery according to any one of claims 1 to 4, characterized in that: The back contact cell further comprises a first passivation layer, wherein the first passivation layer is located between the semiconductor substrate and the first doped semiconductor layer and the intrinsic semiconductor layer respectively; and / or, The back contact cell further includes a second passivation layer, which is located between the second doped semiconductor layer and the semiconductor substrate, the intrinsic semiconductor layer and the second doped portion respectively.

6. The back contact cell according to claim 5, characterized in that: In the case where the back contact battery further includes a first passivation layer, and the first passivation layer is a tunnel passivation layer, the material of the first doped semiconductor layer is doped polysilicon, and the conductivity type is N-type; and / or, When the back contact battery further includes a second passivation layer, and the material of the second passivation layer includes intrinsic amorphous silicon and / or intrinsic microcrystalline silicon, the material of the second doped semiconductor layer is doped amorphous silicon and / or doped microcrystalline silicon, and the conductivity type is P type.

7. The back contact cell according to claim 1, characterized in that: The first surface of the semiconductor substrate and the surface of the semiconductor substrate corresponding to the second region are both velvet surfaces.

8. A method for manufacturing a back contact battery, characterized in that: include: Providing a semiconductor substrate; The semiconductor substrate has a first surface and a second surface opposite to each other; The second surface has first areas and second areas that are alternately spaced and an isolation area between each first area and the second area adjacent to the first area; forming an integrally arranged intrinsic semiconductor material layer on the second surface; forming a first mask layer, wherein the first mask layer covers a portion of the intrinsic semiconductor material layer corresponding to the second region and the isolation region; And under the masking effect of the first mask layer, the portion of the intrinsic semiconductor material layer located on the first region is selectively doped, so that the portion of the intrinsic semiconductor material layer located on the first region and part of the isolation region forms a first doped semiconductor layer, and the portion of the intrinsic semiconductor material layer located on the remaining isolation region forms an intrinsic semiconductor layer; the portion of the first doped semiconductor layer located on the first region is a first doped portion, and the remaining portion is a second doped portion, and the doping concentration of impurities in the second doped portion is less than the doping concentration of impurities in the first doped semiconductor layer; removing the first mask layer; forming at least an insulating mask layer covering the first doped semiconductor layer and the intrinsic semiconductor layer; and selectively removing the portion of the intrinsic semiconductor material layer remaining on the second region at least under the masking effect of the insulating mask layer; forming a second doped semiconductor layer on the insulating mask layer and the second region; The conductivity types of the second doped semiconductor layer and the first doped semiconductor layer are opposite, and at least one of the second doped semiconductor layer and the first doped semiconductor layer is a doped crystalline silicon layer; The intrinsic semiconductor layer is used to electrically isolate the second doped semiconductor layer from the first doped semiconductor layer; The portion of the insulating mask layer located on the first doped portion is removed.

9. The method for manufacturing a back contact battery according to claim 8, characterized in that: In the case where the width of the second doping portion is greater than or equal to 6 um and less than or equal to 120 um along the direction from the second doping portion to the intrinsic semiconductor layer, after selectively doping the portion of the intrinsic semiconductor material layer located on the first region and before removing the first mask layer, the method for manufacturing a back contact battery further includes: The first doped semiconductor layer and the intrinsic semiconductor layer are annealed to make the width of the second doped portion reach a target width.

10. The method for manufacturing a back contact battery according to claim 8, characterized in that: After removing the first mask layer and before forming the second doped semiconductor layer on the insulating mask layer and the second region, the method for manufacturing a back contact battery comprises: forming a mask material layer disposed entirely on the first doped semiconductor layer, the intrinsic semiconductor layer and the remaining portion of the intrinsic semiconductor material layer on the second region; removing the portion of the mask material layer located above the second region, and the remaining portion of the mask material layer forms a second mask layer; Under the masking effect of the second mask layer, selectively removing the portion of the intrinsic semiconductor material layer remaining on the second region; Under the masking effect of at least a portion of the second mask layer, the first surface of the semiconductor substrate and the surface of the semiconductor substrate corresponding to the second region are textured; after the textured treatment, at least a portion of the second mask layer forms the insulating mask layer.

11. The method for manufacturing a back contact battery according to claim 10, characterized in that: Using a laser etching process, sequentially removing the portion of the mask material layer located above the second region and the portion of the intrinsic semiconductor material layer remaining on the second region; and / or, The second mask layer includes a first silicon nitride layer and a second silicon nitride layer spaced apart along the thickness direction of the semiconductor substrate, and an intrinsic silicon layer located between the first silicon nitride layer and the second silicon nitride layer; after the texturing treatment is performed on the first surface of the semiconductor substrate and the surface of the semiconductor substrate corresponding to the second region, before forming a second doped semiconductor layer on the insulating mask layer and the second region, the manufacturing method of the back contact battery also includes: removing the second silicon nitride layer and the intrinsic silicon layer in sequence.

12. The method for manufacturing a back contact battery according to claim 10 or 11, characterized in that: Forming a second doped semiconductor layer on the insulating mask layer and the second region, comprising: forming a second doped semiconductor material layer disposed entirely on the second region and the second mask layer; The portion of the second doped semiconductor material layer corresponding to the first region is selectively removed, so that the remaining portion of the second doped semiconductor material layer forms a second doped semiconductor layer.

13. The method for manufacturing a back contact battery according to claim 8, characterized in that: After providing a semiconductor substrate and before forming a whole layer of an intrinsic semiconductor material layer on the second surface, the method for manufacturing a back contact battery further includes: forming a whole layer of a first passivation material layer on the second surface; After selectively removing the remaining portion of the intrinsic semiconductor material layer on the second region, and before forming a second doped semiconductor layer on the second region and the insulating mask layer, the method for manufacturing a back-contact battery further includes: selectively removing the portion of the first passivation material layer located on the second region, so that the remaining portion of the first passivation material layer forms a first passivation layer.

14. The method for manufacturing a back contact battery according to claim 8 or 13, characterized in that: After selectively removing the portion of the intrinsic semiconductor material layer remaining on the second region, and before forming a second doped semiconductor layer on the insulating mask layer and the second region, the method for manufacturing a back contact battery further includes: forming a second passivation layer on the insulating mask layer.

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