A back contact cell and method of manufacturing the same

Abstract

The application discloses a back contact cell and a manufacturing method thereof, and relates to the technical field of photovoltaics, which is used for preventing leakage between doped semiconductor layers with opposite conductive types in the back contact cell. The back contact cell comprises a semiconductor substrate, a first doped semiconductor layer, an intrinsic semiconductor layer, a second doped semiconductor layer and an insulating mask layer. The first doped semiconductor layer is divided into a first doped part and a second doped part. The second doped part is smaller than the first doped part in impurity doping concentration. The intrinsic semiconductor layer is formed on the part of the second doped part of the isolation area and is integrally formed with the first doped semiconductor layer. The second doped semiconductor layer covers the second area, at least part of the intrinsic semiconductor layer and at least part of the second doped part. The conductive types of the second doped semiconductor layer and the first doped semiconductor layer are opposite, and at least one of the second doped semiconductor layer and the first doped semiconductor layer is a doped crystalline silicon layer.

Description

Technical Field

[0001] This invention relates to the field of photovoltaic technology, and in particular to a back contact battery and its manufacturing method. Background Technology

[0002] A back-contact solar cell refers to a solar cell where both the positive and negative electrodes are located on the back of the cell, with no metal electrodes obstructing the front. Compared to solar cells with obstructed front surfaces, back-contact solar cells have higher short-circuit current and photoelectric conversion efficiency, and are one of the current technological directions for achieving high-efficiency crystalline silicon solar cells.

[0003] However, in existing back-contact batteries, there is a leakage problem between the two doped semiconductor layers located on the back side and with opposite conductivity types, which leads to a decrease in the photoelectric conversion efficiency of the back-contact battery. Summary of the Invention

[0004] The purpose of this invention is to provide a back contact battery and its manufacturing method, which prevents leakage between a first doped semiconductor layer and a second doped semiconductor layer with opposite conductivity types, thereby improving the photoelectric conversion efficiency of the back contact battery.

[0005] To achieve the above objectives, in a first aspect, the present invention provides a back contact battery, comprising: a semiconductor substrate, a first doped semiconductor layer, an intrinsic semiconductor layer, a second doped semiconductor layer, and an insulating mask layer. The semiconductor substrate has opposing first and second surfaces. The second surface has alternating first and second regions, and an isolation region located between each first region and its adjacent second region. The first doped semiconductor layer is formed on the first regions and a portion of the isolation region. The portion of the first doped semiconductor layer on the first region is a first doped portion, and the remaining portion is a second doped portion. The doping concentration of impurities in the second doped portion is less than the doping concentration of impurities in the first doped portion. The intrinsic semiconductor layer is formed on the portion of the isolation region excluding the second doped portion and is integrally formed with the first doped semiconductor layer. The second doped semiconductor layer covers the second region, at least a portion of the intrinsic semiconductor layer, and at least a portion of the second doped portion. The second doped semiconductor layer and the first doped semiconductor layer have opposite conductivity types, and at least one of the second doped semiconductor layer and the first doped semiconductor layer is a doped silicon layer. The intrinsic semiconductor layer is used to electrically isolate the first doped semiconductor layer and the second doped semiconductor layer along a direction parallel to the second surface. An insulating mask layer is located between the second doped semiconductor layer and the intrinsic semiconductor layer and the second doped portion, respectively.

[0006] In the above-described technical solution, both the first doped semiconductor layer and the second doped semiconductor layer are formed on one side of the second surface of the semiconductor substrate, and their conductivity types are opposite. Based on this, when the back-contact battery is in operation, electrons and holes generated after the semiconductor substrate absorbs photons move towards the first doped semiconductor layer and the second doped semiconductor layer, respectively, and are collected and discharged by them to form a photocurrent. Specifically, along the thickness direction of the semiconductor substrate, the second doped semiconductor layer is not only formed on the second region of the second surface of the semiconductor substrate, but also covers at least a portion of the intrinsic semiconductor layer and at least a portion of the second doped portion included in the first doped semiconductor layer. Furthermore, an insulating mask layer is located between the second doped semiconductor layer and the intrinsic semiconductor layer and the second doped portion, respectively. Since the insulating mask layer is a non-conductive film, its presence electrically isolates the second doped semiconductor layer and the second doped portion, which have opposite conductivity types, along the thickness direction of the semiconductor substrate, preventing leakage current from occurring between them along the thickness direction of the semiconductor substrate.

[0007] Secondly, an intrinsic semiconductor layer is formed between the first doped semiconductor layer and the second doped semiconductor layer along a direction parallel to the second surface of the semiconductor substrate. This intrinsic semiconductor layer electrically isolates the first and second doped semiconductor layers along the direction parallel to the second surface, preventing leakage current between them and further reducing the carrier recombination rate on one side of the second surface of the semiconductor substrate, thus improving the photoelectric conversion efficiency of the back contact battery. Furthermore, in actual manufacturing processes, due to machine precision and / or for the purpose of preventing leakage current, the width of the isolation region between the first region and the adjacent second region is relatively large. Therefore, the first doped semiconductor layer includes not only the first doped portion in the first region but also the second doped portion in a portion of the isolation region. When the back contact battery is in operation, the first doped semiconductor layer can not only collect and export electrons or holes corresponding to the first region in a timely manner but also collect and export electrons or holes corresponding to the portion of the isolation region in a timely manner. Therefore, while preventing lateral leakage current between the first and second doped semiconductor layers through the intrinsic semiconductor layer, it can also reduce the carrier recombination rate in the wider isolation region, further improving the photoelectric conversion efficiency of the back contact battery.

[0008] Furthermore, since the second doped portion is located between the first doped portion and the intrinsic semiconductor layer, when the doping concentration of the impurities in the second doped portion located in the partial isolation region is less than the doping concentration of the impurities in the first doped portion located in the first region, the conductivity of the second doped portion can be reduced, the electrical breakdown penetration of the intrinsic semiconductor layer can be reduced, and at the same time, the diffusion of impurities in the second doped portion into the intrinsic semiconductor layer can be suppressed or even eliminated, ensuring that the intrinsic semiconductor layer has good electrical isolation and ensuring that the back contact battery has good electrical performance.

[0009] As one possible implementation, the first doped semiconductor layer is a doped crystalline silicon layer.

[0010] With the above technical solution, compared with doped amorphous silicon layers, doped crystalline silicon layers have higher carrier lateral transport characteristics. Furthermore, since a portion of the insulating mask layer and a portion of the second doped semiconductor layer cover the second doped portion, when the first doped semiconductor layer is a doped crystalline silicon layer, the second doped portion has good carrier lateral transport characteristics. This facilitates the lateral transport of more electrons or holes collected by the second doped portion to the first doped portion, which then discharges them through the exposed first doped portion, further reducing the carrier recombination efficiency in the isolation region. Simultaneously, it also enables the first doped portion to have higher carrier collection characteristics, reducing the carrier recombination efficiency in the first region.

[0011] As one possible implementation, along the direction from the second doped portion to the intrinsic semiconductor layer, the ratio of the width of the second doped portion to the width of the isolation region is greater than or equal to 0.8 and less than 1.

[0012] When the above technical solution is adopted, if the ratio of the width of the second doped portion to the width of the isolation region is within the aforementioned range along the direction from the second doped portion to the intrinsic semiconductor layer, the width of the second doped portion is greater than the width of the intrinsic semiconductor layer. This prevents the reduction in carrier recombination rate at the isolation region due to a smaller width of the second doped portion, ensuring a higher photoelectric conversion efficiency for the back contact cell. Furthermore, since the second doped portion and the intrinsic semiconductor layer are both located on the isolation region, the width of the second doped portion is inversely proportional to the width of the intrinsic semiconductor layer when the width of the isolation region is constant. Moreover, within a certain range, the electrical isolation effect of the intrinsic semiconductor layer along the direction parallel to the second surface is directly proportional to its width. Therefore, when the ratio is within the aforementioned range, it also prevents poor electrical isolation of the intrinsic semiconductor layer due to a smaller width of the second doped portion, ensuring that leakage between the first and second doped semiconductor layers along the direction parallel to the second surface can be prevented through the intrinsic semiconductor layer.

[0013] As one possible implementation, the width of the intrinsic semiconductor layer along the direction from the second doped portion to the intrinsic semiconductor layer is greater than or equal to 6 μm and less than or equal to 120 μm.

[0014] When the above technical solution is adopted, the width of the intrinsic semiconductor layer is within the aforementioned range. This prevents the narrow width of the intrinsic semiconductor layer from affecting its electrical isolation effect along the second direction, ensuring that leakage current is prevented between the first doped semiconductor layer and the second doped semiconductor layer along the second plane. Furthermore, it prevents the narrow width of the second doped portion due to a large width of the intrinsic semiconductor layer, thus avoiding a lower carrier collection capacity and further enhancing the degree to which the carrier recombination rate at the isolation region is reduced through the second doped portion.

[0015] As one possible implementation, the width of the isolation region along the direction from the second doped portion to the intrinsic semiconductor layer is greater than or equal to 30 μm and less than or equal to 200 μm.

[0016] With the above technical solution, the width of the isolation region is within the aforementioned range. This prevents the isolation region from being too small, making it difficult to set a reasonably wide second doped portion and intrinsic semiconductor layer within a small width range, thus ensuring that the second doped portion and intrinsic semiconductor layer have the functions described above. Furthermore, it prevents the first doped semiconductor layer and / or the second doped semiconductor layer from being too small due to the larger width of the intrinsic semiconductor layer, which in turn prevents the width of the first and / or second regions located on one side of the second surface from being too small. This ensures that the first and second doped semiconductor layers can promptly collect and export the carriers corresponding to the first and second regions, further reducing the carrier recombination rate on one side of the second surface.

[0017] As one possible implementation, the doping concentration of the impurities in the second doped region is greater than or equal to 1E18 cm⁻¹. -3 And less than or equal to 5E20cm -3 .

[0018] When the above technical solution is adopted, the doping concentration of impurities in the second doped portion is within the aforementioned range. This prevents the carrier collection capability from being poor due to a low doping concentration of impurities in the second doped portion, further enhancing the degree to which the carrier recombination rate at the isolation region is reduced through the second doped portion. Furthermore, it also prevents carriers from easily diffusing into the intrinsic semiconductor layer due to a high doping concentration of impurities in the second doped portion, ensuring that the intrinsic semiconductor layer has good electrical isolation.

[0019] As one possible implementation, the doping concentration of the impurities in the first doped section is 10 to 100 times that of the impurities in the second doped section. In this case, the higher doping concentration of the impurities in the first doped section allows it to have a higher carrier collection capability. Furthermore, it reduces the manufacturing difficulty of obtaining a first doped section with an excessively high doping concentration.

[0020] As one possible implementation, the doping concentration of impurities in the second doped section gradually decreases along the direction from the second doped section to the intrinsic semiconductor layer. In this case, while ensuring that the impurities in the second doped section have a certain doping concentration, thereby enabling the second doped section to have a certain lateral carrier collection capability, the part of the second doped section with the lowest impurity doping concentration can also contact the intrinsic semiconductor layer, reducing the carrier concentration gradient at the contact point, further suppressing or even eliminating the diffusion of impurities from the second doped section into the intrinsic semiconductor layer, and ensuring that the intrinsic semiconductor layer has good electrical isolation.

[0021] As one possible implementation, the aforementioned back contact battery further includes a first passivation layer, which is located between the semiconductor substrate and the first doped semiconductor layer and the intrinsic semiconductor layer, respectively.

[0022] With the above technical solution, the selective contact structure composed of the first passivation layer and the first doped semiconductor layer has excellent interface passivation effect and can achieve selective collection of charge carriers, reduce the charge carrier recombination rate in the first region and part of the isolation region of the back light surface of the semiconductor substrate, and further improve the photoelectric conversion efficiency of the back contact battery.

[0023] As one possible implementation, the aforementioned back contact battery further includes a second passivation layer, which is located between the second doped semiconductor layer and the semiconductor substrate, the intrinsic semiconductor layer, and the second doped portion.

[0024] With the above technical solution, the selective contact structure composed of the second passivation layer and the second doped semiconductor layer can achieve selective carrier collection and reduce the carrier recombination rate in the second region of the semiconductor substrate back surface. Simultaneously, the second passivation layer and the intrinsic semiconductor layer are located between the portion of the second doped semiconductor layer in the second region and the second doped portion. In this case, both can suppress the carrier recombination rate at a portion of the interface between the second doped semiconductor layer and the corresponding isolation region of the first doped semiconductor layer, further improving the photoelectric conversion efficiency of the back contact cell.

[0025] As one possible implementation, in the case where the back contact battery also includes a first passivation layer, and the first passivation layer is a tunneling passivation layer, the material of the first doped semiconductor layer is doped polycrystalline silicon, and the conductivity type is N-type.

[0026] When the above technical solution is adopted, if the back contact battery also includes a first passivation layer, and the first passivation layer is a tunneling passivation layer, the selective contact structure formed by the first passivation layer and the first doped semiconductor layer is a tunneling passivation contact structure. In this case, the material of the first doped semiconductor layer is doped polycrystalline silicon. Based on this, since the contact resistance between the P-type doped polycrystalline silicon layer and the electrode is high, and the field passivation effect is poor, when the back contact battery includes a tunneling passivation layer as the first passivation layer and a doped polycrystalline silicon layer, if the conductivity type of the first doped semiconductor layer is N-type, the field passivation effect of the first doped semiconductor layer can be further improved, while the contact resistance between the first doped portion and the electrode can be reduced, which is beneficial to improving the electrical performance of the back contact battery. Furthermore, the intrinsic semiconductor layer and the first doped semiconductor layer are integrally formed, and the second doped semiconductor layer is also located on at least a portion of the intrinsic semiconductor layer and at least a portion of the second doped portion included in the first doped semiconductor layer; therefore, the formation sequence of the first doped semiconductor layer precedes the formation sequence of the second doped semiconductor layer. In addition, compared with amorphous silicon, polycrystalline silicon has better heat resistance characteristics. Based on this, when the back contact battery also includes a first passivation layer, and the first passivation layer is a tunneling passivation layer, and the material of the first doped semiconductor layer is doped polysilicon, if a laser etching process is used to remove the portion of the material layer used to manufacture the second doped semiconductor layer corresponding to the first region, the first doped semiconductor layer, made of doped polysilicon, is less affected by the high-temperature laser, or even unaffected, which is beneficial to improving the yield of the back contact battery. Furthermore, in actual manufacturing, the manufacturing cost of heterogeneous contact structures is higher than that of tunneling passivation contact structures. Moreover, tunneling passivation contact structures can be implemented using various processes such as low-pressure chemical vapor deposition, plasma chemical vapor deposition, physical chemical vapor deposition, or plasma-enhanced atomic layer deposition, making them more compatible with back contact battery processes. Heterogeneous contact structures, on the other hand, require the use of plate-type plasma chemical vapor deposition equipment that supports lower formation temperatures. Therefore, when the first passivation layer of the back contact battery is a tunneling passivation layer, and the material of the first doped semiconductor layer is doped polysilicon, it is beneficial to reduce manufacturing costs, reduce investment in plate-type plasma chemical vapor deposition equipment, and save production space.

[0027] As one possible implementation, if the back contact battery further includes a second passivation layer, and the material of the second passivation layer includes intrinsic amorphous silicon and / or intrinsic microcrystalline silicon, the material of the second doped semiconductor layer is doped amorphous silicon and / or doped microcrystalline silicon, and the conductivity type is P-type.

[0028] When the above technical solution is adopted, if the back contact battery further includes a second passivation layer, and the material of the second passivation layer includes intrinsic amorphous silicon and / or intrinsic microcrystalline silicon, the selective contact structure between the second passivation layer and the second doped semiconductor layer is a heterogeneous contact structure. In this case, the material of the second doped semiconductor layer is doped amorphous silicon and / or doped microcrystalline silicon. Based on this, since the contact resistance between the P-type doped polycrystalline silicon layer and the electrode is higher and the field passivation effect is worse than that of the P-type doped amorphous silicon and / or doped microcrystalline silicon layer, in the above case, setting the conductivity type of the second doped semiconductor layer to P-type, rather than setting the conductivity type of the tunneling passivation contact structure to P-type, can further improve the field passivation effect of the first doped semiconductor layer, while reducing the contact resistance between the first doped portion and the electrode, which is beneficial to improving the electrical performance of the back contact battery.

[0029] As one possible implementation, both the first surface of the semiconductor substrate and the surface of the corresponding second region of the semiconductor substrate are textured. In this case, the refractive index of light transmitted from the first surface and the surface of the second region to the semiconductor substrate can be increased, further improving the photoelectric conversion efficiency of the back contact cell. Furthermore, when the surface of the second region is textured, the back-light side of the second doped semiconductor layer formed on the second region also has corresponding undulation characteristics. Compared to a flat surface, a surface with undulation characteristics has a larger specific surface area. Therefore, when the back-light side of the second doped semiconductor layer on the second region has undulation characteristics, it is beneficial to increase the contact area between the second doped semiconductor layer and the electrode, reduce their contact resistance, and further improve the electrical performance of the back contact cell.

[0030] Secondly, the present invention also provides a method for manufacturing a back contact battery, the method comprising: first, providing a semiconductor substrate. The semiconductor substrate has a first surface and a second surface opposite to each other. The second surface has alternating first regions and second regions, and an isolation region located between each first region and its adjacent second region. Next, forming an intrinsic semiconductor material layer integrally disposed on the second surface. Then, forming a first mask layer; the first mask layer covers portions of the intrinsic semiconductor material layer corresponding to the second regions and the isolation regions. Under the masking effect of the first mask layer, selectively doping is performed on the portions of the intrinsic semiconductor material layer located in the first regions, so that the portions of the intrinsic semiconductor material layer located in the first regions and the partial isolation regions form a first doped semiconductor layer, and the portions of the intrinsic semiconductor material layer located in the remaining isolation regions form an intrinsic semiconductor layer. The portions of the first doped semiconductor layer located in the first regions are first doped portions, and the remaining portions are second doped portions, wherein the doping concentration of impurities in the second doped portions is less than the doping concentration of impurities in the first doped semiconductor layer. Then, removing the first mask layer. Next, an insulating mask layer is formed covering at least the first doped semiconductor layer and the intrinsic semiconductor layer; and, at least under the masking effect of the insulating mask layer, the portion of the intrinsic semiconductor material layer remaining in the second region is selectively removed. Next, a second doped semiconductor layer is formed on the insulating mask layer and the second region. The second doped semiconductor layer has the opposite conductivity type to the first doped semiconductor layer, and at least one of the second doped semiconductor layer and the first doped semiconductor layer is a doped silicon layer. The intrinsic semiconductor layer is used to electrically isolate the second doped semiconductor layer and the first doped semiconductor layer. Then, the portion of the insulating mask layer located on the first doped portion is removed.

[0031] As one possible implementation, if the width of the second doped portion is greater than or equal to 6 μm and less than or equal to 120 μm along the direction from the second doped portion to the intrinsic semiconductor layer, after selectively doping the portion of the intrinsic semiconductor material layer located in the first region, before removing the first mask layer, the manufacturing method of the back contact battery further includes: annealing the first doped semiconductor layer and the intrinsic semiconductor layer to make the width of the second doped portion reach the target width.

[0032] In the case of the above technical solution, the second doped portion is formed by diffusion during selective doping of the intrinsic semiconductor material layer located in the first region under the masking effect of the first mask layer. Based on this, along the direction from the second doped portion to the intrinsic semiconductor layer, when the width of the second doped portion is greater than or equal to 6 μm and less than or equal to 120 μm, the width of the second doped portion is relatively large. In this case, annealing the first doped semiconductor layer and the intrinsic semiconductor layer after selective doping can cause the impurities in the second doped portion, or the first doped portion and the second doped portion, to diffuse a longer distance in a direction parallel to the second surface after heating, thereby obtaining a second doped portion with an actual width reaching the target width.

[0033] As one possible implementation, the method for manufacturing a back contact battery after removing the first mask layer and before forming a second doped semiconductor layer on the insulating mask layer and the second region includes: forming a mask material layer integrally disposed on the portion of the first doped semiconductor layer, the intrinsic semiconductor layer, and the intrinsic semiconductor material layer remaining on the second region. Next, removing the portion of the mask material layer above the second region, leaving the remaining portion to form a second mask layer. Then, under the masking action of the second mask layer, selectively removing the portion of the intrinsic semiconductor material layer remaining on the second region. Next, under the masking action of at least a portion of the second mask layer, texturing the first surface of the semiconductor substrate and the surface of the semiconductor substrate corresponding to the second region. After texturing, at least a portion of the second mask layer forms an insulating mask layer.

[0034] When the above technical solution is adopted, the presence of the second mask layer can prevent the portion of the intrinsic semiconductor material layer remaining in the second region from being affected by etching operations and subsequent texturing processes during the selective removal process.

[0035] As one possible implementation, a laser etching process is used to sequentially remove the portion of the mask material layer located above the second region and the portion of the intrinsic semiconductor material layer remaining on the second region.

[0036] With the above technical solution, the laser etching process has high etching precision. Therefore, by using the laser etching process to sequentially remove the portion of the mask material layer above the second region and the portion of the intrinsic semiconductor material layer remaining in the second region, the yield of the manufactured back contact battery can be improved.

[0037] As one possible implementation, the second mask layer includes a first silicon nitride layer and a second silicon nitride layer spaced apart along the thickness direction of the semiconductor substrate, and an intrinsic silicon layer located between the first silicon nitride layer and the second silicon nitride layer. In the above case, after texturing the first surface of the semiconductor substrate and the surface of the corresponding second region of the semiconductor substrate, before forming the second doped semiconductor layer on the insulating mask layer and the second region, the method for manufacturing the back contact cell further includes: sequentially removing the second silicon nitride layer and the intrinsic silicon layer.

[0038] Under the aforementioned technical solution, and assuming other factors remain the same, compared to a single-layer second mask layer, when the second mask layer comprises a first silicon nitride layer, an intrinsic silicon layer, and a second silicon nitride layer, the mask characteristics of the second mask layer can be improved, ensuring that the first doped semiconductor layer and the intrinsic semiconductor layer located beneath it can be protected through the second mask layer. Furthermore, when using laser etching to remove the portion of the mask material layer above the second region and the remaining portion of the intrinsic semiconductor material layer in the second region, because the laser spot is a Gaussian spot with higher energy at the center and lower energy at the edges, to completely remove the portion of the mask material layer above the second region and the remaining portion of the intrinsic semiconductor material layer in the second region, the edges of the laser spot pattern may partially cover the second mask layer. Additionally, the silicon nitride material's film properties change upon heating, enhancing its corrosion resistance. Therefore, during the subsequent texturing process, when the texturing solution etches to the boundary between the second region and the isolation region, it easily etches part of the surface of the semiconductor substrate and the intrinsic semiconductor layer corresponding to the boundary between the isolation region and the second region. When the second mask layer is only a single layer of silicon nitride, the edge portion of the second mask layer has strong corrosion resistance, resulting in an air gap between this part of the isolation region and the edge of the second mask layer. Because the size of this air gap is small, it is difficult for the subsequently formed second doped semiconductor layer to fill the air gap, and the current recombination rate in the region below the air gap is relatively high. In the above case, when the second mask layer includes a first silicon nitride layer, an intrinsic silicon layer, and a second silicon nitride layer, even if the outermost second silicon nitride layer is heated by the heat of the laser spot, resulting in increased corrosion resistance at its edge, it can still be removed by appropriately extending the etching time. Although the first silicon nitride layer located inside protrudes from the textured area after texturing, its edges are not irradiated by laser, which causes changes in the film properties. Furthermore, because the etching time is appropriately extended after the second silicon nitride layer is etched away to completely remove the intrinsic silicon layer covering the first silicon nitride layer, the portion of the first silicon nitride layer located in the textured area is also removed, thus preventing the formation of the aforementioned air gap. This reduces the carrier recombination rate at the boundary between the isolation region and the second region, further improving the photoelectric conversion efficiency of the back contact cell.

[0039] As one possible implementation, forming a second doped semiconductor layer on an insulating mask layer and a second region includes: forming a continuous second doped semiconductor material layer on the second region and the second mask layer. Next, selectively removing portions of the second doped semiconductor material layer corresponding to the first region, so that the remaining portion of the second doped semiconductor material layer forms the second doped semiconductor layer.

[0040] As one possible implementation, after providing a semiconductor substrate, before forming an intrinsic semiconductor material layer integrally disposed on the second surface, the method for manufacturing the back contact cell further includes: forming a first passivation material layer integrally disposed on the second surface. Furthermore, after selectively removing the portion of the intrinsic semiconductor material layer remaining in the second region, before forming a second doped semiconductor layer on the second region and the insulating mask layer, the method for manufacturing the back contact cell further includes: selectively removing the portion of the first passivation material layer located in the second region, so that the remaining portion of the first passivation material layer forms a first passivation layer.

[0041] As one possible implementation, after selectively removing the portion of the intrinsic semiconductor material layer remaining in the second region, before forming the second doped semiconductor layer on the insulating mask layer and the second region, the method for manufacturing the back contact cell further includes: forming a second passivation layer on the insulating mask layer.

[0042] The beneficial effects of the second aspect and its various implementations in this invention can be found in the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here. Attached Figure Description

[0043] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0044] Figure 1 This is a longitudinal sectional view of the first structure of the back contact battery provided in an embodiment of the present invention;

[0045] Figure 2 This is a longitudinal sectional view of a second structure of a back-contact battery provided in an embodiment of the present invention;

[0046] Figure 3 This is a longitudinal sectional view of a third structure of a back-contact battery provided in an embodiment of the present invention.

[0047] Figure 4 A schematic diagram of the back contact battery during the manufacturing process provided in this embodiment of the invention. Figure 1 ;

[0048] Figure 5A schematic diagram of the back contact battery during the manufacturing process provided in this embodiment of the invention. Figure 2 ;

[0049] Figure 6 A schematic diagram of the back contact battery during the manufacturing process provided in this embodiment of the invention. Figure 3 ;

[0050] Figure 7 A schematic diagram of the back contact battery during the manufacturing process provided in this embodiment of the invention. Figure 4 ;

[0051] Figure 8 A schematic diagram of the back contact battery during the manufacturing process provided in this embodiment of the invention. Figure 5 ;

[0052] Figure 9 A schematic diagram of the back contact battery during the manufacturing process provided in this embodiment of the invention. Figure 6 ;

[0053] Figure 10 A schematic diagram of the back contact battery during the manufacturing process provided in this embodiment of the invention. Figure 7 ;

[0054] Figure 11 A schematic diagram of the back contact battery during the manufacturing process provided in this embodiment of the invention. Figure 8 ;

[0055] Figure 12 A schematic diagram of the back contact battery during the manufacturing process provided in this embodiment of the invention. Figure 9 ;

[0056] Figure 13 A schematic diagram of the back contact battery during the manufacturing process provided in this embodiment of the invention. Figure 10 ;

[0057] Figure 14 A schematic diagram of the back contact battery during the manufacturing process provided in this embodiment of the invention. Figure 10 one;

[0058] Figure 15 A schematic diagram of the back contact battery during the manufacturing process provided in this embodiment of the invention. Figure 10 two;

[0059] Figure 16 A schematic diagram of the back contact battery during the manufacturing process provided in this embodiment of the invention. Figure 10 three;

[0060] Figure 17 A schematic diagram of the back contact battery during the manufacturing process provided in this embodiment of the invention. Figure 10 Four. Detailed Implementation

[0061] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0062] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0063] In the context of this disclosure, when a layer / element is referred to as being "on top of" another layer / element, the layer / element may be directly on top of the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "on top of" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0064] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0065] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0066] Solar cells are increasingly being used as a new energy alternative. Photovoltaic solar cells, in particular, are devices that convert sunlight into electrical energy. Specifically, solar cells utilize the photovoltaic principle to generate charge carriers, which are then extracted using electrodes, thus facilitating the efficient use of electrical energy.

[0067] When both the positive and negative electrodes of a solar cell are located on the back side of the cell, it is called a back-contact solar cell. The most significant characteristic of a back-contact solar cell is that there is no metal electrode obstructing the front side, resulting in a higher short-circuit current Isc. This makes back-contact solar cells one of the current technological directions for achieving high-efficiency crystalline silicon solar cells.

[0068] Specifically, the aforementioned back-contact battery typically includes a semiconductor substrate, a first doped semiconductor layer, a second doped semiconductor layer, and an isolation layer. The first and second doped semiconductor layers are alternately formed on the same side of the semiconductor substrate along a direction parallel to the surface of the semiconductor substrate. Furthermore, the second doped semiconductor layer and the first doped semiconductor layer have opposite conductivity types, and the second doped semiconductor layer covers a portion of the first doped semiconductor layer. The isolation layer is located only between the first and second doped semiconductor layers to separate them. In practical applications, doped crystalline silicon layers have a higher carrier transport capacity compared to doped amorphous silicon layers. Therefore, when at least one of the first and second doped semiconductor layers is a doped crystalline silicon layer, it is beneficial to improve its own carrier collection efficiency, reduce the carrier recombination rate on the back side, and improve the photoelectric conversion efficiency of the back-contact battery.

[0069] However, the isolation layer in the aforementioned back-contact battery can only electrically isolate the first doped semiconductor layer and the second doped semiconductor layer along the thickness direction of the semiconductor substrate. When at least one of the first and second doped semiconductor layers is a doped crystalline silicon layer, due to the excellent lateral carrier transport characteristics of the doped crystalline silicon layer, the first and second doped semiconductor layers will be electrically connected along a direction parallel to the semiconductor substrate when the back-contact battery is in operation, resulting in leakage current and a decrease in the photoelectric conversion efficiency of the back-contact battery. In the prior art, an intrinsic amorphous silicon passivation layer or a tunneling silicon dioxide layer is also provided between the first and second doped semiconductor layers. Since both the intrinsic amorphous silicon passivation layer and the tunneling silicon dioxide layer have a tunneling effect, when a highly conductive doped polycrystalline silicon is used as the semiconductor doping layer, it is easy to break down the intrinsic amorphous silicon passivation layer or the tunneling silicon dioxide layer, thereby generating a large leakage current.

[0070] To address the aforementioned technical problems, in a first aspect, embodiments of the present invention provide a back-contact battery. For example... Figure 1As shown, the back contact battery includes: a semiconductor substrate 11, a first doped semiconductor layer 17, an intrinsic semiconductor layer 20, a second doped semiconductor layer 21, and an insulating mask layer 22. The semiconductor substrate 11 has opposing first and second surfaces. The second surface has alternating first regions 14 and second regions 15, and an isolation region 16 located between each first region 14 and its adjacent second region 15. The first doped semiconductor layer 17 is formed on the first region 14 and a portion of the isolation region 16. The portion of the first doped semiconductor layer 17 on the first region 14 is a first doped portion 18, and the remaining portion is a second doped portion 19. The doping concentration of impurities in the second doped portion 19 is less than the doping concentration of impurities in the first doped portion 18. The intrinsic semiconductor layer 20 is formed on the portion of the isolation region 16 other than the second doped portion 19 and is integrally formed with the first doped semiconductor layer 17. The second doped semiconductor layer 21 covers the second region 15, at least a portion of the intrinsic semiconductor layer 20, and at least a portion of the second doped portion 19. The second doped semiconductor layer 21 and the first doped semiconductor layer 17 have opposite conductivity types, and at least one of the second doped semiconductor layer 21 and the first doped semiconductor layer 17 is a doped silicon layer. The intrinsic semiconductor layer 20 is used to electrically isolate the first doped semiconductor layer 17 and the second doped semiconductor layer 21 along a direction parallel to the second surface. An insulating mask layer 22 is located between the second doped semiconductor layer 21 and the intrinsic semiconductor layer 20 and the second doped portion 19, respectively.

[0071] When the above technical solution is adopted, such as Figure 1As shown, the first doped semiconductor layer 17 and the second doped semiconductor layer 21 are both formed on one side of the second surface of the semiconductor substrate 11, and their conductivity types are opposite. Based on this, when the back contact battery is in operation, electrons and holes generated after the semiconductor substrate 11 absorbs photons move toward the first doped semiconductor layer 17 and the second doped semiconductor layer 21, respectively, and are collected and discharged by them to form a photocurrent. Specifically, along the thickness direction of the semiconductor substrate 11, the second doped semiconductor layer 21 is formed not only on the second region 15 of the second surface of the semiconductor substrate 11, but also covers at least a portion of the intrinsic semiconductor layer 20 and at least a portion of the second doped portion 19 included in the first doped semiconductor layer 17. Furthermore, an insulating mask layer 22 is located between the second doped semiconductor layer 21 and the intrinsic semiconductor layer 20 and the second doped portion 19, respectively. Since the insulating mask layer 22 is a non-conductive film, its presence can electrically isolate the second doped semiconductor layer 21 and the second doped portion 19, which have opposite conductivity types, along the thickness direction of the semiconductor substrate 11, preventing leakage current from occurring between them along the thickness direction of the semiconductor substrate 11. Secondly, an intrinsic semiconductor layer 20 is formed between the first doped semiconductor layer 17 and the second doped semiconductor layer 21 along a direction parallel to the second surface of the semiconductor substrate 11. This intrinsic semiconductor layer 20 electrically isolates the first doped semiconductor layer 17 and the second doped semiconductor layer 21 along a direction parallel to the second surface, preventing leakage current between them and further reducing the carrier recombination rate on one side of the second surface of the semiconductor substrate 11, which is beneficial to improving the photoelectric conversion efficiency of the back contact cell. In addition, in the actual manufacturing process, due to the precision of the equipment and / or for the purpose of preventing leakage current, the width of the isolation region 16 located between the first region 14 and the adjacent second region 15 is relatively large. Based on this, the first doped semiconductor layer 17 includes not only the first doped portion 18 located on the first region 14, but also the second doped portion 19 located on the partial isolation region 16. When the back contact battery is in operation, the first doped semiconductor layer 17 can not only collect and export electrons or holes in the corresponding first region 14 in a timely manner, but also collect and export electrons or holes in the corresponding partial isolation region 16 in a timely manner. Therefore, while preventing lateral leakage of the first doped semiconductor layer 17 and the second doped semiconductor layer 21 through the intrinsic semiconductor layer 20, it can also reduce the carrier recombination rate in the wider isolation region 16, further improving the photoelectric conversion efficiency of the back contact battery.Furthermore, since the second doped portion 19 is located between the first doped portion 18 and the intrinsic semiconductor layer 20, when the doping concentration of the impurities in the second doped portion 19 located on the partial isolation region 16 is less than the doping concentration of the impurities in the first doped portion 18 located on the first region 14, the conductivity of the second doped portion 19 can be reduced, the electrical breakdown penetration of the intrinsic semiconductor layer 20 can be reduced, and at the same time, the diffusion of impurities in the second doped portion 19 into the intrinsic semiconductor layer 20 can be suppressed or even eliminated, ensuring that the intrinsic semiconductor layer 20 has a good electrical isolation effect and ensuring that the back contact battery has good electrical performance.

[0072] In practical applications, from a material perspective, the aforementioned semiconductor substrate can be a silicon substrate, a germanium-silicon substrate, or a germanium substrate, etc. From a conductivity type perspective, the aforementioned semiconductor substrate can be an N-type semiconductor substrate or a P-type semiconductor substrate. Structurally, the first surface of the semiconductor substrate corresponds to the light-facing surface of the back contact battery, and the second surface of the semiconductor substrate corresponds to the back-light-receiving surface of the back contact battery. Based on this, as... Figure 1 and Figure 2 As shown, both the light-facing and back-facing surfaces of the semiconductor substrate 11 can be polished surfaces, i.e., relatively flat surfaces. Alternatively, as... Figure 3 As shown, both the light-facing surface of the semiconductor substrate 11 and the surface of the corresponding second region 15 of the semiconductor substrate 11 are textured. In this case, the refractive index of light transmitted from the first surface and the surface of the second region 15 to the semiconductor substrate 11 can be increased, further improving the photoelectric conversion efficiency of the back contact cell. In addition, when the surface of the second region 15 is textured, the back-facing side of the second doped semiconductor layer 21 formed on the second region 15 also has corresponding undulation characteristics. Compared with a plane, a surface with undulation characteristics has a larger specific surface area. Therefore, when the back-facing side of the second doped semiconductor layer 21 on the second region 15 has undulation characteristics, it is beneficial to increase the contact area between the second doped semiconductor layer 21 and the electrode 36, reduce the contact resistance between them, and further improve the electrical performance of the back contact cell.

[0073] In addition, such as Figure 1As shown, the semiconductor substrate 11 has alternating first regions 14 and second regions 15, and an isolation region 16 located between each first region 14 and its adjacent second region 15. It should be understood that the boundaries between the first regions 14, second regions 15, and isolation regions 16 are virtual boundaries. Furthermore, since the portion of the first doped semiconductor layer 17 not covered by the insulating mask layer 22 (the first doped portion 18) is formed on the first region 14, the position, number, and specifications of the first region 14 on the backlight surface of the semiconductor substrate 11 affect the position, number, and specifications of the first doped portions 18 included in the subsequently formed first doped semiconductor layer 17. Correspondingly, since the second doped semiconductor layer 21 is formed in the second region 15 and covers at least a portion of the second doped portions 19 and at least a portion of the intrinsic semiconductor layer 20, the position, number, and specifications of the second region 15 on the semiconductor substrate 11 affect the position, number, and specifications of the portion of the subsequently formed second doped semiconductor layer 21 that directly contacts the semiconductor substrate 11. As for the location of the aforementioned isolation region 16, after the ranges of the first region 14 and the second region 15 are determined, the remaining area on the second surface is the isolation region 16. Based on this, the specific location, quantity, and specifications of the aforementioned first region 14, second region 15, and isolation region 16 on the semiconductor substrate 11 can be set according to the requirements of information such as the location of the corresponding parts of the first doped semiconductor layer 17 and the second doped semiconductor layer 21 in the actual application scenario, and are not specifically limited here.

[0074] Regarding the aforementioned first doped semiconductor layer, in terms of conductivity type, the first doped portion and the second doped portion of the first doped semiconductor layer have the same conductivity type; the conductivity type of the first doped semiconductor layer can be N-type or P-type; the specific conductivity type of the first doped semiconductor layer can be determined according to the actual application scenario, and is not specifically limited here. In terms of material, the first doped semiconductor layer can be a doped amorphous silicon layer or a doped crystalline silicon layer; when the first doped semiconductor layer is a doped crystalline silicon layer, the material of the first doped semiconductor layer can include microcrystalline silicon, monocrystalline silicon, polycrystalline silicon, and nanocrystalline silicon, etc.

[0075] It is worth noting that, compared to doped amorphous silicon layers, doped crystalline silicon layers exhibit higher carrier lateral transport characteristics. Furthermore, as... Figure 1As shown, a portion of the insulating mask layer 22 and a portion of the second doped semiconductor layer 21 cover the second doped portion 19. Therefore, when the first doped semiconductor layer 17 is a doped silicon layer, the second doped portion 19 has good lateral carrier transport characteristics, which facilitates the lateral transport of more electrons or holes collected by the second doped portion 19 to the first doped portion 18, and their discharge through the exposed first doped portion 18, further reducing the carrier recombination efficiency at the isolation region 16. At the same time, it also enables the first doped portion 18 to have higher carrier collection characteristics, reducing the carrier recombination efficiency at the first region 14.

[0076] As for the first doped semiconductor layer, including the first doped portion and the second doped portion, in terms of impurity doping concentration, the specific doping concentration of impurities in the first doped portion and the second doped portion can be determined according to the actual application scenario, as long as the doping concentration of impurities in the second doped portion is less than the doping concentration of impurities in the first doped portion.

[0077] For example, the doping concentration of the impurities in the second doped portion is greater than or equal to 1E18 cm⁻¹. -3 And less than or equal to 5E20cm -3 For example, the doping concentration of impurities in the second doped region can be 1E18 cm⁻¹. -3 5E18 cm -3 1E19 cm -3 5E19cm -3 1E20cm -3 Or 5E20cm -3 In this case, when the doping concentration of the impurities in the second doped section is within the aforementioned range, it can prevent poor carrier collection ability due to a low doping concentration of the impurities in the second doped section, and further improve the degree to which the carrier recombination rate at the isolation region is reduced through the second doped section. Additionally, it can prevent carriers in the second doped section from easily diffusing into the intrinsic semiconductor layer due to a high doping concentration of the impurities, ensuring that the intrinsic semiconductor layer has good electrical isolation.

[0078] For example, along the direction from the second doped portion to the intrinsic semiconductor layer, the doping concentration of impurities in the second doped portion gradually decreases. In this case, while ensuring that the impurities in the second doped portion have a certain doping concentration, thereby enabling the second doped portion to have a certain lateral carrier collection capability, the portion of the second doped portion with the lowest impurity doping concentration can also contact the intrinsic semiconductor layer, reducing the carrier concentration gradient at the contact point, further suppressing or even eliminating the diffusion of impurities from the second doped portion into the intrinsic semiconductor layer, and ensuring that the intrinsic semiconductor layer has good electrical isolation.

[0079] The extent to which the doping concentration of impurities in the second doped section gradually decreases along the direction from the second doped section to the intrinsic semiconductor layer can be determined according to the actual application scenario, and no specific limitation is made here.

[0080] For example, the doping concentration of the impurities in the first doped portion is 10 to 100 times that of the impurities in the second doped portion. For instance, when the doping concentration of the impurities in the second doped portion is 1E18 cm⁻¹ -3 At that time, the doping concentration of impurities in the first doped section can be 1E19 cm⁻¹. -3 3E19 cm -3 5E19 cm -3 7E19cm -3 Or 1E20cm -3 In this case, the higher doping concentration of impurities in the first doped section allows it to have a higher carrier collection capability. Furthermore, it reduces the manufacturing difficulty of obtaining a first doped section with an excessively high doping concentration.

[0081] In terms of dimensions, since the second doped portion and the intrinsic semiconductor layer are both located on the isolation region, and along the direction from the first region to the second region, the width of the intrinsic semiconductor layer affects its isolation effect. Therefore, the width of the intrinsic semiconductor layer and the width of the isolation region can be determined according to the requirement in the actual application scenario that the first doped semiconductor layer and the second doped semiconductor layer are electrically isolated along a direction parallel to the second surface by the intrinsic semiconductor layer. Furthermore, the width of the second doped portion can be determined based on the width of the intrinsic semiconductor layer and the width of the isolation region. This embodiment of the invention does not specifically limit the widths of the second doped portion, the intrinsic semiconductor layer, and the isolation region.

[0082] For example, along the direction from the second doped portion to the intrinsic semiconductor layer, the width of the isolation region can be greater than or equal to 30 μm and less than or equal to 200 μm. For instance, the width of the isolation region can be 30 μm, 50 μm, 80 μm, 100 μm, 150 μm, or 200 μm, etc. In this case, the width of the isolation region is within the above range, which prevents the second doped portion and the intrinsic semiconductor layer from being too small to be properly positioned within a small width range, ensuring that the second doped portion and the intrinsic semiconductor layer have the functions described above. Furthermore, it also prevents the first doped semiconductor layer and / or the second doped semiconductor layer from being too small due to the larger width of the intrinsic semiconductor layer causing the width of the first region and / or the second region located on one side of the second surface to be too small, ensuring that the first doped semiconductor layer and the second doped semiconductor layer can collect and export the carriers corresponding to the first region and the second region in a timely manner, further reducing the carrier recombination rate on one side of the second surface.

[0083] For example, along the direction from the second doped portion to the intrinsic semiconductor layer, the width of the intrinsic semiconductor layer can be greater than or equal to 6 μm and less than or equal to 120 μm. For instance, the width of the intrinsic semiconductor layer can be 6 μm, 10 μm, 20 μm, 50 μm, 80 μm, 100 μm, 110 μm, or 120 μm, etc. In this case, the width of the intrinsic semiconductor layer within the above range can prevent its electrical isolation effect along the parallel second direction from being affected by a small intrinsic semiconductor layer width, ensuring that leakage current is prevented between the first doped semiconductor layer and the second doped semiconductor layer along the parallel second surface. Furthermore, it can also prevent the second doped portion from having a small width due to a large intrinsic semiconductor layer width, thus preventing a low carrier collection capacity and further improving the degree to which the carrier recombination rate at the isolation region is reduced by the second doped portion.

[0084] For example, along the direction from the second doped portion to the intrinsic semiconductor layer, the ratio of the width of the second doped portion to the width of the isolation region can be greater than or equal to 0.8 and less than 1. For instance, the ratio of the width of the second doped portion to the width of the isolation region can be 0.8, 0.82, 0.84, 0.86, 0.88, 0.9, or 0.92, etc. In this case, when the ratio of the width of the second doped portion to the width of the isolation region is within the above range along the direction from the second doped portion to the intrinsic semiconductor layer, the width of the second doped portion is greater than the width of the intrinsic semiconductor layer. This prevents the reduction in carrier recombination rate at the isolation region due to a small width of the second doped portion, ensuring a high photoelectric conversion efficiency for the back contact cell. Furthermore, since the second doped portion and the intrinsic semiconductor layer are both located on the isolation region, when the width of the isolation region is constant, the width of the second doped portion is inversely proportional to the width of the intrinsic semiconductor layer. Moreover, within a certain range, the electrical isolation effect of the intrinsic semiconductor layer along the direction parallel to the second surface is directly proportional to its width. Based on this, when the ratio is within the above range, it can also prevent the poor electrical isolation effect of the intrinsic semiconductor layer due to the small width of the second doped portion, and ensure that leakage current is prevented between the first doped semiconductor layer and the second doped semiconductor layer along the parallel second surface through the intrinsic semiconductor layer.

[0085] The specific width of the second doped region can be determined based on the width of the isolation region and the ratio of the width of the second doped region to the width of the isolation region. For example, when the width of the isolation region is greater than or equal to 30 μm and less than or equal to 200 μm, and the ratio of the width of the second doped region to the width of the isolation region is equal to 0.8, the width of the second doped region can be 24 μm, 50 μm, 80 μm, 100 μm, 150 μm, or 160 μm, etc.

[0086] Regarding the aforementioned intrinsic semiconductor layer, the integral molding of the intrinsic semiconductor layer and the first doped semiconductor layer means that the intrinsic semiconductor layer and the first doped semiconductor layer are formed simultaneously based on the same intrinsic semiconductor material layer. Therefore, the thickness of the intrinsic semiconductor layer is equal to the thickness of the first doped semiconductor layer, and the material of the intrinsic semiconductor layer can be referenced to the material of the first doped semiconductor layer. For example, when the material of the first doped semiconductor layer is doped polysilicon, the material of the intrinsic semiconductor layer is intrinsic polysilicon.

[0087] Regarding the second doped semiconductor layer, in terms of conductivity type, when the first doped semiconductor layer is N-type, the second doped semiconductor layer is P-type; conversely, when the first doped semiconductor layer is P-type, the second doped semiconductor layer is N-type. In terms of material, when the first doped semiconductor layer is amorphous silicon, the second doped semiconductor layer is crystalline silicon; the specific material of this crystalline silicon layer can be found above. When the first doped semiconductor layer is crystalline silicon, the second doped semiconductor layer can be either amorphous silicon or crystalline silicon. The specific material of the second doped semiconductor layer can be determined based on the material of the first doped semiconductor layer and the actual application scenario; no specific limitations are made here.

[0088] It should be noted that when one of the materials of the first doped semiconductor layer and the second doped semiconductor layer is doped amorphous silicon and / or doped microcrystalline silicon, such as Figure 2 and Figure 3 As shown, the aforementioned back contact battery may further include a transparent conductive layer 35 covering the first doped portion 18 and the second doped semiconductor layer 21 to improve the carrier collection rate. Furthermore, the transparent conductive layer 35 has a through-hole insulating trench formed on the portion corresponding to the isolation region 16 to prevent leakage between the first doped semiconductor layer 17 and the second doped semiconductor layer 21 through the transparent conductive layer 35. Specifically, the insulating trench may penetrate only the transparent conductive layer 35, or it may penetrate both the transparent conductive layer 35 and the second doped semiconductor layer 21. Additionally, this embodiment of the invention does not specifically limit the material and thickness of the transparent conductive layer 35.

[0089] The extent to which the second doped semiconductor layer is formed can be determined based on the specific structure of the back contact cell. For example... Figure 1 As shown, in the case where the back contact cell does not include a transparent conductive layer, the second doped semiconductor layer 21 can cover the second region 15, the entire intrinsic semiconductor layer 20, and the entire second doped portion 19. For example... Figure 2 and Figure 3 As shown, in the case where the back contact battery includes the above-mentioned transparent conductive layer 35 and the insulating trench penetrates the transparent conductive layer 35 and the second doped semiconductor layer 21, the second doped semiconductor layer 21 covers the second region 15, part of the intrinsic semiconductor layer 20 and part of the second doped portion 19.

[0090] For the aforementioned insulating mask layer, the material of the insulating mask layer can be any insulating material with a masking function, as long as it can be applied to the back contact battery provided in the embodiments of the present invention. For example, the material of the insulating mask layer can be silicon nitride, silicon oxynitride, or silicon oxycarbide, etc. The thickness of the insulating mask layer can also be determined according to actual needs. For example, the thickness of the insulating mask layer can be greater than or equal to 10 nm and less than or equal to 200 nm.

[0091] As one possible implementation scheme, such as Figure 3 As shown, the aforementioned back contact battery may further include a first passivation layer 23, which is located between the semiconductor substrate 11 and the first doped semiconductor layer 17 and the intrinsic semiconductor layer 20, respectively. In this case, the selective contact structure composed of the first passivation layer 23 and the first doped semiconductor layer 17 has excellent interface passivation effect and can achieve selective collection of charge carriers, reducing the carrier recombination rate in the first region 14 and part of the isolation region 16 on the back surface of the semiconductor substrate 11, and further improving the photoelectric conversion efficiency of the back contact battery.

[0092] Specifically, the material of the first passivation layer can be determined according to the requirements of the selective contact structure formed by the first passivation layer and the first doped semiconductor layer in the actual application scenario, and no specific limitation is made here. For example, when the actual application scenario requires the selective contact structure formed by the first passivation layer and the first doped semiconductor layer to be a tunneling passivation contact structure, the first passivation layer is a tunneling passivation layer (the material of the tunneling passivation layer can be silicon oxide, titanium oxide, or aluminum oxide, etc.), and the first doped semiconductor layer is a doped polycrystalline silicon layer. As another example, when the actual application scenario requires the selective contact structure formed by the first passivation layer and the first doped semiconductor layer to be a heterogeneous contact structure, the material of the first passivation layer includes intrinsic amorphous silicon and / or intrinsic microcrystalline silicon, and the material of the first doped semiconductor layer is doped amorphous silicon and / or doped microcrystalline silicon.

[0093] Preferably, when the back contact battery further includes a first passivation layer, and the first passivation layer is a tunneling passivation layer, the material of the first doped semiconductor layer is doped polycrystalline silicon, and the conductivity type is N-type. In this case, because the contact resistance between the P-type doped polycrystalline silicon layer and the electrode is high, and the field passivation effect is poor, when the back contact battery includes a tunneling passivation layer as the first passivation layer and a doped polycrystalline silicon layer, and the conductivity type of the first doped semiconductor layer is N-type, the field passivation effect of the first doped semiconductor layer can be further improved, while the contact resistance between the first doped portion and the electrode can be reduced, which is beneficial to improving the electrical performance of the back contact battery. Furthermore, as... Figures 5 to 15As shown, the intrinsic semiconductor layer 20 is integrally formed with the first doped semiconductor layer 17, and the second doped semiconductor layer 21 is also located on at least a portion of the intrinsic semiconductor layer 20 and at least a portion of the second doped portion 19 included in the first doped semiconductor layer 17. Therefore, the formation sequence of the first doped semiconductor layer 17 is before the formation sequence of the second doped semiconductor layer 21. In addition, polycrystalline silicon has better heat resistance characteristics compared with amorphous silicon. Based on this, when the back contact cell also includes a first passivation layer 23, and the first passivation layer 23 is a tunneling passivation layer and the material of the first doped semiconductor layer 17 is doped polycrystalline silicon, if a laser etching process is used to remove the portion of the material layer used to manufacture the second doped semiconductor layer 21 corresponding to the first region 14, the first doped semiconductor layer, which is made of doped polycrystalline silicon, is less affected by the high-temperature laser or even unaffected by the high-temperature laser, which is beneficial to improving the yield of the back contact cell. Furthermore, in actual manufacturing processes, the manufacturing cost of heterogeneous contact structures is higher than that of tunneling passivation contact structures. Moreover, tunneling passivation contact structures can be fabricated using various processes such as low-pressure chemical vapor deposition (LPCVD), plasma chemical vapor deposition (PCVDC), physical chemical vapor deposition (PCVDC), or plasma-enhanced atomic layer deposition (PEALD), making them more compatible with back contact battery processes. In contrast, heterogeneous contact structures require plate-type PCVDC equipment with lower formation temperatures. Therefore, when the first passivation layer of the back contact battery is a tunneling passivation layer and the first doped semiconductor layer is made of doped polycrystalline silicon, it helps to reduce manufacturing costs, lower the investment in plate-type PCVDC equipment, and save production space.

[0094] Specifically, the embodiments of the present invention do not impose specific limitations on the thickness of the tunneling passivation layer and the first doped semiconductor layer. For example, the thickness of the tunneling passivation layer can be greater than or equal to 1 nm and less than or equal to 4 nm. The thickness of the first doped semiconductor layer can be greater than or equal to 30 nm and less than or equal to 250 nm.

[0095] As one possible implementation scheme, such as Figure 3 As shown, the aforementioned back contact battery may further include a second passivation layer 24, which is located between the second doped semiconductor layer 21 and the semiconductor substrate 11, the intrinsic semiconductor layer 20, and the second doped portion 19, respectively. In this case, the selective contact structure formed by the second passivation layer 24 and the second doped semiconductor layer 21 can achieve selective collection of charge carriers, reducing the carrier recombination rate in the second region 15 of the back surface of the semiconductor substrate 11. Simultaneously, the second passivation layer 24 and the intrinsic semiconductor layer 20 are also located between the portion of the second doped semiconductor layer 21 located in the second region 15 and the second doped portion 19. Both can suppress the carrier recombination rate at a portion of the interface between the second doped semiconductor layer 21 and the corresponding isolation region 16 of the first doped semiconductor layer 17, further improving the photoelectric conversion efficiency of the back contact battery.

[0096] Specifically, the material of the second passivation layer can be determined according to the requirements of the selective contact structure formed by the second passivation layer and the second doped semiconductor layer in the actual application scenario, and no specific limitation is made here. For example, when the actual application scenario requires the selective contact structure formed by the second passivation layer and the second doped semiconductor layer to be a tunneling passivation contact structure, the second passivation layer is a tunneling passivation layer, and the second doped semiconductor layer is a doped polycrystalline silicon layer. As another example, when the actual application scenario requires the selective contact structure formed by the second passivation layer and the second doped semiconductor layer to be a heterogeneous contact structure, the material of the second passivation layer includes intrinsic amorphous silicon and / or intrinsic microcrystalline silicon, and the material of the second doped semiconductor layer is doped amorphous silicon and / or doped microcrystalline silicon.

[0097] Preferably, when the back contact battery further includes a second passivation layer, and the material of the second passivation layer includes intrinsic amorphous silicon and / or intrinsic microcrystalline silicon, the material of the second doped semiconductor layer is doped amorphous silicon and / or doped microcrystalline silicon, and the conductivity type is P-type.

[0098] Specifically, the embodiments of the present invention do not impose specific limitations on the thickness of the passivation layer and the second doped semiconductor layer. For example, when the material of the second passivation layer includes intrinsic amorphous silicon and / or intrinsic microcrystalline silicon, the thickness of the second passivation layer can be greater than or equal to 2 nm and less than or equal to 10 nm. The thickness of the second doped semiconductor layer can be greater than or equal to 5 nm and less than or equal to 30 nm.

[0099] As mentioned above, when using the above technical solution, compared with P-type doped amorphous silicon and / or doped microcrystalline silicon layers, the P-type doped polycrystalline silicon layer has a higher contact resistance with the electrode and a poorer field passivation effect. Therefore, in the above case, setting the conductivity type of the second doped semiconductor layer to P-type, instead of setting the conductivity type of the tunneling passivation contact structure to P-type, can further improve the field passivation effect of the first doped semiconductor layer, and at the same time reduce the contact resistance between the first doped part and the electrode, which is beneficial to improving the electrical performance of the back contact battery.

[0100] In some cases, such as Figure 2 and Figure 3 As shown, the back contact battery provided in this embodiment of the invention may further include electrodes 36 electrically coupled to the first doped portion 18 and the second doped semiconductor layer 21, respectively, to extract carriers of the corresponding conductivity type. Specifically, the material of the electrodes 36 may be conductive materials such as silver, aluminum, copper, nickel, or titanium.

[0101] In some cases, such as Figure 3As shown, the back-contact battery provided in this embodiment of the invention may further include an interface passivation layer 37 and an anti-reflection layer 38 sequentially stacked on the first surface to reduce the carrier recombination rate on one side of the first surface and increase the refractive index of the first surface on light. Specifically, the materials and thicknesses of the interface passivation layer 37 and the anti-reflection layer 38 can be determined according to the actual application scenario, and are not specifically limited here.

[0102] For example, the material of the interface passivation layer can be intrinsic amorphous silicon, and the material of the antireflection layer can be silicon nitride.

[0103] Secondly, embodiments of the present invention provide a method for manufacturing a back-contact battery. The following will describe, based on... Figures 4 to 17 The cross-sectional view shown illustrates the manufacturing process. Specifically, the manufacturing method of this back contact battery includes the following steps:

[0104] First, such as Figure 4 As shown, a semiconductor substrate 11 is provided. The semiconductor substrate 11 has a first surface 12 and a second surface 13 facing each other. The second surface 13 has alternating first regions 14 and second regions 15, and an isolation region 16 located between each first region 14 and the second region 15 adjacent to it.

[0105] For specific information on the semiconductor substrate material and conductivity type, please refer to the previous text; it will not be repeated here.

[0106] Next, as Figure 5 As shown, an intrinsic semiconductor material layer 25 is formed on the second surface.

[0107] In the actual manufacturing process, the aforementioned intrinsic semiconductor material layer is used to manufacture the first doped semiconductor layer and the intrinsic semiconductor layer mentioned above. Therefore, the material, thickness, and formation process of the intrinsic semiconductor material layer can be determined based on the material and thickness of the first doped semiconductor layer and the intrinsic semiconductor layer.

[0108] For example, when the materials of the first doped semiconductor layer and the intrinsic semiconductor layer are polycrystalline silicon, they can be formed using processes such as low-pressure chemical vapor deposition, plasma chemical vapor deposition, and plasma-enhanced atomic layer deposition. As another example, when the materials of the first doped semiconductor layer and the intrinsic microcrystalline silicon layer are amorphous silicon, they can be formed using processes such as plasma chemical vapor deposition.

[0109] Furthermore, when the manufactured back contact battery also includes a first passivation layer located between the semiconductor substrate and the first doped semiconductor layer and the intrinsic semiconductor layer, such as Figure 5As shown, after providing a semiconductor substrate 11 and before forming an intrinsic semiconductor material layer 25 integrally disposed on the second surface, the method for manufacturing a back contact battery further includes the step of forming a first passivation material layer 33 integrally disposed on the second surface.

[0110] Specifically, the formation process of the first passivation material layer can be determined according to the type of material of the first passivation material layer. For example, when the material of the first passivation material layer includes silicon oxide and the semiconductor substrate is a silicon substrate, the first passivation material layer can be formed by reacting oxygen with the semiconductor substrate at high temperature, or by wet chemical methods (such as reacting the semiconductor substrate with ozone or oxidizing the semiconductor substrate with nitric acid).

[0111] Next, as Figure 6 and Figure 7 As shown, a first mask layer 26 is formed; this first mask layer 26 covers the portion of the intrinsic semiconductor material layer 25 corresponding to the second region 15 and the isolation region 16. Under the masking effect of the first mask layer 26, the portion of the intrinsic semiconductor material layer 25 located in the first region 14 is selectively doped, so that the portion of the intrinsic semiconductor material layer 25 located in the first region 14 and part of the isolation region 16 forms a first doped semiconductor layer 17, and the portion of the intrinsic semiconductor material layer 25 located in the remaining isolation region 16 forms an intrinsic semiconductor layer 20. The portion of the first doped semiconductor layer 17 located in the first region 14 is a first doped portion 18, and the remaining portion is a second doped portion 19. The doping concentration of impurities in the second doped portion 19 is less than the doping concentration of impurities in the first doped semiconductor layer 17.

[0112] In the actual manufacturing process, such as Figure 5 As shown, after forming the intrinsic semiconductor material layer 25, a first mask material layer can be formed entirely on the intrinsic semiconductor material layer 25 using processes such as chemical vapor deposition. Then, as... Figure 6 As shown, laser etching or similar processes can be used to remove the portion of the first mask material layer corresponding to the first region 14, forming the first mask layer 26. The material of the first mask layer 26 can be any material with a masking function, as long as it can be applied to the manufacturing method of the back contact battery provided in this embodiment of the invention. For example, the material of the first mask layer 26 can be silicon oxide or silicon nitride, etc. Then, as... Figure 7 As shown, diffusion, ion implantation or doping source coating processes can be used to selectively dope the portion of the intrinsic semiconductor material layer 25 located in the first region 14 to form the first doped semiconductor layer 17 and the intrinsic semiconductor layer 20.

[0113] It is understood that, since the second doped portion of the first doped semiconductor layer is located below the first mask layer, and impurities are transferred from the first doped portion to the second doped portion through diffusion, when the width of the second doped portion is small, it can be directly formed through the aforementioned selective doping. However, when the width of the second doped portion is greater than or equal to 6 μm and less than or equal to 120 μm along the direction from the second doped portion to the intrinsic semiconductor layer, after selective doping of the portion of the intrinsic semiconductor material layer located in the first region, and before subsequent operations, such as... Figure 8 As shown, the first doped semiconductor layer 17 and the intrinsic semiconductor layer 20 are annealed to make the width of the second doped portion 19 reach the target width. In this case, the second doped portion 19 is formed by diffusion when the portion of the intrinsic semiconductor material layer 25 located in the first region 14 is selectively doped under the masking effect of the first mask layer 26. Based on this, in the direction from the second doped portion 19 to the intrinsic semiconductor layer 20, when the width of the second doped portion 19 is greater than or equal to 6 μm and less than or equal to 120 μm, the width of the second doped portion 19 is relatively large. At this time, annealing the first doped semiconductor layer 17 and the intrinsic semiconductor layer 20 after selective doping can make the impurities in the second doped portion 19, or the first doped portion 18 and the second doped portion 19, diffuse a longer distance in a direction parallel to the second surface after heating, thereby obtaining a second doped portion 19 with an actual width reaching the target width.

[0114] For example, if the width of the second doped portion is 6μm, 10μm, 20μm, 50μm, 80μm, 100μm, 110μm or 120μm along the direction from the second doped portion to the intrinsic semiconductor layer, the first doped semiconductor layer and the intrinsic semiconductor layer can be subjected to the above-mentioned annealing treatment after selectively doping the portion of the intrinsic semiconductor material layer located on the first region and before performing subsequent operations.

[0115] The annealing conditions can be determined based on the specific width of the second doped portion and the actual application scenario; no specific limitations are made here.

[0116] Then, as Figure 9 As shown, the first mask layer is removed. Specifically, the process and conditions used to remove the first mask layer can be determined based on the material of the first mask layer and the actual application scenario; no specific limitations are made here. For example, if the material of the first mask layer is silicon oxide, a wet etching process can be used, and the first mask layer can be removed using a hydrogen fluoride solution.

[0117] Next, as Figure 11 and Figure 12As shown, at least an insulating mask layer 22 is formed covering the first doped semiconductor layer 17 and the intrinsic semiconductor layer 20; and at least under the masking effect of the insulating mask layer 22, the portion of the intrinsic semiconductor material layer 25 remaining on the second region 15 is selectively removed.

[0118] Specifically, the material and thickness of the insulating mask layer can be found in the previous text, and will not be repeated here.

[0119] In the actual manufacturing process, a chemical vapor deposition (CVD) process can be used to form a continuous insulating mask material layer on the portion of the first doped semiconductor layer, the intrinsic semiconductor layer, and the remaining intrinsic semiconductor material layer in the second region. Then, a laser etching process can be used to remove the portion of the insulating mask material layer above the second region, forming an insulating mask layer. Finally, a laser etching process can be used, selectively removing the portion of the intrinsic semiconductor material layer remaining in the second region only under the masking effect of the insulating mask layer.

[0120] Alternatively, after removing the first mask layer and before forming the second doped semiconductor layer 21 on the insulating mask layer and the second region, the method for manufacturing the back contact cell may include the steps of: Figure 10 As shown, a mask material layer 27 is formed integrally on the portion of the first doped semiconductor layer 17, the intrinsic semiconductor layer 20, and the intrinsic semiconductor material layer 25 remaining on the second region 15. Then, as... Figure 11 As shown, the portion of the mask material layer above the second region 15 is removed, and the remaining portion of the mask material layer forms the second mask layer 28. Next, as... Figure 12 As shown, under the masking effect of the second mask layer 28, the portion of the intrinsic semiconductor material layer 25 remaining in the second region 15 is selectively removed. Then, as... Figure 13 As shown, under the masking effect of at least a portion of the second mask layer, the first surface of the semiconductor substrate 11 and the surface of the corresponding second region 15 of the semiconductor substrate 11 are texturized. After texturing, at least a portion of the second mask layer forms an insulating mask layer 22. In this case, the presence of the aforementioned second mask layer 28 can prevent the selective removal of the portion of the intrinsic semiconductor material layer 25 remaining on the second region 15 from being affected by etching operations and subsequent texturing processes. Simultaneously, texturing the surfaces of the first surface and the second region 15 of the semiconductor substrate 11 can increase the refractive index of light on the surfaces of the first surface and the second region 15, thereby improving the photoelectric conversion efficiency of the manufactured back contact cell.

[0121] Specifically, the embodiments of the present invention do not impose specific limitations on the manufacturing process of the mask material layer described above, nor on the material of the second mask layer formed based on the mask material layer, as long as it can be used to manufacture an insulating mask layer and has a masking function during the texturing process. Furthermore, processes such as laser etching can be used to sequentially remove the portion of the mask material layer above the second region and the remaining portion of the intrinsic semiconductor material layer on the second region. In this case, because laser etching has high etching precision, using laser etching to sequentially remove the portion of the mask material layer above the second region and the remaining portion of the intrinsic semiconductor material layer on the second region can improve the yield of the manufactured back contact battery.

[0122] In practical applications, the material of the second mask layer can be the same as that of the insulating mask layer. In this case, after texturing, the remaining portion of the second mask layer forms an insulating mask layer.

[0123] Or, such as Figure 12 As shown, the second mask layer 28 may also include a first silicon nitride layer 29 and a second silicon nitride layer 30 spaced apart along the thickness direction of the semiconductor substrate 11, and an intrinsic silicon layer 31 located between the first silicon nitride layer 29 and the second silicon nitride layer 30. In the above case, after texturing the first surface of the semiconductor substrate 11 and the surface of the semiconductor substrate 11 corresponding to the second region 15, and before forming the second doped semiconductor layer on the insulating mask layer and the second region, the method for manufacturing the back contact battery further includes the step of sequentially removing the second silicon nitride layer 30 and the intrinsic silicon layer 31.

[0124] Under the aforementioned technical solution, and assuming other factors remain the same, compared to a single-layer second mask layer, when the second mask layer comprises a first silicon nitride layer, an intrinsic silicon layer, and a second silicon nitride layer, the mask characteristics of the second mask layer can be improved, ensuring that the first doped semiconductor layer and the intrinsic semiconductor layer located beneath it can be protected through the second mask layer. Furthermore, when using laser etching to remove the portion of the mask material layer above the second region and the remaining portion of the intrinsic semiconductor material layer in the second region 15, because the laser spot is a Gaussian spot with higher energy at the center and lower energy at the edges, to completely remove the portion of the mask material layer above the second region and the remaining portion of the intrinsic semiconductor material layer in the second region, the edges of the laser spot pattern may partially cover the second mask layer. Additionally, the silicon nitride material's film properties change upon heating, enhancing its corrosion resistance. Therefore, during the subsequent texturing process, when the texturing solution etches to the boundary between the second region and the isolation region, it easily etches part of the surface of the semiconductor substrate and the intrinsic semiconductor layer corresponding to the boundary between the isolation region and the second region. When the second mask layer is only a single layer of silicon nitride, the edge portion of the second mask layer has strong corrosion resistance, resulting in an air gap between this part of the isolation region and the edge of the second mask layer. Because the size of this air gap is small, it is difficult for the subsequently formed second doped semiconductor layer to fill the air gap, and the current recombination rate in the region below the air gap is relatively high. In the above case, when the second mask layer includes a first silicon nitride layer, an intrinsic silicon layer, and a second silicon nitride layer, even if the outermost second silicon nitride layer is heated by the heat of the laser spot, resulting in increased corrosion resistance at its edge, it can still be removed by appropriately extending the etching time. Although the first silicon nitride layer located inside protrudes from the textured area after texturing, its edges are not irradiated by laser, which causes changes in the film properties. Furthermore, because the etching time is appropriately extended after the second silicon nitride layer is etched away to completely remove the intrinsic silicon layer covering the first silicon nitride layer, the portion of the first silicon nitride layer located in the textured area is also removed, thus preventing the formation of the aforementioned air gap. This reduces the carrier recombination rate at the boundary between the isolation region and the second region, further improving the photoelectric conversion efficiency of the back contact cell.

[0125] In the actual manufacturing process, as described above, the insulating mask layer is the portion of the first silicon nitride layer remaining in the isolation region. Therefore, the thickness of the first silicon nitride layer can be referenced to the thickness of the insulating mask layer. The intrinsic silicon layer can be an intrinsic amorphous silicon layer or an intrinsic crystalline silicon layer. The crystal state of the intrinsic amorphous silicon layer can be microcrystalline, single-crystal, polycrystalline, or nanocrystalline, etc. As for the thickness of the intrinsic silicon layer and the second silicon nitride layer, it can be determined according to the actual application scenario, and no specific limitation is made here.

[0126] For example, the thickness of the second silicon nitride layer can be greater than or equal to 10 nm and less than or equal to 200 nm. For instance, the thickness of the second silicon nitride layer can be 10 nm, 30 nm, 60 nm, 100 nm, 150 nm, or 200 nm, etc.

[0127] For example, the thickness of the intrinsic silicon layer can be greater than or equal to 10 nm and less than or equal to 100 nm. For instance, the thickness of the intrinsic silicon layer can be 10 nm, 20 nm, 40 nm, 60 nm, 80 nm, or 100 nm, etc.

[0128] Secondly, when the second mask layer comprises a first silicon nitride layer, an intrinsic silicon layer, and a second silicon nitride layer, the intrinsic silicon layer can be formed using processes such as low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD). The first and second silicon nitride layers can be formed using processes such as plasma-enhanced chemical vapor deposition (PECVD). The etchant used to remove the intrinsic silicon layer and the second silicon nitride layer can be determined based on the specific application scenario. For example, it could be a hydrogen fluoride solution.

[0129] It should be noted that if the manufactured back contact battery includes a first passivation layer located between the semiconductor substrate and the first doped semiconductor layer and the intrinsic semiconductor layer, and a first passivation material layer integrally formed before the formation of the intrinsic semiconductor material layer, then after selectively removing the portion of the intrinsic semiconductor material layer remaining in the second region, and before forming the second doped semiconductor layer on the second region and the insulating mask layer, the manufacturing method of the back contact battery further includes the step of: Figure 12 As shown, a portion of the first passivation material layer located in the second region 15 is selectively removed, so that the remaining portion of the first passivation material layer forms the first passivation layer 23. Specifically, the above selective removal process can be achieved using processes such as laser etching.

[0130] Next, as Figure 14 and Figure 15 As shown, a second doped semiconductor layer 21 is formed on the insulating mask layer 22 and the second region 15. The second doped semiconductor layer 21 and the first doped semiconductor layer 17 have opposite conductivity types, and at least one of the second doped semiconductor layer 21 and the first doped semiconductor layer 17 is a doped silicon layer. The intrinsic semiconductor layer 20 is used to electrically isolate the second doped semiconductor layer 21 and the first doped semiconductor layer 17.

[0131] In practical applications, processes such as plasma chemical vapor deposition can be used to form a continuous second doped semiconductor material layer on the second region and the second mask layer. Next, processes such as laser etching can be used to selectively remove portions of the second doped semiconductor material layer corresponding to the first region, leaving the remaining portion of the second doped semiconductor material layer to form the second doped semiconductor layer.

[0132] It should be noted that, in the case where the manufactured back contact battery also includes the second passivation layer described above, after selectively removing the portion of the intrinsic semiconductor material layer remaining on the second region and before forming the second doped semiconductor layer on the insulating mask layer and the second region, the manufacturing method of the back contact battery further includes: forming the second passivation layer on the insulating mask layer.

[0133] Specifically, the second passivation layer can be formed using appropriate deposition and etching processes before the formation of the second doped semiconductor material layer. Alternatively, as... Figure 14 As shown, a second passivation material layer 34 can also be formed entirely before the formation of the second doped semiconductor material layer 32. Then, as... Figure 15 As shown, after forming the second doped semiconductor material layer 32, processes such as laser etching are used to sequentially remove portions of the second doped semiconductor layer 21 and the second passivation material layer 34 corresponding to the first region 14. This simplifies the manufacturing process of the back contact battery and improves manufacturing efficiency.

[0134] Then, as Figure 15 As shown, the portion of the insulating mask layer 22 located on the first doped portion 18 is removed. Specifically, a process such as wet etching can be used to remove the portion of the insulating mask layer 22 located on the first doped portion 18.

[0135] In some cases, such as Figure 16 As shown, after removing the portion of the insulating mask layer 22 located on the first doped portion 18, an interface passivation layer 37 and an antireflection layer 38 can be formed on the first surface using processes such as chemical vapor deposition. Specifically, the materials and thicknesses of the interface passivation layer 37 and the antireflection layer 38 can be referred to the preceding text and will not be repeated here.

[0136] In some cases, after removing the portion of the insulating mask layer located on the first doped portion, processes such as physical vapor deposition can be used to form a transparent conductive layer that is entirely disposed on the first doped portion and the second doped semiconductor layer. Then, as... Figure 17 As shown, an insulating trench that penetrates at least through the transparent conductive layer 35 is formed using processes such as laser etching. Next, electrodes 36, electrically coupled to the first doped portion 18 and the second doped semiconductor layer 21, can be formed using methods such as screen printing, inkjet printing, or laser transfer. The material and thickness of the transparent conductive layer 35, as well as the material of the electrodes 36, can be referred to the preceding text and will not be repeated here.

[0137] The beneficial effects of the second aspect and its various implementations in the embodiments of the present invention can be referred to the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0138] The present invention also provides three embodiments to illustrate the manufacturing method and performance of the back contact battery provided in the embodiments of the present invention.

[0139] Example 1:

[0140] The first step is to put the silicon wafer into a tank-type polishing and cleaning machine for polishing and cleaning to remove the cutting damage layer on the first and second sides of the silicon wafer, and to control the polishing morphology of the two sides by controlling the temperature, time and concentration of the polishing solution.

[0141] The second step involves using chemical vapor deposition (CVD) to sequentially form a first passivation material layer (silicon oxide), an intrinsic semiconductor material layer (polycrystalline silicon), and a first mask material layer (silicon oxide) on the second side of the silicon wafer. Specifically, the first passivation material layer and the intrinsic semiconductor material layer are fabricated using a low-pressure chemical vapor deposition (LPCVD) furnace. The thickness of the first passivation material layer is 1.4 nm, and the thickness of the intrinsic semiconductor material layer is 50 nm. The first mask material layer is grown using LPCVD and has a thickness of 40 nm.

[0142] The third step involves selectively removing the corresponding first mask material layer on the first region using a laser etching process. The remaining portion of the first mask material layer forms the first mask layer. A 355nm picosecond laser is used as the laser in this process.

[0143] Fourth step: Under the masking effect of the first mask layer, phosphorus element is selectively doped into the part of the intrinsic semiconductor material layer corresponding to the first region by high temperature diffusion, so that the part of the intrinsic semiconductor material layer corresponding to the first region forms the first doped part, and the part of the intrinsic semiconductor material located in the partial isolation region and close to the first doped part forms the second doped part.

[0144] Step 5: Wet etching process is used, and the phosphorus-silicon glass layer formed on the first doped part after phosphorus diffusion is removed by HF solution, while the first mask layer is removed at the same time.

[0145] Step 6: Using a chemical vapor deposition (CVD) process, a first silicon nitride layer, an intrinsic amorphous silicon layer, and a second silicon nitride layer are sequentially formed. The intrinsic amorphous silicon layer is formed using plasma-enhanced chemical vapor deposition (PECVD) and has a thickness of 20 nm. Both the first and second silicon nitride layers are formed using PECVD and have a thickness of 60 nm.

[0146] Step 7: Selectively remove portions of the first silicon nitride material layer, the intrinsic amorphous silicon material layer, and the second silicon nitride material layer in the corresponding second region using laser etching to form a second mask layer. Then, under the masking effect of the second mask layer, selectively remove the remaining portion of the intrinsic semiconductor material layer in the second region using laser etching. A 532nm nanosecond laser is used as the laser.

[0147] Step 8: Under the masking effect of at least a portion of the second mask layer, the surfaces of the second region on the first and second sides of the silicon wafer are texturized. The texturing process serves two purposes: first, to remove the damaged layer from the second region surface after laser treatment, thus performing interface cleaning; second, to form a textured surface on the first and second sides. Next, a hydrogen fluoride solution is used to remove the intrinsic silicon layer and the second silicon nitride layer included in the second mask layer.

[0148] Step 9: Using chemical vapor deposition, an integrally formed intrinsic amorphous silicon layer and a P-type amorphous silicon layer are formed. The thickness of the intrinsic amorphous silicon layer is 5 nm, and the thickness of the P-type amorphous silicon layer is 15 nm.

[0149] Step 10: Remove the corresponding intrinsic amorphous silicon layer and P-type amorphous silicon layer on the first region using laser etching. A 532nm picosecond laser is used.

[0150] Step 11: Use a wet etching process to remove the first silicon nitride layer in the corresponding second mask layer on the first region. The main functional reagent used in the wet etching process is HF solution.

[0151] Step 12: Deposit an interface passivation layer of intrinsic amorphous silicon material and an anti-reflection layer of silicon nitride material on the first surface.

[0152] Step 13: Deposit a transparent conductive layer (TCO) on the first doped part and the second doped semiconductor layer, using an ITO film.

[0153] Step fourteen: An insulating trench is formed using laser etching to penetrate at least the transparent conductive layer, ensuring complete structural insulation between the two polarity regions. A 355nm picosecond laser is used.

[0154] Step 15: Print low-temperature silver paste over the two TCO electrodes using screen printing. Then anneal at 200°C for 30 minutes.

[0155] Example 2

[0156] The operation steps of Example 2 are identical to those of Example 1, except for the second step. The difference lies in the second step of Example 2, which alters the deposition method and thickness of the first mask material layer, reducing its fabrication time. Specifically, the first mask material layer is formed using plasma-enhanced chemical vapor deposition (PECVD) and has a thickness of 60 nm.

[0157] Example 3

[0158] The operation steps of Example 3 are identical to those of Example 1, except for step nine. In Example 3, step nine replaces the intrinsic amorphous silicon layer and P-type amorphous silicon layer with an intrinsic amorphous silicon layer and P-type microcrystalline silicon to improve the contact in the P-region. Specifically, the thickness of the P-type microcrystalline silicon layer is 25 nm.

[0159] Table 1 compares the parameters of the three back contact batteries described in Examples 1-3 by testing them.

[0160]

[0161] As shown in Table 1, the back contact battery formed using the manufacturing method provided in this embodiment of the invention has high efficiency. Furthermore, in Example 2, where only the deposition method and thickness of the first mask material layer are changed, without altering the final structure of the back contact battery, the corresponding data for Examples 1 and 2 are approximately the same. In Example 3, after replacing the P-type amorphous silicon layer with a P-type microcrystalline silicon layer with better conductivity, the efficiency and fill factor of the back contact battery are improved, while the bypass resistance and series resistance are reduced.

[0162] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0163] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A back-contact battery, characterized in that, include: A semiconductor substrate having opposing first and second surfaces; The second surface has alternating first and second regions, as well as isolation regions located between each first region and the second region adjacent to it; A first doped semiconductor layer is formed on the first region and a portion of the isolation region; the portion of the first doped semiconductor layer on the first region is a first doped portion, and the remaining portion is a second doped portion; the doping concentration of impurities in the second doped portion is less than the doping concentration of impurities in the first doped portion. An intrinsic semiconductor layer is formed on the portion outside the second doped portion of the isolation region and is integrally formed with the first doped semiconductor layer; A second doped semiconductor layer covers the second region, at least a portion of the intrinsic semiconductor layer, and at least a portion of the second doped portion; The second doped semiconductor layer and the first doped semiconductor layer have opposite conductivity types, and at least one of the second doped semiconductor layer and the first doped semiconductor layer is a doped crystalline silicon layer. The intrinsic semiconductor layer is used to electrically isolate the first doped semiconductor layer and the second doped semiconductor layer along a direction parallel to the second surface; An insulating mask layer is located between the second doped semiconductor layer and the intrinsic semiconductor layer and the second doped portion, respectively.

2. The back contact battery according to claim 1, characterized in that, The first doped semiconductor layer is the doped crystalline silicon layer.

3. The back contact battery according to claim 1, characterized in that, Along the direction from the second doped portion to the intrinsic semiconductor layer, the ratio of the width of the second doped portion to the width of the isolation region is greater than or equal to 0.8 and less than 1; and / or, Along the direction from the second doped portion to the intrinsic semiconductor layer, the width of the intrinsic semiconductor layer is greater than or equal to 6 μm and less than or equal to 120 μm; And / or, Along the direction from the second doped portion to the intrinsic semiconductor layer, the width of the isolation region is greater than or equal to 30 μm and less than or equal to 200 μm.

4. The back contact battery according to claim 1, characterized in that, The doping concentration of impurities in the second doped region is greater than or equal to 1E18 cm⁻¹ -3 And less than or equal to 5E20cm -3 ; and / or, The doping concentration of the impurities in the first doped portion is 10 to 100 times that of the impurities in the second doped portion; and / or, Along the direction from the second doped portion to the intrinsic semiconductor layer, the doping concentration of impurities in the second doped portion gradually decreases.

5. The back contact battery according to any one of claims 1 to 4, characterized in that, The back contact battery further includes a first passivation layer, which is located between the semiconductor substrate and the first doped semiconductor layer and the intrinsic semiconductor layer, respectively; and / or, The back contact battery further includes a second passivation layer, which is located between the second doped semiconductor layer and the semiconductor substrate, the intrinsic semiconductor layer and the second doped portion, respectively.

6. The back contact battery according to claim 5, characterized in that, In the case where the back contact battery further includes a first passivation layer, and the first passivation layer is a tunneling passivation layer, the material of the first doped semiconductor layer is doped polycrystalline silicon, and the conductivity type is N-type. And / or, In the case where the back contact battery further includes a second passivation layer, and the material of the second passivation layer includes intrinsic amorphous silicon and / or intrinsic microcrystalline silicon, the material of the second doped semiconductor layer is doped amorphous silicon and / or doped microcrystalline silicon, and the conductivity type is P-type.

7. The back contact battery according to claim 1, characterized in that, Both the first surface of the semiconductor substrate and the surface of the semiconductor substrate corresponding to the second region are textured.

8. A method for manufacturing a back-contact battery, characterized in that, include: Provide a semiconductor substrate; The semiconductor substrate has a first side and a second side opposite to each other; The second surface has alternating first and second regions, as well as isolation regions located between each first region and the second region adjacent to it; An intrinsic semiconductor material layer is formed integrally on the second surface; A first mask layer is formed, which covers the portion of the intrinsic semiconductor material layer corresponding to the second region and the isolation region; Under the masking effect of the first mask layer, the portion of the intrinsic semiconductor material layer located in the first region is selectively doped, so that the portion of the intrinsic semiconductor material layer located in the first region and part of the isolation region forms a first doped semiconductor layer, and the portion of the intrinsic semiconductor material layer located in the remaining isolation region forms an intrinsic semiconductor layer; the portion of the first doped semiconductor layer located in the first region is a first doped portion, and the remaining portion is a second doped portion, wherein the doping concentration of impurities in the second doped portion is less than the doping concentration of impurities in the first doped semiconductor layer; Remove the first mask layer; At least an insulating mask layer is formed covering the first doped semiconductor layer and the intrinsic semiconductor layer; And at least under the masking effect of the insulating mask layer, the portion of the intrinsic semiconductor material layer remaining in the second region is selectively removed; A second doped semiconductor layer is formed on the insulating mask layer and the second region; The second doped semiconductor layer and the first doped semiconductor layer have opposite conductivity types, and at least one of the second doped semiconductor layer and the first doped semiconductor layer is a doped crystalline silicon layer. The intrinsic semiconductor layer is used to electrically isolate the second doped semiconductor layer and the first doped semiconductor layer; Remove the portion of the insulating mask layer located on the first doped portion.

9. The method for manufacturing a back contact battery according to claim 8, characterized in that, In the direction from the second doped portion to the intrinsic semiconductor layer, where the width of the second doped portion is greater than or equal to 6 μm and less than or equal to 120 μm, after selectively doping the portion of the intrinsic semiconductor material layer located in the first region, before removing the first mask layer, the method for manufacturing the back contact battery further includes: The first doped semiconductor layer and the intrinsic semiconductor layer are annealed to make the width of the second doped portion reach the target width.

10. The method for manufacturing a back contact battery according to claim 8, characterized in that, After removing the first mask layer, before forming a second doped semiconductor layer on the insulating mask layer and the second region, the method for manufacturing the back contact battery includes: forming a mask material layer integrally disposed on the portion of the first doped semiconductor layer, the intrinsic semiconductor layer, and the intrinsic semiconductor material layer remaining on the second region; The portion of the mask material layer located above the second region is removed, and the remaining portion of the mask material layer forms the second mask layer; Under the masking effect of the second mask layer, the portion of the intrinsic semiconductor material layer remaining in the second region is selectively removed; Under the masking effect of at least a portion of the second mask layer, the first surface of the semiconductor substrate and the surface of the semiconductor substrate corresponding to the second region are texturized; after the texturization process, at least a portion of the second mask layer forms the insulating mask layer.

11. The method for manufacturing a back contact battery according to claim 10, characterized in that, A laser etching process is used to sequentially remove the portion of the mask material layer located above the second region, as well as the portion of the intrinsic semiconductor material layer remaining on the second region; And / or, The second mask layer includes a first silicon nitride layer and a second silicon nitride layer spaced apart along the thickness direction of the semiconductor substrate, and an intrinsic silicon layer located between the first silicon nitride layer and the second silicon nitride layer; after texturing the first surface of the semiconductor substrate and the surface of the semiconductor substrate corresponding to the second region, before forming the second doped semiconductor layer on the insulating mask layer and the second region, the manufacturing method of the back contact battery further includes: sequentially removing the second silicon nitride layer and the intrinsic silicon layer.

12. The method for manufacturing a back contact battery according to claim 10 or 11, characterized in that, A second doped semiconductor layer is formed on the insulating mask layer and the second region, including: A second doped semiconductor material layer is formed integrally on the second region and the second mask layer; The portion of the second doped semiconductor material layer corresponding to the first region is selectively removed, so that the remaining portion of the second doped semiconductor material layer forms the second doped semiconductor layer.

13. The method for manufacturing a back contact battery according to claim 8, characterized in that, After providing a semiconductor substrate, and before forming an intrinsic semiconductor material layer integrally disposed on the second surface, the method for manufacturing the back contact battery further includes: forming a first passivation material layer integrally disposed on the second surface; After selectively removing the portion of the intrinsic semiconductor material layer remaining in the second region, and before forming the second doped semiconductor layer on the second region and the insulating mask layer, the method for manufacturing the back contact battery further includes: selectively removing the portion of the first passivation material layer located in the second region, so that the remaining portion of the first passivation material layer forms the first passivation layer.

14. The method for manufacturing a back contact battery according to claim 8 or 13, characterized in that, After selectively removing the portion of the intrinsic semiconductor material layer remaining on the second region, before forming the second doped semiconductor layer on the insulating mask layer and the second region, the method for manufacturing the back contact battery further includes: forming a second passivation layer on the insulating mask layer.

Images