Back contact photovoltaic cell and preparation method thereof

Abstract

The invention discloses a back contact photovoltaic cell and a preparation method thereof, and the back contact photovoltaic cell comprises a silicon substrate, the back surface of the silicon substrate is sequentially and alternately provided with a plurality of first regions and a plurality of second regions, each first region is provided with a first semiconductor layer, and each second region is provided with a second semiconductor layer; the first semiconductor layer is connected with the first transparent electrode pattern, the second semiconductor layer is connected with the second transparent electrode pattern, and the first transparent electrode pattern and the second transparent electrode pattern are isolated from each other through a first gap; the first transparent electrode pattern is close to the edge of the first gap, and the edge of the first transparent electrode pattern is in a wave shape in the direction perpendicular to the first area and extending towards the second area. And / or; the second transparent electrode pattern is close to the edge of the first gap, and the edge of the second transparent electrode pattern is in a wave shape in the direction perpendicular to the first area and extending towards the second area. According to the scheme, the conversion efficiency of the back contact photovoltaic cell can be improved.

Description

[0001] This application is a divisional application. The application date of the parent application is June 14, 2024. The application number is 2024107723062. The name of the invention is: Back-contact photovoltaic cell and its preparation method. Technical Field

[0002] The present invention generally relates to the field of photovoltaic technology, and specifically relates to a back-contact photovoltaic cell and a preparation method thereof. Background Art

[0003] Back-contact photovoltaic cell technology (Interdigitated Back Contact; IBC) moves the front electrode of the cell to the back, and does not set a grid line on the front, eliminating the grid line's blocking of light. Therefore, back-contact photovoltaic cells have a higher conversion efficiency. At present, the general photoelectric conversion efficiency can reach more than 25%.

[0004] However, in the prior art, there is usually a leakage current problem between the P region and the N region of the back-contact photovoltaic cell. In order to solve the leakage current problem, R&D technicians will add a complex isolation structure, which generates more additional process steps and increases the manufacturing cost of the battery. Therefore, how to find a back-contact photovoltaic cell that can reduce leakage current, improve the battery's photoelectric conversion efficiency, and simplify the battery manufacturing process has become a major problem that needs to be urgently solved in the photovoltaic industry. Summary of the invention

[0005] The present application provides a back-contact photovoltaic cell, which improves the conversion efficiency of the back-contact photovoltaic cell by taking into account both structural optimization and reduction of leakage current.

[0006] In one aspect of the present invention, a back-contact photovoltaic cell is provided, comprising a silicon substrate, wherein the silicon substrate has a front side and a back side, wherein the back side is alternately provided with a plurality of first regions and a plurality of second regions, each of the first regions is provided with a first semiconductor layer, and each of the second regions is provided with a second semiconductor layer;

[0007] The first semiconductor layer is connected to a first transparent electrode pattern, the second semiconductor layer is connected to a second transparent electrode pattern, and the first transparent electrode pattern and the second transparent electrode pattern are isolated from each other by a first gap;

[0008] The edge of the first transparent electrode pattern is close to the first gap, and in a direction extending perpendicularly from the first area to the second area, the edge of the first transparent electrode pattern is wavy; and / or;

[0009] The second transparent electrode pattern is close to an edge of the first gap, and in a direction extending perpendicularly from the first area to the second area, the edge of the second transparent electrode pattern is wavy.

[0010] In the present application, a first transparent electrode pattern and a second transparent electrode pattern isolated from each other can be obtained by patterning the same transparent electrode film, that is, the transparent electrode material between the first transparent electrode pattern and the second transparent electrode pattern can be completely removed, thereby avoiding the problem of poor insulation between the first transparent electrode pattern and the second transparent electrode pattern due to incomplete removal of the transparent electrode material, which causes a large leakage current. Since the conversion efficiency of the back-contact photovoltaic cell is negatively correlated with the size of the leakage current, as the leakage current decreases, the conversion efficiency of the back-contact photovoltaic cell of the present invention can be improved. In addition, in the patterned formation of the first transparent electrode pattern and the second transparent electrode pattern in the present application, the edge of the first transparent electrode pattern is close to the edge of the first gap, and the shape of the edge of the first transparent electrode pattern is wavy in the direction extending from the first area to the second area perpendicularly; and / or; the edge of the second transparent electrode pattern is close to the edge of the first gap, and the shape of the edge of the second transparent electrode pattern is wavy in the direction extending from the first area to the second area perpendicularly. This structural setting is conducive to the stress release of the battery and the transparent electrode pattern, avoiding the edge collapse and falling off caused by excessive stress on the edge of the transparent electrode pattern during the formation process. At the same time, the first transparent electrode pattern is made as a whole, which is conducive to the lateral transmission of the collected current on the first transparent electrode pattern. Similarly, the second transparent electrode pattern is also a whole, which is conducive to the lateral transmission of the collected current on the second transparent electrode pattern.

[0011] Optionally, the second semiconductor layer extends from the second region to the first region, and sequentially includes a climbing portion and a covering portion, wherein the covering portion covers a portion of the first semiconductor layer to form an exposed first semiconductor region and a covered first semiconductor region;

[0012] A second transparent electrode pattern is disposed on the second semiconductor layer above the orthographic projection of the second region;

[0013] A first transparent electrode pattern is arranged on the entire exposed first semiconductor region and on a portion of the covering portion extending perpendicularly from the first region to the second region; or,

[0014] A first transparent electrode pattern is disposed on a portion of the exposed first semiconductor region and a portion of the covering portion.

[0015] Optionally, when a second transparent electrode pattern is provided on a portion of the second semiconductor layer above the orthographic projection of the second region, a second gap is formed between an edge of the second transparent electrode pattern and the climbing portion on the cross section of the back-contact photovoltaic cell; preferably, the width of the second gap is 10μm-80μm, preferably 20-50μm.

[0016] In the above scheme, a second gap is formed between the edge of the second transparent electrode pattern and the climbing portion. On the one hand, it can achieve better physical isolation to prevent the generation of leakage current. On the other hand, the gap between the second electrode pattern and the climbing portion is to leave the silicon substrate at the deformation position here, so as to avoid the second transparent electrode pattern from peeling off at the larger deformation position due to the larger deformation here. In addition, according to the deformation amount here, the width of the second gap here is appropriately controlled, and the effect is best within this range.

[0017] Optionally, a third gap is formed between the edge of the first transparent electrode pattern and the climbing portion. Preferably, the width of the third gap is 40 μm-80 μm, preferably 40 μm-60 μm.

[0018] In the above scheme, a third gap is formed between the edge of the first transparent electrode pattern and the climbing portion. On the one hand, it can achieve good physical isolation to prevent leakage current. On the other hand, the gap between the first electrode pattern and the climbing portion is to leave a space for the silicon substrate to deform at this location, so as to avoid the first transparent electrode pattern from peeling off at the larger deformation location due to the larger deformation at this location. In addition, according to the deformation amount here, the width of the third gap here is appropriately controlled, and the effect is best within this range.

[0019] Optionally, the ratio of the width of the covering portion to the width of the third gap is between 1.3-2.

[0020] The maximum ratio of the third gap is reached when the ratio of the width of the above-mentioned covering portion to the width of the third gap is 1.3 times. At this time, the transparent conductive layer on the covering portion that is retained by etching paste or laser etching belongs to the part that meets the process window requirements. This part is retained on the covering portion, which can avoid damage to the transparent conductive layer on the effective power generation area of ​​the exposed area of ​​the first semiconductor. At the same time, under a certain width of the covering portion and the third gap, the width of the covering portion is reduced, the transmission path of holes or electrons in the first semiconductor layer under the covering portion is reduced, the body recombination is reduced, and the power generation efficiency is improved.

[0021] Optionally, the climbing portion is inclined relative to the back side of the silicon substrate. Preferably, the climbing portion has an inclination angle of 5°-80°, preferably 30°-70°, relative to the back side of the silicon substrate.

[0022] Through the above-mentioned setting scheme, the back side of the silicon substrate is tilted, which improves the uniformity of the deposition of intrinsic amorphous silicon here and improves the passivation effect on the semiconductor substrate; at the same time, since the deposited intrinsic amorphous silicon layer has better uniformity and better surface morphology retention, it is beneficial to the deposition and preparation of the doped amorphous silicon layer, forming a doped amorphous silicon layer with better electrical properties, thereby also improving the conversion efficiency of the battery.

[0023] Optionally, the adjacent first semiconductor layer and the silicon substrate form a first groove, the second area is the groove area, the bottom velvet valley portion of the groove area has a TCO island, and the TCO island is away from the climbing part and isolated from the climbing part.

[0024] Through the above-mentioned setting scheme, a TCO island is set in the valley part of the velvet surface at the bottom of the groove in the second area. On the one hand, the TCO island is not electrically connected to the second transparent electrode pattern, ensuring the isolation effect to prevent leakage. On the other hand, the TCO island fills the valley of the velvet surface, making the surface of the back of the battery smoother, improving the reflectivity of the back, thereby increasing the photoelectric conversion effect.

[0025] Optionally, a side of the first transparent electrode pattern close to the first gap has a reduced thickness region, a width of the reduced thickness region is 10 μm-50 μm, and a thickness of the reduced thickness region close to an edge of the first gap is 45 nm-65 nm.

[0026] Optionally, the first semiconductor layer includes a tunneling layer disposed on the silicon substrate, and an N-type doped polysilicon layer is disposed on a side of the tunneling layer away from the silicon substrate;

[0027] The second semiconductor layer includes an intrinsic amorphous silicon layer, and a P-type doped microcrystalline silicon layer is disposed on a side of the intrinsic amorphous silicon layer away from the silicon substrate.

[0028] By setting the above scheme, on the one hand, the conductivity of the first semiconductor layer is improved by setting the tunneling layer and the N-type doped polycrystalline silicon layer, and the conductivity of the polycrystalline silicon is stronger; on the other hand, by setting the intrinsic amorphous silicon layer and the doped microcrystalline silicon layer, a low-temperature process can be used to reduce the complexity of the process. At the same time, the low-temperature process will not affect the performance of the tunneling layer and the N-type doped polycrystalline silicon layer in the previous step, and the influence of the impurity diffusion of the doped elements caused by the secondary high temperature can be avoided. Thirdly, the intrinsic amorphous silicon layer is extended to the first semiconductor layer to form a covering portion, and the surface of the N-type doped polycrystalline silicon layer is further passivated to reduce recombination. At the same time, a P-type doped microcrystalline silicon layer is set. On the intrinsic amorphous silicon layer, due to the isolation and passivation effect of the intrinsic amorphous silicon layer and the conductivity of the low-temperature P-type doped microcrystalline silicon layer itself, the current breakdown short circuit leakage between the P and N-type semiconductor layers is avoided.

[0029] In another aspect of the present invention, a method for preparing a back-contact photovoltaic cell is provided, comprising the following steps:

[0030] A battery precursor is provided, the battery precursor comprising a silicon substrate, a back side of the silicon substrate being alternately provided with a plurality of first regions and a plurality of second regions, each of the first regions being provided with a first semiconductor layer, and each of the second regions being provided with a second semiconductor layer;

[0031] forming a transparent electrode film on the back side of the battery precursor;

[0032] On the transparent electrode film, etching is performed at the junction of the first region and the second region to etch the transparent electrode film to form a first transparent electrode pattern connected to the first semiconductor layer and a second transparent electrode pattern connected to the second semiconductor layer, the first transparent electrode pattern and the second transparent electrode pattern are isolated from each other by a first gap; the first transparent electrode pattern is close to the edge of the first gap, and the shape of the edge of the first transparent electrode pattern is wavy in a direction extending from the first region to the second region at right angles; and / or; the second transparent electrode pattern is close to the edge of the first gap, and the shape of the edge of the second transparent electrode pattern is wavy in a direction extending from the first region to the second region at right angles. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings:

[0034] Figure 1 A rear view of a back-contact photovoltaic cell provided for an embodiment of the present invention;

[0035] Figure 2 for Figure 1 AA section view;

[0036] Figure 3 A rear view of a back-contact photovoltaic cell provided for another embodiment of the present invention;

[0037] Figure 4 Rear view of a back-contact photovoltaic cell provided for another embodiment of the present invention

[0038] Figure 5 for Figure 4 CC section view;

[0039] Figure 6 for Figure 4 EE cross-sectional view;

[0040] Figure 7 A rear view of a back-contact photovoltaic cell provided for another embodiment of the present invention;

[0041] Figure 8 A rear view of a back-contact photovoltaic cell provided for another embodiment of the present invention;

[0042] Fig. 9 A rear view of a back-contact photovoltaic cell provided for another embodiment of the present invention;

[0043] Fig.10 Another embodiment of the present invention provides a back contact photovoltaic cell corresponding to Figure 1 Sectional view at the AA position;

[0044] Fig.11 A rear view of a back-contact photovoltaic cell provided for another embodiment of the present invention;

[0045] Figure 12-Figure 21 The embodiment of the present invention provides a corresponding Fig.11 Schematic diagram of the preparation process structure at the FF section position;

[0046] Fig. 22 Another embodiment of the present invention provides a back contact photovoltaic cell corresponding to Fig.11 Cross-sectional view at the FF position.

[0047] Description of reference numerals:

[0048] N-type silicon substrate 1, first transparent electrode pattern 11, transparent conductive film 101, tunneling layer 2, second transparent electrode pattern 21, N-type doped polycrystalline silicon layer 3, intrinsic amorphous silicon layer 4, P-type microcrystalline silicon layer 5, anti-reflection layer 6, hydrogenated silicon nitride layer 7, etching paste 8, first area Q1, second area Q2, electrode D, climbing part P, covering part G, film opening area L, first gap W1, second gap W2, third gap W3, partial positions J1, J2, J3, edges B1, B2, middle areas C1, C2, first thickness reduction area S1, second thickness reduction area S2, width W4, thickness T1, maximum thinning amount T2. DETAILED DESCRIPTION

[0049] The present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the relevant invention, rather than to limit the invention. It is also necessary to explain that, for ease of description, only the parts related to the invention are shown in the accompanying drawings.

[0050] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0051] The "patterning process" involved in the embodiments of the present invention includes deposition of film layers, coating of photoresist, mask exposure, development, etching, stripping of photoresist and other processes, which are mature preparation processes in the relevant technology. The "photolithography process" mentioned in this embodiment includes coating of film layers, mask exposure and development, which are mature preparation processes in the relevant technology. Deposition can adopt known processes such as sputtering, evaporation, chemical vapor deposition, etc., coating can adopt known coating processes, etching can adopt known methods, and epitaxial growth also adopts known methods, which are not specifically limited here.

[0052] In the description of this embodiment, it is necessary to understand that a "thin film" refers to a thin film made by depositing, coating or growing a certain material on a substrate. If the "thin film" does not require a composition process or a photolithography process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" still requires a composition process or a photolithography process during the entire production process, it is called a "thin film" before the composition process and a "layer" after the composition process. The "layer" after the composition process or the photolithography process contains at least one "pattern". For example, but not limited to, the thickness of the thin film referred to in this article can be less than 100μm.

[0053] In the related technologies of solar cells, the selective passivation contact technology separates metal from semiconductor, avoiding serious recombination caused by direct contact between metal and semiconductor. At the same time, this selective passivation contact structure has obvious selectivity for the passage of specific carriers. One carrier can pass effectively while shielding the other carrier, avoiding the recombination of the two carriers in the electrode collection area, thereby effectively improving the photoelectric conversion efficiency of solar cell devices. Typical representatives of this selective passivation contact structure in solar energy technology are tunnel oxide passivated contact solar cells (TOPCon) and heterojunction solar cells (HIT). Both of these cell structures are double-sided electrode structures, and the common efficiency bottleneck is that the shading caused by the front metal cannot be avoided. For the TOPCon structure, the front side is still in direct contact between the metal and the silicon base. In addition to shading, the problem of serious metal recombination still exists; for the HIT structure, although the front metal recombination is effectively suppressed, the parasitic absorption of the incident light by the amorphous silicon / ITO layer causes a serious loss of short-circuit current density.

[0054] In order to reduce the shading effect of the front electrode, the interdigitated back contact photovoltaic cell technology (Interdigitated Back Contact; IBC) was born. IBC moves the front electrode of the cell to the back, thereby avoiding the shading and recombination of the front electrode, effectively improving the conversion efficiency of the cell. The TBC (Tunneloxide Back Contact) or HBC (Hetero-Junction Back Contact) technology that combines IBC technology with TOPCon or HJT technology further reduces the recombination of the metal on the back of IBC. In 2017, Kaneka announced a HBC cell conversion efficiency of up to 26.7%, showing the powerful efficiency advantage of this structure.

[0055] The back n-region and p-region of the traditional HBC battery structure are formed by a stacked structure of intrinsic amorphous silicon and N-type doped amorphous silicon (abbreviated as i / n a-Si:H) and a stacked structure of intrinsic amorphous silicon and P-type doped amorphous silicon (abbreviated as i / p a-Si:H) to form a cross-finger pattern. During the manufacturing process, the damage of the laser to the n- and p-regions needs to be strictly controlled, especially for the n-region, where the laser process window is narrow, which increases the process difficulty. HBC batteries also have the following disadvantages in the manufacturing process: a large number of masks and mask removal technologies are used to form patterns, such as the photolithography technology commonly used in the semiconductor field, which has high production costs and difficult process control; in terms of equipment fixed investment, the CVD equipment for depositing amorphous silicon thin films is expensive and has low production capacity. These aspects restrict the efficiency improvement and cost reduction of HBC batteries and limit its industrial application.

[0056] As the TOPCon battery process is mature, the TBC battery that absorbs the key technical processes of the TOPCon battery has become the most cost-effective IBC battery process route. SunPower and domestic companies that have tried to mass-produce IBC batteries have transformed to this technical route. Based on the IBC battery structure, TBC replaces the n-region and p-region structures on the back of the IBC from phosphorus diffusion and boron diffusion doped substrate silicon to SiOx / n+poly Si and SiOx / p+poly Si structures. This structure solves the serious metal recombination of the n and p regions. In addition, this tunneling oxide layer passivation contact structure also effectively suppresses the serious Auger recombination problem caused by direct doping of impurities in the substrate in the traditional IBC structure. However, TBC cells have the following disadvantages: the preparation process is long, and the high-temperature preparation of p poly and n poly leads to serious concentric circles on the silicon wafer, among which p poly is passivated at 10fa and n poly can reach 4fa; after the interdigitated structure on the back is completed, it is generally necessary to use laser etching to isolate the P-region transparent electrode pattern and the N-region transparent electrode pattern, but the removal of the transparent electrode material in the laser etching area is not ideal, resulting in poor insulation between the P-region transparent electrode pattern and the N-region transparent electrode pattern, resulting in a large leakage current, which affects the conversion efficiency of the back-contact heterojunction solar cell.

[0057] To this end, the present invention adopts a transparent electrode pattern isolated from each other by a first gap, and a transparent electrode pattern edge thickness less than the thickness of the middle area, so as to take into account both structural optimization and reduction of leakage current, thereby improving the conversion efficiency of the back-contact photovoltaic cell, as described below for details.

[0058] First, refer to Figure 1 , Figure 2 As shown, the present invention provides a back-contact photovoltaic cell, comprising a silicon substrate, wherein a plurality of first regions Q1 and a plurality of second regions Q2 are alternately arranged on the back side of the silicon substrate, and each of the first regions Q1 is provided with a first semiconductor layer.

[0059] The first region Q1 is provided with a first transparent electrode pattern 11 connected to the first semiconductor layer, and the second region Q2 is provided with a second transparent electrode pattern 21 connected to the second semiconductor layer, and the first transparent electrode pattern 11 and the second transparent electrode pattern 21 are isolated from each other by a first gap W1; the thickness of the edge of the first transparent electrode pattern 11 close to the first gap W1 is less than the thickness of the middle region C1 of the first transparent electrode pattern 11; the thickness of the edge of the second transparent electrode pattern 21 close to the first gap W1 is less than the thickness of the middle region C2 of the second transparent electrode pattern 21.

[0060] Of course, in other examples, only the thickness of the edge of the first transparent electrode pattern 11 close to the first gap W1 may be less than the thickness of the middle area C1 of the first transparent electrode pattern 11; or, the thickness of the edge of the second transparent electrode pattern 21 close to the first gap W1 may be less than the thickness of the middle area C2 of the second transparent electrode pattern 21.

[0061] Optionally, the width of the first gap W1 (the dimension in the X-axis direction, also in the horizontal direction) is 60μm-120μm, for example but not limited to 60μm, 65μm, 70μm, 72μm, 76μm, 80μm, 83μm, 90μm, 97μm, 100μm, 105μm, 110μm, 120μm, etc.

[0062] For example but not limited to, the silicon substrate uses an N-type silicon substrate 1, which has a longer minority carrier diffusion length, so that the photogenerated minority carriers will not be recombined before reaching the back junction region and will be separated by the electric field of the back junction region to form current.

[0063] The materials of the first transparent electrode pattern 11 and the second transparent electrode pattern 21 can be transparent conductive oxides (Transparent Conductive Oxides; TCO). TCO includes: Indium Tin Oxide (ITO), Zinc Oxide (ZnO), Cadmium Tin Oxide (CTO), Aluminum Zinc Oxide (AZO), Indium Zinc Oxide (IZO), Titanium Dioxide (TiO2), Indium Hydroxide Doped (In(OH)3), Indium Tungsten Oxide (IWO), etc. In this example, the materials of the first transparent electrode pattern 11 and the second transparent electrode pattern 21 are ITO.

[0064] In this solution, the material of the first semiconductor layer includes polycrystalline silicon, and the material of the second semiconductor layer includes microcrystalline silicon.

[0065] The polysilicon may be N-type doped to form an N-type doped layer; and the microcrystalline silicon may be P-type doped to form a P-type doped layer.

[0066] Among them, the first transparent electrode pattern 11 is connected to the first semiconductor layer by directly setting the first transparent electrode pattern 11 of ITO material on the N-type doped layer of polycrystalline silicon material. According to the specific situation, the contact area between the first transparent electrode pattern 11 and the N-type doped layer of polycrystalline silicon material can be increased as much as possible to expand the area for collecting current. In addition, since the surface of polycrystalline silicon has many defects and surface recombination is prone to occur, by setting the first transparent electrode pattern 11 on the surface of the N-type doped layer of polycrystalline silicon material, the first transparent electrode pattern 11 can block or reduce the recombination center of the surface defects of the N-type doped layer of polycrystalline silicon material, reduce the recombination on the surface of the N-type doped layer of polycrystalline silicon material, and help improve the conversion efficiency of the back contact photovoltaic cell.

[0067] In the present application, the first transparent electrode pattern 11 and the second transparent electrode pattern 21 isolated from each other can be obtained by patterning the same transparent electrode film, that is, the transparent electrode material between the first transparent electrode pattern 11 and the second transparent electrode pattern 21 can be completely removed, thereby avoiding the problem of poor insulation between the first transparent electrode pattern 11 and the second transparent electrode pattern 21 due to incomplete removal of the transparent electrode material, which causes a large leakage current. Since the conversion efficiency of the back-contact photovoltaic cell is negatively correlated with the size of the leakage current, as the leakage current decreases, the conversion efficiency of the back-contact photovoltaic cell of the present invention can be improved. In addition, in the patterned formation of the first transparent electrode pattern 11 and the second transparent electrode pattern 21, the thickness of the edge of the first transparent electrode pattern 11 close to the first gap W1 is less than the thickness of the middle area C1 of the first transparent electrode pattern 11; and / or; the thickness of the edge of the second transparent electrode pattern 21 close to the first gap W1 is less than the thickness of the middle area C2 of the second transparent electrode pattern 21. This structural setting is conducive to the stress release of the battery and the transparent electrode pattern, avoiding the edge collapse and falling off caused by excessive stress at the edge of the transparent electrode pattern during the formation process. At the same time, the first transparent electrode pattern 11 is made as a whole, which is conducive to the lateral transmission of the collected current on the first transparent electrode pattern 11. Similarly, the second transparent electrode pattern 21 is also made as a whole, which is conducive to the lateral transmission of the collected current on the second transparent electrode pattern 21.

[0068] Optional, at least see also Figure 2As shown, a first thickness reduction area S1 is provided in the peripheral area of ​​the first transparent electrode pattern 11 close to the first gap W1 , and the thickness of the first thickness reduction area S1 gradually decreases from the middle area C1 of the first transparent electrode pattern 11 to the outer boundary of the first transparent electrode pattern 11 .

[0069] A second reduced thickness region S2 is disposed in the peripheral area of ​​the second transparent electrode pattern 21 close to the first gap W1 , and the thickness of the second reduced thickness region S2 gradually decreases from the middle area C2 of the second transparent electrode pattern 21 to the outer boundary of the second transparent electrode pattern 21 .

[0070] In other examples, the first reduced thickness region S1 may be provided only in the peripheral region of the first transparent electrode pattern 11 close to the first gap W1 ; the second reduced thickness region S2 may be provided only in the peripheral region of the second transparent electrode pattern 21 close to the first gap W1 .

[0071] In the above scheme, the thickness of the peripheral area gradually increases along the edge direction away from the peripheral area, which can linearly ensure that the binding force of each transparent electrode pattern is in the middle area of ​​the transparent electrode. If there is a local tension change in the peripheral area, due to the thinness of the peripheral area, the tension change will not have a significant impact on the middle area. The lateral tension generated by the tension change in the peripheral area can only automatically expand and contract linearly in the peripheral area, or even if there is a crack, it will be linearly cracked in the peripheral area and will not be directly transmitted to the middle area, thereby ensuring the lateral transmission performance of the battery. It should be noted that the thickness of the edge of the first transparent electrode pattern is greater than the thickness of the thinning area, which can also play a technical effect of preventing hot spots.

[0072] Optional, at least see also Figure 3 As shown, the edge of the first transparent electrode pattern 11 is close to the first gap W1, and the edge B1 of the first transparent electrode pattern 11 is wavy in a direction extending perpendicularly from the first area Q1 to the second area Q2.

[0073] The second transparent electrode pattern 21 is close to the edge of the first gap W1 , and the edge B2 of the second transparent electrode pattern 21 is wavy in a direction perpendicular to the first region Q1 and extending toward the second region Q2 .

[0074] Among them, at least refer to Figure 3 As shown, the direction in which the first region Q1 extends toward the second region Q2 is the X-axis direction, and the direction perpendicular to the first region Q1 extending toward the second region Q2 is the Y-axis direction.

[0075] In other examples, refer to Figure 4 , Figure 7-Figure 9In any of the examples shown, only the edge B1 of the first transparent electrode pattern 11 is wavy; in other examples, only the edge B2 of the second transparent electrode pattern 21 is wavy.

[0076] The wave shape may be an irregular curve.

[0077] Through the above-mentioned setting scheme, the edge of the transparent electrode pattern layer is set to be wavy, which can reduce the edge stress of the transparent electrode pattern and avoid hidden cracks of the transparent electrode pattern caused by stress changes at the edge of the silicon substrate, thereby affecting the lateral transmission performance.

[0078] Optionally, the second semiconductor layer extends from the second region Q2 to the first region Q1, and sequentially includes a climbing portion P and a covering portion G, wherein the covering portion G covers a portion of the first semiconductor layer to form an exposed first semiconductor region and a covered first semiconductor region; wherein the exposed first semiconductor region refers to the portion of the first semiconductor layer not covered by the covering portion G, and the covered first semiconductor region refers to the portion of the first semiconductor layer covered by the covering portion G.

[0079] In the above scheme, the second semiconductor layer extends from the second region Q2 to the first region Q1, and sequentially includes a climbing portion P and a covering portion G. It can be understood that the second semiconductor layer located in the first region Q1 is an integrated structure with the climbing portion P and the covering portion G, and the three are prepared by the same process and made of the same material.

[0080] A second transparent electrode pattern 21 is disposed on the second semiconductor layer above the orthographic projection of the second region Q2.

[0081] The second transparent electrode pattern 21 disposed on the second semiconductor layer above the orthographic projection of the second region Q2 may at least adopt the following schemes:

[0082] Optional, see Figure 7 As shown, the second transparent electrode pattern 21 is disposed on the entire second semiconductor layer above the orthographic projection of the second region Q2 . That is, the area within the second region Q2 except the climbing portion P is covered by the second transparent electrode pattern 21 .

[0083] The above solution maximizes the lateral derivation of the surface of the second region Q2 by arranging the second transparent electrode pattern 21 on the entire layer above the orthographic projection of the second region Q2, reduces the transmission path of holes or electrons in the semiconductor layer, and avoids recombination.

[0084] Optional, at least refer to Figure 3As shown, a second transparent electrode pattern 21 is disposed on a portion of the second semiconductor layer above the orthographic projection of the second region Q2 . That is, a portion of the second semiconductor layer above the orthographic projection of the second region Q2 is exposed outside the second transparent electrode pattern 21 . Figure 3 In the embodiment, the second transparent electrode pattern 21 is not disposed on a portion J2 above the second semiconductor layer between the two ascending portions P in the second region Q2.

[0085] in, Figure 2 , Figure 5-Figure 6 In any of the examples shown in , there is a second gap W2 between the boundary of the second transparent electrode pattern 21 and the boundary of the climbing portion P. When the boundary of the second transparent electrode pattern 21 is a non-linear line, the value of the second gap W2 is a variable value, and the second gap W2 may be equal or unequal depending on the position.

[0086] The above scheme is that in the process of applying the etching paste above the orthographic projection of the second region Q2 or on the covering portion G, in order to facilitate the process, the process window of the etching paste is increased, and part of the etching paste is allowed to etch into the transparent conductive layer above the orthographic projection of the second region Q2, so that the second transparent electrode pattern 21 formed is arranged on the part of the second semiconductor layer above the orthographic projection of the second region Q2.

[0087] Optional, see Figure 3 As shown, the second transparent electrode pattern 21 is disposed on the portion of the second semiconductor layer above the orthographic projection of the second region Q2 and on the portion of the covering portion G. That is, a portion of the second transparent electrode pattern 21 extends to a portion J3 of the covering portion G, and the second transparent electrode pattern 21 is not disposed on a portion J2 above the second semiconductor layer between the two climbing portions P in the second region Q2.

[0088] The above scheme is that in the process of applying the etching paste above the orthographic projection of the second area Q2 or on the part of the covering portion G, in order to facilitate the process, the process window of the etching paste is increased, and part of the etching paste is allowed to be etched to the transparent conductive layer above the orthographic projection of the second area Q2, and part of the covering portion G is not etched with the etching paste, thereby forming a second transparent electrode pattern 21 arranged on part of the second semiconductor layer and part of the covering portion G above the orthographic projection of the second area Q2.

[0089] In the above scheme, since the second semiconductor layer extends from the second region Q2 to the first region Q1 and sequentially includes a climbing portion P and a covering portion G, and the covering portion G covers a portion of the first semiconductor layer, by providing the climbing portion at the junction of the first region Q1 and the second region Q2, the isolation distance between the first transparent electrode pattern and the second transparent electrode pattern can be extended to improve the isolation performance; a first gap W1 is provided between the first transparent electrode pattern 11 and the second transparent electrode pattern 21, so that the first transparent electrode pattern 11 is disconnected from the second transparent electrode pattern 21, so as to improve the anti-leakage effect between the first region Q1 and the second region Q2. With the improvement of the anti-leakage effect, the conversion efficiency of the back contact photovoltaic cell is correspondingly improved.

[0090] A first transparent electrode pattern 11 is disposed on the entire exposed first semiconductor region and on a portion of the covering portion extending in a direction perpendicular to the first region Q1 toward the second region Q2 .

[0091] Among them, refer to Figure 4 As shown, the direction in which the first region Q1 extends toward the second region Q2 is the X-axis direction, and the direction perpendicular to the first region Q1 extending toward the second region Q2 is the Y-axis direction; then in the Y-axis direction, a portion of the covering portion G is provided with the first transparent electrode pattern 11; that is, in the Y-axis direction, a portion of the covering portion G is provided with the first transparent electrode pattern 11 (see also Figure 6 As shown), the first transparent electrode pattern 11 is not provided on the remaining portion of the covering portion G (see also Figure 5 shown).

[0092] In addition, refer to Figure 8 As shown, the first transparent electrode pattern 11 may also be arranged in such a manner that the first transparent electrode pattern 11 is arranged on the exposed first semiconductor region and the covering portion G.

[0093] That is, the first transparent electrode pattern 11 is not disposed at a partial position J1 of the exposed first semiconductor region, and the first semiconductor layer is exposed at the partial position J1. The first transparent electrode pattern 11 is disposed at a partial area along the X-axis direction and / or along the Y-axis direction of the covering portion G, and the first transparent electrode pattern 11 is not disposed at the remaining area.

[0094] Optionally, when a second transparent electrode pattern 21 is provided on a portion of the second semiconductor layer above the orthographic projection of the second region Q2, on the cross section of the back contact photovoltaic cell, for example Figure 1On the AA position section, a second gap W2 is formed between the edge of the second transparent electrode pattern 21 and the climbing portion P; preferably, the width of the second gap is 10μm-80μm, for example but not limited to 10μm, 15μm, 20μm, 22μm, 26μm, 30μm, 33μm, 40μm, 47μm, 50μm, 55μm, 60μm, 70μm, 73μm, 80μm, etc.; preferably 20-50μm.

[0095] A second gap W2 is formed between the edge of the second transparent electrode pattern 21 and the climbing portion P. On the one hand, it can achieve good physical isolation to prevent the generation of leakage current. On the other hand, the gap between the second transparent electrode pattern 21 and the climbing portion P is to leave a position where the silicon substrate is deformed, so as to avoid the second transparent electrode pattern 21 from peeling off at a larger deformation position due to a larger phase change. In addition, according to the deformation amount here, the width of the second gap W2 here is appropriately controlled, and the effect is best within the above range.

[0096] As an implementable manner, a third gap is formed between the edge of the first transparent electrode pattern and the climbing portion. Preferably, the width of the third gap is 40μm-80μm, for example but not limited to 40μm, 45μm, 50μm, 52μm, 56μm, 60μm, 63μm, 70μm, 80μm, etc.; preferably 40-60μm.

[0097] The area of ​​the third gap W3 is located within the range of the covering portion G. Since the area of ​​the covering portion G is the overlapping area where the first semiconductor layer and the second semiconductor layer extend out of the second area Q2, this area belongs to the dead zone of the back-contact photovoltaic cell, which cannot lead out carriers from the surface of the second semiconductor layer. Therefore, when the total first gap W1 remains unchanged, the width of the third gap W3 can be increased as much as possible and the width of the second gap W2 can be reduced.

[0098] In the above scheme, a third gap W3 is formed between the edge of the first transparent electrode pattern 11 and the climbing portion P. On the one hand, it can achieve good physical isolation to prevent the generation of leakage current. On the other hand, the gap between the first transparent electrode pattern 11 and the climbing portion P is to leave a position where the silicon substrate is deformed, so as to avoid the first transparent electrode pattern 11 from peeling off at a larger deformation position due to a larger phase change. In addition, according to the deformation amount here, the width of the third gap W3 here is appropriately controlled, and the effect is best within this range.

[0099] Optionally, the ratio of the width of the third gap W3 to the width of the second gap W2 is between 1 and 3 times.

[0100] In the above scheme, the width of the second gap W2 plus the width of the third gap W3 is the width of the first gap W1 between the first transparent electrode pattern 11 and the second transparent electrode pattern 21. Therefore, while ensuring the isolation effect, without further expanding the first gap W1, the third gap W3 extends from the overlapping area of ​​the second area Q2 in the first semiconductor layer and the second semiconductor layer of the back-contact photovoltaic cell. This overlapping area belongs to the dead zone of the longitudinal transmission. Therefore, in this part, the width of the third gap W3 can be increased, and the width of the second gap W2 can be adjusted and reduced accordingly to control the total width of the first gap W1 within a reasonable range. Further, when the ratio of the width of the third gap W3 to the width of the second gap W2 is between 1 and 3 times, it can be within a certain range of the first gap W1, that is, the first gap is within the range of 60μm-120μm. The smallest third gap W3 can maximize the current collection area and improve the battery fill factor, thereby improving the photoelectric conversion efficiency while ensuring the isolation effect and the isolation opening process window.

[0101] Optionally, the width of the covering portion P is 60 μm-80 μm, for example but not limited to 60 μm, 62 μm, 65 μm, 68 μm, 70 μm, 73 μm, 75 μm, 77 μm, 80 μm, etc.

[0102] In the back-contact photovoltaic cell, the covering part P is the overlapping area of ​​the first semiconductor layer and the second semiconductor layer. This overlapping area belongs to the dead zone of longitudinal transmission. In order to achieve the maximum power generation efficiency, it is expected to reduce the width of the dead zone. However, if the dead zone is completely eliminated, the first semiconductor layer will be formed alone at the junction of the climbing part P and the covering part G. Since the etching of the silicon substrate at the junction of the climbing part P and the covering part G is formed during the alkali texturing process, in the direction perpendicular to the first area Q1 extending to the second area Q2, the edge of the junction of the climbing part P and the covering part G is not a straight line. Due to the different texturing rates, the climbing part produces a curved arc, and a bare silicon substrate appears. In order to passivate the exposed silicon substrate here and make the second semiconductor layer cover the exposed part of the first area Q1, the width of the covering part G is set at 60μm-80μm.

[0103] Optionally, the ratio of the width of the covering portion G to the width of the third gap W3 is between 1.3-2.

[0104] The ratio of the width of the above-mentioned covering portion G to the width of the third gap W3 reaches the maximum ratio of the third gap W3 when it is 1.3 times. At this time, the transparent conductive layer on the covering portion G that is retained by etching paste or laser etching belongs to the part that meets the process window requirements. This part is retained on the covering portion G, which can avoid the transparent conductive layer on the effective power generation area of ​​the exposed area of ​​the first semiconductor from being damaged. At the same time, under a certain width of the covering portion G and the third gap W3, the width of the covering portion G is reduced, the transmission path of holes or electrons in the first semiconductor layer under the covering portion G is reduced, the body recombination is reduced, and the power generation efficiency is improved.

[0105] Optionally, a vertical distance between a surface of the covering portion G away from the silicon substrate and a position on the silicon substrate is greater than a vertical distance between a surface of the second transparent electrode pattern 21 away from the silicon substrate and a position on the silicon substrate.

[0106] Through the above-mentioned setting, that is, taking the front side of the silicon substrate as a reference, the surface of the covering portion G is set to be higher than the surface of the second transparent electrode pattern 21, thereby ensuring that there is a gap between the first transparent electrode pattern 11 and the second transparent electrode pattern 21 on the surface of the covering portion G, thereby further reducing the generation of leakage current.

[0107] Optionally, the first semiconductor layer includes a tunneling layer 2 disposed on the silicon substrate, and an N-type doped polysilicon layer is disposed on a side of the tunneling layer 2 facing away from the silicon substrate.

[0108] The material of the tunneling layer 2 is, for example but not limited to, silicon dioxide. That is, the tunneling layer 2 is a tunneling silicon dioxide layer, and its thickness may be 1 nm-4 nm, preferably 1 nm-1.8 nm.

[0109] Phosphorus, arsenic, antimony, selenium, tellurium and other materials may be doped into polysilicon to form an N-type doped polysilicon layer. The thickness of the N-type doped polysilicon layer is 30nm-250nm. In this example, phosphorus doping is used, and the phosphorus doping concentration in the N-type doped crystalline silicon layer is 8E19-5E20cm-3, preferably 3-9E20cm-3.

[0110] The tunneling layer 2 is arranged on the polished back side of the silicon substrate, that is, the tunneling layer 2 is arranged on the polished surface, which is conducive to improving the deposition uniformity of the tunneling layer 2. In addition, the thickness of the tunneling layer is relatively thin, generally 1nm-4nm, preferably 1nm-1.8nm. If the surface of the silicon substrate has a high velvet undulation, it is not conducive to the deposition uniformity of the tunneling layer 2, and in the subsequent polycrystalline annealing process, the uneven surface will further deteriorate the unevenness at high temperature, and will interact with the uneven velvet surface, and the velvet pyramid will produce a cliff-like exposed silicon substrate surface, which affects the tunneling effect of the battery; while in this solution, the surface of the silicon substrate is polished to be smoother, which improves the uniformity of the tunneling layer 2, thereby improving the tunneling passivation effect and reducing the composite loss.

[0111] The second semiconductor layer includes an intrinsic amorphous silicon layer, and a P-type doped microcrystalline silicon layer is disposed on a side of the intrinsic amorphous silicon layer away from the silicon substrate.

[0112] Boron, aluminum, gallium, indium, beryllium, magnesium and other materials can be doped into microcrystalline silicon to form a P-type doped microcrystalline silicon layer. This example uses boron doping, and the boron doping concentration in the P-type doped microcrystalline silicon layer is 10E20cm -3 -10E21cm -3 .

[0113] The thickness of the intrinsic amorphous silicon layer is 10nm-20nm, and the thickness of the P-type doped microcrystalline silicon layer is 5nm-45nm, preferably 10nm-20nm.

[0114] By setting the above scheme, on the one hand, the conductivity of the first semiconductor layer is improved by setting the tunneling layer 2 and the N-type doped polycrystalline silicon layer, and the conductivity of the polycrystalline silicon is stronger; on the other hand, by setting the intrinsic amorphous silicon layer and the doped microcrystalline silicon layer, a low-temperature process can be used to reduce the complexity of the process. At the same time, the low-temperature process will not affect the performance of the tunneling layer and the N-type doped polycrystalline silicon layer in the previous step, and the influence of the impurity diffusion of the doped elements caused by the secondary high temperature can be avoided. Thirdly, the intrinsic amorphous silicon layer is extended to the first semiconductor layer to form a covering portion G, and the surface of the N-type doped polycrystalline silicon layer is further passivated to reduce recombination. At the same time, a P-type doped microcrystalline silicon layer is set. On the intrinsic amorphous silicon layer, due to the isolation and passivation effect of the intrinsic amorphous silicon layer and the conductivity of the low-temperature P-type doped microcrystalline silicon layer itself, the current breakdown short circuit leakage between the P and N-type semiconductor layers is avoided.

[0115] The climbing portion P covers the first semiconductor layer including microcrystalline silicon. Therefore, the quality of microcrystalline silicon deposition is worse at locations where the lateral transmission is weak and where high and low climbing structures exist, further deteriorating the conductivity of the first semiconductor layer at the climbing structure, thereby further improving the anti-leakage effect between the first region Q1 and the second region Q2. As the anti-leakage effect improves, the conversion efficiency of the back-contact photovoltaic cell is correspondingly improved.

[0116] In addition, by setting a second gap W2 between the second transparent electrode pattern 21 and the climbing portion P; since the second semiconductor layer includes microcrystalline silicon, the position where the microcrystalline silicon directly contacts the second transparent electrode pattern 21 has good conductivity, and there is no electrical transmission of the transparent electrode pattern in the second gap W2. Since the microcrystalline silicon has poor lateral conductivity, the leakage current between the first transparent electrode pattern 11 and the second transparent electrode pattern 21 is weakened.

[0117] Optionally, a velvet surface is provided on the front side of the silicon substrate, a velvet surface is provided on the front side of the silicon substrate, an intrinsic amorphous silicon layer is provided on the velvet surface, or an aluminum oxide layer is provided on the velvet surface.

[0118] Through the above arrangement, the front surface of the silicon substrate can be passivated to reduce recombination, and on the other hand, the performance of the front intrinsic amorphous silicon layer and the aluminum oxide layer is stable, which can extend the life of the battery.

[0119] Optionally, an anti-reflection layer is provided on the surface of the intrinsic amorphous silicon facing away from the silicon substrate, or an anti-reflection layer 6 is provided on the surface of the aluminum oxide layer facing away from the silicon substrate.

[0120] By setting the above scheme, the reflection of sunlight is reduced, the utilization rate of sunlight is improved, and the conversion efficiency of the back contact photovoltaic cell can be improved.

[0121] Optional, see Fig.10 As shown, the climbing portion P is inclined relative to the back side of the silicon substrate. Preferably, the inclination angle α of the climbing portion P relative to the back side of the silicon substrate is 5°-80°, for example but not limited to 5°, 9°, 11°, 15°, 20°, 30°, 40°, 45°, 50°, 53°, 58°, 65°, 70°, 80°, etc., preferably 30°-70°.

[0122] Through the above-mentioned setting scheme, the climbing portion P is arranged obliquely on the back side of the silicon substrate, which improves the uniformity of the deposition of intrinsic amorphous silicon here and improves the passivation effect on the semiconductor substrate; at the same time, since the deposited intrinsic amorphous silicon layer has better uniformity and better surface morphology retention, it is beneficial to the deposition and preparation of the doped amorphous silicon layer, forming a doped amorphous silicon layer with better electrical properties, thereby also improving the conversion efficiency of the battery.

[0123] Optional, at least refer to Fig. 22 As shown, the adjacent first semiconductor layer and the silicon substrate form a first groove, the second region Q2 is the groove region, and the bottom velvet valley portion of the groove region has a TCO island 22, and the TCO island 22 is away from the climbing portion P and isolated from the climbing portion P.

[0124] When texturing is performed on the front side of the silicon substrate, texturing can be performed simultaneously in the second area Q2 on the back side of the silicon substrate.

[0125] Through the above-mentioned setting scheme, a TCO island 22 is set in the valley part of the velvet surface of the second area. On the one hand, the TCO island 22 is not electrically connected to the second transparent electrode pattern 22, thereby ensuring the isolation effect and preventing leakage. On the other hand, the TCO island 22 fills the valley of the velvet surface, making the surface of the back of the battery smoother, improving the reflectivity of the back, and thus increasing the photoelectric conversion effect.

[0126] As an achievable method, at least refer to Fig. 20 As shown, an isolation protection layer 102 is provided at the position of the second semiconductor layer located at the first gap W1; or, an isolation protection layer 102 is provided at the position of the climbing portion P and the covering portion G of the second semiconductor layer; or, an isolation protection layer 102 is provided at the position of the second semiconductor layer located at the first gap W1, and at the climbing portion P and the covering portion G of the second semiconductor layer. By providing the isolation protection layer 102, it is possible to prevent metal ions from being scattered in the second semiconductor layer and / or the climbing portion P and the covering portion G in the first gap W1 during the preparation process of the back contact photovoltaic cell of the solution of the present invention, thereby causing the passivation layer in the region to be damaged, thereby seriously affecting the performance of the cell.

[0127] As an implementation manner, the isolation protection layer 102 is a silicon oxide layer or an ink layer.

[0128] For example but not limited to, a silicon oxide layer serving as the isolation protection layer 102 may be formed by deposition; an ink layer serving as the isolation protection layer 102 may be formed by printing or printing.

[0129] As an implementable manner, a thickness reduction zone is provided in the peripheral area of ​​the first transparent electrode pattern 11 , and the thickness of the thickness reduction zone gradually decreases from the middle area of ​​the first transparent electrode pattern 11 to the outer boundary of the first transparent electrode pattern 11 .

[0130] As an achievable method, see at least Figure 2 , Fig.19As shown, the first transparent electrode pattern 11 has a thickness reduction area on one side close to the first gap W1, and the thickness reduction area is the first thickness reduction area S1. The width W4 of the first thickness reduction area S1 is 10μm-50μm, the thickness T1 of the first thickness reduction area S1 close to the edge of the first gap W1 is 45nm-65nm, and the maximum thinning amount T2 of the first thickness reduction area S1 is 3nm-15nm.

[0131] In a second aspect, the present invention provides a method for preparing the above-mentioned back-contact photovoltaic cell, comprising the following steps:

[0132] A battery precursor is provided, the battery precursor comprising a silicon substrate, a plurality of first regions Q1 and a plurality of second regions Q2 are alternately arranged on the back side of the silicon substrate, each of the first regions Q1 is provided with a first semiconductor layer, each of the second regions Q2 is provided with a second semiconductor layer, the second semiconductor layer extends from the second region Q2 to the first region Q1, and sequentially comprises a climbing portion P and a covering portion G, the covering portion G covers a portion of the first semiconductor layer;

[0133] forming a transparent electrode film on the back side of the battery precursor;

[0134] The transparent electrode film is etched at least at a position corresponding to the climbing portion P and a partially covered portion G close to the climbing portion P, so as to form an isolated first transparent electrode pattern 11 and a second transparent electrode pattern 21 by etching the transparent electrode film.

[0135] The embodiments of the present invention are described in detail below. It should be noted that the embodiments described below are exemplary and are only used to explain the present invention, and cannot be interpreted as limiting the present invention. In addition, if not explicitly stated, all reagents used in the following embodiments are commercially available, or can be synthesized according to this article or known methods, and the reaction conditions not listed are also easily available to those skilled in the art.

[0136] Example 1

[0137] This embodiment provides a back-contact photovoltaic cell, and the preparation method thereof is as follows:

[0138] S101: Reference Fig.11 , Fig.12 As shown, an N-type silicon substrate 1 is provided, and at least the front side and the back side of the N-type silicon substrate 1 are polished by a wet polishing process.

[0139] Before polishing, the N-type silicon substrate 1 needs to be cleaned to remove impurities, particles and organic matter on the surface. Generally, deionized water, alkaline solution (such as sodium hydroxide NaOH) and acidic solution (such as dilute nitric acid HNO3) can be used for multi-step cleaning.

[0140] For example, but not limited to, the N-type silicon substrate 1 is placed in a tank-type alkaline polishing machine for polishing and cleaning. The working volume of the tank of the cleaning machine is 360L. First, the N-type silicon substrate 1 is pre-cleaned to remove organic and other contaminants generated during the cutting and transportation of the N-type silicon substrate 1. In this embodiment, the No. 1 solution (SC1) of the standard RCA cleaning is used for cleaning. The No. 1 solution is composed of NH4OH-H2O2-H2O, and the volume ratio of the three is 1:1:5. The temperature during cleaning is 65°C. The main function of the SC1 reagent cleaning is alkaline oxidation to remove particles on the silicon wafer, and can oxidize and remove a small amount of organic matter and metal atomic pollution such as Au, Ag, Cu, Ni, Cd, Zn, Ca, Cr, etc. on the surface; after water washing and residual chemicals, alkaline polishing treatment is performed. The alkaline polishing formula is 5.97%wt KOH, the temperature is 80°C, and the alkaline polishing treatment time is 300s to remove damage and polish. Then SC1 cleaning, ozone cleaning, and finally acid washing and dehydration are performed to complete polishing and cleaning. After polishing, the polished surface has a plurality of tower bases remaining in the unit cell, and the maximum distance between any two points of the tower base is 4 μm-6 μm. For example, the size of the tower base remaining after polishing can be controlled by controlling the concentration, temperature and polishing time of the polishing liquid.

[0141] S102: In a low pressure chemical vapor deposition (LPCVD) device, the N-type silicon substrate 1 is subjected to thermal oxidation treatment to form a tunneling layer 2 made of silicon dioxide on the front and back sides of the N-type silicon substrate 1. The thickness of the tunneling layer 2 can be 1nm-5nm, such as 1nm, 1.5nm, 1.8nm, 2nm, 2.3nm, 2.6nm, 3nm, 3.5nm, 4nm, 4.7nm, 5nm, etc. Then, an intrinsic polysilicon layer is deposited on each tunneling layer 2. In addition to LPCVD, plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), and plasma enhanced atomic layer deposition (PEALD) can also be used to deposit the intrinsic polysilicon layer to prepare the tunneling layer 2 and the intrinsic or in-situ doped poly Si. Preferably, LPCVD is used to deposit the back tunneling layer 2 and the polysilicon (poly) layer at a high temperature of 600-800°C. The deposition of the intrinsic a-si:H+a-si:H(N) film layer in the existing HBC battery structure mostly uses expensive PECVD equipment, while the present application uses inexpensive LPCVD equipment to replace the expensive PECVD equipment, effectively reducing the equipment investment cost.

[0142] During the process of forming the tunneling layer 2 and the intrinsic polysilicon layer, a certain amount of silicon dioxide and intrinsic polysilicon will be formed on the side of the N-type silicon substrate 1 .

[0143] It should be noted that various wrap-around plating is not shown in the drawings.

[0144] S103: Phosphorus is diffused into the intrinsic amorphous silicon layer 4 on the front and back sides of the N-type silicon substrate 1 to form an N-type doped polysilicon layer 3. The phosphorus doping concentration is 8E19-5E20cm -3 (For example, it can be 8E19 / 9E19 / 1E20 / 2E20 / 3E20 / 4E20 / 5E20cm -3 ).

[0145] Phosphorus diffusion can be carried out in a tube furnace.

[0146] During the phosphorus diffusion process, a phosphorus silicon glass layer (PSG) is formed on the surface of the N-type doped polysilicon layer, and PSG is plated around the side.

[0147] S104: Remove the PSG on the front side, back side and surrounding plating.

[0148] For example, but not limited to, PSG may be removed by hydrofluoric acid in a tank cleaning apparatus.

[0149] S105: Depositing a hydrogenated silicon nitride layer 7 (SiNx:H) on the N-type doped polysilicon layer on the back side.

[0150] For example, a hydrogenated silicon nitride layer 7 can be deposited in a tubular PECVD device. The hydrogenated silicon nitride layer 7 can be used as a mask for subsequent processes. When laser film opening is performed subsequently, the hydrogenated silicon nitride layer 7 acts as a laser energy absorption layer, which has the effect of reducing the effect of the laser film opening process on the passivation effect of the N region, and also has the effect of providing a hydrogen source to further passivate the polysilicon and silicon substrate, thereby improving the passivation effect and protecting the N-type doped crystalline silicon layer 3 from being corroded by alkali during the texturing process. The thickness of the hydrogenated silicon nitride layer 7 can be 50nm-110nm. The deposition temperature of the hydrogenated silicon nitride layer 7 can be 400℃-600℃.

[0151] Wherein, hydrogenated silicon nitride wrapping is formed on at least the front N-type doped polysilicon layer 3 .

[0152] S106: opening the dehydrogenated silicon nitride layer 7 within the second region Q2 to form a mask.

[0153] For example, the hydrogenated silicon nitride layer 7 within the second region Q2 may be removed by laser etching. In some examples, after the hydrogenated silicon nitride layer 7 within the second region Q2 is removed, etching downwards is continued so that a portion of the N-type doped polysilicon layer on the back is also etched away. In other examples, after the hydrogenated silicon nitride layer 7 within the second region Q2 is removed, etching downwards is continued until the surface of the N-type silicon substrate 1 is etched, that is, the N-type doped polysilicon layer and the tunneling layer 2 within the second region Q2 are both removed.

[0154] In this example, a portion of the N-type doped polysilicon layer on the back side is etched away as an example.

[0155] S107: Reference Fig.13 As shown, texturing is performed on the front and back sides of the N-type silicon substrate 1 respectively.

[0156] The entire front surface of the N-type silicon substrate 1 is textured, and the back surface is textured only within the second region Q2 to form a pyramid light trapping structure, namely, a textured structure 12 , at a corresponding position.

[0157] Before texturing, hydrofluoric acid is first used for cleaning to remove the hydrogenated silicon nitride layer 7 remaining after laser film opening, the tunneling layer 2 and the N-type doped polysilicon layer 3 in the second region, and the tunneling layer 2 and the N-type doped polysilicon layer 3 on the front side of the N-type silicon substrate 1.

[0158] Among them, a potassium hydroxide solution with a concentration of 0.8% to 1.2% can be used for texturing. For example, a potassium hydroxide solution with a mass fraction of 0.8%, 0.9%, 0.95%, 1% or 1.2% can be used as a texturing additive in a tank cleaning machine to texturize the N-type silicon substrate 1 to form a velvet surface on the front side of the N-type silicon substrate 1 and the second area Q2 on the back side of the N-type silicon substrate 1.

[0159] After the texturing is completed, the SC1 cleaning tank - CP smoothing tank - SC2 cleaning tank - pickling tank can be used for cleaning respectively; among them, the function of the SC1 cleaning tank is mainly to remove contamination and chemical residues on the surface of the intermediate part, the function of the CP smoothing tank is to smooth the top and bottom of the pyramid to prevent the epitaxial growth of amorphous silicon deposition, the function of the SC2 cleaning tank is to remove the metal residue of the N-type silicon substrate 1, and the function of the pickling tank is to complete the chemical passivation of the intermediate part and form a hydrophobic structure.

[0160] The hydrogenated silicon nitride plating on the front surface of the N-type silicon substrate 1 can be removed after the texturing is completed, while the hydrogenated silicon nitride plating on the side surface can be retained or not according to the actual situation.

[0161] S108: Reference Fig.14 As shown, an intrinsic amorphous silicon layer 4 is deposited on the front and back sides of the component formed after texturing.

[0162] The plate-type PECVD equipment can be used to deposit the intrinsic amorphous silicon layer 4 on the front and back sides respectively. The intrinsic amorphous silicon layer 4 can be deposited on the front side first, and then on the back side; or the intrinsic amorphous silicon layer 4 can be deposited on the back side first, and then on the front side. When depositing the intrinsic amorphous silicon layer 4, the intrinsic amorphous silicon layer 4 will only be formed on part of the side surface, and will not be plated around the opposite side of the current deposition surface.

[0163] S109: Reference Fig.15 As shown, a P-type microcrystalline silicon layer 5 is deposited on the front and back sides of the component formed in step S108, and SiN is deposited on the P-type microcrystalline silicon layer 5 on the front side. x Anti-reflection layer 6.

[0164] Among them, there will be SiN on the back and sides x During the wrap-around plating, there will be P-type amorphous silicon wrap-around plating on the side.

[0165] S110: Reference Fig.16As shown, the intrinsic amorphous silicon layer 4 and the P-type microcrystalline silicon layer 5 are opened in the first region Q1 until the N-type doped polysilicon layer 3 is exposed. Fig.10 , the two sides of the film opening area L are covered parts G.

[0166] For example, the intrinsic amorphous silicon layer 4 and the P-type microcrystalline silicon layer 5 may be opened in the first region Q1 by laser etching.

[0167] S111: After the film is opened, the SiN on the back is removed by wet etching process. x Oxides and residues remaining in the plating and film opening areas.

[0168] For example, a chain pickling machine can be used to etch the SiN on the back side. x Oxides and residues remaining in the plating and film opening areas.

[0169] S112: Reference Fig.17 As shown, after the wet etching process, a transparent conductive film 101 is deposited on the back side.

[0170] The material of the transparent conductive film 101 is, for example, ITO, etc. The thickness of the transparent conductive film 101 can be 10nm-300nm; for example, 10nm, 20nm, 35nm, 40nm, 60nm, 85nm, 100nm, 110nm, 130nm, 150nm, 180nm, 210nm, 240nm, 270nm, 300nm, etc.

[0171] S113: Reference Fig.18 As shown, the transparent conductive film 101 is disconnected at the boundary between the first region Q1 and the second region Q2 to form a first transparent electrode pattern 11 and a second transparent electrode pattern 21 .

[0172] For example, by screen printing, a viscous etching paste 8 containing phosphoric acid is formed at least at the position corresponding to the climbing portion P and the partial covering portion G near the climbing portion P, and the etching paste 8 is solidified to avoid excessive flow during the etching process, so that the etching paste 8 disconnects the transparent conductive film 101 to form a first transparent electrode pattern 11 and a second transparent electrode pattern 21 isolated from each other, wherein the first transparent electrode pattern 11 is set on the entire layer of the exposed first semiconductor region and the part of the covering portion G extending perpendicular to the first region Q1 to the second region, or the first transparent electrode pattern 11 is set on the part of the exposed first semiconductor region and the part of the covering portion G. After the etching of the transparent conductive film 101 is completed, the above-mentioned second gap W2 and third gap W3 are formed. In a certain cross section, for example but not limited to the plane parallel to the AA cross section, the second gap W2 is 20μm and the third gap W3 is 50μm. The sizes of the second gap W2 and the third gap W3 in the following different examples are at the same cross-sectional position as in this example.

[0173] Etching is performed by etching paste 8 so that the thickness of the edge of the first transparent electrode pattern 11 close to the first gap W1 is smaller than the thickness of the middle area C1 of the first transparent electrode pattern 11; the thickness of the edge of the second transparent electrode pattern 21 close to the first gap W1 is smaller than the thickness of the middle area of ​​the second transparent electrode pattern 21.

[0174] In addition, the transparent conductive film 101 is disconnected by using the etching paste 8 to form the first transparent electrode pattern 11 and the second transparent electrode pattern 21. Compared with the method of disconnecting the transparent conductive film 101 by laser etching or photolithography, the present solution can effectively disconnect the transparent conductive film 101, thereby reducing the problem of residual transparent conductive material and large leakage current caused by laser etching of the transparent conductive film 101. It also solves the problem that photolithography etching needs to go through several processes such as dry film lamination, exposure, development, etching, and dry film removal, resulting in a long production process for the battery, high difficulty in controlling the manufacturing process, and limitations in production capacity and cost, which cannot meet the problem of large-scale production.

[0175] Among them, the thickness reduction area of ​​the first transparent electrode pattern on one side close to the first gap W1 is the first thickness reduction area B1, the width W4 of the first thickness reduction area B1 is 10μm-50μm, and the thickness T1 of the first thickness reduction area B1 close to the edge of the first gap W1 is 45nm-65nm.

[0176] S114: Reference Fig.19 As shown, the etching paste 8 residue is removed.

[0177] For example, the etching paste 8 residue is removed by wet alkaline etching. When the etching paste 8 residue is removed by wet alkaline etching, the first transparent electrode pattern 11 and the second transparent electrode pattern 21 are not affected.

[0178] S115: Reference Fig. 20 As shown, an isolation protection layer 102 is respectively disposed at the position of the second semiconductor layer located at the first gap W1 , and at the positions of the climbing portion P and the covering portion G of the second semiconductor layer.

[0179] In this example, the ink layer serving as the isolation protection layer 102 is formed by printing ink.

[0180] In other examples, an isolation protection layer 102 may be further provided at the position of the second semiconductor layer located at the first gap W1; or, an isolation protection layer 102 may be provided at the positions of the climbing portion P and the covering portion G of the second semiconductor layer.

[0181] S116: Reference Fig.21 As shown, an electrode D is formed on the first transparent electrode pattern 11 and the second transparent electrode pattern 21 .

[0182] Metal paste is printed on the first transparent electrode pattern 11 and the second transparent electrode pattern 21 by screen printing, and the metal paste is cured to form corresponding electrodes.

[0183] Electrodes may also be formed by inkjet printing, laser transfer, chemical plating, electroplating or PVD.

[0184] The tunneling layer 2 and the N-type doped polysilicon layer 3 are formed at a high temperature of 600-800°C, and are located on the polished surface of the N-type silicon substrate 1. The contact interface between the electrode in the first region Q1 and the N-type doped polysilicon layer 3 is a smooth contact, and the N-type doped polysilicon layer 3 formed under a high temperature environment has a smooth surface structure that can ensure the passivation effect of the tunneling layer 2. Due to the high temperature process, the film layer has good adhesion and compactness, and the bonding force with the electrode is also strong. The intrinsic amorphous silicon layer 4 and the P-type microcrystalline silicon layer 5 in the second region Q2 have not undergone the high temperature process of the tunneling layer 2 and the N-type doped polysilicon layer 3 in the first region Q1. The electrode is connected to the P-type microcrystalline silicon layer 5, and the connection effect needs to be improved. The contact area of ​​a simple smooth surface structure is small, which is not conducive to the bonding force of the electrode. Therefore, a velvet structure is set in the second region Q2 to increase the specific surface area of ​​the contact surface and improve the bonding force between the electrode and the P-type microcrystalline silicon layer 5.

[0185] Example 2

[0186] This embodiment provides a back-contact photovoltaic cell. The difference between this embodiment and Embodiment 1 is mainly as follows:

[0187] On the front side of the N-type silicon substrate 1, the intrinsic amorphous silicon layer 4 and the SiN x The P-type microcrystalline silicon layer 5 is not provided between the anti-reflection layers 6 .

[0188] Example 3

[0189] This embodiment provides a back-contact photovoltaic cell. The difference between this embodiment and Embodiment 1 is mainly as follows:

[0190] The second gap W2 is 10 μm, and the third gap W3 is 50 μm.

[0191] Example 4

[0192] This embodiment provides a back-contact photovoltaic cell. The difference between this embodiment and Embodiment 1 is mainly as follows:

[0193] The second gap W2 is 20 μm, and the third gap W3 is 60 μm.

[0194] Example 5

[0195] This embodiment provides a back-contact photovoltaic cell. The difference between this embodiment and Embodiment 1 is mainly as follows:

[0196] The second gap W2 is 20 μm, and the third gap W3 is 70 μm.

[0197] Example 6

[0198] This embodiment provides a back-contact photovoltaic cell. The difference between this embodiment and Embodiment 1 is mainly as follows:

[0199] The second gap W2 is 30 μm, and the third gap W3 is 60 μm.

[0200] Example 7

[0201] This embodiment provides a back-contact photovoltaic cell. The difference between this embodiment and Embodiment 2 is mainly as follows:

[0202] The second gap W2 is 30 μm, and the third gap W3 is 70 μm.

[0203] Example 8

[0204] This embodiment provides a back-contact photovoltaic cell. The difference between this embodiment and Embodiment 2 is mainly as follows:

[0205] The second gap W2 is 30 μm, and the third gap W3 is 80 μm.

[0206] Example 9

[0207] This embodiment provides a back-contact photovoltaic cell. The difference between this embodiment and Embodiment 2 is mainly as follows:

[0208] The second gap W2 is 40 μm, and the third gap W3 is 80 μm.

[0209] Example 10

[0210] This embodiment provides a back-contact photovoltaic cell. The difference between this embodiment and Embodiment 1 is mainly as follows:

[0211] The second region Q2 is the groove region. A TCO island 22 is provided at a trough portion of the bottom pile surface of the groove region. The TCO island 22 is away from the climbing portion P and isolated from the climbing portion P.

[0212] Embodiment 11

[0213] This embodiment provides a back-contact photovoltaic cell. The difference between this embodiment and Embodiment 1 is mainly as follows:

[0214] In S207, the steps before texturing are replaced by using HF solution to perform roller-liquid etching on the front side of the intermediate component of S206, removing the hydrogenated silicon nitride plated around the front side and the hydrogenated silicon nitride on the side part, and the removed hydrogenated silicon nitride on the side extends from the front to the back, and the removed width accounts for less than 80% of the width of the side of the back contact battery. (After texturing, the side of the battery has velvet from the front to the back, but no velvet near the back. The local velvet on the side increases light trapping, and no velvet near the back is retained at the edge of the back side. The tunneling layer has a passivation effect and reduces carrier recombination.)

[0215] Example 12

[0216] This embodiment provides a back-contact photovoltaic cell. The difference between this embodiment and Embodiment 1 is mainly as follows:

[0217] In S208, an aluminum oxide passivation layer and a hydrogenated silicon nitride anti-reflection layer are deposited on the front side of the component formed after texturing.

[0218] In S209 , intrinsic amorphous silicon and P-type doped microcrystalline silicon are deposited on the back side of the component formed after S208 .

[0219] Comparative Example 1

[0220] This comparative example provides a back-contact photovoltaic cell, and the preparation method thereof is as follows:

[0221] S201: providing an N-type silicon substrate 1, and polishing at least the front side and the back side of the N-type silicon substrate 1 by using a wet polishing process.

[0222] Before polishing, the N-type silicon substrate 1 needs to be cleaned to remove impurities, particles and organic matter on the surface. Generally, deionized water, alkaline solution (such as sodium hydroxide NaOH) and acidic solution (such as dilute nitric acid HNO3) can be used for multi-step cleaning.

[0223] For example, but not limited to, the N-type silicon substrate 1 is placed in a tank-type alkaline polishing machine for polishing and cleaning. The working volume of the tank of the cleaning machine is 360L. First, the N-type silicon substrate 1 is pre-cleaned to remove organic and other contaminants generated during the cutting and transportation of the N-type silicon substrate 1. In this embodiment, the No. 1 solution of the standard RCA cleaning is used for cleaning. The No. 1 solution is composed of NH4OH-H2O2-H2O, and the volume ratio of the three is 1:1:5. The temperature during cleaning is 65°C. The main function of the SC-1 reagent cleaning is alkaline oxidation to remove particles on the silicon wafer, and can oxidize and remove a small amount of organic matter and metal atomic pollution such as Au, Ag, Cu, Ni, Cd, Zn, Ca, Cr, etc. on the surface; after water washing and residual chemicals, alkaline polishing treatment is performed. The alkaline polishing formula is 5.97%wt KOH, the temperature is 80°C, and the alkaline polishing treatment time is 300s to remove damage and polish. Then SC1 cleaning, ozone cleaning, and finally acid washing and dehydration are performed to complete polishing and cleaning. After polishing, the polished surface has a plurality of tower bases remaining in the unit cell, and the maximum distance between any two points of the tower base is 4 μm-6 μm. For example, the size of the tower base remaining after polishing can be controlled by controlling the concentration, temperature and polishing time of the polishing liquid.

[0224] S202: In a low pressure chemical vapor deposition (LPCVD) device, the N-type silicon substrate 1 is subjected to thermal oxidation treatment to form a tunneling layer 2 made of silicon dioxide on the front and back of the N-type silicon substrate 1. The thickness of the tunneling layer 2 can be 1nm-5nm, such as 1nm, 1.5nm, 1.8nm, 2nm, 2.3nm, 2.6nm, 3nm, 3.5nm, 4nm, 4.7nm, 5nm, etc. Then, an intrinsic polysilicon layer is deposited on each tunneling layer 2. In addition to LPCVD, the deposition of the intrinsic polysilicon layer can also be carried out by plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), plasma enhanced atomic layer deposition (PEALD), etc. Generally, it is preferred to use LPCVD to deposit the back tunneling layer 2 and the intrinsic polysilicon layer at a high temperature of 600-800° C. Using LPCVD equipment for deposition can reduce equipment cost investment.

[0225] During the process of forming the tunneling layer 2 and the intrinsic polysilicon layer, a certain amount of silicon dioxide and intrinsic polysilicon will be formed on the side of the N-type silicon substrate 1 .

[0226] It should be noted that various wrap-around plating is not shown in the drawings.

[0227] S203: Phosphorus is diffused into the intrinsic amorphous silicon layer 4 on the front and back sides of the N-type silicon substrate 1 to form an N-type doped polysilicon layer 3. The phosphorus doping concentration is 8E19-5E20cm -3 (For example, it can be 8E19 / 9E19 / 1E20 / 2E20 / 3E20 / 4E20 / 5E20cm -3 ).

[0228] Phosphorus diffusion can be carried out in a tube furnace.

[0229] During the phosphorus diffusion process, a phosphorus silicon glass layer (PSG) is formed on the surface of the N-type doped polysilicon layer, and PSG is plated around the side.

[0230] S204: Remove the PSG on the front side, back side and surrounding plating.

[0231] For example, but not limited to, PSG may be removed by hydrofluoric acid in a tank cleaning apparatus.

[0232] S205: Depositing a hydrogenated silicon nitride layer 7 (SiNx:H) on the N-type doped polysilicon layer on the back side.

[0233] For example, a hydrogenated silicon nitride layer 7 can be deposited in a tubular PECVD device. The hydrogenated silicon nitride layer 7 can be used as a mask for subsequent processes. When laser film opening is performed later, the hydrogenated silicon nitride layer 7 acts as a laser energy absorption layer, which has the effect of reducing the effect of the laser film opening process on the passivation effect of the N region, and also has the effect of providing a hydrogen source to further passivate the polysilicon and silicon substrate, thereby improving the passivation effect and protecting the N-type doped crystalline silicon layer 3 from being corroded by alkali during the texturing process. The thickness of the hydrogenated silicon nitride layer 7 can be 50nm-110nm.

[0234] Wherein, hydrogenated silicon nitride wrapping is formed on at least the front N-type doped polysilicon layer 3 .

[0235] S206: opening the dehydrogenated silicon nitride layer 7 within the second region Q2 to form a mask.

[0236] For example, the hydrogenated silicon nitride layer 7 within the second region Q2 may be removed by laser etching. In some examples, after the hydrogenated silicon nitride layer 7 within the second region Q2 is removed, etching downwards is continued so that a portion of the N-type doped polysilicon layer on the back is also etched away. In other examples, after the hydrogenated silicon nitride layer 7 within the second region Q2 is removed, etching downwards is continued until the surface of the N-type silicon substrate 1 is etched, that is, the N-type doped polysilicon layer and the tunneling layer 2 within the second region Q2 are both removed.

[0237] In this example, a portion of the N-type doped polysilicon layer on the back side is etched away as an example.

[0238] S207: Texturing is performed on the front side and the back side of the N-type silicon substrate 1 respectively.

[0239] The entire front surface of the N-type silicon substrate 1 is textured, and the back surface is textured only within the second region Q2 to form a pyramid light trapping structure, namely, a textured structure 12 , at a corresponding position.

[0240] Before texturing, hydrofluoric acid is first used for cleaning to remove the hydrogenated silicon nitride layer 7 remaining after laser film opening, the tunneling layer 2 and the N-type doped polysilicon layer 3 in the second region, and the tunneling layer 2 and the N-type doped polysilicon layer 3 on the front side of the N-type silicon substrate 1.

[0241] Among them, a potassium hydroxide solution with a concentration of 0.8% to 1.2% can be used for texturing. For example, a potassium hydroxide solution with a mass fraction of 0.8%, 0.9%, 0.95%, 1% or 1.2% can be used as a texturing additive in a tank cleaning machine to texturize the N-type silicon substrate 1 to form a velvet surface on the front side of the N-type silicon substrate 1 and the second area Q2 on the back side of the N-type silicon substrate 1.

[0242] After the texturing is completed, the SC1 cleaning tank - CP smoothing tank - SC2 cleaning tank - pickling tank can be used for cleaning respectively; among them, the function of the SC1 cleaning tank is mainly to remove contamination and chemical residues on the surface of the intermediate part, the function of the CP smoothing tank is to smooth the top and bottom of the pyramid to prevent the epitaxial growth of amorphous silicon deposition, the function of the SC2 cleaning tank is to remove the metal residue of the N-type silicon substrate 1, and the function of the pickling tank is to complete the chemical passivation of the intermediate part and form a hydrophobic structure.

[0243] The hydrogenated silicon nitride plating on the front surface of the N-type silicon substrate 1 can be removed after the texturing is completed, while the hydrogenated silicon nitride plating on the side surface can be retained or not according to the actual situation.

[0244] S208: depositing an intrinsic amorphous silicon layer 4 on the front and back sides of the component formed after texturing.

[0245] The plate-type PECVD equipment can be used to deposit the intrinsic amorphous silicon layer 4 on the front and back sides respectively. The intrinsic amorphous silicon layer 4 can be deposited on the front side first, and then on the back side; or the intrinsic amorphous silicon layer 4 can be deposited on the back side first, and then on the front side. When depositing the intrinsic amorphous silicon layer 4, the intrinsic amorphous silicon layer 4 will only be formed on part of the side surface, and will not be plated around the opposite side of the current deposition surface.

[0246] S209: depositing a P-type microcrystalline silicon layer 5 on the front and back of the component formed in step S208, and depositing SiN on the P-type microcrystalline silicon layer 5 on the front. x Anti-reflection layer 6.

[0247] Among them, there will be SiN on the back and sides x During the wrap-around plating, there will be P-type amorphous silicon wrap-around plating on the side.

[0248] S210 : opening the intrinsic amorphous silicon layer 4 and the P-type microcrystalline silicon layer 5 in the first region Q1 until the N-type doped polycrystalline silicon layer 3 is exposed.

[0249] For example, the intrinsic amorphous silicon layer 4 and the P-type microcrystalline silicon layer 5 may be opened in the first region Q1 by laser etching.

[0250] S211: After the film is opened, the SiN on the back is removed by wet etching process. x Oxides and residues remaining in the plating and film opening areas.

[0251] For example, a chain pickling machine can be used to etch the SiN on the back side. x Oxides and residues remaining in the plating and film opening areas.

[0252] S212: After the wet etching process, a transparent conductive film 101 is deposited on the back side.

[0253] The material of the transparent conductive film 101 is, for example, ITO, etc. The thickness of the transparent conductive film 101 can be 10nm-300nm; for example, 10nm, 20nm, 35nm, 40nm, 60nm, 85nm, 100nm, 110nm, 130nm, 150nm, 180nm, 210nm, 240nm, 270nm, 300nm, etc.

[0254] S213 : disconnecting the transparent conductive film 101 at the boundary between the first region Q1 and the second region Q2 to form a first transparent electrode pattern 11 and a second transparent electrode pattern 21 .

[0255] For example, by laser film opening, the transparent conductive film 101 is etched and disconnected at the climbing portion P at the junction of the first region Q1 and the second region Q2 to form the first transparent electrode pattern 11 and the second transparent electrode pattern 21, and have the second gap W2 and the third gap W3. The second gap W2 is 20 μm, and the third gap W3 is 50 μm. The power of the laser is 28W.

[0256] When the transparent conductive film 101 is cut off by laser etching, the high temperature generated due to the high laser energy will affect the passivation of the back-contact photovoltaic cell, thereby affecting the electrical performance of the back-contact photovoltaic cell.

[0257] Comparative Example 2

[0258] This comparative example provides a back-contact photovoltaic cell, which is mainly different from comparative example 1 in that the power of the laser is 31W.

[0259] Comparative Example 3

[0260] This comparative example provides a back-contact photovoltaic cell, which is mainly different from comparative example 1 in that the power of the laser is 34W.

[0261] Comparative Example 4

[0262] This comparative example provides a back-contact photovoltaic cell, which is mainly different from comparative example 1 in that the power of the laser is 37W.

[0263] The energy conversion efficiency Eta, parallel resistance Rsh, open circuit voltage Voc, fill factor FF, and leakage current I-RV of the back contact photovoltaic cells prepared in Examples 1-10 and Comparative Examples 1-4 were tested for performance, and the results are shown in the following table:

[0264]

[0265]

[0266] It is not difficult to see from the above that the leakage current of each example of the present solution is much smaller than that of each comparative example.

[0267] It should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like used above to indicate orientations or positional relationships are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, the meaning of "multiple" is two or more.

[0268] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with the technical features with similar functions disclosed in this application (but not limited to) by each other.

Claims

1. A back contact photovoltaic cell, characterized in that: The silicon substrate comprises a front side and a back side, the back side is provided with a plurality of first regions and a plurality of second regions in sequence and alternately, each of the first regions is provided with a first semiconductor layer, and each of the second regions is provided with a second semiconductor layer; The first semiconductor layer is connected to a first transparent electrode pattern, the second semiconductor layer is connected to a second transparent electrode pattern, and the first transparent electrode pattern and the second transparent electrode pattern are isolated from each other by a first gap; The edge of the first transparent electrode pattern is close to the first gap, and in a direction extending perpendicularly from the first area to the second area, the edge of the first transparent electrode pattern is wavy; and / or; The second transparent electrode pattern is close to an edge of the first gap, and in a direction extending perpendicularly from the first area to the second area, the edge of the second transparent electrode pattern is wavy.

2. The back contact photovoltaic cell according to claim 1, characterized in that: The second semiconductor layer extends from the second region to the first region, and sequentially includes a climbing portion and a covering portion, wherein the covering portion covers a portion of the first semiconductor layer to form an exposed first semiconductor region and a covered first semiconductor region; A second transparent electrode pattern is disposed on the second semiconductor layer above the orthographic projection of the second region; A first transparent electrode pattern is arranged on the entire exposed first semiconductor region and on a portion of the covering portion extending in a direction perpendicular to the first region toward the second region; or, A first transparent electrode pattern is disposed on a portion of the exposed first semiconductor region and a portion of the covering portion.

3. The back contact photovoltaic cell according to claim 2, characterized in that: When a second transparent electrode pattern is provided on a portion of the second semiconductor layer above the orthographic projection of the second region, a second gap is formed between an edge of the second transparent electrode pattern and the climbing portion on the cross section of the back-contact photovoltaic cell; preferably, the width of the second gap is 10μm-80μm, preferably 20-50μm.

4. The back contact photovoltaic cell according to claim 3, characterized in that: A third gap is formed between the edge of the first transparent electrode pattern and the climbing portion. Preferably, the width of the third gap is 40 μm-80 μm, preferably 40 μm-60 μm.

5. The back contact photovoltaic cell according to claim 4, characterized in that: The ratio of the width of the covering portion to the width of the third gap is between 1.3 and 2.

6. The back contact photovoltaic cell according to claim 2, characterized in that: The climbing portion is inclined relative to the back side of the silicon substrate. Preferably, the climbing portion has an inclination angle of 5°-80°, preferably 30°-70°, relative to the back side of the silicon substrate.

7. The back contact photovoltaic cell according to claim 2, characterized in that: The adjacent first semiconductor layer and the silicon substrate form a first groove, the second area is the bottom area of ​​the first groove, the second area has a velvet surface, the valley part of the velvet surface has a TCO island, and the TCO island is far away from the climbing part and isolated from the climbing part.

8. The back contact photovoltaic cell according to claim 1, characterized in that: The first transparent electrode pattern has a reduced thickness region on one side close to the first gap, the width of the reduced thickness region is 10 μm-50 μm, and the thickness of the reduced thickness region close to the edge of the first gap is 45 nm-65 nm.

9. The back contact photovoltaic cell according to any one of claims 1 to 8, characterized in that: The first semiconductor layer comprises a tunneling layer disposed on the silicon substrate, and an N-type doped polysilicon layer is disposed on a side of the tunneling layer away from the silicon substrate; The second semiconductor layer includes an intrinsic amorphous silicon layer, and a P-type doped microcrystalline silicon layer is disposed on a side of the intrinsic amorphous silicon layer away from the silicon substrate.

10. A method for preparing a back-contact photovoltaic cell, characterized in that: The following steps are involved: A battery precursor is provided, the battery precursor comprising a silicon substrate, a back side of the silicon substrate being alternately provided with a plurality of first regions and a plurality of second regions, each of the first regions being provided with a first semiconductor layer, and each of the second regions being provided with a second semiconductor layer; forming a transparent electrode film on the back side of the battery precursor; On the transparent electrode film, etching is performed at the junction of the first region and the second region to etch the transparent electrode film to form a first transparent electrode pattern connected to the first semiconductor layer and a second transparent electrode pattern connected to the second semiconductor layer, the first transparent electrode pattern and the second transparent electrode pattern are isolated from each other by a first gap; the first transparent electrode pattern is close to the edge of the first gap, and the shape of the edge of the first transparent electrode pattern is wavy in a direction extending from the first region to the second region at right angles; and / or; the second transparent electrode pattern is close to the edge of the first gap, and the shape of the edge of the second transparent electrode pattern is wavy in a direction extending from the first region to the second region at right angles.

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