Solar cell and photovoltaic module

Abstract

The invention discloses a solar cell and a photovoltaic module, the solar cell comprises a silicon substrate, the silicon substrate comprises a first surface and a second surface which are oppositely arranged, and the second surface comprises a first area and a second area which are distributed at an interval. A tunneling passivation contact structure and a second electrode are arranged in a partial area of the second surface, the projection of the tunneling passivation contact structure on the second surface of the silicon substrate is located in the first area, and the tunneling passivation contact structure comprises a tunneling layer in direct contact with the silicon substrate and a second doping layer arranged on the tunneling layer; and the second electrode is in contact with the second doped layer. Only the tunneling passivation contact structure is stacked on the metal region on the back of the solar cell, and no tunneling passivation contact structure is stacked on the non-metal region, so that parasitic absorption of the back of the cell can be reduced, current can be remarkably improved, the contact performance of the back electrode and the second doping layer is not affected, and the service life of the cell is prolonged. And the cell efficiency and the double-sided rate are remarkably improved while the process window is improved.

Description

Technical Field

[0001] The invention belongs to the technical field of photovoltaic cells, and in particular relates to a solar cell and a photovoltaic module. Background Art

[0002] With the rapid development of the photovoltaic industry, the performance and efficiency requirements of solar cells in the domestic and foreign photovoltaic markets are also constantly increasing, and industry manufacturers have focused on the research and development of high-efficiency batteries. TOPCon (Tunnel Oxide Passivated Contact) cells can improve the surface passivation performance of the cell, reduce the metal contact composite current, and effectively increase the open circuit voltage and short circuit current of the cell by sequentially preparing an ultra-thin tunnel oxide layer and a doped polysilicon layer on the back of the silicon substrate. In recent years, the market share of TOPCon cells has risen rapidly, and has gradually surpassed PERC cells to become the mainstream technology for solar cells.

[0003] Both the n+ polarity and the p+ polarity in TOPCon cells have excellent passivation and conductivity properties, and are compatible with traditional industrial production, and have broad development prospects. With the continuous optimization of TOPCon cells, the parasitic absorption of the back polysilicon layer (poly) has become the primary factor limiting the improvement of TOPCon cell efficiency and bifaciality.

[0004] In TOPCon cells, the back polysilicon layer is doped with phosphorus to form a doped polysilicon layer (N+Poly), which has three main functions: 1. Provide field passivation effect; 2. As a phosphorus-rich layer, it greatly improves the contact on the back; 3. Isolates the direct contact between the Ag metal and the silicon substrate, reducing metal recombination. In addition to the above advantages, the parasitic absorption of the polysilicon layer is its biggest disadvantage. Parasitic absorption refers to an optical absorption mechanism that does not generate electron-hole pairs in the silicon body, thereby reducing the utilization rate of light. In order to reduce the recombination of the Ag metal area on the back, the thickness of the polysilicon layer is generally greater than 100nm. Reducing the thickness of the polysilicon layer while ensuring that the passivation of the metal area is not lost has become the main optimization direction of TOPCon cells.

[0005] Therefore, in view of the above technical problems, it is necessary to provide a solar cell and a photovoltaic module. Summary of the invention

[0006] The object of the present invention is to provide a photovoltaic cell and a photovoltaic module to reduce the parasitic absorption on the back of the cell and increase the current of the cell.

[0007] In order to achieve the above purpose, the technical solution provided by an embodiment of the present invention is as follows:

[0008] A solar cell comprises a silicon substrate, the silicon substrate comprises a first surface and a second surface arranged opposite to each other, the second surface comprises a first region and a second region distributed at intervals, a tunneling passivation contact structure and a second electrode are arranged in a partial region of the second surface, the projection of the tunneling passivation contact structure on the second surface of the silicon substrate is located in the first region, the tunneling passivation contact structure comprises a tunneling layer directly in contact with the silicon substrate and a second doping layer arranged on the tunneling layer, and the second electrode is in contact with the second doping layer.

[0009] In one embodiment, a first doping layer and a first electrode are formed on the first surface of the silicon substrate, the doping type of the first doping layer is opposite to the doping type of the silicon substrate, and the first electrode is in contact with the first doping layer.

[0010] In one embodiment, the first doped layer is a P-type doped layer; and / or,

[0011] The surface doping concentration of the first doping layer is 3E18cm -3 ~3E19cm -3 .

[0012] In one embodiment, a first passivation layer and / or a first anti-reflection layer is stacked on the first doped layer.

[0013] In one embodiment, the first passivation layer is an aluminum oxide passivation layer with a thickness of 2nm to 7nm or 3nm to 6nm; the first anti-reflection layer is a stacked film formed by any one or more of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer, with a thickness of 60nm to 130nm.

[0014] In one embodiment, the second doped layer is a doped polysilicon layer, and the doping type of the second doped layer is the same as the doping type of the silicon substrate.

[0015] In one embodiment, the silicon substrate is an N-type silicon substrate, and the second doped layer is an N-type doped polysilicon layer; and / or,

[0016] The surface doping concentration of the second doping layer is 1E20cm -3 ~1E21cm -3 , with a thickness of 1nm~150nm or 50nm~100nm.

[0017] In one embodiment, the tunneling layer is a silicon oxide layer, a silicon oxynitride layer, or a combination of the two, and has a thickness of 0.5 nm to 3 nm or 1.5 nm to 2.5 nm.

[0018] In one embodiment, a second passivation layer and / or a second anti-reflection layer is at least partially stacked on the second surface of the silicon substrate, and the second passivation layer and / or the second anti-reflection layer is stacked on the second region of the second surface and on the tunnel passivation contact structure.

[0019] In one embodiment, the second passivation layer is an aluminum oxide passivation layer with a thickness of 2nm to 7nm or 3nm to 6nm; and / or,

[0020] The second anti-reflection layer is a stacked film formed by any one or more of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer, and has a thickness of 60 nm to 130 nm.

[0021] In one embodiment, the first region includes a plurality of first sub-regions that are distributed in parallel and at equal intervals, the second electrode includes a plurality of gate lines that are distributed in parallel, and the width of the first sub-region is greater than or equal to the width of the gate line.

[0022] In one embodiment, the width of the first sub-region is 50 μm to 150 μm, and the width of the gate line is 15 μm to 100 μm.

[0023] In one embodiment, a pyramid velvet structure is formed on the first surface of the silicon substrate; and / or,

[0024] The second surface of the silicon substrate is a polished surface.

[0025] Another embodiment of the present invention provides a technical solution as follows:

[0026] A photovoltaic component comprises the above-mentioned solar cell.

[0027] Compared with the prior art, the present invention has the following beneficial effects:

[0028] The back side of the solar cell of the present invention has only a tunnel passivation contact structure stacked on the metal area, and there is no tunnel passivation contact structure on the non-metal area, which can reduce the parasitic absorption on the back side of the battery, and the current can be significantly improved without affecting the contact performance between the back electrode and the second doping layer. The process window is improved while the battery efficiency and bifaciality are significantly improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0030] Figure 1is a schematic structural diagram of a solar cell in Example 1 of the present invention;

[0031] Figure 2 for Figure 1 Schematic diagram of the local structure at A in the middle;

[0032] Figure 3 is a schematic plan view of the second surface of the silicon substrate in Example 1 of the present invention;

[0033] Figure 4 is a plan view schematically showing the second surface and the second electrode in Example 1 of the present invention;

[0034] Figures 5a to 5j is a process flow chart of preparing a solar cell in Example 1 of the present invention;

[0035] Figure 6 Schematic diagram of a laser scanning pattern in a laser process in Example 1 of the present invention;

[0036] Figures 7a to 7c A process flow chart of preparing a first doping layer on the first surface of a silicon substrate in Example 2 of the present invention;

[0037] Figures 8a to 8j is a process flow chart of preparing a solar cell in Example 3 of the present invention;

[0038] Fig. 9 Schematic diagram of laser pattern in the laser film opening process in Example 3 of the present invention;

[0039] Fig.10 This is a surface morphology image of the second area on the silicon substrate after the chemical etching process in Example 3 of the present invention.

[0040] Description of main reference numerals:

[0041] 10-substrate, 11-first doped layer, 11'-boron-doped amorphous silicon layer, 21-first passivation layer, 31-first anti-reflection layer, 12-tunneling layer, 13-second doped layer, 131-oxide layer, 22-second passivation layer, 32-second anti-reflection layer, 41-first electrode, 42-second electrode, 421-secondary gate line, 50-mask, S1-first surface, S2-second surface, S21-first region, S22-second region, 101-first sub-region, 102-second sub-region. DETAILED DESCRIPTION

[0042] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0043] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0044] The present invention discloses a solar cell, comprising a silicon substrate, wherein the silicon substrate comprises a first surface and a second surface arranged opposite to each other, the second surface comprises a first region and a second region distributed at intervals, a partial region of the second surface is provided with a tunneling passivation contact structure and a second electrode, a projection of the tunneling passivation contact structure on the second surface of the silicon substrate is located in the first region, the tunneling passivation contact structure comprises a tunneling layer directly in contact with the silicon substrate and a second doping layer arranged on the tunneling layer, and the second electrode is in contact with the second doping layer.

[0045] The invention also discloses a photovoltaic assembly, comprising the solar cell mentioned above.

[0046] The back side of the solar cell of the present invention has only a tunnel passivation contact structure stacked on the metal area, and there is no tunnel passivation contact structure on the non-metal area, which can reduce the parasitic absorption on the back side of the battery, and the current can be significantly improved without affecting the contact performance between the back electrode and the second doping layer. The process window is improved while the battery efficiency and bifaciality are significantly improved.

[0047] The present invention is further described below with reference to specific examples.

[0048] Embodiment 1:

[0049] Ginseng Figure 1 The solar cell in this embodiment is a schematic diagram of the structure of the solar cell, which is a TOPCon cell, including a silicon substrate 10, Figure 5aAs shown, the silicon substrate 10 includes a first surface S1 and a second surface S2 that are relatively arranged, and the second surface S2 includes a first area S21 and a second area S22. The first surface S1 is the front side (i.e., the light-receiving side) of the silicon substrate 10, and the second surface S2 is the back side (i.e., the backlight side) of the silicon substrate 10. The first area S21 is a back metal area, and the second area S22 is a back non-metal area.

[0050] The silicon substrate 10 in this embodiment is an N-type silicon substrate, and the resistivity is 0.3 Ω·cm to 7 Ω·cm, preferably 0.5 Ω·cm to 3.5 Ω·cm.

[0051] Furthermore, a light trapping structure is formed on the first surface S1 of the silicon substrate 10. For example, a pyramid velvet structure can be formed on the first surface S1 of the silicon substrate 10 by alkali texturing, and the size of the pyramid is 0.5μm to 3μm. The second surface S2 of the silicon substrate 10 is a polished surface, which can be the surface of the light trapping structure after chemical polishing, or the surface of the back of the original silicon substrate after direct chemical polishing. For example, in this embodiment, a pyramid velvet structure can be formed on the second surface S2 of the silicon substrate 10 by alkali texturing, and the size of the pyramid is 0.5μm to 3μm, and then the back is alkali polished to obtain a polished surface. Compared with the back of a conventional silicon substrate, a plurality of tower bases will be formed on the polished surface (the tower base is the base left after the pyramid velvet structure is polished).

[0052] In this embodiment, a first doping layer 11 (i.e., an emitter) is formed at the first surface S1 of the silicon substrate 10 by a diffusion process or a PECVD process, thereby forming a PN junction, and generating minority carrier-hole pairs after light exposure. Exemplarily, the first doping layer 11 in this embodiment is a P-type doping layer (i.e., a P+ emitter), which is formed below the first surface S1 of the silicon substrate (i.e., inside the silicon substrate) by a boron doping process, and the surface doping concentration is 3E18cm -3 ~3E19cm -3 , square resistance is 40Ω / sq~300Ω / sq, preferably 150Ω / sq~280Ω / sq.

[0053] Ginseng Figure 1 Combined with Figure 2 As shown, in this embodiment, a tunneling passivation contact structure is provided only on the first region S21 on the second surface S2 of the silicon substrate 10, while no tunneling passivation contact structure is provided on the second region S22.

[0054] Specifically, a tunneling layer 12 and a second doping layer 13 are sequentially stacked on the first region S21, and the projections of the tunneling layer 12 and the second doping layer 13 on the second surface S2 of the silicon substrate 10 are located within the first region S21. The tunneling layer 12 is directly in contact with the second surface S2 of the silicon substrate 10 in the first region S21, and can provide a good interface passivation effect in the first region S21. The second doping layer 13 can provide a field passivation effect. At the same time, because the doping concentration of this layer is relatively high, the contact can be improved and the resistance can be reduced.

[0055] The tunneling layer 12 is a silicon oxide layer, a silicon oxynitride layer, or a combination of the two, preferably a silicon oxide layer, with a thickness of 0.5 nm to 3 nm, preferably 1.5 nm to 2.5 nm; the second doping layer 13 is a phosphorus-doped polysilicon layer, with a surface doping concentration of 2E20 cm -3 ~3E21cm -3 , preferably 5E20cm -3 ~2E21cm -3 The thickness is 1nm to 150nm, preferably 50nm to 100nm. The thickness of the second doping layer of this embodiment is further reduced, which can reduce parasitic absorption without affecting the metallization contact performance, increase the short-circuit current density of the battery, and significantly improve the battery efficiency and bifaciality.

[0056] Preferably, in this embodiment, a first passivation layer 21 and a first anti-reflection layer 31 are sequentially stacked on the first surface S1 of the silicon substrate 10, and a second passivation layer 22 and a second anti-reflection layer 32 are sequentially stacked on the second surface S2 of the silicon substrate 10. The second passivation layer 22 and the second anti-reflection layer 32 cover the second doping layer 13 and extend into the second region S22. In the second region S22, the second passivation layer 22 is in direct contact with the silicon substrate 10. The first passivation layer 21 can provide excellent field passivation and chemical passivation effects, the second passivation layer 22 can provide a chemical passivation effect, and the first anti-reflection layer 31 can reduce reflectivity and increase light utilization.

[0057] Exemplarily, the first passivation layer 21 and the second passivation layer 22 are both aluminum oxide passivation layers with a thickness of 2nm to 7nm, preferably 3nm to 6nm; the first anti-reflection layer 31 and the second anti-reflection layer 32 can be a stacked film formed by any one or more of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer, with a thickness of 60nm to 130nm, preferably a silicon nitride layer. Silicon nitride is chemically inactive, has strong acid and alkali corrosion resistance, and can reduce the sensitivity of the battery to the environment.

[0058] In addition, the first electrode 41 in this embodiment is located on the first surface S1 of the silicon substrate 10 and contacts the first doping layer 11, and the second electrode 42 is located on the second surface S2 of the silicon substrate 10, specifically on the first area S21 in the second surface S2, and contacts the second doping layer 13.

[0059] Ginseng Figure 3 As shown, in this embodiment, the first region S21 includes a plurality of first sub-regions 101 that are parallel and equally spaced, and the second region S22 includes a plurality of second sub-regions 102 that are parallel and equally spaced, and the first sub-regions 101 and the second sub-regions 102 are staggered. The width of the first sub-region 101 is smaller than the width of the second sub-region 102, for example, the ratio of the widths of the two can be 1: (5-20), preferably, the first region S21 occupies about 10% of the area of ​​the entire second surface S2.

[0060] Combination Figure 4 As shown, the second electrode 42 is a gate line electrode, which at least includes a plurality of parallel thin gate lines 421, and the width of the first sub-region 101 is greater than or equal to the width of the thin gate lines 421. Optionally, the second electrode 42 may also include a plurality of main gate lines (not shown) perpendicular to the thin gate lines 421.

[0061] In this embodiment, taking a 210TOPCon battery as an example, the size is 203.396±15mm, there are 230 fine grid lines 421, the width is 15μm to 100μm, and the spacing between adjacent fine grid lines is 0.907±0.015mm. The spacing between adjacent first sub-regions 101 is equal to the spacing between adjacent fine grid lines, and a fine grid line 421 is distributed on each first sub-region 101, and the width of the first sub-region 101 is greater than the width of the fine grid line 421. The width of the first sub-region is 50μm to 150μm, such as the width of the fine grid line is 40μm, and the width of the first sub-region is 80μm.

[0062] The method for preparing a solar cell in this embodiment specifically includes the following steps:

[0063] 1. Double-sided velveting

[0064] Ginseng Figure 5a As shown, a silicon substrate 10 is provided, and the silicon substrate 10 includes a first surface S1 and a second surface S2 that are arranged opposite to each other. The second surface S2 includes a first area S21 and a second area S22. The first surface S1 is the front side (i.e., the light-receiving side) of the silicon substrate 10, and the second surface S2 is the back side (i.e., the backlight side) of the silicon substrate 10. The first area S21 is a back metal area, and the second area S22 is a back non-metal area.

[0065] The silicon substrate 10 in this embodiment is an N-type silicon substrate, and the resistivity is 0.3 Ω·cm to 7 Ω·cm, preferably 0.5 Ω·cm to 3.5 Ω·cm.

[0066] Ginseng Figure 5b As shown, in this embodiment, the first surface S1 and the second surface S2 of the silicon substrate 10 are formed with a pyramid texture structure by an alkali texturing process, and the size of the pyramid is 0.5 μm to 3 μm.

[0067] 2. Boron Diffusion

[0068] Ginseng Figure 5c As shown, a P-type doped first doping layer (i.e., a P+ emitter) 11 is formed at the first surface S1 of the silicon substrate 10 by a boron diffusion process. Specifically, a boron source (e.g., BCl3 or BBr3, etc.) is used in a high-temperature furnace tube for diffusion, and a layer of silicon oxide is formed on the outer layer. After diffusion, the surface doping concentration of the first doping layer is 3E18cm -3 ~3E19cm -3 , the square resistance is 40Ω / sq~300Ω / sq, preferably 150Ω / sq~250Ω / sq. In the boron diffusion process, BSG (not shown) is formed on the second surface S2 of the silicon substrate.

[0069] In this embodiment, the outer silicon layer of the first surface S1 of the silicon substrate 10 is transformed into a boron diffusion layer. Figure 5c The total thickness of the silicon substrate 10 and the first doping layer 11 after the boron diffusion is Figure 5b The thickness of the silicon substrate 10 before the boron diffusion is uniform.

[0070] 3. Back polishing

[0071] Ginseng Figure 5d As shown, the silicon substrate after boron diffusion is first passed through a single-sided chain device, and a hydrofluoric acid solution is used to remove the back silicon oxide. The back side is then alkaline polished to remove the edge junction and back side wrap (BSG), and finally cleaned.

[0072] 4. Preparation of back-side tunneling passivation structure

[0073] Ginseng Figure 5e As shown, a tunneling layer 12 and a second doping layer 13 stacked in sequence are prepared on the second surface S2.

[0074] Illustratively, in this embodiment, a PECVD process is used to first deposit a silicon oxide tunneling layer with a thickness of 1nm to 3nm on the back side, and then deposit a phosphorus-doped amorphous silicon layer or multiple phosphorus-doped amorphous silicon layers with different doping concentrations, with a total thickness of 1nm to 150nm, preferably 50nm to 100nm.

[0075] 5. Laser oxidation

[0076] Ginseng Figure 5f As shown, the second doping layer 13 on the first region S21 is processed by a laser process, the second doping layer 13 on the first region S21 is crystallized and an oxide layer 131 is formed on the surface of the second doping layer on the first region S21.

[0077] In this embodiment, the second doped layer 13 before the laser process is a phosphorus-doped amorphous silicon layer. The laser process can crystallize the phosphorus-doped amorphous silicon layer on the first region S21, activate phosphorus, and transform the phosphorus-doped amorphous silicon layer into a phosphorus-doped polycrystalline silicon layer; at the same time, the instantaneous high temperature of the laser is used to form silicon oxide (SiO X ) layer, the silicon oxide layer serves as a mask for subsequent processes.

[0078] Specifically, the laser process is carried out in an atmosphere containing oxygen, and the volume concentration of oxygen is 20% to 80%; the laser power is 1W to 100W, preferably 30W to 60W; the laser frequency is 1kHz to 1000kHz, preferably 300kHz to 600kHz; the laser scanning rate is 10000mm / s to 100000mm / s, preferably 30000mm / s to 60000mm / s; the number of laser processing times is 1 to 100 times, preferably 1 to 10 times. The surface doping concentration of the second doping layer 13 after laser processing is 2E20cm -3 ~3E21cm -3 , preferably 5E20cm -3 ~2E21cm -3 The thickness of the formed oxide layer 131 is 1 nm to 50 nm.

[0079] For example, in a specific embodiment, the volume concentration of oxygen in the laser process is 50%, the laser power is 50 W, the laser frequency is 500 kHz, the laser scanning rate is 50000 mm / s, the number of laser processing times is 2 times, and the surface doping concentration of the phosphorus-doped amorphous silicon layer is 9E20 cm -3 The thickness of the silicon oxide layer formed by oxidation on the surface of the phosphorus-doped amorphous silicon layer is 0.01nm to 10nm.

[0080] Ginseng Figure 6 The figure shows the laser scanning pattern in the laser process of this embodiment. The black line portion corresponds to the laser scanning area, that is, the first area S21 (i.e., the metal area), and the blank portion is the second area S22 (i.e., the non-metal area). After the laser process, the first area S21 is a tunneling layer + phosphorus-doped polysilicon layer + silicon oxide layer structure, and the second area S22 is a tunneling layer + phosphorus-doped amorphous silicon layer structure.

[0081] It should be understood that the laser scanning pattern in the present invention can be designed according to different electrode structures, so as to crystallize the amorphous silicon layer under the laser scanning area (i.e., the back metal area) and form a patterned silicon oxide mask. The laser scanning patterns for other electrode structures will not be illustrated one by one here.

[0082] In the prior art, a doped amorphous silicon layer is usually converted into a doped polysilicon layer by high temperature annealing. At this time, a mask layer needs to be deposited separately by a process such as PECVD, and the mask is patterned. However, the present invention uses a one-step laser process to achieve the conversion of doped amorphous silicon to doped polysilicon and the preparation of a patterned mask, which greatly simplifies the process flow.

[0083] 6. De-plating and chemical etching

[0084] Ginseng Figure 5g As shown, a chemical etching process is used to remove all the second doping layer 13 on the second region S22 and the oxide layer 131 on the first region S21, and the tunneling layer 12 and the second doping layer 13 on the first region S21 are retained.

[0085] This step specifically includes:

[0086] Alkali etching: using an alkaline solution in an alkaline washing tank to remove all the second doping layer 13 on the second region S22, and simultaneously remove the front and edge plating, the mass fraction of the alkaline solution is 3% to 15%, and the processing time is 100s to 500s, preferably 350s;

[0087] Pickling: using an acid solution in a pickling tank to remove the tunneling layer 12 on the second region and the oxide layer 131 on the first region, and simultaneously remove the PSG on the front side, the mass fraction of the acid solution is 5% to 20%, and the processing time is 100s to 500s, preferably 300s;

[0088] Finally, RCA cleaning is performed. RCA cleaning is a prior art and will not be described in detail here.

[0089] Preferably, the acid solution in this embodiment is obtained by mixing industrial-grade hydrofluoric acid solution (mass fraction ~40%) and water in a certain proportion, and the alkaline solution is obtained by mixing industrial-grade sodium hydroxide solution (mass fraction ~32%) and water in a certain proportion.

[0090] In the prior art, a front chain process (pickling) is usually required before the alkaline etching step, and the silicon oxide mask with edge plating is removed on one side through a chain hydrofluoric acid tank. However, the silicon oxide mask is not prepared by the PECVD process, and no plating is formed on the edge, so there is no need to go through the front chain process.

[0091] During the alkaline etching process, the second doped layer 13 (i.e., the phosphorus-doped amorphous silicon layer) on the second region S22 is corroded, which can reduce the parasitic absorption on the back side of the battery and significantly improve the current. The first region S21 has silicon oxide to block the corrosion of the alkaline solution, thereby not affecting the contact performance between the back electrode and the second doped layer.

[0092] 7. Preparation of passivation layer

[0093] Ginseng Figure 5h As shown, the first passivation layer 21 and the second passivation layer 22 are respectively prepared on the first surface S1 and the second surface S2 of the silicon substrate by the ALD process. The first passivation layer 21 and the second passivation layer 22 are both aluminum oxide passivation layers with a thickness of 2nm to 7nm, preferably 3nm to 6nm.

[0094] After the de-plating and chemical etching steps, the tunneling layer and the doped polysilicon layer on the first area S21 can still ensure the passivation effect, while there is no passivation layer protection on the second area S22. Therefore, while preparing the first passivation layer 21 on the front side, it is necessary to prepare the second passivation layer 22 on the back side at the same time, so as to ensure a good interface passivation effect on the second area S22.

[0095] In addition, under high-temperature sintering conditions to ensure good front contact, the second passivation layer 22 has a certain barrier effect on the back paste, so the second doping layer 13 can be further thinned, thereby improving the short-circuit current density of the battery.

[0096] 8. Preparation of anti-reflection layer

[0097] Ginseng Figure 5i As shown, a first anti-reflection layer 31 and a second anti-reflection layer 32 are respectively prepared on a first surface S1 and a second surface S2 of a silicon substrate by a PECVD process. The first anti-reflection layer 31 and the second anti-reflection layer 32 can be a stacked film formed by any one or more of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer, with a thickness of 60nm to 130nm.

[0098] 9. Printing metal electrodes

[0099] Ginseng Figure 5j As shown, the first electrode 41 and the second electrode 42 are printed on the front and back sides respectively by screen printing, and then sintering and light injection or electric injection treatment are performed to form ohmic contacts.

[0100] The first electrode 41 and the second electrode 42 are gate line electrodes in the prior art, and usually include a main gate line and a fine gate line. It is worth noting that since the fine gate line in the second electrode 42 needs to be printed on the first region S21, the width of the first sub-region 101 needs to be greater than the width of the fine gate line 421 in the second electrode 42, so that the fine gate line 421 can be aligned.

[0101] TOPCon batteries can be prepared through the above steps, and finally the battery cells can be tested, sorted and stored.

[0102] Embodiment 2:

[0103] The structure and preparation method of the solar cell in this embodiment are substantially the same as those in Example 1, except that the first doping layer 11 in Example 1 is prepared below the first surface S1 of the silicon substrate by a boron diffusion process, while the first doping layer 11 in this embodiment is prepared above the first surface S1 of the silicon substrate by a PECVD process.

[0104] Specifically, in this embodiment, a boron-doped amorphous silicon layer 11 ′ is first deposited on the first surface S1 by using a PECVD process, and then a first doped layer 11 , ie, a P-type doped polysilicon layer, is formed after high-temperature oxidation annealing.

[0105] Ginseng Figure 7a As shown, firstly, the silicon substrate 10 is double-sided textured, and the texture process is exactly the same as that in Example 1, which will not be described again here.

[0106] Ginseng Figure 7b As shown, a boron-doped amorphous silicon layer 11' is first deposited on the first surface S1 by a PECVD process. Exemplarily, in the PECVD process, N2O is first introduced to form a silicon oxide layer (not shown) on the first surface S1, then SiH4 and trimethyl boron are introduced to form a boron-doped amorphous silicon layer on the silicon oxide layer, and finally N2O is introduced to form a silicon oxynitride mask (not shown).

[0107] Ginseng Figure 7c As shown, finally, a first doped layer 11 is formed by a high temperature oxidation annealing process. The P-type doped amorphous silicon layer can be transformed into a P-type doped polysilicon layer by the high temperature oxidation annealing process.

[0108] Different from the first embodiment, in the present embodiment, a P-type doped polysilicon layer is prepared on the surface of the silicon substrate 10 by a PECVD process and an annealing method, and the thickness of the silicon substrate 10 is constant during this process. Figure 7c After the annealing, the total thickness of the silicon substrate 10 and the first doping layer 11 is equal to Figure 7b The total thickness of the silicon substrate 10 and the boron-doped amorphous silicon layer 11' before annealing is greater than Figure 7a The thickness of the silicon substrate 10 before the PECVD process.

[0109] Embodiment 3:

[0110] The structure of the solar cell in this embodiment is exactly the same as that in Embodiment 1, but the preparation method is different. The preparation method of the solar cell in this embodiment specifically includes the following steps:

[0111] 1. Double-sided velveting

[0112] Ginseng Figure 8a As shown, a silicon substrate 10 is provided, and the silicon substrate 10 includes a first surface S1 and a second surface S2 that are arranged opposite to each other. The second surface S2 includes a first area S21 and a second area S22. The first surface S1 is the front side (i.e., the light-receiving side) of the silicon substrate 10, and the second surface S2 is the back side (i.e., the backlight side) of the silicon substrate 10. The first area S21 is a back metal area, and the second area S22 is a back non-metal area.

[0113] The silicon substrate 10 in this embodiment is an N-type silicon substrate with a resistivity of 0.3 Ω·cm to 7 Ω·cm, preferably 0.5 Ω·cm to 3.5 Ω·cm. Figure 8b As shown, the first surface S1 and the second surface S2 of the silicon substrate 10 are formed with a pyramid texture structure (not shown) by an alkali texturing process, and the size of the pyramid is 0.5 μm to 3 μm.

[0114] 2. Boron Diffusion

[0115] Ginseng Figure 8c As shown, a P-type doped first doping layer (i.e., a P+ emitter) 11 is formed at the first surface S1 of the silicon substrate 10 by a boron diffusion process. Specifically, a boron source (e.g., BCl3 or BBr3, etc.) is used in a high-temperature furnace tube for diffusion, and a layer of silicon oxide is formed on the outer layer. After diffusion, the surface doping concentration of the first doping layer is 3E18cm -3 ~3E19cm -3 , the square resistance is 250Ω / sq~300Ω / sq, preferably 250Ω / sq~280Ω / sq. In the boron diffusion process, BSG (not shown) is formed on the second surface S2 of the silicon substrate.

[0116] In this embodiment, the outer silicon layer of the first surface S1 of the silicon substrate 10 is transformed into a boron diffusion layer. Figure 8c The total thickness of the silicon substrate 10 and the first doping layer 11 after the boron diffusion is Figure 8b The thickness of the silicon substrate 10 before the boron diffusion is uniform.

[0117] It should be understood that in other embodiments, the first doping layer 11 can also be prepared by using the PECVD process. The specific PECVD process is exactly the same as the PECVD process in Example 2, and will not be described in detail here.

[0118] 3. Back polishing

[0119] Ginseng Figure 8d As shown, the silicon substrate after boron diffusion is first passed through a single-sided chain device, and a hydrofluoric acid solution is used to remove the back silicon oxide. The back side is then alkaline polished to remove the edge junction and back side wrap (BSG), and finally cleaned.

[0120] 4. Preparation of back-side tunneling passivation structure

[0121] Ginseng Figure 8e As shown, a tunneling layer 12, a second doping layer 13 and a mask 50 stacked in sequence are prepared on the second surface S2.

[0122] Illustratively, in this embodiment, a PECVD process is used to first deposit a 1nm to 3nm thick silicon oxide tunneling layer on the back side, and then deposit a layer of phosphorus-doped amorphous silicon or multiple layers of phosphorus-doped amorphous silicon layers with different doping concentrations, with a total thickness of 1nm to 120nm, preferably 80nm to 100nm, and finally deposit a layer of silicon oxide mask, with a mask thickness of 2nm to 50nm, preferably 15nm to 20nm.

[0123] 5. Annealing activation

[0124] Annealing is performed in a high-temperature annealing furnace at a temperature of 880°C to 980°C, preferably 900°C to 950°C. After annealing, the phosphorus-doped amorphous silicon layer is transformed into a phosphorus-doped polysilicon layer. Phosphorus is activated by annealing to form a tunnel passivation contact structure on the back side.

[0125] 6. Laser film opening

[0126] Ginseng Figure 8f As shown, the laser film opening process is used to remove the mask on the second area S22.

[0127] After annealing, the back structure of the silicon substrate is tunneling layer (SiO2) + doped polysilicon layer (N+poly) + mask (SiO2). The laser processing mainly acts on the mask (SiO2). For the silicon oxide mask with a thickness of 15nm to 20nm, the laser power in the laser film opening process is 45W to 55W, preferably 50W, the scanning speed is 40000mm / s to 60000mm / s, preferably 50000mm / s, and the laser frequency is 500KHz to 600KHz, preferably 500KHz.

[0128] Ginseng Fig. 9 The figure shows the laser pattern in the laser film opening process in this embodiment. The black line portion corresponds to the metal area, namely the first area S21, and the blank portion is the laser scanning area, namely the second area S22. The laser scanning area is the second area S22 (i.e. the non-metal area on the back side). The mask 50 on the second area S22 is removed by the laser film opening process to expose the doped polysilicon layer underneath.

[0129] It should be understood that the laser pattern in the present invention can be designed according to different electrode structures, so that the mask in the laser scanning area (i.e., the non-metallic area on the back) is removed and the mask in the metal area on the back is retained. The laser patterns for other electrode structures will not be illustrated one by one here.

[0130] 7. De-plating and chemical etching

[0131] Ginseng Figure 8g As shown, this step specifically includes:

[0132] Pickling 1: Use an acid solution in the pickling tank to remove the mask around the edge of the silicon substrate, the mass fraction of the acid solution is 5% to 30%, and the processing time is 30s to 100s, preferably 60s. Exemplarily, in this step, the front side of the silicon substrate is passed through a chain hydrofluoric acid tank to remove the silicon oxide mask around the edge on one side.

[0133] Alkali etching: using an alkaline solution in an alkaline washing tank to remove the second doping layer 13 on the second region S22, the mass fraction of the alkaline solution is 3% to 15%, and the processing time is 100s to 500s, preferably 350s;

[0134] Pickling 2: using an acid solution in an acid pickling tank to remove the tunneling layer 12 on the second area S22 and the mask 50 on the first area S21, the mass fraction of the acid solution is 5% to 20%, and the processing time is 100s to 500s, preferably 300s;

[0135] Finally, RCA cleaning is performed. RCA cleaning is a prior art and will not be described in detail here.

[0136] Preferably, the acid solution in this embodiment is obtained by mixing industrial-grade hydrofluoric acid solution (mass fraction ~40%) and water in a certain proportion, and the alkaline solution is obtained by mixing industrial-grade sodium hydroxide solution (mass fraction ~32%) and water in a certain proportion.

[0137] After the laser film opening process, the mask on the second area S22 has been removed by laser. In the alkaline etching step, the doped polysilicon in the second area S22 will be etched by the alkaline solution. After 350s, the doped polysilicon in the second area S22 has been completely etched. Since the first area S21 is protected by the mask, the doped polysilicon on the first area S21 is not affected.

[0138] During the alkaline etching process, the second doped layer 13 (i.e., the phosphorus-doped polysilicon layer) on the second region S22 is corroded, which can reduce the parasitic absorption on the back side of the battery and significantly improve the current; while the first region S21 has a mask to block the corrosion of the alkaline solution, thereby not affecting the contact performance between the back electrode and the second doped layer.

[0139] 8. Preparation of passivation layer

[0140] Ginseng Figure 8h As shown, the ALD process is used to prepare the first passivation layer 21 and the second passivation layer 22 on the first surface S1 and the second surface S2 of the silicon substrate respectively. The first passivation layer 21 is an aluminum oxide passivation layer with a thickness of 2nm to 7nm, preferably 3nm to 6nm, and the second passivation layer 22 is an aluminum oxide passivation layer with a thickness of 3nm to 5nm.

[0141] After the de-plating and chemical etching steps, the tunneling layer and the doped polysilicon layer on the first area S21 can still ensure the passivation effect, while there is no passivation layer protection on the second area S22. Therefore, while preparing the first passivation layer on the front side, it is necessary to prepare the second passivation layer on the back side at the same time to ensure a good interface passivation effect on the second area S22.

[0142] In addition, under high-temperature sintering conditions to ensure good front contact, the second passivation layer 22 has a certain barrier effect on the back paste, so the second doping layer 13 can be further thinned, thereby improving the short-circuit current density of the battery.

[0143] 9. Preparation of anti-reflection layer

[0144] Ginseng Figure 8i As shown, a first anti-reflection layer 31 and a second anti-reflection layer 32 are respectively prepared on a first surface S1 and a second surface S2 of a silicon substrate by a PECVD process. The first anti-reflection layer 31 and the second anti-reflection layer 32 can be a stacked film formed by any one or more of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer, with a thickness of 60nm to 130nm.

[0145] 10. Printing metal electrodes

[0146] Ginseng Figure 8j As shown, the first electrode 41 and the second electrode 42 are printed on the front and back sides respectively by screen printing, and then sintering and light injection or electric injection treatment are performed to form ohmic contacts.

[0147] The first electrode 41 and the second electrode 42 are gate line electrodes in the prior art, and usually include a main gate line and a secondary gate line. It is worth noting that since the secondary gate line in the second electrode 42 needs to be printed on the first area S21, the width of the first sub-area 101 needs to be greater than the width of the secondary gate line 421 in the second electrode 42, so that the secondary gate line 421 can be aligned.

[0148] The process flow in this embodiment is texturing → boron diffusion → back polishing → PE-poly → annealing → laser film opening → de-wrap plating → ALD → PECVD → screen printing. TOPCon batteries can be prepared through the above steps, and finally the battery cells are tested, sorted and stored.

[0149] Comparative Example 1:

[0150] Compared with Example 3, the entire back surface of the silicon substrate in this comparative example has a tunneling passivation contact structure of a tunneling layer + a doped polysilicon layer, and the rest is the same as Example 3.

[0151] The process flow in this comparative example is texturing→boron diffusion→back polishing→PE-poly→annealing→de-coating→ALD→PECVD→screen printing, which is the mass production process flow in the prior art.

[0152] Comparative Example 2:

[0153] The process flow in this comparative example is texturing → boron diffusion → back polishing → LP-poly + phosphorus diffusion → annealing → laser → de-coating → ALD → PECVD → screen printing.

[0154] Compared with Example 3, in this comparative example, laser is used to remove the PSG (phosphosilicate glass), polysilicon (poly) and SiO2 tunneling layer generated after LP-poly+ phosphorus diffusion (~870°C) in the non-metallic area in one step, and then chemical etching is used to remove the remaining polysilicon.

[0155] The TOPCon batteries prepared in Example 1 and Comparative Example 1 were tested, and the performance parameters shown in Table 1 were obtained.

[0156] Table 1: TOPCon battery performance parameter comparison table

[0157]

[0158]

[0159] It can be seen that the battery performance of Example 3 is greatly improved compared with that of Comparative Example 1, the short-circuit current Isc can be increased by about 1%, the battery conversion efficiency Eta can be increased by about 0.4%, the back side parasitic absorption can be greatly reduced, and the bifaciality can be increased by about 6% at most.

[0160] Compared with Comparative Example 2, in Example 3, laser is used to open the silicon oxide mask, and polysilicon and tunneling silicon oxide are removed by chemical etching process, while in Comparative Example 2, laser is used to remove PSG, polysilicon and tunneling silicon oxide in one step. Example 3 has at least the following advantages:

[0161] 1. Adjust the laser parameters for the silicon oxide mask, and use the laser film opening process to remove only the silicon oxide mask in the non-metallic area without affecting the passivation performance of the metal area;

[0162] 2. Compared with PSG, the silicon oxide mask has a higher crystallization temperature and better density, which can better block the damage of the laser to the amorphous silicon layer on the silicon substrate;

[0163] 3. Chemical etching is used to remove polysilicon and tunneling silicon oxide, which is gentler and less damaging than laser removal. At the same time, chemical etching will form Fig.10 The tower base shown (the tower base is the base left after the pyramid velvet structure is polished) can further increase the photoelectric conversion efficiency and improve the bifaciality.

[0164] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0165] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A solar cell, characterized in that: The solar cell includes a silicon substrate, which includes a first surface and a second surface arranged opposite to each other, the second surface includes a first area and a second area distributed at intervals, a tunneling passivation contact structure and a second electrode are provided in a partial area of ​​the second surface, the projection of the tunneling passivation contact structure on the second surface of the silicon substrate is located in the first area, the tunneling passivation contact structure includes a tunneling layer directly in contact with the silicon substrate and a second doping layer arranged on the tunneling layer, and the second electrode is in contact with the second doping layer.

2. The solar cell according to claim 1, characterized in that A first doping layer and a first electrode are formed on the first surface of the silicon substrate. The doping type of the first doping layer is opposite to the doping type of the silicon substrate, and the first electrode is in contact with the first doping layer.

3. The solar cell according to claim 2, characterized in that: The first doped layer is a P-type doped layer; and / or, The surface doping concentration of the first doping layer is 3E18cm -3 ~3E19cm -3 .

4. The solar cell according to claim 2, characterized in that: A first passivation layer and / or a first anti-reflection layer is stacked on the first doping layer.

5. The solar cell according to claim 4, characterized in that: The first passivation layer is an aluminum oxide passivation layer with a thickness of 2nm to 7nm or 3nm to 6nm; the first anti-reflection layer is a stacked film formed by any one or more of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer with a thickness of 60nm to 130nm.

6. The solar cell according to claim 1, characterized in that The second doping layer is a doped polysilicon layer, and the doping type of the second doping layer is the same as the doping type of the silicon substrate.

7. The solar cell according to claim 1, characterized in that The silicon substrate is an N-type silicon substrate, and the second doped layer is an N-type doped polysilicon layer; and / or, The surface doping concentration of the second doping layer is 1E20cm -3 ~1E21cm -3 , with a thickness of 1nm~150nm or 50nm~100nm.

8. The solar cell according to claim 1, characterized in that The tunneling layer is a silicon oxide layer, a silicon oxynitride layer, or a combination of the two, and has a thickness of 0.5 nm to 3 nm or 1.5 nm to 2.5 nm.

9. The solar cell according to claim 1, characterized in that: A second passivation layer and / or a second anti-reflection layer is at least partially stacked on the second surface of the silicon substrate. The second passivation layer and / or the second anti-reflection layer is stacked on the second region of the second surface and on the tunnel passivation contact structure.

10. The solar cell according to claim 9, characterized in that: The second passivation layer is an aluminum oxide passivation layer with a thickness of 2nm to 7nm or 3nm to 6nm; and / or, The second anti-reflection layer is a stacked film formed by any one or more of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer, and has a thickness of 60 nm to 130 nm.

11. The solar cell according to claim 1, characterized in that: The first region includes a plurality of first sub-regions that are distributed in parallel and at equal intervals, the second electrode includes a plurality of gate lines that are distributed in parallel, and the width of the first sub-region is greater than or equal to the width of the gate line.

12. The solar cell according to claim 11, characterized in that: The width of the first sub-region is 50 μm to 150 μm, and the width of the gate line is 15 μm to 100 μm.

13. The solar cell according to claim 1, characterized in that A pyramid texture structure is formed on the first surface of the silicon substrate; and / or, The second surface of the silicon substrate is a polished surface.

14. A photovoltaic module, characterized in that: The photovoltaic module comprises several solar cells according to any one of claims 1 to 13.

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