Solar cell and photovoltaic module

Abstract

The invention discloses a solar cell and a photovoltaic module. The solar cell comprises a silicon substrate; the silicon substrate is provided with a light receiving surface and a backlight surface which are opposite, and a side surface arranged between the light receiving surface and the backlight surface; a protective layer is arranged on the side surface and comprises a first conductive layer, an insulating layer and a second conductive layer which are sequentially arranged on the side surface; the first conductive layer and the second conductive layer are opposite in conductivity type. The first conductive layer and the second conductive layer are insulated and isolated by using the insulating layer, so that the conductive layer formed on the side surface of the silicon substrate through winding plating does not need to be specially removed in the preparation process of the battery, and the production process of the battery is simplified. Moreover, shielding protection is formed on the side surface of the silicon substrate by using the protective layer, so that the risks of damage and electric leakage caused by direct exposure of the side surface of the silicon substrate can be avoided, carrier recombination on the side surface of the silicon substrate can be reduced, and the conversion efficiency of the battery is improved.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of the Chinese patent application filed with the Chinese Patent Office on January 16, 2024, with application number 202410065730.3 and titled “A solar cell and photovoltaic module”, and the priority of the Chinese patent application filed with the Chinese Patent Office on September 14, 2024, with application number 202411295529.0 and titled “A back contact cell and photovoltaic module”, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application belongs to the field of photovoltaic technology, and specifically relates to a solar cell and a photovoltaic module. Background Art

[0004] A solar cell is a device that can convert sunlight into electrical energy. Specifically, when the solar cell is in operation, sunlight shines on the semiconductor pn junction of the solar cell, forming new hole-electron pairs. Under the action of the built-in electric field of the pn junction, photogenerated holes flow to the p region, and photogenerated electrons flow to the n region. When the circuit is connected, current can be generated. Among them, a solar cell in which both the positive electrode and the negative electrode are on the back of the cell is a back-contact cell. Compared with a double-sided contact solar cell, the front of the back-contact cell is not blocked by a metal electrode, so that the light-receiving side of the back-contact cell has a higher light utilization rate. Therefore, the back-contact cell has a higher short-circuit current and photoelectric conversion efficiency, and is one of the current technical directions for achieving high-efficiency crystalline silicon cells.

[0005] However, existing back-contact cells passivate the front and back sides of the silicon substrate, while the sides of the silicon substrate are directly exposed. This causes severe side recombination and the risk of damage, thereby reducing the efficiency of the back-contact cell. Summary of the invention

[0006] The present application aims to provide a solar cell and a photovoltaic module, which can protect the side of the silicon substrate by a film layer arranged on the side of the silicon substrate, thereby reducing the risk of damage to the side. At the same time, the side of the silicon substrate can be passivated to reduce carrier recombination on the side of the silicon substrate and improve the conversion efficiency of the back contact cell.

[0007] In order to solve the above technical problems, this application is implemented as follows:

[0008] In a first aspect, the present application provides a solar cell, comprising: a silicon substrate; the silicon substrate having a light-receiving surface and a backlight surface opposite to each other, and a side surface disposed between the light-receiving surface and the backlight surface;

[0009] A protective layer is arranged on the side surface. Along the direction away from the silicon substrate, the protective layer comprises a first conductive layer, an insulating layer and a second conductive layer arranged on the side surface in sequence. The first conductive layer and the second conductive layer have opposite conductive types.

[0010] In the present application, a protective layer is provided on the side of the silicon substrate, and the protective layer includes a first conductive layer, an insulating layer, and a second conductive layer provided on the side of the silicon substrate. The insulating layer is used to insulate and isolate the first conductive layer from the second conductive layer, so that the conductive layer formed by plating on the side of the silicon substrate does not need to be removed during the battery preparation process, which helps to simplify the battery production process. In addition, the protective layer can play a role in passivation protection of the side of the silicon substrate, which can not only avoid the risk of damage and leakage caused by direct exposure of the side of the silicon substrate, but also reduce the carrier recombination on the side of the silicon substrate, thereby improving the conversion efficiency of the battery.

[0011] Optionally, along a direction parallel to the backlight surface, the backlight surface has first regions and second regions that are alternately arranged; a first conductive layer is formed in the first region, and a second conductive layer is formed in the second region.

[0012] Optionally, the protective layer further includes a first passivation layer located between the side surface and the first conductive layer and a second passivation layer located between the insulating layer and the second conductive layer;

[0013] Along the direction parallel to the backlight surface, the backlight surface has a first area and a second area that are alternately arranged; along the direction away from the silicon substrate, the first area has a first passivation layer and a first conductive layer formed in sequence, and the second area has a second passivation layer and a second conductive layer formed in sequence; an insulating layer is provided between the first area and the second area.

[0014] Optionally, the junction between the side surface and the backlight surface is the first position, the junction between the side surface and the light-receiving surface is the second position, and the thickness of the protective layer at the first position is greater than the thickness of the protective layer at the second position.

[0015] Optionally, the thickness of the protective layer at the first position is D1, and the thickness of the protective layer at the second position is D2, satisfying: 1<D1 / D2≤10.

[0016] Optionally, the total thickness of the first passivation layer and the first conductive layer on the backlight surface is H1, the total thickness of the first passivation layer and the first conductive layer at the first position is H11, and the total thickness of the first passivation layer and the first conductive layer at the second position is H12, satisfying: H12<H11≤H1.

[0017] Optionally, the total thickness of the first passivation layer and the first conductive layer at the first position on the side is H11 and the total thickness of the first passivation layer and the first conductive layer at the second position on the side is H12 which satisfies: 0.2≤H12 / H11<1.

[0018] Optionally, a total thickness H1 of the first passivation layer and the first conductive layer on the backlight surface and a total thickness H11 of the first passivation layer and the first conductive layer located at the first position satisfy: 0.5≤H11 / H1≤1.

[0019] Optionally, a total thickness H1 of the first passivation layer and the first conductive layer on the backlight surface and a total thickness H12 of the first passivation layer and the first conductive layer located at the second position satisfy: 0.2≤H12 / H1≤0.6.

[0020] Optionally, the thickness of the insulating layer on the backlight surface is H2, the thickness of the insulating layer at the first position is H21, and the thickness of the insulating layer at the second position is H22, satisfying: H22<H21≤H2.

[0021] Optionally, the thickness of the insulating layer at the first position on the side surface is H21 and the thickness of the insulating layer at the second position on the side surface is H22 which satisfies: 0.2≤H22 / H21<1.

[0022] Optionally, a thickness H2 of the insulating layer on the backlight surface and a thickness H21 of the insulating layer located at the first position satisfy: 0.5≤H21 / H2≤1.

[0023] Optionally, the thickness H2 of the insulating layer on the backlight surface and the total thickness H22 of the insulating layer located at the second position satisfy: 0.2≤H22 / H2≤0.6.

[0024] Optionally, the total thickness of the second passivation layer and the second conductive layer on the backlight surface is H3, the total thickness of the second passivation layer and the second conductive layer at the first position is H31, and the total thickness of the second passivation layer and the second conductive layer at the second position is H32, satisfying: H32<H31≤H3.

[0025] Optionally, the total thickness of the second passivation layer and the second conductive layer at the first position on the side is H31 and the total thickness of the second passivation layer and the second conductive layer at the second position on the side is H32, which satisfies: 0.2≤H32 / H31<1.

[0026] Optionally, a total thickness H3 of the second passivation layer and the second conductive layer on the backlight surface and a total thickness H31 of the second passivation layer and the second conductive layer located at the first position satisfy: 0.5≤H31 / H3≤1.

[0027] Optionally, a total thickness H3 of the second passivation layer and the second conductive layer on the backlight surface and a total thickness H32 of the second passivation layer and the second conductive layer located at the second position satisfy: 0.2≤H32 / H3≤0.6.

[0028] Optionally, the protective layer further includes a third passivation layer and an anti-reflection layer, the third passivation layer is arranged on a side of the second conductive layer away from the side surface, and the anti-reflection layer is arranged on a side of the third passivation layer away from the second conductive layer;

[0029] A third passivation layer and an anti-reflection layer are sequentially formed on the light-receiving surface in a direction away from the silicon substrate.

[0030] Optionally, the total thickness of the third passivation layer and the anti-reflection layer on the light receiving surface is H4, the total thickness of the third passivation layer and the anti-reflection layer at the first position is H41, and the total thickness of the third passivation layer and the anti-reflection layer at the second position is H42, satisfying: H41<H42≤H4.

[0031] Optionally, the total thickness of the third passivation layer and the anti-reflection layer at the first position on the side is H41 and the total thickness of the third passivation layer and the anti-reflection layer at the second position on the side is H42 which satisfies: 0.1≤H42 / H41<1.

[0032] Optionally, the total thickness H4 of the third passivation layer and the anti-reflection layer on the light-receiving surface and the total thickness H41 of the third passivation layer and the anti-reflection layer located at the first position satisfy: 0.1≤H41 / H4≤0.4.

[0033] Optionally, the total thickness H4 of the third passivation layer and the anti-reflection layer on the light-receiving surface and the total thickness H42 of the third passivation layer and the anti-reflection layer located at the second position satisfy: 0.5≤H42 / H4≤0.8.

[0034] Optionally, the protective layer further comprises: a transparent conductive layer, the transparent conductive layer being arranged on a side of the anti-reflection layer away from the side surface;

[0035] At least one of the first region and the second region is provided with a transparent conductive layer, and the transparent conductive layer is provided on a side of the first conductive layer and / or the second conductive layer away from the backlight surface.

[0036] Optionally, the thickness of the transparent conductive layer located on the backlight surface is H5, the thickness of the transparent conductive layer located at the first position is H51, and the thickness of the transparent conductive layer located at the second position is H52, satisfying: H52<H51≤H5.

[0037] Optionally, the thickness of the transparent conductive layer at the first position on the side surface is H51 and the thickness of the transparent conductive layer at the second position on the side surface is H52 which satisfies: 0.3≤H52 / H51<1.

[0038] Optionally, the thickness H5 of the transparent conductive layer on the backlight surface and the thickness H51 of the transparent conductive layer located at the first position satisfy: 0.5≤H51 / H5≤1.

[0039] Optionally, the thickness H5 of the transparent conductive layer on the backlight surface and the thickness H52 of the transparent conductive layer located at the second position satisfy: 0.2≤H52 / H5≤0.5.

[0040] In a first group of possible implementation schemes of the first aspect, further, the solar cell is a back contact cell;

[0041] The first conductive layer is a first doped silicon layer, the second conductive layer is a second doped silicon layer, and the insulating layer includes a surface passivation layer and an anti-reflection layer;

[0042] The back contact cell comprises: a first interface passivation layer, a first doped silicon layer, a surface passivation layer, an anti-reflection layer, an intrinsic silicon layer, a second doped silicon layer and a transparent conductive layer, which are sequentially arranged on the side surface in a direction away from the silicon substrate;

[0043] Wherein, along the thickness direction of the silicon substrate, the surface passivation layer and the anti-reflection layer are also sequentially arranged on the light-receiving surface, and the surface passivation layer and the anti-reflection layer extend from the light-receiving surface to the side surface.

[0044] In the present application, when the above technical solution is adopted, on the side of the silicon substrate and in the direction away from the side, a first interface passivation layer, a first doped silicon layer, a surface passivation layer, an anti-reflection layer, an intrinsic silicon layer, a second doped silicon layer and a transparent conductive layer are sequentially arranged. The presence of the above film layers can isolate the side of the silicon substrate from the external environment, reducing the risk of damage such as scratches on the side of the silicon substrate due to extrusion, collision and other factors after transportation or packaging. At the same time, it can also reduce the risk of water vapor and the like entering the battery from the side of the battery to cause battery failure, thereby increasing the service life of the back contact battery. In addition, the surface passivation layer and the anti-reflection layer are not only located on the light-receiving surface of the silicon substrate, but also extend to the side of the silicon substrate. At this time, on the side of the silicon substrate, the first doped silicon layer and the second doped silicon layer of opposite conductivity types can be isolated by the surface passivation layer and the anti-reflection layer to prevent the two from being turned on and leaking electricity, so that the back contact battery has a higher conversion efficiency. In addition, the surface passivation layer and the anti-reflection layer are arranged on the light-receiving surface to reduce carrier recombination and surface reflectivity. The two layers are then extended to the side of the silicon substrate, and can also be used to isolate the first doped silicon layer and the second doped silicon layer. There is no need to form other insulating layers through other deposition steps to prevent leakage between the first doped silicon layer and the second doped silicon layer. The manufacturing process of the back contact battery can be simplified. At the same time, there is no need to consider the compatibility between the film layer that isolates the first doped silicon layer and the second doped silicon layer and other structures in the back contact battery, ensuring that the back contact battery has a higher yield. At the same time, not only the first interface passivation layer and the first doped silicon layer arranged on the side of the silicon substrate have a passivation effect on the silicon substrate, but the surface passivation layer that achieves insulation isolation between the first doped silicon layer and the second doped silicon layer on the side can also passivate the side of the silicon substrate, further reducing the carrier recombination rate on the side of the silicon substrate and improving the conversion efficiency of the back contact battery.

[0045] In addition, in the actual manufacturing process, the order in which the corresponding film layers are formed on the backlight side and the light-receiving side of the silicon substrate affects the order in which the corresponding film layers are formed on the side of the silicon substrate. Since the order in which the film layers are formed on the backlight side and the light-receiving side of the silicon substrate is closely related to the process, battery structure, equipment, etc., the order in which the film layers are formed on the backlight side and the light-receiving side of the silicon substrate cannot be adjusted arbitrarily, that is to say, the order in which the film layers are formed on the side of the silicon substrate cannot be adjusted arbitrarily, and needs to be comprehensively considered based on the requirements for the order in which the film layers are formed on the side of the silicon substrate, the technical problems to be solved, as well as the requirements for the order in which the film layers are formed on the front and back sides, the technical problems to be solved, etc.

[0046] Optionally, the backlight surface includes a first region and a second region; the first interface passivation layer and the first doped silicon layer are located in the first region; the intrinsic silicon layer and the second doped silicon layer are located in the second region, and extend from the second region to the first region, and cover part of the first interface passivation layer and the first doped silicon layer; the insulating layer also includes an insulating mask layer; the insulating mask layer is arranged between the first doped silicon layer and the surface passivation layer located on the side, and the insulating mask layer is also arranged between the intrinsic silicon layer and the first doped silicon layer located on the backlight surface along the thickness direction of the silicon substrate. In the case of adopting the above technical solution, on the backlight surface of the silicon substrate, the intrinsic silicon layer and the second doped silicon layer are not only stacked in sequence in the second region along the thickness direction of the silicon substrate, but also cover part of the first interface passivation layer and the first doped silicon layer. At this time, the formation range of the intrinsic silicon layer and the second doped silicon layer on the backlight side of the silicon substrate is relatively large, which is conducive to reducing the etching range of the entire layer of the intrinsic silicon layer and the second doped silicon layer during the manufacturing process, and is conducive to improving the etching capacity. Moreover, the portion where the intrinsic silicon layer and the second doped silicon layer cover the first doped silicon layer can protect the edge of the first doped silicon layer, prevent the etchant from affecting the edge of the first doped silicon layer, and ensure that the edge of the first doped silicon layer has a higher carrier collection efficiency. The insulating mask layer can separate the first doped silicon layer and the second doped silicon layer on the side together with the surface passivation layer and the anti-reflection layer, further suppressing the side leakage. At the same time, the side of the silicon substrate can also be passivated to further reduce the number of defects on the side of the silicon substrate. In addition, the insulating mask layer is also formed on the side, which is also conducive to reducing the thickness requirements for the intrinsic silicon layer. While ensuring that there is a lower forward leakage between the first doped silicon layer and the second doped silicon layer, the intrinsic silicon layer has a lower tunneling resistance, which is conducive to improving the carrier collection efficiency of the second doped silicon layer on the backlight side.

[0047] Optionally, on the side surface of the silicon substrate, the thickness of the insulating mask layer gradually increases along the direction from the light-receiving surface to the backlight surface.

[0048] Optionally, the insulating mask layer disposed on the side is located on a local area of ​​the side; along the thickness direction of the silicon substrate, the ratio between the maximum extension length of the insulating mask layer on the side and the thickness of the silicon substrate is less than or equal to 80%. In the case of adopting the above technical solution, it can be understood that the greater the extension length of the insulating mask layer on the side, the first doped silicon layer and the second doped silicon layer in the side of the silicon substrate can be isolated by forming a larger insulating mask layer, the lower the forward leakage of the back contact battery, and the stronger the protective effect of the insulating mask layer on the side of the silicon substrate. The smaller the extension length of the insulating mask layer on the side, the larger the range of the reverse leakage area formed between the first doped silicon layer and the second doped silicon layer in the side of the silicon substrate, and the lower the risk of hot spots of the back contact battery. Based on this, when the ratio of the maximum extension length of the insulating mask layer on the side to the thickness of the silicon substrate is less than or equal to 80%, the forward leakage, hot spot risk and side protection of the back contact battery can be regulated by adjusting the maximum extension length of the insulating mask layer on the side according to the actual application scenario requirements of the back contact battery, which is conducive to achieving a balance between the forward leakage, hot spot risk and side protection of the back contact battery.

[0049] Optionally, the first interface passivation layer and the first doped silicon layer arranged on the side are only located on a local area of ​​the side and close to the backlight surface; wherein, along the thickness direction of the silicon substrate, the ratio between the maximum extension length of the first interface passivation layer and the first doped silicon layer on the side and the thickness of the silicon substrate is greater than or equal to 70%; and / or, the surface of the area on the side not covered by the first interface passivation layer and the first doped silicon layer is velvet, and the ratio between the maximum extension length of the velvet on the side and the thickness of the silicon substrate is less than or equal to 30%; and / or, on the side, the surface reflectivity of the area not covered by the first interface passivation layer and the first doped silicon layer is less than the surface reflectivity of the area covered by the first interface passivation layer and the first doped silicon layer; and / or, the surface of the area on the side not covered by the first interface passivation layer and the first doped silicon layer is velvet; and / or, the surface of the area on the side covered by the first interface passivation layer and the first doped silicon layer is a polished surface. In the case of adopting the above technical solution, as mentioned above, the first interface passivation layer and the first doped silicon layer have a passivation effect on the side of the silicon substrate. Therefore, when the ratio between the maximum extension length of the first interface passivation layer and the first doped silicon layer on the side and the thickness of the silicon substrate is greater than or equal to 70%, it is ensured that the first interface passivation layer and the first doped silicon layer have a larger formation range on the side of the silicon substrate, so that more areas of the surface in the side have a lower carrier recombination rate, further improving the conversion efficiency of the back contact battery. In addition, most areas of the side of the silicon substrate are covered with the first interface passivation layer and the first doped silicon layer. At this time, the first interface passivation layer and the first doped silicon layer have a protective effect on most areas of the side of the silicon substrate, and when preventing the intrusion of water vapor, etc., it is ensured that the side of the silicon substrate has a thicker stacking protection, further improving the protection effect of the side of the silicon substrate. The surface of the area on the side that is not covered with the first interface passivation layer and the first doped silicon layer is velvet, and the application principle of the beneficial effect of the ratio between the maximum extension length of the velvet on the side and the thickness of the silicon substrate is less than or equal to 30% can be referred to the above, and will not be repeated here. In addition, compared with the area on the side that is covered with the first interface passivation layer and the first doped silicon layer, the surface reflectivity of the area on the side of the silicon substrate that is not covered with the first interface passivation layer and the first doped silicon layer is smaller. At this time, although the passivation effect of the surface of the area on the side of the silicon substrate that is not covered with the first interface passivation layer and the first doped silicon layer is relatively low, the surface of this area has a relatively high light trapping effect, which is conducive to more light being refracted from the side of the side of the silicon substrate close to the light-receiving surface into the silicon substrate, which is conducive to improving the conversion efficiency of the back contact battery. In addition, there is no need to strictly control the manufacturing conditions in order to retain all the first interface passivation layer and the first doped silicon layer on the side in the process of removing the first interface passivation layer and the first doped silicon layer plated on the light-receiving surface, thereby reducing the difficulty of manufacturing the back contact battery.Furthermore, when the surface of the area covering the first interface passivation layer and the first doped silicon layer in the side surface is a polished surface, the surface of the area covering the first interface passivation layer and the first doped silicon layer in the side surface is relatively flat, which is conducive to forming a thicker first interface passivation layer and first doped silicon layer in this area, thereby enhancing the passivation effect of the first interface passivation layer and the first doped silicon layer on the corresponding area of ​​the side surface, and further improving the conversion efficiency of the back contact battery.

[0050] Optionally, the thickness of each part of the first interface passivation layer and / or the first doped silicon layer is the same. In this case, it is beneficial to make each part of the first interface passivation layer and / or the first doped silicon layer have a higher passivation effect, so that each region in the silicon substrate corresponding to the first interface passivation layer and / or the first doped silicon layer in the silicon substrate has a relatively low carrier recombination rate, further improving the conversion efficiency of the back contact battery.

[0051] Optionally, on the side of the silicon substrate, the thickness of the surface passivation layer is equal, or the thickness of the surface passivation layer gradually increases in the direction from the backlight surface to the light-receiving surface. In the case of adopting the above technical solution, within a certain range, the thickness of the surface passivation layer is proportional to its own passivation effect and insulation isolation effect. Based on this, when the thickness of the surface passivation layer is equal on the side of the silicon substrate, each part of the surface passivation layer has a higher passivation effect and a higher insulation isolation characteristic, which is conducive to making each area covered with the surface passivation layer on the side of the silicon substrate have a lower number of surface defects, and is also conducive to better realizing the electrical isolation effect of the first doped silicon layer and the second doped silicon layer through the surface passivation layer with uniform thickness, reducing forward leakage. When the thickness of the surface passivation layer gradually increases in the direction from the backlight surface to the light-receiving surface, the part of the surface passivation layer on the side close to the light-receiving surface has a higher passivation effect and better insulation isolation characteristics, further reducing the number of surface defects in the area close to the light-receiving surface on the side of the silicon substrate, while further reducing the leakage risk between the first doped silicon layer and the second doped silicon layer, which is conducive to increasing the open circuit voltage and fill factor of the back contact battery.

[0052] Optionally, on the side of the silicon substrate, the thickness of the anti-reflection layer gradually increases from the backlight surface to the light-receiving surface. In this case, the portion of the surface passivation layer on the side close to the light-receiving surface has better insulation isolation characteristics, further reducing the leakage risk between the first doped silicon layer and the second doped silicon layer, which is beneficial to increase the open circuit voltage and fill factor of the back contact battery.

[0053] Optionally, on the side of the silicon substrate, the thickness of at least one of the intrinsic silicon layer, the second doped silicon layer and the transparent conductive layer gradually increases from the light-receiving surface to the backlight surface. In the case of adopting the above technical solution, on the side of the silicon substrate, the thickness of at least one of the intrinsic silicon layer, the second doped silicon layer and the transparent conductive layer is larger near the backlight surface, which is beneficial to improve the protective effect of the film layer on the area near the backlight surface of the side of the silicon substrate, and can further improve the structural reliability of the side of the back contact battery.

[0054] Optionally, the surface passivation layer and anti-reflection layer arranged on the side are located on a local area of ​​the side and close to the light-receiving surface; along the thickness direction of the silicon substrate, the ratio between the maximum extension length of the surface passivation layer and the anti-reflection layer on the side and the thickness of the silicon substrate is less than or equal to 80%. In the case of adopting the above technical solution, when the surface passivation layer and the anti-reflection layer are formed on the light-receiving surface and the side of the silicon substrate, the surface passivation layer and the anti-reflection layer may also be formed on the backlight side due to plating. In order to eliminate the influence of the surface passivation layer and the anti-reflection layer on the backlight surface on the carrier collection efficiency of the second interface passivation layer and the second doped silicon layer, it is necessary to remove the part of the two that is plated around the backlight surface. Based on this, when the surface passivation layer and the anti-reflection layer arranged on the side can be located on a local area of ​​the side, the difficulty of removing the part of the surface passivation layer and the anti-reflection layer that is plated around the backlight surface can be reduced, and the manufacturing precision requirements can be reduced. In addition, in the area of ​​the side of the silicon substrate that is not covered by the surface passivation layer and the anti-reflection layer, the first doped silicon layer can be electrically contacted with the second doped silicon layer of opposite conductivity type to itself through the second interface passivation layer, thereby forming a diode structure with a lower reverse breakdown voltage on the side of the silicon substrate, which is beneficial to reduce the risk of hot spots of the back contact battery and improve the anti-burning ability of the back contact battery. Alternatively, the surface passivation layer arranged on the side is located on a local area of ​​the side and close to the light-receiving surface; along the thickness direction of the silicon substrate, the ratio between the maximum extension length of the surface passivation layer on the side and the thickness of the silicon substrate is less than or equal to 80%, and the beneficial effects corresponding to this feature are not repeated here.

[0055] Optionally, the material of the surface passivation layer includes at least one of aluminum oxide, intrinsic amorphous silicon, and doped silicon glass. When the above technical solution is adopted, aluminum oxide and intrinsic amorphous silicon contain hydrogen. When the material of the surface passivation layer includes aluminum oxide and / or intrinsic amorphous silicon, the silicon substrate and the first doped silicon layer can be hydrogen passivated to further improve the passivation effect of the surface passivation layer. The doped silicon glass is doped with impurities of the corresponding conductive type, and the silicon substrate and the first doped silicon layer can also be field passivated, which can also further improve the passivation effect of the surface passivation layer. Secondly, the manufacturing process of the surface passivation layer made of doped silicon glass is also relatively simple, which is conducive to reducing the difficulty of manufacturing back-contact batteries.

[0056] Optionally, the thickness of the first doped silicon layer is greater than or equal to 30 nm and less than or equal to 140 nm. When the above technical solution is adopted, the presence of the transparent conductive layer can improve the carrier collection efficiency and leave a margin for thinning the first doped silicon layer. In other words, without reducing the carrier collection efficiency, the thickness of the first doped silicon layer can be appropriately reduced due to the presence of the transparent conductive layer. Based on this, when the thickness of the first doped silicon layer is within the above range, the thickness of the first doped silicon layer is relatively small, which is conducive to reducing its own parasitic absorption and further improving the working efficiency of the back contact battery. In addition, the deposition time of the first doped silicon layer can be reduced, and the production efficiency of the first doped silicon layer can be improved.

[0057] Optionally, the thickness of the intrinsic silicon layer is greater than or equal to 8 nm and less than or equal to 14 nm. In this case, the thickness of the intrinsic silicon layer is relatively large, which is conducive to enhancing the isolation effect of the intrinsic silicon layer on the first doped silicon layer and the second doped silicon layer and reducing the risk of forward leakage.

[0058] Optionally, in the side of the silicon substrate, the area where the first interface passivation layer and the first doped silicon layer are provided has a tower-shaped texture structure; wherein the thickness of the first interface passivation layer located at the bottom surface of the tower-shaped texture structure is less than the thickness of the first interface passivation layer located at the side wall of the tower-shaped texture structure. In the case of adopting the above technical solution, it can be understood that the bottom surface of the tower-shaped texture structure and the side wall of the tower-shaped texture structure have different crystal orientations. Specifically, the bottom surface of the tower-shaped texture structure is a

[110] crystal orientation, and the number of dangling bonds on the surface of the

[110] crystal orientation is relatively small; while the side wall of the tower-shaped texture structure is a

[111] crystal orientation, and the number of dangling bonds on the

[111] crystal orientation is relatively large. Based on this, when the thickness of the first interface passivation layer located on the bottom surface of the tower-shaped texture structure is less than the thickness of the first interface passivation layer located on the side wall of the tower-shaped texture structure, it is beneficial for the portion of the thickness of the first interface passivation layer located on the side wall of the tower-shaped texture structure to have a relatively high passivation effect, thereby meeting the demand for high passivation effect of the side wall of the tower-shaped texture structure, reducing the carrier recombination rate of the side wall of the tower-shaped texture structure, and further improving the working efficiency of the back contact battery.

[0059] Optionally, the side of the silicon substrate has a tower-like texture structure; wherein the thickness of the first interface passivation layer at the bottom surface of the tower-like texture structure is less than the thickness of the first interface passivation layer at the side wall of the tower-like texture structure; the thickness of the intrinsic silicon layer at the bottom surface of the tower-like texture structure is greater than the thickness of the intrinsic silicon layer at the side wall of the tower-like texture structure; and / or the thickness of the second doped silicon layer at the bottom surface of the tower-like texture structure is greater than the thickness of the second doped silicon layer at the side wall of the tower-like texture structure. When the above technical solution is adopted, the thickness relationship of the first interface passivation layer at the bottom surface and the side wall of the tower-shaped texture structure is opposite to the thickness relationship of the intrinsic silicon layer and / or the second doped silicon layer at the bottom surface and the side wall of the tower-shaped texture structure. At this time, the thickness of the first interface passivation layer at the side wall of the tower-shaped texture structure is relatively large, which can make up for the fact that the thickness of the intrinsic silicon layer and / or the second doped silicon layer at the side wall of the tower-shaped texture structure is relatively small, resulting in weaker passivation effect and protection effect of the first interface passivation layer; and, the thickness of the intrinsic silicon layer and / or the second doped silicon layer at the bottom surface of the tower-shaped texture structure is relatively large, which can make up for the fact that the thickness of the first interface passivation layer at the bottom surface of the tower-shaped texture structure is relatively small, resulting in weaker passivation effect and protection effect of the first interface passivation layer, thereby ensuring that under the common passivation effect and protection effect of the first interface passivation layer, and the intrinsic silicon layer and / or the second doped silicon layer, the bottom and side surfaces of the tower-shaped texture structure corresponding to the side surface of the silicon substrate have a higher passivation effect and protection strength.

[0060] Optionally, in the side of the silicon substrate, the surface of the region where the first interface passivation layer and the first doped silicon layer are provided has a tower-shaped texture structure. Moreover, the thickness of the first interface passivation layer located at the bottom surface of the tower-shaped texture structure is greater than the thickness of the first interface passivation layer located on the side wall of the tower-shaped texture structure.

[0061] Optionally, a doped layer is formed in the side of the silicon substrate; the dopant in the doped layer includes the dopant in the first doped silicon layer. When the above technical solution is adopted, the doped layer can form a high-low junction with the first doped silicon layer, so that the energy band between the first doped silicon layer and the side of the silicon substrate is more matched, the passivation effect of the first doped silicon layer on the side of the silicon substrate is improved, and the open circuit voltage of the back contact battery is increased.

[0062] In a second group of possible implementation schemes of the first aspect, further, the solar cell is a back contact cell;

[0063] The first conductive layer is a first doped silicon layer, the second conductive layer is a second doped silicon layer, and the insulating layer includes an insulating mask layer; wherein the back contact battery includes: a first interface passivation layer, a first doped silicon layer, an insulating mask layer, an intrinsic silicon layer, a second doped silicon layer and a transparent conductive layer, which are sequentially arranged on the side surface in a direction away from the silicon substrate; wherein the back contact battery includes a surface passivation layer arranged on the light-receiving surface, and the surface passivation layer extends from the light-receiving surface to the side surface; the back contact battery also includes a second interface passivation layer arranged on the backlight surface and located between the silicon substrate and the second doped silicon layer, and the second interface passivation layer extends from the backlight surface to the side surface; on the side surface, the intrinsic silicon layer includes a surface passivation layer and a second interface passivation layer stacked in a direction away from the side surface.

[0064] In the present application, when the above technical solution is adopted, in addition to the intrinsic silicon layer disposed between the first doped silicon layer and the second doped silicon layer, an insulating mask layer is also disposed, which can reduce the thickness requirement of the intrinsic silicon layer while ensuring the reduction of forward leakage loss, reduce the tunneling resistance of the intrinsic silicon layer, and help improve the collection efficiency of the second doped silicon layer disposed on the backlight side of the silicon substrate for carriers, and further improve the conversion efficiency of the back contact battery. In addition, the presence of the insulating mask layer can also enhance the protection of the side of the silicon substrate, and further improve the side structure reliability of the back contact battery. In addition, in the actual manufacturing process, the order in which the corresponding film layers are formed on the backlight side and the light-receiving side of the silicon substrate affects the order in which the corresponding film layers are formed on the side of the silicon substrate. Since the order in which the film layers are formed on the backlight side and the light-receiving side of the silicon substrate is closely related to the process, battery structure, equipment, etc., the order in which the film layers are formed on the backlight side and the light-receiving side of the silicon substrate cannot be adjusted arbitrarily, that is to say, the order in which the film layers are formed on the side of the silicon substrate cannot be adjusted arbitrarily, and needs to be comprehensively considered based on the requirements for the order in which the film layers are formed on the side of the silicon substrate, the technical problems to be solved, as well as the requirements for the order in which the film layers are formed on the front and back sides, the technical problems to be solved, etc.

[0065] Optionally, the back contact cell further includes an anti-reflection layer disposed on the light-receiving surface, the anti-reflection layer extending from the light-receiving surface to the side surface; on the side surface, the anti-reflection layer is disposed between the second doped silicon layer and the transparent conductive layer in the direction away from the side surface. In the case of adopting the above technical solution, an anti-reflection layer is added to the film layer disposed on the side surface of the silicon substrate, which can further improve the protection of the side surface of the silicon substrate, reduce the risk of damage to the side surface of the silicon substrate, and reduce the forward leakage loss. In addition, in this case, the anti-reflection layer is directly formed on the side of the second doped silicon layer away from the silicon substrate. Because there is a difference between the materials of the surface passivation layer and the second doped silicon layer, and the anti-reflection layer is more easily deposited on the surface passivation layer. Based on this, compared with the anti-reflection layer being directly formed on the surface passivation layer, when the anti-reflection layer is directly formed on the side of the second doped silicon layer away from the silicon substrate, the anti-reflection layer can be reduced in the coating range on the backlight side, thereby reducing the etching amount when removing the anti-reflection layer on the backlight side, thereby improving the manufacturing efficiency.

[0066] Optionally, the first interface passivation layer and the first doped silicon layer arranged on the side are only located on a local area of ​​the side and close to the backlight surface; wherein, along the thickness direction of the silicon substrate, the ratio between the maximum extension length of the first interface passivation layer and the first doped silicon layer on the side and the thickness of the silicon substrate is greater than or equal to 70%; and / or, the surface of the area on the side not covered by the first interface passivation layer and the first doped silicon layer is velvet, and the ratio between the maximum extension length of the velvet on the side and the thickness of the silicon substrate is less than or equal to 30%; and / or, on the side, the surface reflectivity of the area not covered by the first interface passivation layer and the first doped silicon layer is less than the surface reflectivity of the area covered by the first interface passivation layer and the first doped silicon layer; and / or, the surface of the area on the side not covered by the first interface passivation layer and the first doped silicon layer is velvet; and / or, the surface of the area on the side covered by the first interface passivation layer and the first doped silicon layer is a polished surface.

[0067] Optionally, the thicknesses of various parts of the first interface passivation layer and / or the first doped silicon layer are the same.

[0068] Optionally, the thickness of the surface passivation layer is uniform on the side surfaces of the silicon substrate, or the thickness of the surface passivation layer gradually increases along the direction from the backlight surface to the light-receiving surface.

[0069] Optionally, on the side surface of the silicon substrate, the thickness of the anti-reflection layer gradually increases along the direction from the backlight surface to the light-receiving surface.

[0070] Optionally, on the side surface of the silicon substrate, the thickness of at least one of the intrinsic silicon layer, the second doped silicon layer and the transparent conductive layer gradually increases along the direction from the light-receiving surface to the backlight surface.

[0071] Optionally, the surface passivation layer and anti-reflection layer arranged on the side are located on a local area of ​​the side and close to the light receiving surface; along the thickness direction of the silicon substrate, the ratio between the maximum extension length of the surface passivation layer and the anti-reflection layer on the side and the thickness of the silicon substrate is less than or equal to 80%.

[0072] Optionally, the material of the surface passivation layer includes at least one of aluminum oxide, intrinsic amorphous silicon, and doped silicon glass.

[0073] Optionally, the thickness of the first doped silicon layer is greater than or equal to 30 nm and less than or equal to 140 nm.

[0074] Optionally, the thickness of the intrinsic silicon layer is greater than or equal to 8 nm and less than or equal to 14 nm.

[0075] Optionally, in the side of the silicon substrate, an area where a first interface passivation layer and a first doped silicon layer are provided has a tower-like texture structure; wherein the thickness of the first interface passivation layer at the bottom surface of the tower-like texture structure is less than the thickness of the first interface passivation layer at the side wall of the tower-like texture structure.

[0076] Optionally, in the side of the silicon substrate, the surface of the region where the first interface passivation layer and the first doped silicon layer are provided has a tower-shaped texture structure. Moreover, the thickness of the first interface passivation layer located at the bottom surface of the tower-shaped texture structure is greater than the thickness of the first interface passivation layer located on the side wall of the tower-shaped texture structure.

[0077] Optionally, the side of the silicon substrate has a tower-like texture structure; wherein the thickness of the first interface passivation layer at the bottom surface of the tower-like texture structure is less than the thickness of the first interface passivation layer at the side wall of the tower-like texture structure; the thickness of the intrinsic silicon layer at the bottom surface of the tower-like texture structure is greater than the thickness of the intrinsic silicon layer at the side wall of the tower-like texture structure; and / or the thickness of the second doped silicon layer at the bottom surface of the tower-like texture structure is greater than the thickness of the second doped silicon layer at the side wall of the tower-like texture structure.

[0078] Optionally, a doping layer is formed in the side surface of the silicon substrate; the dopant in the doping layer includes the dopant in the first doped silicon layer.

[0079] It should be understood that the same or similar optional schemes in the second group and the first group of the first aspect have the same or similar technical effects, which will not be elaborated here.

[0080] In a second aspect, the present application provides a photovoltaic module, comprising any one of the above-mentioned solar cells.

[0081] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0082] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0083] Figure 1 is a schematic diagram of a solar cell according to an embodiment of the present application;

[0084] Figure 2 is a schematic diagram of a silicon substrate according to an embodiment of the present application;

[0085] Figure 3 is a schematic structural diagram of an edge of a solar cell according to an embodiment of the present application;

[0086] Figure 4 is a schematic diagram of the structure at the edge of another solar cell according to an embodiment of the present application;

[0087] Figure 5 is one of the structural schematic diagrams of another edge of a solar cell according to an embodiment of the present application;

[0088] Figure 6 This is a second structural schematic diagram of another edge of a solar cell according to an embodiment of the present application;

[0089] Figure 7 is a partial side cross-sectional view of a solar cell according to an embodiment of the present application;

[0090] Figure 8 One of the schematic longitudinal cross-sectional views of the structure of a back-contact battery provided in an embodiment of the present application;

[0091] Fig. 9 A second schematic longitudinal cross-sectional view of the structure of a back-contact battery provided in an embodiment of the present application;

[0092] Fig.10 The third schematic longitudinal cross-sectional view of the structure of the back contact battery provided in the embodiment of the present application;

[0093] Fig.11 A fourth schematic longitudinal cross-sectional view of the structure of a back-contact battery provided in an embodiment of the present application;

[0094] Fig.12 A fifth schematic longitudinal cross-sectional view of the structure of a back-contact battery provided in an embodiment of the present application;

[0095] Fig.13 A sixth schematic longitudinal cross-sectional view of the structure of a back-contact battery provided in an embodiment of the present application;

[0096] Fig.14 The seventh schematic longitudinal cross-sectional view of the structure of the back contact battery provided in the embodiment of the present application;

[0097] Fig.15 This is the eighth schematic longitudinal cross-sectional view of the structure of the back-contact battery provided in an embodiment of the present application.

[0098] Reference numerals:

[0099] 100-silicon substrate; 110-light-receiving surface; 120-backlight surface;

[0100] 120a-first area; 120b-second area;

[0101] 130-side; 130a-first position; 130b-second position;

[0102] 200-protective layer; 201-first passivation layer; 202-first conductive layer; 203-insulating layer; 204-second passivation layer; 205-second conductive layer; 206-third passivation layer; 207-anti-reflection layer; 208-transparent conductive layer;

[0103] 12 - first doped silicon layer; 13 - surface passivation layer; 15 - intrinsic silicon layer; 16 - second doped silicon layer; 20 - first interface passivation layer; 21 - insulating mask layer; 22 - second interface passivation layer. DETAILED DESCRIPTION

[0104] The embodiments of the present application will be described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and should not be construed as limitations on the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application.

[0105] The term "first" or "second" in the specification and claims of this application may include one or more of the features explicitly or implicitly. In the description of this application, unless otherwise specified, "plurality" means two or more. In addition, "and / or" in the specification and claims means at least one of the connected objects, and the character " / " generally means that the objects connected before and after are in an "or" relationship.

[0106] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0107] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0108] The following is a detailed description of the solar cell and photovoltaic module provided by the embodiment of the present application through specific embodiments and their application scenarios in conjunction with the accompanying drawings. Figure 1 As shown, Figure 1 The schematic diagram of the solar cell of the embodiment of the present application is shown. The solar cell according to some embodiments of the present application includes: a silicon substrate 100; the silicon substrate 100 has a light-receiving surface 110 and a backlight surface 120 opposite to each other, and a side surface 130 arranged between the light-receiving surface 110 and the backlight surface 120; a protective layer 200 is arranged on the side surface 130, such as Figure 3 As shown, the protection layer 200 includes a first conductive layer 202, an insulating layer 203 and a second conductive layer 205 which are sequentially arranged on the side surface 130; the first conductive layer 202 and the second conductive layer 205 have opposite conductivity types.

[0109] In the embodiment of the present application, a protective layer 200 is provided on the side 130 of the silicon substrate 100, and the protective layer 200 includes a first conductive layer 202, an insulating layer 203, and a second conductive layer 205. The insulating layer 203 is used to insulate and isolate the first conductive layer 202 from the second conductive layer 205, so that the conductive layer formed by plating on the side 130 of the silicon substrate 100 does not need to be specially removed during the battery preparation process, which helps to simplify the battery production process. In addition, the protective layer 200 can play a passivation protection role on the side 130 of the silicon substrate 100, which can not only avoid the risk of damage and leakage caused by direct exposure of the side 130 of the silicon substrate 100, but also reduce the carrier recombination of the side 130 of the silicon substrate 100, thereby improving the conversion efficiency of the battery.

[0110] Combine the following Figures 1 to 7 , the structure of the solar cell of some embodiments of the present application is described in detail.

[0111] Specifically, Figure 2 As shown, Figure 2 A schematic diagram of a silicon substrate of an embodiment of the present application is shown. The silicon substrate 100 in the solar cell has a light-receiving surface 110 and a backlight surface 120 opposite to each other, and side surfaces 130 arranged around the silicon substrate 100. Among them, the light-receiving surface 110 is a side of the silicon substrate 100 that receives incident light, the backlight surface 120 is a side of the silicon substrate 100 that is away from the light-receiving surface 110, and the side surface 130 connects the light-receiving surface 110 and the backlight surface 120. Furthermore, a protective layer 200 is arranged on the side surfaces 130 around the silicon substrate 100, so as to use the protective layer 200 to shield and protect the side surfaces 130 around the silicon substrate 100.

[0112] It is understandable that in the solar cell manufacturing process, it is usually necessary to process and form a first conductive layer 202 and a second conductive layer 205 of different conductive types on the light-receiving surface 110 and / or the backlight surface 120 of the silicon substrate 100. In this process, a winding plating layer is inevitably formed on the side 130 of the silicon substrate 100. In order to avoid the leakage problem caused by the direct contact and conduction of the first conductive layer 202 and the second conductive layer 205 formed by the winding plating on the side 130, in the embodiment of the present application, an insulating layer 203 is provided between the first conductive layer 202 and the second conductive layer 205 on the side 130 to insulate and isolate the first conductive layer 202 and the second conductive layer 205. In this way, in the battery manufacturing process, there is no need to specifically remove the first conductive layer 202 and the second conductive layer 205 wound on the side 130, which can not only solve the leakage problem of the side 130 caused by the winding plating, but also simplify the processing technology. Furthermore, the protection layer 200 formed by the insulating layer 203 and the first conductive layer 202 and the second conductive layer 205 can also play a role in passivation protection of the side surface 130 , which helps to improve the battery performance.

[0113] It should be noted that the insulating layer 203 disposed on the side surface 130 of the silicon substrate 100 in the embodiment of the present application can be prepared separately in the battery manufacturing process. It can also be based on the existing battery manufacturing process, in the process of preparing the film layer structure on the backlight surface 120 and / or the light-receiving surface 110 of the silicon substrate 100, the corresponding insulating layer 203 is formed on the surrounding side surfaces 130 of the silicon substrate 100 at the same time, and can be flexibly arranged according to actual conditions, and the embodiment of the present application is not limited to this.

[0114] In some embodiments, the electrical properties of the first conductive layer 202 and the second conductive layer 205 are opposite. Among them, one of the first conductive layer 202 and the second conductive layer 205 can be set as: N-type amorphous silicon layer, N-type microcrystalline silicon layer, a mixed layer of N-type amorphous silicon and microcrystalline silicon, N-type transition metal compound layer, N-type polycrystalline silicon layer, etc. The other of the first conductive layer 202 and the second conductive layer 205 can be set as: P-type amorphous silicon, P-type microcrystalline silicon, a mixed layer of P-type amorphous silicon and microcrystalline silicon, P-type transition metal compound layer or P-type polycrystalline silicon layer, etc.

[0115] In some embodiments, the insulating layer 203 can be made of materials such as silicon nitride, silicon oxide, silicon oxynitride, and silicon carbide. Of course, the insulating layer 203 can also be made of other materials, which is not limited in the embodiments of the present application.

[0116] Alternatively, if Figure 7 As shown, along a direction parallel to the backlight surface 120 , the backlight surface 120 has first regions 120 a and second regions 120 b that are alternately arranged; the first regions 120 a are formed with a first conductive layer 202 , and the second regions 120 b are formed with a second conductive layer 205 .

[0117] It can be understood that the solar cell structure in the embodiment of the present application can be applied to a back-contact cell, for example, can be applied to a HBC cell, in which the PN junction and the metal grid line are both arranged on the backlight surface 120 of the cell.

[0118] In the process of preparing the back contact battery, it is necessary to deposit a first conductive layer 202 in the first area 120a of the backlight surface 120 of the silicon substrate 100, and to deposit a second conductive layer 205 in the second area 120b. In this process, the side surface 130 of the silicon substrate 100 will be plated with the first conductive layer 202 and the second conductive layer 205 at the same time. By providing an insulating layer 203 between the first conductive layer 202 and the second conductive layer 205 on the side surface 130, it is possible to avoid leakage problems caused by direct contact and conduction between the first conductive layer 202 and the second conductive layer 205 on the side surface 130 of the silicon substrate 100. At the same time, the protective layer 200 can also play a role in passivation protection of the side surface 130.

[0119] In specific applications, the insulating layer 203 can be set only on the side 130 of the silicon substrate 100; or the insulating layer 203 can be set on both the side 130 and the backlight surface 120 of the silicon substrate 100. For example, the insulating layer 203 is also set between the first area 120a and the second area 120b. It can be flexibly set according to actual conditions and is not limited in this application.

[0120] Alternatively, if Figure 3 As shown, the protection layer 200 further includes a first passivation layer 201 located between the side surface 130 of the silicon substrate 100 and the first conductive layer 202, and a second passivation layer 204 located between the insulating layer 203 and the second conductive layer 205; Figure 7 As shown, along the direction parallel to the backlight surface 120, the backlight surface 120 has a first area 120a and a second area 120b alternately arranged; along the direction away from the silicon substrate 100, the first area 120a is sequentially formed with a first passivation layer 201 and a first conductive layer 202, and the second area 120b is sequentially formed with a second passivation layer 204 and a second conductive layer 205; an insulating layer 203 is provided between the first area 120a and the second area 120b.

[0121] In the embodiment of the present application, by setting a first passivation layer 201 between the silicon substrate 100 and the first conductive layer 202, and setting a second passivation layer 204 between the insulating layer 203 and the second conductive layer 205, while forming a shielding protection for the side surface 130 of the silicon substrate 100, the passivation effect of the entire protective layer 200 on the side surface 130 of the silicon substrate 100 can be further enhanced, thereby improving the conversion efficiency of the battery.

[0122] Furthermore, by setting the film layer structure of the side surface 130 of the silicon substrate 100 to match the film layer structure of the backlight surface 120 of the silicon substrate 100, when the film layer structure of the backlight surface 120 of the silicon substrate 100 is processed and formed in the battery processing technology, a corresponding protective layer 200 can be formed on the side surface 130 of the silicon substrate 100 at the same time. In this way, the processing flow can be simplified and the processing efficiency can be improved.

[0123] It is understandable that in the film layer structures of the backlight surface 120 and the side surface 130 of the silicon substrate 100, the same type of film layer structures can be formed by one-time processing using corresponding processes. For example, the first passivation layer 201 can be deposited on the backlight surface 120 and the side surface 130 of the silicon substrate 100 using the PECVD process. Correspondingly, the first conductive layer 202 can also be further deposited on the surface of the first passivation layer 201 using the PECVD process. In this way, the first passivation layer 201 and the first conductive layer 202 can be obtained by processing the backlight surface 120 and the side surface 130 of the silicon substrate 100 at the same time.

[0124] Among them, Figure 7 As shown, Figure 7 A partial side cross-sectional view of a solar cell according to an embodiment of the present application is shown; the backlight surface 120 of the silicon substrate 100 has alternating first regions 120a and second regions 120b, a first passivation layer 201 and a first conductive layer 202 are sequentially provided on the backlight surface of the silicon substrate 100 in the first region 120a, a second passivation layer 204 and a second conductive layer 205 are sequentially provided on the backlight surface of the silicon substrate 100 in the second region 120b, and an insulating layer 203 is provided between the first region 120a and the second region 120b to insulate and isolate the first region 120a from the second region 120b.

[0125] In specific applications, a processing technique such as a PECVD process can be used to sequentially form a first passivation layer 201, a first conductive layer 202, and an insulating layer 203 on the backlight surface 120 and the surrounding side surfaces 130 of the silicon substrate 100. Further, a mask layer is set on the surface of the insulating layer 203 on the backlight surface 120 of the silicon substrate 100, and the film layer structure of the backlight surface 120 of the silicon substrate 100 is patterned through processes such as photolithography or laser and etching to form a first region 120a and a second region 120b on the backlight surface 120, and the first passivation layer 201 and the first conductive layer 202 in the second region 120b are removed. Then, a processing technique such as a PECVD process is used to form a second passivation layer 204 and a second conductive layer 205 in the second region 120b, and at the same time, a second passivation layer 204 and a second conductive layer 205 are also formed on the surrounding side surfaces 130 of the silicon substrate 100.

[0126] In this way, the protective layer 200 formed on the four sides 130 of the silicon substrate 100 can be matched with the film structure of the backlight surface 120 of the silicon substrate 100, so that the protective layer 200 on the side 130 of the silicon substrate 100 can be processed without increasing the processing steps. This helps to simplify the processing flow of the battery and can also achieve shielding protection for the side 130 of the silicon substrate 100.

[0127] It should be noted that the specific film layer structure on the backlight surface 120 of the silicon substrate 100 can be set according to actual needs, and the embodiment of the present application does not limit this.

[0128] In some other embodiments, the first passivation layer 201 and the second passivation layer 204 may be configured as at least one of an amorphous silicon layer, a hydrogenated amorphous silicon layer, a carbon-doped amorphous silicon layer, and an intrinsic amorphous silicon layer.

[0129] Of course, the specific structures and preparation materials of the first conductive layer 202, the second conductive layer 205, the first passivation layer 201 and the second passivation layer 204 can be flexibly selected according to the structural design of the solar cell, and the embodiments of the present application do not limit this.

[0130] Alternatively, if Figure 1 As shown, the junction of the side surface 130 and the backlight surface 120 is a first position 130a, and the junction of the side surface 130 and the light receiving surface 110 is a second position 130b. The thickness of the protective layer 200 at the first position 130a is greater than the thickness of the protective layer 200 at the second position 130b.

[0131] In the embodiment of the present application, the thickness of the protective layer 200 on the side close to the backlight surface 120 of the silicon substrate 100 is greater than the thickness on the side close to the light-receiving surface 110 of the silicon substrate 100, thereby strengthening the protection effect on the side 130 of the silicon substrate 100 close to the backlight surface 120.

[0132] Generally, in a back contact cell, the P+ and N+ emitters, the back field, and the positive and negative electrodes are all arranged on the backlight surface 120 of the silicon substrate 100. Therefore, the surrounding side surfaces 130 of the silicon substrate 100 are at a greater risk of leakage on the side close to the backlight surface 120. Therefore, in the embodiment of the present application, the protective layer 200 of the side surface 130 of the silicon substrate 100 is arranged to have a thickness greater on the side close to the backlight surface 120 than on the side close to the light receiving surface 110, so as to increase the protective effect of the protective layer 200 on the side of the silicon substrate 100 close to the backlight surface 120.

[0133] Alternatively, if Figure 1 As shown, the thickness of the protective layer 200 at the first position 130a is D1, and the thickness of the protective layer 200 at the second position 130b is D2, which satisfies: 1<D1 / D2≤10; optionally, 2.5≤D1 / D2≤10.

[0134] In the embodiment of the present application, a reasonable value range of the ratio D1 / D2 between the thickness D1 of the protective layer 200 at the first position 130a and the thickness D2 of the protective layer 200 at the second position 130b of the side surface 130 of the silicon substrate 100 is set, so that the thickness of the protective layer 200 at different positions of the side surface 130 of the silicon substrate 100 is different. In this way, effective shielding protection can be formed for the entire side surface 130 of the silicon substrate 100, and the material consumption required for preparing the protective layer 200 can be appropriately reduced.

[0135] Exemplarily, the ratio D1 / D2 of the total thickness D1 of the protective layer 200 at the first position 130a to the total thickness D2 of the protective layer 200 at the second position 130b can be set to any value such as 1.5, 2, 2.5, 3, 3.5, 4, 5, 6, 7, 8, 9, 10, or a range between any two values.

[0136] The thickness of the protective layer 200 on the side 130 of the silicon substrate 100 refers to the straight-line distance between the side of the protective layer 200 facing the silicon substrate 100 and the side of the protective layer 200 facing away from the silicon substrate 100 along a direction perpendicular to the side 130 of the silicon substrate 100 .

[0137] Alternatively, if Figure 3 As shown, the total thickness of the first passivation layer 201 and the first conductive layer 202 on the backlight surface 120 is H1, the total thickness of the first passivation layer 201 and the first conductive layer 202 at the first position 130a on the side 130 is H11, and the total thickness of the first passivation layer 201 and the first conductive layer 202 at the second position 130b on the side 130 is H12, satisfying: H12<H11≤H1.

[0138] In the embodiment of the present application, the total thickness of the first passivation layer 201 and the first conductive layer 202 located on the side surface 130 of the silicon substrate 100 is set to be less than or equal to the total thickness of the first passivation layer 201 and the first conductive layer 202 located on the backlight surface 120 of the silicon substrate 100, so as to reduce the material loss required for preparing the first passivation layer 201 and the first conductive layer 202 while satisfying the requirement of shielding and protecting the side surface 130 of the silicon substrate 100. In addition, the total thickness H11 of the first passivation layer 201 and the first conductive layer 202 at the first position 130a is greater than the total thickness H12 at the second position 130b, thereby strengthening the protection of the side surface 130 of the silicon substrate 100 close to the backlight surface 120.

[0139] It is understandable that the first passivation layer 201 on the backlight surface 120 and the side surface 130 of the silicon substrate 100 in the embodiment of the present application can be obtained by a one-time molding process. For example, a PECVD process can be used to simultaneously deposit the first passivation layer 201 on the backlight surface 120 and the side surface 130 of the silicon substrate 100. Similarly, a one-time molding process can also be used to process the surface of the first passivation layer 201 on the backlight surface 120 and the side surface 130 of the silicon substrate 100 to obtain the first conductive layer 202, so that the first conductive layer 202 covers the surface of the first passivation layer 201.

[0140] It should be noted that the first passivation layer 201 and the first conductive layer 202 may be prepared by a PECVD process or other preparation processes, which is not limited in the embodiment of the present application.

[0141] Optionally, the total thickness H11 of the first passivation layer 201 and the first conductive layer 202 at the first position 130a on the side surface 130 and the total thickness H12 of the first passivation layer 201 and the first conductive layer 202 at the second position 130b on the side surface 130 satisfy: 0.2≤H12 / H11<1. By setting a reasonable value range of H12 / H11, the first passivation layer 201 and the first conductive layer 202 can be used to shield and protect the side surface of the silicon substrate 100, and at the same time, the protection of the side surface 130 of the silicon substrate 100 close to the backlight surface 120 is strengthened.

[0142] Specifically, the ratio H12 / H11 of the total thickness H12 of the first passivation layer 201 and the first conductive layer 202 on the side 130 at the second position 130b to the total thickness H11 at the first position 130a can be set to any number such as 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, 0.95, or a range between any two values.

[0143] Alternatively, if Figure 3 As shown, the total thickness H1 of the first passivation layer 201 and the first conductive layer 202 on the backlight surface 120 and the total thickness H11 of the first passivation layer 201 and the first conductive layer 202 at the first position 130 a on the side surface 130 satisfy: 0.5≤H11 / H1≤1.

[0144] In the embodiment of the present application, by setting a reasonable value range of the ratio H11 / H1 of the total thickness H11 of the first passivation layer 201 and the first conductive layer 202 at the first position 130a on the side 130 of the silicon substrate 100 to the total thickness H1 of the first passivation layer 201 and the first conductive layer 202 on the backlight surface 120 of the silicon substrate 100, the structure of the first passivation layer 201 and the first conductive layer 202 on the side 130 of the silicon substrate 100 can be reasonably set according to the structure of the first passivation layer 201 and the first conductive layer 202 on the backlight surface 120 of the silicon substrate 100, thereby achieving a passivation protection effect on the side 130 of the silicon substrate 100, reducing carrier recombination on the side 130, and also reducing the material loss in preparing the first passivation layer 201 and the first conductive layer 202, thereby reducing production costs.

[0145] Exemplarily, the ratio H11 / H1 of the total thickness H11 of the first passivation layer 201 and the first conductive layer 202 at the first position 130a on the side 130 to the total thickness H1 of the first passivation layer 201 and the first conductive layer 202 on the backlight surface 120 can be set to any number such as 0.5, 0.55, 0.6, 0.65, 0.7, 0.75, 0.8, 0.85, 0.9, 0.95, 1, or a range between any two values.

[0146] Alternatively, if Figure 3 As shown, the total thickness H1 of the first passivation layer 201 and the first conductive layer 202 on the backlight surface 120 and the total thickness H12 of the first passivation layer 201 and the first conductive layer 202 at the second position 130 b on the side surface 130 satisfy: 0.2≤H12 / H1≤0.6.

[0147] In the embodiment of the present application, by setting a reasonable value range of the ratio H12 / H1 of the total thickness H12 of the first passivation layer 201 and the first conductive layer 202 at the second position 130b on the side 130 of the silicon substrate 100 to the total thickness H1 of the first passivation layer 201 and the first conductive layer 202 on the backlight surface 120 of the silicon substrate 100, the structure of the first passivation layer 201 and the first conductive layer 202 on the side 130 of the silicon substrate 100 can be reasonably set according to the structure of the first passivation layer 201 and the first conductive layer 202 on the backlight surface 120 of the silicon substrate 100, thereby achieving a passivation protection effect on the side 130 of the silicon substrate 100, and can also reduce the material loss in preparing the first passivation layer 201 and the first conductive layer 202, thereby reducing the production cost.

[0148] Exemplarily, the ratio H12 / H1 of the total thickness H12 of the first passivation layer 201 and the first conductive layer 202 at the second position 130b on the side 130 to the total thickness H1 of the first passivation layer 201 and the first conductive layer 202 on the backlight surface 120 can be set to any number such as 0.2, 0.25, 0.3, 0.35, 0.4, 0.45, 0.5, 0.55, 0.6, or a range between any two values.

[0149] It should be noted that the total thickness H1 of the first passivation layer 201 and the first conductive layer 202 on the backlight surface 120 of the silicon substrate 100 refers to the total thickness of the first passivation layer 201 and the first conductive layer 202 on the backlight surface 120 of the silicon substrate 100 along a direction perpendicular to the backlight surface 120. The total thickness of the first passivation layer 201 and the first conductive layer 202 on the side surface 130 of the silicon substrate 100 refers to the total thickness of the first passivation layer 201 and the first conductive layer 202 on the side surface 130 of the silicon substrate 100 along a direction perpendicular to the side surface 130.

[0150] Alternatively, if Figure 3 As shown, the thickness of the insulating layer 203 on the backlight surface 120 is H2, the thickness of the insulating layer 203 at the first position 130a on the side surface 130 is H21, and the thickness of the insulating layer 203 at the second position 130b on the side surface 130 is H22, satisfying: H22<H21≤H2.

[0151] In the embodiment of the present application, the thickness of the insulating layer 203 on the side surface 130 of the silicon substrate 100 is set to be less than or equal to the thickness of the insulating layer 203 on the backlight surface 120 of the silicon substrate 100, so as to reduce the material loss of the insulating layer 203 while using the insulating layer 203 to shield and protect the side surface 130 of the silicon substrate 100. In addition, the thickness H21 of the insulating layer 203 on the side surface 130 of the silicon substrate 100 at the first position 130a is greater than the thickness H22 at the second position 130b, so as to strengthen the protection of the side surface 130 of the silicon substrate 100 close to the backlight surface 120.

[0152] It is understandable that the insulating layer 203 on the backlight surface 120 and the side surface 130 of the silicon substrate 100 in the embodiment of the present application can be obtained by a one-time molding process. For example, a PECVD process can be used to simultaneously deposit the insulating layer 203 on the backlight surface 120 and the side surface 130 of the silicon substrate 100. It should be noted that the specific preparation method of the insulating layer 203 can be flexibly set according to actual conditions, and the embodiment of the present application is not limited to this.

[0153] Optionally, a thickness H21 of the insulating layer 203 at the first position 130 a on the side surface 130 and a thickness H22 of the insulating layer 203 at the second position 130 b on the side surface 130 satisfy: 0.2≤H22 / H21<1.

[0154] In the embodiment of the present application, a reasonable value range of H22 / H21 is set so that the insulating layer 203 can be used to insulate and isolate the first conductive layer 202 and the second conductive layer 205 on the side surface 130, and then a protective layer is formed by the insulating layer 203 and the first conductive layer 202 and the second conductive layer 205 to shield and protect the side surface 130 of the silicon substrate 100. At the same time, the protection of the side surface 130 of the silicon substrate 100 close to the backlight surface 120 can be strengthened.

[0155] Specifically, the ratio H22 / H21 of the thickness H22 of the insulating layer 203 on the side 130 at the second position 130b to the thickness H21 at the first position 130a can be set to any number such as 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, 0.95, or a range between any two values.

[0156] Alternatively, if Figure 3 As shown, the thickness H2 of the insulating layer 203 on the backlight surface 120 and the thickness H21 of the insulating layer 203 located at the first position 130 a on the side surface 130 satisfy: 0.5≤H21 / H2≤1.

[0157] In the embodiment of the present application, by setting a reasonable value range of the ratio H21 / H2 of the thickness H21 of the insulating layer 203 at the first position 130a of the side surface 130 of the silicon substrate 100 to the thickness H2 of the insulating layer 203 on the backlight surface 120 of the silicon substrate 100, the structure of the insulating layer 203 on the side surface 130 of the silicon substrate 100 can be reasonably set according to the structure of the insulating layer 203 on the backlight surface 120 of the silicon substrate 100, thereby facilitating actual processing and forming. At the same time, the insulating layer 203 is used to form a protective layer 200 with the first conductive layer 202 and the second conductive layer 205 to shield and protect the side surface 130 of the silicon substrate 100, and it can also reduce the material loss required for preparing the insulating layer 203, thereby reducing production costs.

[0158] Exemplarily, the ratio H21 / H2 of the thickness H21 of the insulating layer 203 at the first position 130a on the side 130 to the thickness H2 of the insulating layer 203 on the backlight surface 120 can be set to any number such as 0.5, 0.55, 0.6, 0.65, 0.7, 0.75, 0.8, 0.85, 0.9, 0.95, 1, or a range between any two values.

[0159] Alternatively, if Figure 3 As shown, the thickness H2 of the insulating layer 203 on the backlight surface 120 and the total thickness H22 of the insulating layer 203 located at the second position 130 b on the side surface 130 satisfy: 0.2≤H22 / H2≤0.6.

[0160] In the embodiment of the present application, by setting a reasonable value range of the ratio H22 / H2 of the thickness H22 of the insulating layer 203 at the second position 130b of the side surface 130 of the silicon substrate 100 to the thickness H2 of the insulating layer 203 on the backlight surface 120 of the silicon substrate 100, the structure of the insulating layer 203 on the side surface 130 of the silicon substrate 100 can be reasonably set according to the structure of the insulating layer 203 on the backlight surface 120 of the silicon substrate 100, thereby facilitating actual processing and forming. At the same time, the insulating layer 203 is used to form a protective layer 200 with the first conductive layer 202 and the second conductive layer 205 to shield and protect the side surface 130 of the silicon substrate 100, and it can also reduce the material loss required for preparing the insulating layer 203 and reduce the production cost.

[0161] Exemplarily, the ratio H22 / H2 of the total thickness H22 of the insulating layer 203 at the second position 130b on the side 130 to the thickness H2 of the insulating layer 203 on the backlight surface 120 can be set to any number such as 0.2, 0.25, 0.3, 0.35, 0.4, 0.45, 0.5, 0.55, 0.6, or a range between any two values.

[0162] It should be noted that the thickness H2 of the insulating layer 203 on the backlight surface 120 of the silicon substrate 100 refers to the thickness of the insulating layer 203 on the backlight surface 120 along a direction perpendicular to the backlight surface 120. The thickness of the insulating layer 203 on the side surface 130 of the silicon substrate 100 refers to the thickness of the insulating layer 203 on the side surface 130 along a direction perpendicular to the side surface 130.

[0163] Alternatively, if Figure 3 As shown, the total thickness of the second passivation layer 204 and the second conductive layer 205 on the backlight surface 120 is H3, the total thickness of the second passivation layer 204 and the second conductive layer 205 at the first position 130a on the side 130 is H31, and the total thickness of the second passivation layer 204 and the second conductive layer 205 at the second position 130b on the side 130 is H32, satisfying: H32<H31≤H3.

[0164] In the embodiment of the present application, the total thickness of the second passivation layer 204 and the second conductive layer 205 located on the side surface 130 of the silicon substrate 100 is set to be less than or equal to the total thickness of the second passivation layer 204 and the second conductive layer 205 located on the backlight surface 120 of the silicon substrate 100, so as to reduce the material loss of the second passivation layer 204 and the second conductive layer 205 while satisfying the shielding protection of the side surface 130 of the silicon substrate 100. In addition, the second passivation layer 204 and the second conductive layer 205 are set on the side surface 130 of the silicon substrate 100, and the total thickness H31 at the first position 130a is greater than the total thickness H32 at the second position 130b, thereby strengthening the protection of the side surface 130 of the silicon substrate 100 close to the backlight surface 120.

[0165] It is understandable that the second passivation layer 204 on the backlight surface 120 and the side surface 130 of the silicon substrate 100 in the embodiment of the present application can be obtained by a one-time molding process. For example, a PECVD process can be first used to simultaneously deposit the second passivation layer 204 on the backlight surface 120 and the side surface 130 of the silicon substrate 100. Similarly, a one-time molding process can also be used to further process the surface of the second passivation layer 204 to obtain the second conductive layer 205, so that the second conductive layer 205 covers the surface of the second passivation layer 204.

[0166] It should be noted that the second passivation layer 204 and the second conductive layer 205 may be prepared by a PECVD process or other preparation processes, which is not limited in the embodiment of the present application.

[0167] Optionally, the total thickness H31 of the second passivation layer 204 and the second conductive layer 205 at the first position 130a on the side surface 130 and the total thickness H32 of the second passivation layer 204 and the second conductive layer 205 at the second position 130b on the side surface 130 satisfy: 0.2≤H32 / H31<1. By setting a reasonable value range of H32 / H31, the second passivation layer 204 and the second conductive layer 205 can be used to passivate the side surface 130 of the silicon substrate 100, and the protection of the side surface 130 of the silicon substrate 100 close to the backlight surface 120 can be strengthened.

[0168] Specifically, the ratio H32 / H31 of the total thickness H32 of the second passivation layer 204 and the second conductive layer 205 at the second position 130b to the total thickness H31 at the first position 130a can be set to any number such as 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, 0.95, or a range between any two values. Figure 3 As shown, the total thickness H3 of the second passivation layer 204 and the second conductive layer 205 on the backlight surface 120 and the total thickness H31 of the second passivation layer 204 and the second conductive layer 205 at the first position 130 a on the side surface 130 satisfy: 0.5≤H31 / H3≤1.

[0169] In the embodiment of the present application, by setting a reasonable value range of the ratio H31 / H3 of the total thickness H31 of the second passivation layer 204 and the second conductive layer 205 at the first position 130a on the side 130 of the silicon substrate 100 to the total thickness H3 of the second passivation layer 204 and the second conductive layer 205 on the backlight surface 120, the structure of the second passivation layer 204 and the second conductive layer 205 on the side 130 of the silicon substrate 100 can be reasonably set according to the structure of the second passivation layer 204 and the second conductive layer 205 on the backlight surface 120 of the silicon substrate 100, so as to play a passivation protection role on the side 130 of the silicon substrate 100, and can also reduce the material loss in preparing the second passivation layer 204 and the second conductive layer 205, thereby reducing the production cost.

[0170] Exemplarily, the ratio H31 / H3 of the total thickness H31 of the second passivation layer 204 and the second conductive layer 205 at the first position 130a on the side 130 to the total thickness H3 of the second passivation layer 204 and the second conductive layer 205 on the backlight surface 120 can be set to any number such as 0.5, 0.55, 0.6, 0.65, 0.7, 0.75, 0.8, 0.85, 0.9, 0.95, 1, or a range between any two values.

[0171] Alternatively, if Figure 3As shown, the total thickness H3 of the second passivation layer 204 and the second conductive layer 205 on the backlight surface 120 and the total thickness H32 of the second passivation layer 204 and the second conductive layer 205 at the second position 130 b on the side surface 130 satisfy: 0.2≤H32 / H3≤0.6.

[0172] In the embodiment of the present application, by setting a reasonable value range of the ratio H32 / H3 of the total thickness H32 of the second passivation layer 204 and the second conductive layer 205 located at the second position 130b on the side surface 130 of the silicon substrate 100 to the total thickness H3 of the second passivation layer 204 and the second conductive layer 205 on the backlight surface 120 of the silicon substrate 100, the structure of the second passivation layer 204 and the second conductive layer 205 on the side surface 130 of the silicon substrate 100 can be reasonably set according to the structure of the second passivation layer 204 and the second conductive layer 205 on the backlight surface 120 of the silicon substrate 100. This can play a passivation protection role on the side surface 130 of the silicon substrate 100, and can also reduce the material loss of preparing the second passivation layer 204 and the second conductive layer 205, thereby reducing the production cost.

[0173] Exemplarily, the ratio of the total thickness H32 of the second passivation layer 204 and the second conductive layer 205 at the second position 130b on the side 130 to the total thickness H3 of the second passivation layer 204 and the second conductive layer 205 on the backlight surface 120 can be set to any number such as 0.2, 0.25, 0.3, 0.35, 0.4, 0.45, 0.5, 0.55, 0.6, or a range between any two values.

[0174] It should be noted that the total thickness H3 of the second passivation layer 204 and the second conductive layer 205 on the backlight surface 120 of the silicon substrate 100 refers to the total thickness of the second passivation layer 204 and the second conductive layer 205 on the backlight surface 120 in a direction perpendicular to the backlight surface 120. The total thickness of the second passivation layer 204 and the second conductive layer 205 on the side surface 130 of the silicon substrate 100 refers to the total thickness of the second passivation layer 204 and the second conductive layer 205 on the side surface 130 in a direction perpendicular to the side surface 130.

[0175] Alternatively, if Figure 4 As shown, Figure 4 A schematic diagram of the edge of another solar cell according to an embodiment of the present application is shown; the protective layer 200 also includes a third passivation layer 206 and an anti-reflection layer 207, the third passivation layer 206 is arranged on the side of the second conductive layer 205 away from the side 130, and the anti-reflection layer 207 is arranged on the side of the third passivation layer 206 away from the second conductive layer 205; along the direction away from the silicon substrate 100, the third passivation layer 206 and the anti-reflection layer 207 are sequentially formed on the light receiving surface 110.

[0176] In the embodiment of the present application, a third passivation layer 206 and an anti-reflection layer 207 are formed on both the light-receiving surface 110 and the side surface 130 of the silicon substrate 100, so as to meet the structural design requirements of the light-receiving surface 110 of the silicon substrate 100, and at the same time, a third passivation layer 206 and an anti-reflection layer 207 are correspondingly formed on the side surface 130 of the silicon substrate 100, thereby enhancing the shielding and protection effect on the side surface 130 of the silicon substrate 100.

[0177] It is understandable that the third passivation layer 206 in the light-receiving surface 110 and the side surface 130 of the silicon substrate 100 can be obtained by a one-time molding process. For example, a PECVD process can be used to simultaneously deposit and form the third passivation layer 206 on the light-receiving surface 110 and the side surface 130 of the silicon substrate 100. Similarly, a one-time molding process can also be used to process the surface of the third passivation layer 206 on the light-receiving surface 110 and the side surface 130 of the silicon substrate 100 to obtain the anti-reflection layer 207, so that the anti-reflection layer 207 covers the surface of the third passivation layer 206.

[0178] In some embodiments, the third passivation layer 206 can be made of at least one of an amorphous silicon layer, a hydrogenated amorphous silicon layer, a carbon-doped amorphous silicon layer, and an intrinsic amorphous silicon layer. The anti-reflection layer 207 can be made of one or more of silicon oxide, titanium oxide, silicon nitride, and silicon carbide.

[0179] It should be noted that the materials and specific preparation processes of the third passivation layer 206 and the anti-reflection layer 207 can be flexibly set according to actual needs, and the embodiments of the present application do not limit this.

[0180] Alternatively, if Figure 4 As shown, the total thickness of the third passivation layer 206 and the anti-reflection layer 207 on the light receiving surface 110 is H4, the total thickness of the third passivation layer 206 and the anti-reflection layer 207 located at the first position 130a on the side 130 is H41, and the total thickness of the third passivation layer 206 and the anti-reflection layer 207 located at the second position 130b on the side 130 is H42, satisfying: H41<H42≤H4.

[0181] In the embodiment of the present application, the total thickness of the third passivation layer 206 and the anti-reflection layer 207 located on the side 130 of the silicon substrate 100 is set to be less than or equal to the total thickness of the third passivation layer 206 and the anti-reflection layer 207 located on the light-receiving surface 110 of the silicon substrate 100, so that the third passivation layer 206 and the anti-reflection layer 207 can be used to shield and protect the side 130 of the silicon substrate 100 without affecting the conversion efficiency of the battery. In addition, the third passivation layer 206 and the anti-reflection layer 207 are set on the side 130 of the silicon substrate 100, and the total thickness H42 at the second position 130b is greater than the total thickness H41 at the first position 130a, so that the third passivation layer 206 and the anti-reflection layer 207 form a smooth transition in size at the junction area between the edge of the light-receiving surface 110 of the silicon substrate 100 and the side 130, so as to enhance the protection effect on the edge of the silicon substrate 100.

[0182] Optionally, the total thickness H41 of the third passivation layer 206 and the anti-reflection layer 207 at the first position 130a on the side surface 130 and the total thickness H42 of the third passivation layer 206 and the anti-reflection layer 207 at the second position 130b on the side surface 130 satisfy: 0.1≤H42 / H41<1. By setting a reasonable value range of H42 / H41, the third passivation layer 206 and the anti-reflection layer 207 can be used to shield and protect the side surface 130 of the silicon substrate 100, and at the same time, it is convenient for actual processing and forming.

[0183] Specifically, the ratio H42 / H41 of the total thickness H42 of the third passivation layer 206 and the anti-reflection layer 207 on the side 130 at the second position 130b to the total thickness H41 at the first position 130a can be set to any number such as 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, 0.95, or a range between any two values.

[0184] Alternatively, if Figure 4 As shown, the total thickness H4 of the third passivation layer 206 and the anti-reflection layer 207 on the light receiving surface 110 and the total thickness H41 of the third passivation layer 206 and the anti-reflection layer 207 at the first position 130a on the side surface 130 satisfy: 0.1≤H41 / H4≤0.4.

[0185] In the embodiment of the present application, by setting a reasonable value range of the ratio H41 / H4 of the total thickness H41 of the third passivation layer 206 and the anti-reflection layer 207 located at the first position 130a on the side surface 130 of the silicon substrate 100 to the total thickness H4 of the third passivation layer 206 and the anti-reflection layer 207 on the light-receiving surface 110 of the silicon substrate 100, the structure of the third passivation layer 206 and the anti-reflection layer 207 on the side surface 130 of the silicon substrate 100 can be reasonably set according to the structure of the third passivation layer 206 and the anti-reflection layer 207 on the light-receiving surface 110 of the silicon substrate 100. Furthermore, the third passivation layer 206 and the anti-reflection layer 207 are used to further shield and protect the side surface 130 of the silicon substrate 100, and the material loss of preparing the third passivation layer 206 and the anti-reflection layer 207 can also be reduced, thereby reducing the production cost.

[0186] Exemplarily, the ratio of the total thickness H41 of the third passivation layer 206 and the anti-reflection layer 207 located at the first position 130a on the side 130 to the total thickness H4 of the third passivation layer 206 and the anti-reflection layer 207 on the light receiving surface 110 can be set to any number such as 0.1, 0.15, 0.2, 0.25, 0.3, 0.35, 0.4, or a range between any two values.

[0187] Alternatively, if Figure 4 As shown, the total thickness H4 of the third passivation layer 206 and the anti-reflection layer 207 on the light receiving surface 110 and the total thickness H42 of the third passivation layer 206 and the anti-reflection layer 207 at the second position 130b on the side surface 130 satisfy: 0.5≤H42 / H4≤0.8.

[0188] In the embodiment of the present application, by setting a reasonable value range of the ratio H42 / H4 of the total thickness H42 of the third passivation layer 206 and the anti-reflection layer 207 located at the second position 130b on the side surface 130 of the silicon substrate 100 to the total thickness H4 of the third passivation layer 206 and the anti-reflection layer 207 on the light-receiving surface 110 of the silicon substrate 100, the structure of the third passivation layer 206 and the anti-reflection layer 207 on the side surface 130 of the silicon substrate 100 can be reasonably set according to the structure of the third passivation layer 206 and the anti-reflection layer 207 on the light-receiving surface 110 of the silicon substrate 100. Furthermore, the third passivation layer 206 and the anti-reflection layer 207 are used to further shield and protect the side surface 130 of the silicon substrate 100, and the material loss of preparing the third passivation layer 206 and the anti-reflection layer 207 can also be reduced, thereby reducing the production cost.

[0189] Exemplarily, the ratio H42 / H4 of the total thickness H42 of the third passivation layer 206 and the anti-reflection layer 207 at the second position 130b on the side 130 to the total thickness H4 of the third passivation layer 206 and the anti-reflection layer 207 on the light receiving surface 110 can be set to any number such as 0.5, 0.55, 0.6, 0.65, 0.7, 0.75, 0.8, or a range between any two values.

[0190] It should be noted that the total thickness H4 of the third passivation layer 206 and the anti-reflection layer 207 on the light-receiving surface 110 of the silicon substrate 100 refers to the total thickness of the third passivation layer 206 and the anti-reflection layer 207 on the light-receiving surface 110 in a direction perpendicular to the light-receiving surface 110. The total thickness of the third passivation layer 206 and the anti-reflection layer 207 on the side surface 130 of the silicon substrate 100 refers to the total thickness of the third passivation layer 206 and the anti-reflection layer 207 on the side surface 130 in a direction perpendicular to the side surface 130.

[0191] Alternatively, if Figure 7 and Figure 8 As shown, Figure 7 and Figure 8 A schematic diagram of another structure at the edge of a solar cell is shown. The protective layer 200 further includes: a transparent conductive layer 208, which is disposed on the side of the anti-reflection layer 207 away from the side surface 130; a transparent conductive layer 208 is disposed in at least one of the first region 120a and the second region 120b, and the transparent conductive layer 208 is disposed on the side of the first conductive layer 202 and / or the second conductive layer 205 away from the backlight surface 120.

[0192] In the embodiment of the present application, a transparent conductive layer 208 is provided on both the backlight surface 120 and the side surface 130 of the silicon substrate 100 so as to meet the structural design requirements of the backlight surface 120 of the silicon substrate 100 and, at the same time, form a corresponding transparent conductive layer 208 on the side surface 130 of the silicon substrate 100, thereby further enhancing the shielding and protection effect on the side surface 130 of the silicon substrate 100.

[0193] The transparent conductive layer 208 on the backlight surface 120 and the side surface 130 of the silicon substrate 100 can be prepared by the same process. For example, the transparent conductive layer 208 can be deposited on the backlight surface 120 and the side surface 130 of the silicon substrate 100 by using the PECVD process. Of course, the transparent conductive layer 208 can also be prepared by other processing techniques, which is not limited in the embodiment of the present application.

[0194] Exemplarily, the transparent conductive layer 208 can be made of materials such as indium tin oxide, conductive polymer, fluorine-doped tin dioxide, aluminum-doped zinc oxide, etc., or other types of transparent conductive materials. It can be flexibly selected according to actual needs, and the embodiments of the present application are not limited to this.

[0195] Alternatively, if Figure 6 As shown, the thickness of the transparent conductive layer 208 at the backlight surface 120 is H5, the thickness of the transparent conductive layer 208 at the first position 130a on the side 130 is H51, and the thickness of the transparent conductive layer 208 at the second position 130b on the side 130 is H52, satisfying: H52<H51≤H5.

[0196] In the embodiment of the present application, the thickness of the transparent conductive layer 208 located on the side surface 130 of the silicon substrate 100 is set to be less than or equal to the thickness of the transparent conductive layer 208 located on the backlight surface 120 of the silicon substrate 100, so that the transparent conductive layer 208 can be used to shield and protect the side surface 130 of the silicon substrate 100 without affecting the conversion efficiency of the battery. In addition, the transparent conductive layer 208 on the side surface 130 of the silicon substrate 100 is set to have a thickness H51 at the first position 130a greater than the thickness H52 at the second position 130b, thereby strengthening the protection of the side surface 130 of the silicon substrate 100 close to the backlight surface 120. At the same time, the transparent conductive layer 208 forms a smooth transition in size at the junction area between the edge of the backlight surface 120 and the side surface 130, so as to enhance the protection of the edge of the silicon substrate 100.

[0197] Optionally, the thickness H51 of the transparent conductive layer 208 at the first position 130a on the side surface 130 and the thickness H52 of the transparent conductive layer 208 at the second position 130b on the side surface 130 satisfy: 0.3≤H52 / H51<1. By setting the ratio H52 / H51, the transparent conductive layer 208 can be used to shield and protect the side surface 130 of the silicon substrate 100, and at the same time, it is convenient for actual processing and forming.

[0198] Specifically, a ratio H52 / H51 of the thickness H51 of the transparent conductive layer 208 on the side 130 at the second position 130b to that at the first position 130a can be set to any number such as 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, 0.95, or a range between any two values.

[0199] Alternatively, if Figure 6 As shown, the thickness H5 of the transparent conductive layer 208 on the backlight surface 120 and the thickness H51 of the transparent conductive layer 208 located at the first position 130 a on the side surface 130 satisfy: 0.5≤H51 / H5≤1.

[0200] In the embodiment of the present application, by setting a reasonable value range of the ratio H51 / H5 of the thickness H51 of the transparent conductive layer 208 at the first position 130a on the side surface 130 of the silicon substrate 100 and the thickness H5 of the transparent conductive layer 208 on the backlight surface 120 of the silicon substrate 100, the structure of the transparent conductive layer 208 on the side surface 130 of the silicon substrate 100 can be reasonably set according to the structure of the transparent conductive layer 208 on the backlight surface 120 of the silicon substrate 100. In addition, the transparent conductive layer 208 can be used to further shield and protect the side surface 130 of the silicon substrate 100, and the material loss of the transparent conductive layer 208 can be reduced, thereby reducing the production cost.

[0201] Exemplarily, the ratio H51 / H5 of the thickness H51 of the transparent conductive layer 208 at the first position 130a on the side 130 to the thickness H5 of the transparent conductive layer 208 on the backlight surface 120 can be set to any number such as 0.5, 0.55, 0.6, 0.65, 0.7, 0.75, 0.8, 0.85, 0.9, 0.95, 1, or a range between any two values.

[0202] Alternatively, if Figure 6 As shown, the thickness H5 of the transparent conductive layer 208 on the backlight surface 120 and the thickness H52 of the transparent conductive layer 208 located at the second position 130 b on the side surface 130 satisfy: 0.2≤H52 / H5≤0.5.

[0203] In the embodiment of the present application, by setting a reasonable value range of the ratio H52 / H5 of the thickness H52 of the transparent conductive layer 208 at the second position 130b on the side surface 130 of the silicon substrate 100 and the thickness H5 of the transparent conductive layer 208 on the backlight surface 120 of the silicon substrate 100, the structure of the transparent conductive layer 208 on the side surface 130 of the silicon substrate 100 can be reasonably set according to the structure of the transparent conductive layer 208 on the backlight surface 120 of the silicon substrate 100. In addition, the transparent conductive layer 208 can be used to shield and protect the side surface 130 of the silicon substrate 100, and the material loss of the transparent conductive layer 208 can be reduced, thereby reducing the production cost.

[0204] Exemplarily, the ratio H52 / H5 of the thickness H52 of the transparent conductive layer 208 at the second position 130b on the side 130 to the thickness H5 of the transparent conductive layer 208 on the backlight surface 120 can be set to any number such as 0.2, 0.25, 0.3, 0.35, 0.4, 0.45, 0.5, or a range between any two values.

[0205] In some embodiments, electrodes are respectively disposed in the first region and the second region on the backlight surface 120 of the silicon substrate 100 . The specific structure of the electrodes can be found in the related art, and the embodiments of the present application will not be described in detail here.

[0206] In some embodiments, the preparation process of the solar cell in the embodiment of the present application includes:

[0207] Step 1: Polishing and cleaning the silicon substrate 100, the silicon substrate 100 comprises a light receiving surface 110, a backlight surface 120, and a side surface 130 disposed between the light receiving surface 110 and the backlight surface 120, wherein the backlight surface 120 has first areas 120a and second areas 120b alternately disposed.

[0208] Step 2: Deposit the first passivation layer 201, the first conductive layer 202 and the insulating layer 203 on the entire surface of the backlight surface 120 and the side surface 130 of the silicon substrate 100 in sequence. The thickness of the first passivation layer 201 is in the range of 4-200 nm, the thickness of the first conductive layer 202 is in the range of 4-300 nm, and the thickness of the insulating layer 203 is in the range of 30-300 nm. The deposition method can be PECVD, LPCVD and other processes, which are not limited here.

[0209] Step 3: Use laser to remove the insulating layer 203 in the second area 120b of the backlight surface 120 of the silicon substrate 100 to form an opening. The wavelength of the laser used can be 355nm, 532nm, 1064nm, etc.

[0210] Step 4: Use an alkaline solution to perform etching to remove the first passivation layer 201 and the first conductive layer 202 at the opening, exposing the silicon substrate 100 in the second region 120b; at the same time, the silicon substrate 100 at the opening and the light-receiving surface 110 of the silicon substrate 100 are textured and cleaned. The alkaline etching solution used can be an alkaline solution such as NaOH and KOH.

[0211] Step 5: Deposit the second passivation layer 204 and the second conductive layer 205 on the entire surface and the side surface 130 of the backlight surface 120 of the silicon substrate 100 in sequence. The thickness of the second passivation layer 204 is in the range of 4-200 nm, and the thickness of the second conductive layer 205 is in the range of 5-300 nm. The deposition method can be PECVD, LPCVD and other processes, which are not limited here.

[0212] Step 6: Use laser to remove the second passivation layer 204 and the second conductive layer 205 covering the first region 120a. The laser wavelength used may be 355nm, 532nm, 1064nm, etc.

[0213] Step 7: Etch the insulating layer 203 in the first region 120a using a wet process.

[0214] Step 8: Deposit the third passivation layer 206 and the anti-reflection layer 207 on the light-receiving surface 110 and the side surface 130 of the silicon substrate 100 in sequence. The thickness of the third passivation layer 206 is in the range of 4-200 nm, and the thickness of the anti-reflection layer 207 is in the range of 5-300 nm. The deposition method may be PECVD, LPCVD or other processes, which are not limited here.

[0215] Step 9: Deposit a transparent conductive layer in the first area 120a and the second area 120b of the backlight surface 120 of the silicon substrate 100. The thickness of the transparent conductive layer is in the range of 10-300nm, and the deposition method can be PVD, RPD process, etc.

[0216] Step 10: Prepare metal electrodes in the first region 120a and the second region 120b using a screen printing process.

[0217] In other examples, referring to the above-mentioned preparation process, the process parameters in the preparation process are adjusted to control the thickness of the film structure deposited on the side 130 of the silicon substrate 100, thereby preparing solar cells with different structures, and performing performance tests such as open circuit voltage, short circuit current and conversion efficiency on the corresponding solar cells.

[0218] Among them, in Comparative Example 1, only the film layer structure is deposited on the backlight surface 120 and the light-receiving surface 110 of the silicon substrate 100, and the coating layer existing on the side surface 130 of the silicon substrate 100 is removed during the preparation process to expose the side surface 130 of the silicon substrate 100. In Examples 1 to 3, and Comparative Examples 2 to 4, while the film layer is formed on the backlight surface 120 and the light-receiving surface 110 of the silicon substrate 100, a corresponding film layer structure is formed on the side surface 130 of the silicon substrate 100, and the difference is that the total thickness of the film layer structure formed on the side surface 130 of the silicon substrate 100 is different.

[0219] In addition, for the convenience of comparative analysis, the performance data results of comparative example 1 are used as a benchmark to convert the test data of other groups into proportional values. The specific test results are shown in Table 1 below:

[0220] Table 1

[0221] Group D1(nm) D2(nm) D1 / D2 Conversion efficiency Open circuit voltage Short circuit current Comparative Example 1 0 0 0 1 1 1 Comparative Example 2 600 40 15 0.9998 0.9997 0.9999 Comparative Example 3 600 30 20 0.9996 0.9995 0.9999 Comparative Example 4 600 20 30 0.9995 0.9994 0.9996 Example 1 600 240 2.5 1.001 1.001 1.001 Example 2 600 120 5 1.001 1.0009 1.0008 Example 3 600 60 10 1.0009 1.0009 1.0006

[0222] It can be seen from the test data in Table 1 that, compared with directly exposing the side 130 of the silicon substrate 100 to the outside, by forming a corresponding film layer structure on the side 130 of the silicon substrate 100, a shielding and protective effect can be formed on the side 130 of the silicon substrate 100, thereby avoiding the risk of damage and leakage of the side 130 of the silicon substrate 100. When the film layer structure is formed on the side 130, by reasonably setting the thickness of the film layer structure on the side 130 of the silicon substrate 100, a passivation effect can be achieved on the side 130 of the silicon substrate 100, thereby reducing the recombination of carriers on the side 130 and improving the performance of the solar cell.

[0223] Furthermore, by controlling the thickness D1 of the film structure on the side 130 of the silicon substrate 100 at the first position 130a (i.e., the side close to the backlight surface 120) and the thickness D2 at the second position 130b (i.e., the side close to the light-receiving surface 110) within a certain range, the side 130 of the silicon substrate 100 is passivated and protected, thereby reducing the recombination of carriers on the side 130. Since the thickness of the protective layer 200 on the side 130 generally does not exceed the sum of the thickness of the film layer on the backlight surface 120 and the film layer on the light-receiving surface 110, that is, the thickness of the protective layer 200 on the side 130 is within a relatively fixed range, if the ratio of D1 / D2 is too large, the value of D1 is too small, and it is difficult to form a reliable shielding protection for the part of the side 130 of the silicon substrate 100 close to the light-receiving surface 110, and the passivation effect of the part of the side 130 close to the light-receiving surface 110 is poor, which reduces the overall performance of the solar cell.

[0224] To this end, in the embodiment of the present application, the ratio range of the thickness D1 of the protective layer 200 at the first position 130a and the thickness D2 at the second position 130b is set to be: 1<D1 / D2≤10. In this way, not only can the protection of the side 130 of the silicon substrate 100 be improved, but also the performance of the solar cell can be appropriately improved.

[0225] Combine the following Figures 8 to 14 , the structure of solar cells of other embodiments of the first aspect of the present application are described in detail.

[0226] exist Figures 8 to 14 In the solar cell shown, the solar cell is a back contact cell; the first conductive layer 202 is a first doped silicon layer 12 , the second conductive layer 205 is a second doped silicon layer 16 , and the insulating layer 203 includes a surface passivation layer 13 and an anti-reflection layer 207 .

[0227] like Figure 8As shown, the back contact cell provided by the embodiment of the present application includes: a silicon substrate 100, a first interface passivation layer 20, a first doped silicon layer 12, a surface passivation layer 13, an anti-reflection layer 207, an intrinsic silicon layer 15, a second doped silicon layer 16 and a transparent conductive layer 208. The silicon substrate 100 includes a backlight surface and a light-receiving surface arranged opposite to each other, and a side surface connecting the backlight surface and the light-receiving surface. In the direction away from the side surface, the first interface passivation layer 20, the first doped silicon layer 12, the surface passivation layer 13, the anti-reflection layer 207, the intrinsic silicon layer 15, the second doped silicon layer 16 and the transparent conductive layer 208 are sequentially arranged on the side surface. The first doped silicon layer 12 and the second doped silicon layer 16 have opposite conductivity types. Among them, along the thickness direction of the silicon substrate 100, the surface passivation layer 13 and the anti-reflection layer 207 are also sequentially arranged on the light-receiving surface, and the surface passivation layer 13 and the anti-reflection layer 207 extend from the light-receiving surface to the side surface.

[0228] It can be understood that in this section, the first interface passivation layer 20 can also be referred to as the aforementioned first passivation layer 201, the intrinsic silicon layer 15 can also be referred to as the aforementioned second passivation layer 204, and “along the direction away from the side” is also “along the direction away from the silicon substrate”.

[0229] When the above technical solution is adopted, Figure 8As shown, on the side of the silicon substrate 100, and in the direction away from the side, a first interface passivation layer 20, a first doped silicon layer 12, a surface passivation layer 13, an anti-reflection layer 207, an intrinsic silicon layer 15, a second doped silicon layer 16 and a transparent conductive layer 208 are sequentially arranged. The presence of each film layer can isolate the side of the silicon substrate 100 from the external environment, reducing the risk of scratches and other damage to the side of the silicon substrate 100 due to extrusion, collision and other factors after transportation or packaging. At the same time, it can also reduce the risk of water vapor and the like entering the battery from the side of the battery and causing the battery to fail, thereby increasing the service life of the back contact battery. In addition, the surface passivation layer 13 and the anti-reflection layer 207 are not only located on the light-receiving surface of the silicon substrate 100, but also extend to the side of the silicon substrate 100. At this time, on the side of the silicon substrate 100, the first doped silicon layer 12 and the second doped silicon layer 16 of opposite conductivity types can be separated by the surface passivation layer 13 and the anti-reflection layer 207 to prevent the two from conducting and leaking electricity, reduce the forward leakage loss, and make the back contact battery have a higher conversion efficiency. In addition, the surface passivation layer 13 and the anti-reflection layer 207 are arranged on the light-receiving surface to reduce carrier recombination and surface reflectivity. Then, the two are extended to the side of the silicon substrate 100, and can also be used to separate the first doped silicon layer 12 and the second doped silicon layer 16. There is no need to form other insulating layers through other deposition steps to prevent leakage between the first doped silicon layer 12 and the second doped silicon layer 16, which can simplify the manufacturing process of the back contact battery. At the same time, there is no need to consider the compatibility between the film layer that separates the first doped silicon layer 12 and the second doped silicon layer 16 and other structures in the back contact battery, ensuring that the back contact battery has a higher yield. At the same time, not only the first interface passivation layer 20 and the first doped silicon layer 12 arranged on the side of the silicon substrate 100 have a passivation effect on the silicon substrate 100, but the surface passivation layer 13 that realizes the insulation isolation of the first doped silicon layer 12 and the second doped silicon layer 16 on the side can also passivate the side of the silicon substrate 100, further reducing the carrier recombination rate on the side of the silicon substrate 100 and improving the conversion efficiency of the back contact battery.

[0230] In addition, it is worth noting that in the actual manufacturing process, the order in which the corresponding film layers are formed on the backlight side and the light-receiving side of the silicon substrate affects the order in which the corresponding film layers are formed on the side of the silicon substrate. Since the order in which the film layers are formed on the backlight side and the light-receiving side of the silicon substrate is closely related to the process, battery structure, equipment, etc., the order in which the film layers are formed on the backlight side and the light-receiving side of the silicon substrate cannot be adjusted arbitrarily, that is to say, the order in which the film layers are formed on the side of the silicon substrate cannot be adjusted arbitrarily, and needs to be comprehensively considered based on the requirements for the order in which the film layers are formed on the side of the silicon substrate, the technical problems to be solved, as well as the requirements for the order in which the film layers are formed on the front and back sides, and the technical problems to be solved.

[0231] In actual application, the present embodiment does not specifically limit the conductivity type of the silicon substrate. The conductivity type of the silicon substrate can be N-type, P-type, or intrinsic type.

[0232] In the above case, if Figure 8 As shown, the back contact cell includes a first interface passivation layer 20, a first doped silicon layer 12, an intrinsic silicon layer 15, a second doped silicon layer 16 and a transparent conductive layer 208 which are not only arranged on the side of the silicon substrate 100, but also arranged on the backlight side of the silicon substrate 100. Specifically, on the backlight side of the silicon substrate 100, the transparent conductive layer 208 covers the first doped silicon layer 12 and the second doped silicon layer 16 on the side away from the silicon substrate 100, and a through isolation groove is arranged in the transparent conductive layer 208 to disconnect the part of the transparent conductive layer 208 corresponding to the first doped silicon layer 12 from the part of the transparent conductive layer 208 corresponding to the second doped silicon layer 16 to prevent short circuit. As for the distribution of the first interface passivation layer 20, the first doped silicon layer 12, the intrinsic silicon layer 15 and the second doped silicon layer 16 on the backlight side of the silicon substrate 100, it can be set according to actual needs and is not specifically limited here.

[0233] For example, the backlight surface may include a first region and a second region that do not overlap each other, the first interface passivation layer and the first doped silicon layer are arranged on the first region, and the intrinsic silicon layer and the second doped silicon layer are sequentially stacked on the second region in a direction away from the silicon substrate. In this case, the distribution range of the first region and the second region on the backlight surface can be determined according to the distribution of the first doped silicon layer and the second doped silicon layer on the backlight surface in an actual application scenario.

[0234] Exemplarily, the backlight surface may include a first region and a second region that are spaced apart, and a third region between the first region and the second region. The first interface passivation layer and the first doped silicon layer are disposed on the first region, and the intrinsic silicon layer and the second doped silicon layer are sequentially stacked on the second region in a direction away from the silicon substrate. In this case, the distribution range of the first region and the second region on the backlight surface may be determined according to the distribution of the first doped silicon layer and the second doped silicon layer on the backlight surface in an actual application scenario. The third region is a region on the backlight surface where the first doped silicon layer and the second doped silicon layer are not disposed.

[0235] For example, Figure 8As shown, the backlight surface includes a first region 120a and a second region 120b that are spaced apart. The first interface passivation layer 20 and the first doped silicon layer 12 are arranged on the first region 120a. The intrinsic silicon layer 15 and the second doped silicon layer 16 are arranged in the second region 120b, and extend from the second region 120b to the first region 120a, and cover a portion of the first interface passivation layer 20 and the first doped silicon layer 12. In this case, on the backlight surface of the silicon substrate 100, the intrinsic silicon layer 15 and the second doped silicon layer 16 are not only stacked in sequence in the second region 120b along the thickness direction of the silicon substrate 100, but also cover a portion of the first interface passivation layer 20 and the first doped silicon layer 12. At this time, the formation range of the intrinsic silicon layer 15 and the second doped silicon layer 16 on the backlight side of the silicon substrate 100 is relatively large, which is conducive to reducing the etching range of the entire layer of the intrinsic silicon layer 15 and the second doped silicon layer 16 during the manufacturing process, and is conducive to improving the etching capacity. Moreover, the portion where the intrinsic silicon layer 15 and the second doped silicon layer 16 cover the first doped silicon layer 12 can protect the edge of the first doped silicon layer 12, prevent the etchant from affecting the edge of the first doped silicon layer 12, and ensure that the edge of the first doped silicon layer 12 has a higher carrier collection efficiency. In addition, no isolation groove is provided between the first interface passivation layer 20, the first doped silicon layer, the second interface passivation layer, and the second doped silicon layer, so the contact area between the first interface passivation layer, the first doped silicon layer 12 and the silicon substrate 100, and the contact area between the intrinsic silicon layer 15, the second doped silicon layer 16 and the silicon substrate 100 can be maximized, thereby improving the utilization rate of the silicon substrate 100, and further improving the photoelectric conversion efficiency. Specifically, in this case, the distribution range of the first region 120a on the backlight surface can be determined according to the distribution of the first doped silicon layer 12 on the backlight surface in the actual application scenario. The distribution range of the second region 120 b on the backlight surface may be determined according to the distribution of the portion of the second doped silicon layer 16 that does not overlap the first doped silicon layer 12 in an actual application scenario.

[0236] As for the surface morphology of the silicon substrate, the light-receiving surface of the silicon substrate can be a polished surface or a velvet surface. Among them, when the light-receiving surface of the silicon substrate is a velvet surface, it can improve its own light-trapping effect and further improve the conversion efficiency of the back-contact battery. Secondly, the backlight surface of the silicon substrate can be a polished surface; or, in the backlight surface of the silicon substrate, the surface of the area corresponding to the first interface passivation layer and the first doped silicon layer can be a polished surface, and the surface in contact with the intrinsic silicon layer and the second doped silicon layer can be a velvet surface. At this time, after at least removing the first interface passivation layer and the first doped silicon layer covering the area corresponding to the intrinsic silicon layer and the second doped silicon layer in the backlight surface, the light-receiving surface is subjected to a velvet treatment, and the surface of the area corresponding to the intrinsic silicon layer and the second doped silicon layer in the backlight surface is also subjected to a velvet treatment, so as to increase the contact area between the second doped silicon layer and the transparent conductive layer and reduce the contact loss between the two.

[0237] In addition, the side morphology of the silicon substrate can be determined according to the formation range of the first interface passivation layer and the first doped silicon layer on the side of the silicon substrate and the actual manufacturing process, and is not specifically limited here. Figure 8 As shown, the first interface passivation layer 20 and the first doped silicon layer 12 disposed on the side cover the entire area of ​​the side. Fig. 9 As shown, the first interface passivation layer 20 and the first doped silicon layer 12 disposed on the side may be located on a local area of ​​the side and close to the backlight surface; in this case, it can be understood that in the actual manufacturing process, when the first doped silicon layer 12 is formed on the backlight surface and the side of the silicon substrate 100, the first doped silicon layer 12 may be plated on the light-receiving surface. The first doped silicon layer 12 located on the light-receiving surface has parasitic absorption and needs to be removed to improve the utilization rate of light by the silicon substrate. Based on this, when the first interface passivation layer 20 and the first doped silicon layer 12 disposed on the side are located on a local area of ​​the side, there is no need to strictly control the manufacturing conditions in order to retain all the first doped silicon layer 12 formed on the side in the process of removing the first interface passivation layer 20 and the first doped silicon layer 12 plated on the light-receiving surface, thereby reducing the manufacturing difficulty of the back contact battery.

[0238] Among them, Figure 8 As shown, when the first interface passivation layer 20 and the first doped silicon layer 12 disposed on the side cover the entire area of ​​the side, the surface reflectivity and / or surface morphology of each partial area of ​​the side of the silicon substrate 100 can be substantially the same. At this time, the surface of each area of ​​the side of the silicon substrate 100 can be a polished surface, or can be a suede surface or the like.

[0239] For example, Fig.10 As shown, when the first interface passivation layer 20 and the first doped silicon layer 12 disposed on the side are located on a local area of ​​the side and close to the backlight surface, the surface reflectivity of the area on the side that is not covered with the first doped silicon layer 12 can be less than the surface reflectivity of the area on the side that is covered with the first interface passivation layer 20 and the first doped silicon layer 12. At this time, although the passivation effect of the surface of the area on the side of the silicon substrate 100 that is not covered with the first interface passivation layer 20 and the first doped silicon layer 12 is relatively low, the surface of this area has a relatively high light trapping effect, which is conducive to refracting more light from the side of the side of the silicon substrate 100 close to the light-receiving surface into the silicon substrate 100, which is conducive to improving the conversion efficiency of the back contact cell.

[0240] Among them, when the surface reflectivity of the area on the side not covered by the first interface passivation layer and the first doped silicon layer is less than the surface reflectivity of the area on the side covered with the first interface passivation layer and the first doped silicon layer, the surface morphology of the area on the side not covered by the first interface passivation layer and the first doped silicon layer can be the same as the surface morphology of the area on the side covered with the first interface passivation layer and the first doped silicon layer, while the size of the texture structure on the surface of the area on the side not covered by the first interface passivation layer and the first doped silicon layer is different from the size of the texture structure on the surface of the area on the side covered with the first interface passivation layer and the first doped silicon layer.

[0241] For example: the surface of the area on the side that is not covered by the first interface passivation layer and the first doped silicon layer and the surface of the area on the side that is covered by the first interface passivation layer and the first doped silicon layer can both have a tower-like texture structure, and the side length of the tower-like texture structure on the surface of the area on the side that is not covered by the first interface passivation layer and the first doped silicon layer is smaller than the side length of the tower-like texture structure on the surface of the area on the side that is covered by the first interface passivation layer and the first doped silicon layer, and / or the height of the tower-like texture structure on the surface of the area on the side that is not covered by the first interface passivation layer and the first doped silicon layer is greater than the height of the tower-like texture structure on the surface of the area on the side that is covered by the first interface passivation layer and the first doped silicon layer.

[0242] For another example: the surface of the area on the side not covered by the first interface passivation layer and the first doped silicon layer and the surface of the area on the side covered by the first interface passivation layer and the first doped silicon layer may both have a pyramid-shaped texture structure, and the side length (or diagonal, height) of the bottom of the pyramid-shaped texture structure on the surface of the area on the side not covered by the first interface passivation layer and the first doped silicon layer is greater than the side length (or diagonal, height) of the pyramid-shaped texture structure on the surface of the area on the side covered by the first interface passivation layer and the first doped silicon layer.

[0243] Alternatively, when the surface reflectivity of the area on the side surface not covered with the first interface passivation layer and the first doped silicon layer is less than the surface reflectivity of the area on the side surface covered with the first interface passivation layer and the first doped silicon layer, the surface morphology of the area on the side surface not covered with the first interface passivation layer and the first doped silicon layer may also be different from the surface morphology of the area on the side surface covered with the first interface passivation layer and the first doped silicon layer. In this case, the surface morphologies of the two areas on the side surface may be determined based on the reflectivity relationship and the actual manufacturing process, and are not specifically limited here.

[0244] For example, Fig.10As shown, the surface of the area on the side that is not covered by the first interface passivation layer 20 and the first doped silicon layer 12 can be a velvet surface. In this case, the surface of the area on the side that is not covered by the first interface passivation layer 20 and the first doped silicon layer 12 has a relatively high light trapping effect, which is conducive to refracting more light from the side of the side of the silicon substrate 100 close to the light receiving surface into the silicon substrate 100, which is conducive to improving the conversion efficiency of the back contact cell.

[0245] For example, Fig.10 As shown, the surface of the area covered with the first interface passivation layer 20 and the first doped silicon layer 12 in the side surface is a polished surface. In this case, the surface of the area covered with the first interface passivation layer 20 and the first doped silicon layer 12 in the side surface is relatively flat, which is conducive to forming a thicker first interface passivation layer 20 and the first doped silicon layer 12 in the area, enhancing the passivation effect of the first interface passivation layer 20 and the first doped silicon layer 12 on the corresponding area of ​​the side surface, and further improving the conversion efficiency of the back contact battery.

[0246] For the first doped silicon layer, from the aspect of the arrangement of the material, the crystal phase of the first doped silicon layer can be amorphous, microcrystalline, nanocrystalline, single crystal or polycrystalline, etc. The specific crystal phase of the first doped silicon layer can be determined according to the type of the first interface passivation layer. Among them, the first interface passivation layer can be a tunneling passivation layer such as a tunneling oxide layer, in which case the first doped silicon layer is a doped crystalline silicon layer, and the material of the doped crystalline silicon layer may include polycrystalline silicon and / or single crystal silicon. Alternatively, the first interface passivation layer may also be an intrinsic silicon passivation layer such as intrinsic amorphous silicon, in which case the materials of the first interface passivation layer and the first doped silicon layer may include at least one of amorphous silicon, nanocrystalline silicon and microcrystalline silicon.

[0247] It is worth noting that when the first interface passivation layer is a tunneling passivation layer and the first doped silicon layer is a doped crystalline silicon layer, the first interface passivation layer has a higher film density, which further enhances its passivation effect on the silicon substrate, thereby further reducing the surface defects of the silicon substrate and improving the conversion efficiency of the back contact battery.

[0248] In terms of thickness, Figure 8 As shown, the thickness of each part of the first doped silicon layer 12 can be the same; Fig. 9 As shown, or the thickness of the first doped silicon layer 12 disposed on the backlight side may be greater than the thickness of the first doped silicon layer 12 disposed on the side. When the thickness of each part of the first doped silicon layer 12 is the same, it is beneficial for each part of the first doped silicon layer 12 to have a higher passivation effect, so that each region corresponding to the first doped silicon layer 12 in the silicon substrate 100 has a relatively low carrier recombination rate, further improving the conversion efficiency of the back contact battery.

[0249] As for the specific thickness of the first doped silicon layer, it can be determined according to actual needs and the material of the first doped silicon layer, and no specific limitation is made here. For example, the thickness of the first doped silicon layer can be greater than or equal to 30nm and less than or equal to 140nm. For example: the thickness of the first doped silicon layer can be 30nm, 40nm, 50nm, 60nm, 80nm, 100nm, 120nm, 130nm or 140nm, etc. In this way, the presence of the transparent conductive layer can improve the collection efficiency of carriers and leave a margin for thinning the first doped silicon layer. In other words, without reducing the carrier collection efficiency, the thickness of the first doped silicon layer can be appropriately reduced due to the presence of the transparent conductive layer. Based on this, when the thickness of the first doped silicon layer is within the above range, the thickness of the first doped silicon layer is small, which is conducive to reducing its own parasitic absorption and further improving the working efficiency of the back contact battery; and the deposition time of the first doped silicon layer can also be reduced to improve the production efficiency of the first doped silicon layer. In addition, the thickness of the first doped silicon layer cannot be too small to avoid affecting the collection of carriers.

[0250] For the first interface passivation layer, Figure 8 As shown, the thickness of each part of the first interface passivation layer 20 can be the same; or, the thickness of the first interface passivation layer arranged on the backlight side can be greater than the thickness of the first interface passivation layer arranged on the side. When the thickness of each part of the first interface passivation layer is the same, it is beneficial for each part of the first interface passivation layer 20 to have a higher passivation effect, so that each area corresponding to the first interface passivation layer 20 in the silicon substrate 100 has a relatively low carrier recombination rate, further improving the conversion efficiency of the back contact battery.

[0251] As for the specific thickness of the first interface passivation layer, it can be determined according to actual needs and the material of the first interface passivation layer, and is not specifically limited here.

[0252] In addition, in the side of the silicon substrate, when the surface of the region where the first interface passivation layer and the first doped silicon layer are provided has a tower-like texture structure, the thickness of the first interface passivation layer located at the bottom surface of the tower-like texture structure can be equal to the thickness of the first interface passivation layer located on the side wall of the tower-like texture structure. In this case, the first interface passivation layer has a high passivation effect on both the bottom surface and the side wall of the tower-like texture structure.

[0253] Alternatively, the thickness of the first interface passivation layer located on the bottom surface of the tower-shaped texture structure may also be less than the thickness of the first interface passivation layer located on the side wall of the tower-shaped texture structure. In this case, it can be understood that the bottom surface of the tower-shaped texture structure and the side surface of the tower-shaped texture structure have different crystal orientations. Specifically, the bottom surface of the tower-shaped texture structure is the

[110] crystal orientation, and the number of dangling bonds on the surface of the

[110] crystal orientation is relatively small; while the side surface of the tower-shaped texture structure is the

[111] crystal orientation, and the number of dangling bonds in the

[111] crystal orientation is relatively large. Based on this, when the thickness of the first interface passivation layer located on the bottom surface of the tower-shaped texture structure is less than the thickness of the first interface passivation layer located on the side wall of the tower-shaped texture structure, it is beneficial to make the thickness of the first interface passivation layer located on the side wall of the tower-shaped texture structure have a relatively high passivation effect, meet the demand for high passivation effect on the side surface of the tower-shaped texture structure, reduce the carrier recombination rate on the side surface of the tower-shaped texture structure, and further improve the working efficiency of the back contact battery.

[0254] The thickness of the first interface passivation layer at the bottom surface of the tower-shaped texture structure and the thickness of the first interface passivation layer on the side wall of the tower-shaped texture structure can be determined according to the requirements for the passivation effect of different areas of the tower-shaped texture structure and the actual manufacturing process, and are not specifically limited here.

[0255] Exemplarily, the thickness of the first interface passivation layer located at the bottom surface of the tower base-shaped texture structure can be greater than or equal to 0.5nm and less than or equal to 1.5nm. For example: the thickness of the first interface passivation layer located at the bottom surface of the tower base-shaped texture structure can be 0.5nm, 0.6nm, 0.8nm, 1nm, 1.2nm, 1.3nm or 1.5nm, etc. In this case, the thickness of the first interface passivation layer located at the bottom surface of the tower base-shaped texture structure is within the above range, which is beneficial to prevent the first interface passivation layer from being located at the bottom surface of the tower base-shaped texture structure. The thickness is small and the passivation effect of the part on the silicon substrate is relatively low, while reducing the carrier recombination rate on the side of the tower base-shaped texture structure.

[0256] Exemplarily, the thickness of the first interface passivation layer on the side wall of the tower-shaped texture structure can be greater than or equal to 0.5nm and less than or equal to 2nm. For example, the thickness of the first interface passivation layer on the side wall of the tower-shaped texture structure can be 0.5nm, 0.8nm, 1nm, 1.2nm, 1.5nm, 1.8nm or 2nm. In this case, the thickness of the first interface passivation layer on the side wall of the tower-shaped texture structure is within the above range, which is conducive to preventing the passivation effect of the first interface passivation layer from being low due to the small thickness of the part, and reducing the carrier recombination rate on the side of the tower-shaped texture structure.

[0257] As for the formation range of the first interface passivation layer and the first doped silicon layer on the side of the silicon substrate, as mentioned above, the first interface passivation layer and the first doped silicon layer disposed on the side may cover the entire area of ​​the side. Alternatively, the first interface passivation layer and the first doped silicon layer disposed on the side may also be located only on a local area of ​​the side and close to the backlight surface; in this case, the extension range of the first interface passivation layer and the first doped silicon layer on the side may be set according to the actual manufacturing process and actual needs, and is not specifically limited here.

[0258] For example, Fig.10 As shown, along the thickness direction of the silicon substrate 100, the ratio between the maximum extension length of the first interface passivation layer 20 and the first doped silicon layer 12 on the side and the thickness of the silicon substrate 100 can be greater than or equal to 70%. For example, the ratio between the maximum extension length of the first interface passivation layer 20 and the first doped silicon layer 12 on the side and the thickness of the silicon substrate 100 can be 70%, 75%, 80%, 85%, 90%, 95% or 98%, etc. In this case, as described above, the first interface passivation layer 20 and the first doped silicon layer 12 have a passivation effect on the side of the silicon substrate 100, so when the ratio between the maximum extension length of the first interface passivation layer 20 and the first doped silicon layer 12 on the side and the thickness of the silicon substrate 100 is greater than or equal to 70%, it is ensured that the first interface passivation layer 20 and the first doped silicon layer 12 have a larger formation range on the side of the silicon substrate 100, so that more areas of the surface in the side have a lower carrier recombination rate, further improving the conversion efficiency of the back contact battery. Furthermore, most of the side surfaces of the silicon substrate 100 are covered with the first interface passivation layer 20 and the first doped silicon layer 12. At this time, the first interface passivation layer 20 and the first doped silicon layer 12 have a protective effect on most of the side surfaces of the silicon substrate 100, and prevent the intrusion of water vapor and the like, thereby ensuring that the side surfaces of the silicon substrate 100 have a thicker laminated protection, thereby further improving the protective effect of the side surfaces of the silicon substrate 100.

[0259] Exemplarily, in the case where the first interface passivation layer and the first doped silicon layer disposed on the side are only located on a local area of ​​the side and close to the backlight surface, the surface of the area of ​​the side that is not covered by the first interface passivation layer and the first doped silicon layer is velvet, and the ratio between the maximum extension length of the velvet on the side and the thickness of the silicon substrate can be less than or equal to 30%. For example: the ratio between the maximum extension length of the velvet on the side and the thickness of the silicon substrate can be 1%, 5%, 10%, 15%, 20%, 25% or 30%, etc. The application principle of the beneficial effect in this case can refer to the application principle of the beneficial effect of the ratio between the maximum extension length of the first interface passivation layer and the first doped silicon layer on the side and the thickness of the silicon substrate being greater than or equal to 70% as described above, which will not be repeated here.

[0260] As for the surface passivation layer and the anti-reflection layer, the embodiments of the present application do not specifically limit the materials of the surface passivation layer and the anti-reflection layer, as long as they can be applied to the back contact battery provided in the embodiments of the present application.

[0261] Exemplarily, the material of the surface passivation layer may include at least one of aluminum oxide, intrinsic amorphous silicon, and doped silicon glass. Among them, the conductivity type of the doped silicon glass is the same as or opposite to the conductivity type of the first doped silicon layer. Specifically, the material of the surface passivation layer may include only aluminum oxide, intrinsic amorphous silicon, or doped silicon glass. Alternatively, the material of the surface passivation layer may include any two of aluminum oxide, intrinsic amorphous silicon, and doped silicon glass. Alternatively, the material of the surface passivation layer may also include aluminum oxide, intrinsic amorphous silicon, and doped silicon glass at the same time. Specifically, when the material of the surface passivation layer includes at least two types, the distribution between different materials can be determined according to actual needs and the actual manufacturing process, and is not specifically limited here. In this case, aluminum oxide and intrinsic amorphous silicon contain hydrogen. When the material of the surface passivation layer includes aluminum oxide and / or intrinsic amorphous silicon, the silicon substrate and the first doped silicon layer can be hydrogen passivated to further improve the passivation effect of the surface passivation layer. The doped silicon glass is doped with impurities of the corresponding conductive type, which can also perform field passivation on the silicon substrate and the first doped silicon layer, and can further improve the passivation effect of the surface passivation layer. Secondly, the manufacturing process of the surface passivation layer made of doped silicon glass is also relatively simple, which helps to reduce the difficulty of manufacturing back contact batteries.

[0262] By way of example, the material of the anti-reflection layer may include silicon nitride and / or silicon nitride oxide, etc.

[0263] As for the formation range of the surface passivation layer and the anti-reflection layer on the side of the silicon substrate, Figures 8 to 10 As shown, along the thickness direction of the silicon substrate 100, the surface passivation layer 13 and the anti-reflection layer 207 can cover various areas of the side surface of the silicon substrate 100, that is, cover the entire side surface. Fig.11As shown, the surface passivation layer 13 and the anti-reflection layer 207 arranged on the side surface may also be located on a local area of ​​the side surface and close to the light-receiving surface. In this case, it can be understood that in the actual manufacturing process, when the surface passivation layer 13 and the anti-reflection layer 207 are formed on the light-receiving surface and the side surface of the silicon substrate 100, in order to ensure that the surface passivation layer 13 and the anti-reflection layer 207 with a larger coverage area are formed on the side surface, the surface passivation layer 13 and the anti-reflection layer 207 may be plated around the backlight side. The surface passivation layer 13 and the anti-reflection layer 207 on the backlight side will affect the carrier collection effect of the intrinsic silicon layer 15 and the second doped silicon layer 16 formed later, so it is necessary to remove the surface passivation layer 13 and the anti-reflection layer 207 on the backlight side. Based on this, when the surface passivation layer 13 and the anti-reflection layer 207 arranged on the side are located on a local area of ​​the side, there is no need to strictly control the manufacturing conditions in order to retain all the surface passivation layer 13 and the anti-reflection layer 207 on the side during the process of removing the surface passivation layer 13 and the anti-reflection layer 207 plated on the backlight surface, thereby reducing the manufacturing difficulty of the back contact battery.

[0264] Specifically, it can be understood that the greater the extension length of the surface passivation layer and the anti-reflection layer on the side, the first doped silicon layer and the second doped silicon layer in the side of the silicon substrate can be isolated by forming a larger surface passivation layer and anti-reflection layer, and the forward leakage of the back contact battery is lower. At the same time, the surface passivation layer and the anti-reflection layer have the largest protection range for the side of the silicon substrate. The smaller the extension length of the surface passivation layer and the anti-reflection layer on the side, the larger the range of the reverse leakage area formed between the first doped silicon layer and the second doped silicon layer in the side of the silicon substrate, and the lower the hot spot risk of the back contact battery. Based on this, the extension range of the surface passivation layer and the anti-reflection layer on the side can be determined according to the forward leakage loss, side protection, hot spot risk of the back contact battery in the actual application scenario, and the actual manufacturing process, and is not specifically limited here.

[0265] Exemplarily, along the thickness direction of the silicon substrate, the ratio between the maximum extension length of the surface passivation layer and the anti-reflection layer on the side and the thickness of the silicon substrate can be less than or equal to 80%. For example: the ratio between the maximum extension length of the surface passivation layer and the anti-reflection layer on the side and the thickness of the silicon substrate can be 5%, 10%, 15%, 20%, 30%, 40%, 50%, 60%, 70% or 80%, etc. In this case, the difficulty of removing the surface passivation layer and the anti-reflection layer around the backlight surface can be reduced, and the manufacturing precision requirements can be reduced. In addition, in the area of ​​the side of the silicon substrate that is not covered with the surface passivation layer and the anti-reflection layer, the first doped silicon layer can be electrically contacted with the second doped silicon layer of the opposite conductivity type to itself through the intrinsic silicon layer, thereby forming a diode structure with a lower reverse breakdown voltage on the side of the silicon substrate, which is conducive to reducing the risk of hot spots of the back contact battery and improving the anti-burning ability of the back contact battery. In addition, according to the actual application scenario requirements of the back-contact battery, the forward leakage, hot spot risk and side protection of the back-contact battery can be regulated by adjusting the maximum extension length of the surface passivation layer and the anti-reflection layer on the side, which is conducive to achieving a balance between the forward leakage, hot spot risk and side protection of the back-contact battery.

[0266] As for the thickness of the surface passivation layer and the anti-reflection layer, the thickness of the surface passivation layer and / or the anti-reflection layer on the light-receiving side of the silicon substrate can be roughly the same, so that each area on the light-receiving side of the silicon substrate corresponds to a higher passivation effect, and it is beneficial for each area on the light-receiving side of the back contact cell to have a relatively low reflectivity, thereby further improving the conversion efficiency of the back contact cell.

[0267] As for the thickness of the surface passivation layer and the anti-reflection layer on the side of the silicon substrate, the thickness of the surface passivation layer and / or the anti-reflection layer on each part of the side of the silicon substrate can be the same. In this case, within a certain range, the thickness of the surface passivation layer is proportional to its own passivation effect and insulation isolation effect. Based on this, when the thickness of the surface passivation layer is equal on the side of the silicon substrate, each part of the surface passivation layer has a higher passivation effect and a higher insulation isolation characteristic, which is conducive to making each area covered with the surface passivation layer on the side of the silicon substrate have a lower number of surface defects, and is also conducive to better realizing the electrical isolation effect of the first doped silicon layer and the second doped silicon layer through the surface passivation layer with uniform thickness, reducing forward leakage. Secondly, when the thickness of the anti-reflection layer on each part of the side of the silicon substrate is the same, it is conducive to making each part of the anti-reflection layer in the side have a higher insulation characteristic and protective effect, which is conducive to better realizing the electrical isolation effect of the first doped silicon layer and the second doped silicon layer through the anti-reflection layer with uniform thickness, reducing forward leakage, and improving the structural reliability of the side of the back contact battery.

[0268] Or, if Fig.11As shown, on the side of the silicon substrate 100, the thickness of the surface passivation layer 13 and / or the anti-reflection layer 207 can be gradually increased in the direction from the backlight surface to the light-receiving surface. In this case, it can be understood that when the thickness of the surface passivation layer 13 gradually increases in the direction from the backlight surface to the light-receiving surface, the portion of the surface passivation layer 13 on the side close to the light-receiving surface has a higher passivation effect and better insulation isolation characteristics, further reducing the number of surface defects in the area close to the light-receiving surface in the side of the silicon substrate 100, while further reducing the leakage risk between the first doped silicon layer 12 and the second doped silicon layer 16, which is conducive to increasing the open circuit voltage and fill factor of the back contact battery. When the thickness of the anti-reflection layer 207 gradually increases in the direction from the backlight surface to the light-receiving surface, the portion of the surface passivation layer 13 on the side close to the light-receiving surface has better insulation isolation characteristics, further reducing the leakage risk between the first doped silicon layer 12 and the second doped silicon layer 16, which is conducive to increasing the open circuit voltage and fill factor of the back contact battery.

[0269] Among them, on the side of the silicon substrate, the thickness of the surface passivation layer and / or the anti-reflection layer gradually increases in the direction from the backlight surface to the light-receiving surface, and the thickness of the surface passivation layer and / or the anti-reflection layer close to the backlight surface or the light-receiving surface can be set according to actual needs and are not specifically limited here.

[0270] For the intrinsic silicon layer and the second doped silicon layer, from the material aspect, the material of the intrinsic silicon layer and / or the second doped silicon layer may include at least one of amorphous silicon, microcrystalline silicon and nanocrystalline silicon. Secondly, the conductivity type of the second doped silicon layer and the first doped silicon layer can be determined according to the material of the first doped silicon layer and the actual application scenario, as long as the conductivity types of the first doped silicon layer and the second doped silicon layer are opposite. Specifically, the conductivity type of the first doped silicon layer can be N-type, in which case the conductivity type of the second doped silicon layer is P-type. Alternatively, the conductivity type of the first doped silicon layer can also be P-type, in which case the conductivity type of the second doped silicon layer is N-type.

[0271] Optionally, when the material of the first doped silicon layer includes polycrystalline silicon, the conductivity type of the first doped silicon layer may be N-type, and the conductivity type of the second doped silicon layer may be P-type. In this case, compared with P-type doped amorphous silicon, P-type doped microcrystalline silicon and P-type doped nanocrystalline silicon materials, the contact resistance between the P-type doped polycrystalline silicon material and the electrode is higher and the field passivation effect is poorer. Therefore, when the conductivity type of the first doped silicon layer is set to N-type and the conductivity type of the second doped silicon layer is set to P-type, the field passivation effect of the first doped silicon layer can be further improved, and at the same time, the contact resistance between the first doped silicon layer and the electrode can be reduced, which is beneficial to improving the electrical performance of the back contact battery.

[0272] As for the formation range of the intrinsic silicon layer and the second doped silicon layer on the side of the silicon substrate, Figures 8 to 10As shown, along the thickness direction of the silicon substrate 100, the intrinsic silicon layer 15 and the second doped silicon layer 16 can cover various regions of the side surface of the silicon substrate 100, that is, the entire side surface. Fig.12 As shown, the intrinsic silicon layer 15 and the second doped silicon layer 16 disposed on the side may also be located on a local area of ​​the side and close to the backlight surface. In this case, it can be understood that in the actual manufacturing process, when the intrinsic silicon layer 15 and the second doped silicon layer 16 are formed on the backlight surface and the side of the silicon substrate 100, in order to ensure that the intrinsic silicon layer 15 and the second doped silicon layer 16 with a larger coverage area are formed on the side, the intrinsic silicon layer 15 and the second doped silicon layer 16 may be plated around the light-receiving side. However, the intrinsic silicon layer 15 and the second doped silicon layer 16 on the light-receiving surface have parasitic absorption, so it is necessary to remove the intrinsic silicon layer 15 and the second doped silicon layer 16 on the light-receiving surface. Based on this, when the intrinsic silicon layer 15 and the second doped silicon layer 16 disposed on the side are located on a local area of ​​the side, it is not necessary to strictly control the manufacturing conditions in order to retain all the intrinsic silicon layer 15 and the second doped silicon layer 16 on the side in the process of removing the intrinsic silicon layer 15 and the second doped silicon layer 16 plated around the light-receiving surface, thereby reducing the manufacturing difficulty of the back contact battery. Specifically, in this case, the extension range of the intrinsic silicon layer 15 and the second doped silicon layer 16 on the side can be determined based on the passivation and protection requirements for the side of the silicon substrate 100 in the actual application scenario, the anti-leakage requirements between the first doped silicon layer 12 and the second doped silicon layer 16 arranged on the side of the silicon substrate 100, and the actual manufacturing process, and is not specifically limited here.

[0273] As for the thickness of the intrinsic silicon layer and the second doped silicon layer on the side of the silicon substrate, the thickness of the two on the side of the silicon substrate along the direction from the backlight surface to the light receiving surface can be substantially the same. Fig.12 As shown, on the side of the silicon substrate 100, the thickness of the intrinsic silicon layer 15 and / or the second doped silicon layer 16 gradually increases from the light-receiving surface to the backlight surface. In this case, it is beneficial to improve the protective effect of the intrinsic silicon layer 15 and / or the second doped silicon layer 16 on the area near the backlight surface of the side of the silicon substrate 100, and the structural reliability of the side in the back contact battery can be further improved.

[0274] Exemplarily, the thickness of the intrinsic silicon layer may be greater than or equal to 8 nm and less than or equal to 14 nm. For example, the thickness of the intrinsic silicon layer may be 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm or 14 nm. In this case, the thickness of the intrinsic silicon layer is relatively large, which is conducive to enhancing the isolation effect of the intrinsic silicon layer on the first doped silicon layer and the second doped silicon layer, and reducing the risk of forward leakage.

[0275] In addition, in the side of the silicon substrate, when the surface of the region covered with the intrinsic silicon layer and / or the second doped silicon layer has a tower-shaped texture structure, the thickness of the intrinsic silicon layer and / or the second doped silicon layer located at the bottom of the tower-shaped texture structure can be equal to the thickness of the intrinsic silicon layer and / or the second doped silicon layer located at the side wall of the tower-shaped texture structure; or, the thickness of the intrinsic silicon layer and / or the second doped silicon layer located at the bottom of the tower-shaped texture structure can also be greater than the thickness of the intrinsic silicon layer and / or the second doped silicon layer located at the side wall of the tower-shaped texture structure. It can be understood that the portion of the intrinsic silicon layer and / or the second doped silicon layer located at the bottom of the tower-shaped texture structure accounts for a large proportion of the side, so when the thickness of the intrinsic silicon layer and / or the second doped silicon layer located at the bottom of the tower-shaped texture structure is large, the portion of the intrinsic silicon layer and / or the second doped silicon layer that accounts for a large proportion can have a higher passivation and protection effect, which can further reduce the number of defects on the side of the back contact battery and improve the protection of the side of the silicon substrate. Of course, the thickness of the intrinsic silicon layer and / or the second doped silicon layer located at the bottom surface of the tower-shaped texture structure can also be smaller than the thickness of the intrinsic silicon layer and / or the second doped silicon layer located at the side wall of the tower-shaped texture structure, so as to improve the applicability of the back-contact battery provided in the embodiment of the present application in different application scenarios.

[0276] Herein, "the thickness of the intrinsic silicon layer and / or the second doped silicon layer at the bottom surface of the tower-shaped texture structure" may refer to the thickness of the intrinsic silicon layer at the bottom surface of the tower-shaped texture structure, or the thickness of the second doped silicon layer at the bottom surface of the tower-shaped texture structure; of course, it may also refer to the sum of the thicknesses of the intrinsic silicon layer and the second doped silicon layer at the bottom surface of the tower-shaped texture structure. Herein, "the thickness of the intrinsic silicon layer and / or the second doped silicon layer at the side wall of the tower-shaped texture structure" is similar to the above explanation and will not be repeated here.

[0277] In addition, when comparing the thickness at the bottom surface of the tower-shaped texture structure and the thickness at the side wall of the tower-shaped texture structure, the same film layer should be compared, for example, the intrinsic silicon layer, or the second doped silicon layer, or the sum of the thicknesses of the intrinsic silicon layer and the second doped silicon layer.

[0278] As a possible implementation scheme, in the case where the side of the silicon substrate has a tower-shaped texture structure, the thickness of the first interface passivation layer at the bottom surface of the tower-shaped texture structure can be less than the thickness of the first interface passivation layer at the side wall of the tower-shaped texture structure. In addition, the thickness of the intrinsic silicon layer at the bottom surface of the tower-shaped texture structure is greater than the thickness of the intrinsic silicon layer at the side wall of the tower-shaped texture structure; and / or, the thickness of the second doped silicon layer at the bottom surface of the tower-shaped texture structure is greater than the thickness of the second doped silicon layer at the side wall of the tower-shaped texture structure. "The thickness of the intrinsic silicon layer at the bottom surface of the tower-shaped texture structure is greater than the thickness of the intrinsic silicon layer at the side wall of the tower-shaped texture structure; and the thickness of the second doped silicon layer at the bottom surface of the tower-shaped texture structure is greater than the thickness of the second doped silicon layer at the side wall of the tower-shaped texture structure." means that the sum of the thickness of the intrinsic silicon layer and the second doped silicon layer at the bottom surface of the tower-shaped texture structure is greater than the sum of the thickness of the intrinsic silicon layer and the second doped silicon layer at the side wall of the tower-shaped texture structure. Specifically, in the intrinsic silicon layer and the second doped silicon layer, only the thickness of the intrinsic silicon layer at the bottom of the tower-shaped texture structure may be greater than the thickness of the intrinsic silicon layer at the sidewall of the tower-shaped texture structure, and the thickness of the second doped silicon layer at the bottom of the tower-shaped texture structure is less than or equal to the thickness of the second doped silicon layer at the sidewall of the tower-shaped texture structure; or in the intrinsic silicon layer and the second doped silicon layer, the thickness of the intrinsic silicon layer at the bottom of the tower-shaped texture structure is less than or equal to the thickness of the intrinsic silicon layer at the sidewall of the tower-shaped texture structure, and the thickness of the second doped silicon layer at the bottom of the tower-shaped texture structure is greater than the thickness of the second doped silicon layer at the sidewall of the tower-shaped texture structure. It is also possible that in the intrinsic silicon layer and the second doped silicon layer, the thickness of the intrinsic silicon layer at the bottom of the tower-shaped texture structure is greater than the thickness of the intrinsic silicon layer at the sidewall of the tower-shaped texture structure, and the thickness of the second doped silicon layer at the bottom of the tower-shaped texture structure is also greater than the thickness of the second doped silicon layer at the sidewall of the tower-shaped texture structure.

[0279] When the above technical solution is adopted, the thickness relationship of the first interface passivation layer at the bottom surface and the side wall of the tower-shaped texture structure is opposite to the thickness relationship of the intrinsic silicon layer and / or the second doped silicon layer at the bottom surface and the side wall of the tower-shaped texture structure. At this time, the thickness of the first interface passivation layer at the side wall of the tower-shaped texture structure is relatively large, which can make up for the fact that the thickness of the intrinsic silicon layer and / or the second doped silicon layer at the side wall of the tower-shaped texture structure is relatively small, so that the passivation effect and protection effect of the first interface passivation layer are relatively weak due to the small thickness of the first interface passivation layer at the bottom surface of the tower-shaped texture structure, ensuring that under the common passivation effect and protection effect of the first interface passivation layer, and the intrinsic silicon layer and / or the second doped silicon layer, the side of the silicon substrate corresponding to the bottom surface and the side of the tower-shaped texture structure have a higher passivation effect and protection strength.

[0280] For the transparent conductive layer, Figure 8 As shown, along the thickness direction of the silicon substrate 100, the transparent conductive layer 208 can cover various areas on the side of the silicon substrate 100. Alternatively, as shown in FIG. Fig.12 As shown, the transparent conductive layer 208 disposed on the side may also be located on a local area of ​​the side and close to the backlight surface. In this case, it is not necessary to strictly control the manufacturing conditions in order to retain all of the transparent conductive layer 208 on the side in the process of removing the transparent conductive layer 208 plated on the light-receiving surface, thereby reducing the difficulty of manufacturing the back contact battery. Specifically, in this case, the extension range of the transparent conductive layer 208 on the side can be determined based on the protection requirements for the side of the silicon substrate 100 in the actual application scenario, the anti-leakage requirements between the first doped silicon layer 12 and the second doped silicon layer 16 disposed on the side of the silicon substrate 100, and the actual manufacturing process, and is not specifically limited here.

[0281] As for the thickness of the transparent conductive layer on the side of the silicon substrate, the thickness of the transparent conductive layer on the side of the silicon substrate may be substantially the same along the direction from the backlight surface to the light receiving surface. Fig.12 As shown, on the side of the silicon substrate 100, the thickness of the transparent conductive layer 208 gradually increases from the light-receiving side to the backlight side. In this case, it is beneficial to improve the protective effect of the transparent conductive layer 208 on the area near the backlight side of the side of the silicon substrate 100, and the structural reliability of the side of the back contact battery can be further improved.

[0282] In addition, the material of the transparent conductive layer may include indium tin oxide, aluminum-doped zinc oxide, fluorine-doped tin oxide, antimony-doped tin oxide, or the like.

[0283] As a possible implementation, Fig.13 As shown, the back contact cell may further include an insulating mask layer 21. The insulating mask layer 21 is disposed between the first doped silicon layer 12 and the surface passivation layer 13 located on the side, and the insulating mask layer 21 is also disposed between the intrinsic silicon layer 15 and the first doped silicon layer 12 on the backlight side along the thickness direction of the silicon substrate 100. In this case, the insulating mask layer 21 can separate the first doped silicon layer 12 and the second doped silicon layer 16 on the side together with the surface passivation layer 13 and the anti-reflection layer 207, further suppressing the side leakage. At the same time, the side of the silicon substrate 100 can also be passivated to further reduce the number of defects on the side of the silicon substrate 100. In addition, the insulating mask layer 21 is also formed on the side, which is also conducive to reducing the thickness requirement of the intrinsic silicon layer 15. While ensuring that there is a lower forward leakage between the first doped silicon layer 12 and the second doped silicon layer 16, the thickness of the intrinsic silicon layer 15 is smaller to have a lower tunneling resistance, which is conducive to improving the carrier collection efficiency of the second doped silicon layer 16 on the backlight side.

[0284] In terms of materials, the material of the insulating mask layer may include any insulating material with a mask protection function, and is not specifically limited here. For example, the insulating mask layer may include at least one of a doped silicon glass layer, an aluminum oxide layer, and a silicon nitride layer. The conductivity type of the doped silicon glass layer is opposite to the conductivity type of the first doped silicon layer.

[0285] In terms of side coverage, Fig.13 As shown, along the thickness direction of the silicon substrate 100, the insulating mask layer 21 can cover various areas on the side of the silicon substrate 100. Alternatively, as shown in FIG. Fig.14 As shown, the insulating mask layer 21 disposed on the side surface may also be located on a local area of ​​the side surface. The application principle of the beneficial effect in this case can refer to the application principle of the beneficial effect of the transparent conductive layer 208 being located on a local area of ​​the side surface and close to the backlight surface as described above, and will not be repeated here. Among them, when the insulating mask layer 21 disposed on the side surface is located on a local area of ​​the side surface, the insulating mask layer 21 located on the side surface may be close to the backlight side, may be close to the light receiving side, or may be located in the middle area of ​​the side surface.

[0286] Specifically, when an insulating mask layer is formed on the backlight surface and the side surface of the silicon substrate, an insulating mask layer may also be plated on the light-receiving surface. In this case, when removing the insulating mask layer plated on the light-receiving surface, if the portion of the insulating mask layer located on the side and close to the light-receiving surface is also removed together, and when removing the surface passivation layer and the anti-reflection layer plated on the backlight surface, the etchant has no effect or little effect on the insulating mask layer, then the insulating mask layer located on the side of the back-contact battery is close to the backlight side. Alternatively, when removing the insulating mask layer plated on the light-receiving surface, the insulating mask layer on the side is not affected; and when removing the surface passivation layer and the anti-reflection layer plated on the backlight surface, the etchant removes the portion of the insulating mask layer on the side close to the backlight side, then the insulating mask layer located on the side of the back-contact battery is close to the light-receiving side. Alternatively, when removing the insulating mask layer that is plated around the light-receiving surface, the corresponding etchant removes the portion of the insulating mask layer located on the side and close to the light-receiving surface; and when removing the surface passivation layer and the anti-reflection layer that are plated around the backlight surface, the etchant removes the portion of the insulating mask layer on the side close to the backlight surface. In this case, the insulating mask layer on the side of the back-contact battery may be located in the middle area of ​​the side.

[0287] In addition, in this case, the extension range of the insulating mask layer on the side can be determined based on the passivation and protection requirements for the side of the silicon substrate in the actual application scenario, the anti-leakage requirements between the first doped silicon layer and the second doped silicon layer arranged on the side of the silicon substrate, and the actual manufacturing process, and no specific limitation is made here.

[0288] Exemplarily, the ratio between the maximum extension length of the insulating mask layer on the side and the thickness of the silicon substrate can be less than or equal to 80%. For example, the ratio between the maximum extension length of the insulating mask layer on the side and the thickness of the silicon substrate can be 5%, 10%, 20%, 30%, 40%, 50%, 60%, 70% or 80%, etc. In this case, it can be understood that the greater the extension length of the insulating mask layer on the side, the first doped silicon layer and the second doped silicon layer in the side of the silicon substrate can be separated by forming a larger insulating mask layer, the lower the forward leakage of the back contact battery, and the stronger the protective effect of the insulating mask layer on the side of the silicon substrate. The smaller the extension length of the insulating mask layer on the side, the larger the range of the reverse leakage area formed between the first doped silicon layer and the second doped silicon layer in the side of the silicon substrate, and the lower the risk of hot spots of the back contact battery. Based on this, when the ratio of the maximum extension length of the insulating mask layer on the side to the thickness of the silicon substrate is less than or equal to 80%, the forward leakage, hot spot risk and side protection of the back contact battery can be regulated by adjusting the maximum extension length of the insulating mask layer on the side according to the actual application scenario requirements of the back contact battery, which is conducive to achieving a balance between the forward leakage, hot spot risk and side protection of the back contact battery.

[0289] As for the thickness of the insulating mask layer on the side of the silicon substrate, its thickness on the side of the silicon substrate can be substantially the same along the direction from the backlight surface to the light-receiving surface. Fig.14 As shown, the thickness of the insulating mask layer 21 gradually increases from the light-receiving surface to the backlight surface on the side of the silicon substrate 100. The application principle of the beneficial effect in this case is similar to the application principle of the beneficial effect of the thickness of the surface passivation layer 13 gradually increasing from the backlight surface to the light-receiving surface on the side of the silicon substrate 100 described above, and will not be repeated here.

[0290] As a possible implementation scheme, a doping layer can also be formed in the side of the silicon substrate. The dopant in the doping layer includes the dopant in the first doped silicon layer. In this case, the doping layer is formed by controlling the manufacturing process, the concentration of the dopant in the first doped silicon layer, the thickness of the first doped silicon layer, and the thickness and compactness of the first interface passivation layer when forming the first doped silicon layer, so that part of the dopant in the first doped silicon layer passes through the first interface passivation layer and enters the side area of ​​the silicon substrate; or the doping layer and the first doped silicon layer can be formed separately. Based on this, the doping layer can form a high-low junction with the first doped silicon layer, so that the energy band between the first doped silicon layer and the side of the silicon substrate is more matched, the passivation effect of the first doped silicon layer on the side of the silicon substrate is improved, and the open circuit voltage of the back contact battery is increased. Specifically, the formation range of the doping layer, the doping concentration of the dopant in the doping layer, etc. can be determined according to the formation range of the first interface passivation layer and the first doped silicon layer on the side, the thickness and compactness of the first interface passivation layer, and the doping concentration of the first doped silicon layer, or according to actual needs, and are not specifically limited here.

[0291] Combine the following Fig.15 , the structure of solar cells of some other embodiments of the first aspect of the present application are described in detail.

[0292] Reference Fig.15 As shown, Fig.15 The schematic diagram of the back contact cell of the embodiment of the present application is shown. The solar cell is a back contact cell; the first conductive layer 202 is a first doped silicon layer 12 , the second conductive layer 205 is a second doped silicon layer 16 , and the insulating layer 203 includes an insulating mask layer 21 .

[0293] Specifically, Fig.15 As shown, the back contact cell includes: a silicon substrate, a first interface passivation layer 20, a first doped silicon layer 12, an insulating mask layer 21, an intrinsic silicon layer 15, a second doped silicon layer 16 and a transparent conductive layer 208. The silicon substrate includes a backlight surface and a light-receiving surface that are arranged opposite to each other, and a side surface connecting the backlight surface and the light-receiving surface. In the direction away from the side surface, the first interface passivation layer 20, the first doped silicon layer 12, the insulating mask layer 21, the intrinsic silicon layer 15, the second doped silicon layer 16 and the transparent conductive layer 208 are arranged on the side surface in sequence. The first doped silicon layer 12 and the second doped silicon layer 16 have opposite conductivity types. Among them, the back contact battery includes a surface passivation layer 13 arranged on the light-receiving surface, and the surface passivation layer 13 extends from the light-receiving surface to the side; the back contact battery also includes a second interface passivation layer 22 arranged on the backlight surface and located between the silicon substrate and the second doped silicon layer 16, and the second interface passivation layer 22 extends from the backlight surface to the side; on the side, the intrinsic silicon layer 15 includes a surface passivation layer 13 and a second interface passivation layer 22 stacked in a direction away from the side.

[0294] It can be understood that in this section, the first interface passivation layer 20 can also be referred to as the aforementioned first passivation layer 201, the intrinsic silicon layer 15 can also be referred to as the aforementioned second passivation layer 204, and “along the direction away from the side” is also “along the direction away from the silicon substrate”.

[0295] In the case of adopting the above technical solution, in addition to the intrinsic silicon layer, an insulating mask layer is also provided between the first doped silicon layer and the second doped silicon layer, which can reduce the thickness requirement of the intrinsic silicon layer while ensuring the reduction of forward leakage loss, reduce the tunneling resistance of the intrinsic silicon layer, and help improve the hand collection efficiency of the second doped silicon layer provided on the backlight side of the silicon substrate for carriers, and further improve the conversion efficiency of the back contact battery. In addition, the presence of the insulating mask layer can also enhance the protection of the side of the silicon substrate, and further improve the side structure reliability of the back contact battery.

[0296] In the above case, if Fig.15 As shown, the back contact cell includes a first interface passivation layer 20, a first doped silicon layer 12, an insulating mask layer 21, an intrinsic silicon layer 15, a second doped silicon layer 16 and a transparent conductive layer 208 which are not only arranged on the side of the silicon substrate 100, but also arranged on the backlight side of the silicon substrate 100. Specifically, on the backlight side of the silicon substrate 100, the transparent conductive layer 208 covers the first doped silicon layer 12 and the second doped silicon layer 16 on the side away from the silicon substrate 100, and a penetrating isolation groove is arranged in the transparent conductive layer 208 to disconnect the part of the transparent conductive layer 208 corresponding to the first doped silicon layer 12 from the part of the transparent conductive layer 208 corresponding to the second doped silicon layer 16 to prevent short circuit. As for the distribution of the first interface passivation layer 20, the first doped silicon layer 12, the insulating mask layer 21, the intrinsic silicon layer 15 and the second doped silicon layer 16 on the backlight side of the silicon substrate 100, reference can be made to the above description in Figure 8-Figure 14 The distribution of the first interface passivation layer 20, the first doped silicon layer 12, the intrinsic silicon layer 15 and the second doped silicon layer 16 on the backlight side of the silicon substrate 100 described in the description is not specifically limited here.

[0297] Alternatively, in the side of the back contact cell, the second doped silicon layer may be in direct contact with the transparent conductive layer. Fig.15As shown, the back contact cell may also include an anti-reflection layer 207 disposed on the light-receiving surface, and the anti-reflection layer 207 extends from the light-receiving surface to the side. On the side, the anti-reflection layer 207 is disposed between the second doped silicon layer 16 and the transparent conductive layer 208 in the direction away from the side. In this case, an anti-reflection layer is added to the film layer disposed on the side of the silicon substrate, which can further improve the protection of the side of the silicon substrate, reduce the risk of damage to the side of the silicon substrate, and reduce the forward leakage loss. In addition, in this case, the anti-reflection layer is directly formed on the side of the second doped silicon layer away from the silicon substrate. Because there is a difference between the materials of the surface passivation layer and the second doped silicon layer, and the anti-reflection layer is easier to deposit on the surface passivation layer. Based on this, compared with the anti-reflection layer being directly formed on the surface passivation layer, when the anti-reflection layer is directly formed on the side of the second doped silicon layer away from the silicon substrate, the coating range of the anti-reflection layer on the side of the backlight surface can be reduced, thereby reducing the etching amount when removing the anti-reflection layer on the backlight surface, thereby improving the manufacturing efficiency.

[0298] The insulating mask layer may cover various areas on the side. Alternatively, Fig.15 As shown, the insulating mask layer 21 can also be arranged on a local area of ​​the side surface and close to the side of the backlight surface. The coverage of the insulating mask layer 21 on the side surface can refer to the corresponding description in the previous text, which will not be repeated here.

[0299] It should be understood that in the first aspect, various features in different embodiments may be applied separately or in combination as needed.

[0300] Combine the following Figure 3 and Figure 8 , the structure of solar cells of some further embodiments of the first aspect of the present application are described in detail.

[0301] In some embodiments, the solar cell is a back contact cell, comprising: a silicon substrate 100, a first interface passivation layer 20, a first doped silicon layer 12, a surface passivation layer 13, an anti-reflection layer 207, an intrinsic silicon layer 15, a second doped silicon layer 16 and a transparent conductive layer 208. The silicon substrate 100 comprises a backlight surface and a light-receiving surface arranged opposite to each other, and a side surface connecting the backlight surface and the light-receiving surface. In the direction away from the side surface, the first interface passivation layer 20, the first doped silicon layer 12, the surface passivation layer 13, the anti-reflection layer 207, the intrinsic silicon layer 15, the second doped silicon layer 16 and the transparent conductive layer 208 are sequentially arranged on the side surface. The first doped silicon layer 12 and the second doped silicon layer 16 have opposite conductivity types. Among them, along the thickness direction of the silicon substrate 100, the surface passivation layer 13 and the anti-reflection layer 207 are also sequentially arranged on the light-receiving surface, and the surface passivation layer 13 and the anti-reflection layer 207 extend from the light-receiving surface to the side surface. The protective layer 200 includes a first doped silicon layer 12, a surface passivation layer 13, an anti-reflection layer 207, and a second doped silicon layer 16, and the insulating layer 203 includes a surface passivation layer 13 and an anti-reflection layer 207. The junction of the side surface 130 and the backlight surface 120 is a first position 130a, and the junction of the side surface 130 and the light receiving surface 110 is a second position 130b. The thickness of the protective layer 200 at the first position 130a is D1, and the thickness of the protective layer 200 at the second position 130b is D2, which satisfies: 1<D1 / D2≤10; preferably, 2.5≤D1 / D2≤10.

[0302] In addition, the surface passivation layer 13 and the anti-reflection layer 207 are not only located on the light-receiving surface of the silicon substrate 100, but also extend to the side of the silicon substrate 100. At this time, on the side of the silicon substrate 100, the first doped silicon layer 12 and the second doped silicon layer 16 of opposite conductivity types can be separated by the surface passivation layer 13 and the anti-reflection layer 207 to prevent the two from being turned on and leaking electricity, thereby reducing forward leakage loss, so that the back contact cell has a higher conversion efficiency. In addition, the surface passivation layer 13 and the anti-reflection layer 207 are arranged on the light-receiving surface to reduce carrier recombination and surface reflectivity. The two are then extended to the side of the silicon substrate 100, and can also be used to isolate the first doped silicon layer 12 and the second doped silicon layer 16. There is no need to form other insulating layers through other deposition steps to prevent leakage between the first doped silicon layer 12 and the second doped silicon layer 16. The manufacturing process of the back contact battery can be simplified. At the same time, there is no need to consider the compatibility between the film layer that isolates the first doped silicon layer 12 and the second doped silicon layer 16 and other structures in the back contact battery, ensuring that the back contact battery has a high yield. At the same time, not only the first interface passivation layer 20 and the first doped silicon layer 12 arranged on the side of the silicon substrate 100 have a passivation effect on the silicon substrate 100, but the surface passivation layer 13 that realizes the insulation isolation of the first doped silicon layer 12 and the second doped silicon layer 16 on the side can also passivate the side of the silicon substrate 100, further reducing the carrier recombination rate on the side of the silicon substrate 100 and improving the conversion efficiency of the back contact battery. Furthermore, by setting a reasonable value range of the ratio D1 / D2 between the thickness D1 of the protective layer 200 at the first position 130a and the thickness D2 of the protective layer 200 at the second position 130b of the side surface 130 of the silicon substrate 100, the thickness of the protective layer 200 at different positions of the side surface 130 of the silicon substrate 100 is different. In this way, effective shielding protection can be formed for the entire side surface 130 of the silicon substrate 100, and the material consumption required for preparing the protective layer 200 can be appropriately reduced.

[0303] Further, the thickness of the insulating layer 203 (i.e., the surface passivation layer 13 and the anti-reflection layer 207) on the backlight surface 120 is H2, the thickness of the insulating layer 203 at the first position 130a on the side surface 130 is H21, and the thickness of the insulating layer 203 at the second position 130b on the side surface 130 is H22, satisfying: H22<H21≤H2. The technical effect of H22<H21≤H2 can be referred to the above, and will not be repeated here.

[0304] Further, the total thickness of the first passivation layer 201 (i.e., the first interface passivation layer 20) and the first conductive layer 202 (i.e., the first doped silicon layer 12) on the backlight surface 120 is H1, the total thickness of the first passivation layer 201 and the first conductive layer 202 at the first position 130a on the side surface 130 is H11, and the total thickness of the first passivation layer 201 and the first conductive layer 202 at the second position 130b on the side surface 130 is H12, satisfying: H12<H11≤H1. For the technical effect of H12<H11≤H1, please refer to the above text and will not be repeated here.

[0305] Furthermore, the total thickness of the second passivation layer 204 (i.e., the intrinsic silicon layer 15) and the second conductive layer 205 (i.e., the second doped silicon layer 16) on the backlight surface 120 is H3, the total thickness of the second passivation layer 204 and the second conductive layer 205 at the first position 130a on the side 130 is H31, and the total thickness of the second passivation layer 204 and the second conductive layer 205 at the second position 130b on the side 130 is H32, satisfying: H32<H31≤H3. For the technical effect of H32<H31≤H3, please refer to the above text and will not be repeated here.

[0306] Combine the following Figure 3 and Fig.15 , the structure of solar cells of other embodiments of the first aspect of the present application are described in detail.

[0307] In other embodiments, the solar cell is a back contact cell, comprising: a silicon substrate, a first interface passivation layer 20, a first doped silicon layer 12, an insulating mask layer 21, an intrinsic silicon layer 15, a second doped silicon layer 16 and a transparent conductive layer 208. The silicon substrate comprises a backlight surface and a light receiving surface arranged opposite to each other, and a side surface connecting the backlight surface and the light receiving surface. In the direction away from the side surface, the first interface passivation layer 20, the first doped silicon layer 12, the insulating mask layer 21, the intrinsic silicon layer 15, the second doped silicon layer 16 and the transparent conductive layer 208 are sequentially arranged on the side surface. The first doped silicon layer 12 and the second doped silicon layer 16 have opposite conductivity types. The back contact cell includes a surface passivation layer 13 disposed on the light receiving surface, and the surface passivation layer 13 extends from the light receiving surface to the side surface; the back contact cell also includes a second interface passivation layer 22 disposed on the back light surface and located between the silicon substrate and the second doped silicon layer 16, and the second interface passivation layer 22 extends from the back light surface to the side surface; on the side surface, the intrinsic silicon layer 15 includes a surface passivation layer 13 and a second interface passivation layer 22 stacked in a direction away from the side surface. The protective layer 200 includes a first doped silicon layer 12, an insulating mask layer 21, and a second doped silicon layer 16, and the insulating layer 203 includes an insulating mask layer 21. The junction of the side surface 130 and the back light surface 120 is a first position 130a, and the junction of the side surface 130 and the light receiving surface 110 is a second position 130b. The thickness of the protective layer 200 at the first position 130 a is D1 , and the thickness of the protective layer 200 at the second position 130 b is D2 , which satisfies: 1<D1 / D2≤10; preferably, 2.5≤D1 / D2≤10.

[0308] In addition to the intrinsic silicon layer, an insulating mask layer is also provided between the first doped silicon layer and the second doped silicon layer. While ensuring the reduction of forward leakage loss, the thickness requirement of the intrinsic silicon layer can also be reduced, and the tunneling resistance of the intrinsic silicon layer can be reduced, which is conducive to improving the hand collection efficiency of the second doped silicon layer arranged on the backlight side of the silicon substrate for carriers, and further improving the conversion efficiency of the back contact battery. In addition, the presence of the insulating mask layer can also enhance the protection of the side of the silicon substrate, and further improve the side structure reliability of the back contact battery. In addition, by setting a reasonable value range of the ratio D1 / D2 between the thickness D1 of the protective layer 200 at the first position 130a of the side 130 of the silicon substrate 100 and the thickness D2 of the protective layer 200 at the second position 130b, the thickness of the protective layer 200 at the side 130 of the silicon substrate 100 is different at different positions. In this way, it can not only achieve effective shielding protection for the entire side 130 of the silicon substrate 100, but also appropriately reduce the material consumption required for preparing the protective layer 200.

[0309] Further, the thickness of the insulating layer 203 (i.e., the insulating mask layer 21) on the backlight surface 120 is H2, the thickness of the insulating layer 203 at the first position 130a on the side surface 130 is H21, and the thickness of the insulating layer 203 at the second position 130b on the side surface 130 is H22, satisfying: H22<H21≤H2. The technical effect of H22<H21≤H2 can be referred to the above, and will not be repeated here.

[0310] Further, the total thickness of the first passivation layer 201 (i.e., the first interface passivation layer 20) and the first conductive layer 202 (i.e., the first doped silicon layer 12) on the backlight surface 120 is H1, the total thickness of the first passivation layer 201 and the first conductive layer 202 at the first position 130a on the side surface 130 is H11, and the total thickness of the first passivation layer 201 and the first conductive layer 202 at the second position 130b on the side surface 130 is H12, satisfying: H12<H11≤H1. For the technical effect of H12<H11≤H1, please refer to the above text and will not be repeated here.

[0311] Furthermore, the total thickness of the second passivation layer 204 (i.e., the intrinsic silicon layer 15) and the second conductive layer 205 (i.e., the second doped silicon layer 16) on the backlight surface 120 is H3, the total thickness of the second passivation layer 204 and the second conductive layer 205 at the first position 130a on the side 130 is H31, and the total thickness of the second passivation layer 204 and the second conductive layer 205 at the second position 130b on the side 130 is H32, satisfying: H32<H31≤H3. For the technical effect of H32<H31≤H3, please refer to the above text and will not be repeated here.

[0312] In a second aspect, an embodiment of the present application further provides a photovoltaic assembly, comprising the solar cell in any of the above embodiments.

[0313] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any possible one or more embodiments or examples.

[0314] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

[0315] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0316] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A solar cell, wherein: include: Silicon substrate; The silicon substrate has a light-receiving surface and a backlight surface opposite to each other, and a side surface arranged between the light-receiving surface and the backlight surface; A protective layer is disposed on the side surface. Along a direction away from the silicon substrate, the protective layer comprises a first conductive layer, an insulating layer and a second conductive layer which are sequentially disposed on the side surface. The first conductive layer and the second conductive layer have opposite conductivity types.

2. The solar cell according to claim 1, wherein: Along a direction parallel to the backlight surface, the backlight surface has first areas and second areas that are alternately arranged; the first areas are formed with the first conductive layer, and the second areas are formed with the second conductive layer.

3. The solar cell according to claim 1, wherein: The protection layer further includes a first passivation layer located between the side surface and the first conductive layer, and a second passivation layer located between the insulating layer and the second conductive layer; Along a direction parallel to the backlight surface, the backlight surface has a first area and a second area that are alternately arranged; Along the direction away from the silicon substrate, the first region is sequentially formed with the first passivation layer and the first conductive layer, and the second region is sequentially formed with the second passivation layer and the second conductive layer; the insulating layer is arranged between the first region and the second region.

4. The solar cell according to claim 3, wherein: The junction between the side surface and the backlight surface is a first position, and the junction between the side surface and the light-receiving surface is a second position. The thickness of the protective layer at the first position is greater than the thickness of the protective layer at the second position.

5. The solar cell according to claim 4, wherein: The thickness of the protective layer at the first position is D1, and the thickness of the protective layer at the second position is D2, satisfying: 1<D1 / D2≤10.

6. The solar cell according to claim 4, wherein: The thickness of the insulating layer on the backlight surface is H2, the thickness of the insulating layer at the first position on the side surface is H21, and the thickness of the insulating layer at the second position on the side surface is H22. H2, H21, and H22 satisfy at least one of the following relationships: H22<H21≤H2, 0.2≤H22 / H21<1, 0.5≤H21 / H2≤1, 0.2≤H22 / H2≤0.

6.

7. The solar cell according to claim 4, wherein: The total thickness of the first passivation layer and the first conductive layer on the backlight surface is H1, the total thickness of the first passivation layer and the first conductive layer at the first position on the side is H11, and the total thickness of the first passivation layer and the first conductive layer at the second position on the side is H12. H1, H11, and H12 satisfy at least one of the following relationships: H12<H11≤H1, 0.2≤H12 / H11<1, 0.5≤H11 / H1≤1, 0.2≤H12 / H1≤0.

6.

8. The solar cell according to claim 4, wherein: The total thickness of the second passivation layer and the second conductive layer on the backlight surface is H3, the total thickness of the second passivation layer and the second conductive layer at the first position on the side is H31, and the total thickness of the second passivation layer and the second conductive layer at the second position on the side is H32. H3, H31, and H32 satisfy at least one of the following relationships: H32<H31≤H3, 0.2≤H32 / H31<1, 0.5≤H31 / H3≤1, 0.2≤H32 / H3≤0.

6.

9. The solar cell according to claim 4, wherein: The protective layer further comprises a third passivation layer and an anti-reflection layer, wherein the third passivation layer is arranged on a side of the second conductive layer away from the side surface, and the anti-reflection layer is arranged on a side of the third passivation layer away from the second conductive layer; The third passivation layer and the anti-reflection layer are sequentially formed on the light-receiving surface in a direction away from the silicon substrate.

10. The solar cell according to claim 9, wherein: The total thickness of the third passivation layer and the anti-reflection layer on the light receiving surface is H4, the total thickness of the third passivation layer and the anti-reflection layer at the first position on the side is H41, and the total thickness of the third passivation layer and the anti-reflection layer at the second position on the side is H42. H4, H41, and H42 satisfy at least one of the following relationships: H41<H42≤H4, 0.1≤H42 / H41<1, 0.1≤H41 / H4≤0.4, 0.5≤H42 / H4≤0.

8.

11. The solar cell according to claim 4, wherein: The protective layer further comprises: a transparent conductive layer, the transparent conductive layer being arranged on a side of the second conductive layer away from the side surface; The transparent conductive layer is disposed in at least one of the first region and the second region, and the transparent conductive layer is disposed on a side of the first conductive layer and / or the second conductive layer facing away from the backlight surface.

12. The solar cell according to claim 11, wherein: The thickness of the transparent conductive layer located on the backlight surface is H5, the thickness of the transparent conductive layer located on the first position on the side is H51, and the thickness of the transparent conductive layer located on the second position on the side is H52. H5, H51, and H52 satisfy at least one of the following relationships: H52<H51≤H5, 0.3≤H52 / H51<1, 0.5≤H51 / H5≤1, 0.2≤H52 / H5≤0.

5.

13. The solar cell according to claim 1, wherein: The solar cell is a back contact cell; The first conductive layer is a first doped silicon layer, the second conductive layer is a second doped silicon layer, and the insulating layer includes a surface passivation layer and an anti-reflection layer; The back contact cell comprises: a first interface passivation layer, the first doped silicon layer, the surface passivation layer, the anti-reflection layer, the intrinsic silicon layer, the second doped silicon layer and a transparent conductive layer, which are sequentially arranged on the side surface in a direction away from the silicon substrate; Wherein, along the thickness direction of the silicon substrate, the surface passivation layer and the anti-reflection layer are also sequentially arranged on the light receiving surface, and the surface passivation layer and the anti-reflection layer extend from the light receiving surface to the side surface.

14. The solar cell according to claim 13, wherein: The backlight surface includes a first area and a second area; the first interface passivation layer and the first doped silicon layer are located in the first area; the intrinsic silicon layer and the second doped silicon layer are located in the second area, and extend from the second area to the first area, and cover a portion of the first interface passivation layer and the first doped silicon layer; The insulating layer also includes an insulating mask layer; the insulating mask layer is arranged between the first doped silicon layer located on the side and the surface passivation layer, and the insulating mask layer is also arranged between the intrinsic silicon layer located on the backlight side and the first doped silicon layer along the thickness direction of the silicon substrate.

15. The solar cell according to claim 14, wherein: On the side surface of the silicon substrate, the thickness of the insulating mask layer gradually increases along the direction from the light-receiving surface to the backlight surface; And / or, the insulating mask layer arranged on the side is located on a local area of ​​the side; along the thickness direction of the silicon substrate, the ratio between the maximum extension length of the insulating mask layer on the side and the thickness of the silicon substrate is less than or equal to 80%.

16. The solar cell according to claim 1, wherein: The solar cell is a back contact cell; The first conductive layer is a first doped silicon layer, the second conductive layer is a second doped silicon layer, and the insulating layer includes an insulating mask layer; The back contact cell comprises: a first interface passivation layer, the first doped silicon layer, the insulating mask layer, the intrinsic silicon layer, the second doped silicon layer and a transparent conductive layer which are sequentially arranged on the side surface in a direction away from the silicon substrate; the back contact cell comprises a surface passivation layer arranged on the light receiving surface, and the surface passivation layer extends from the light receiving surface to the side surface; the back contact cell also comprises a second interface passivation layer which is arranged on the backlight surface and is located between the silicon substrate and the second doped silicon layer, and the second interface passivation layer extends from the backlight surface to the side surface; on the side surface, the intrinsic silicon layer comprises the surface passivation layer and the second interface passivation layer which are stacked in a direction away from the side surface.

17. The solar cell according to claim 16, wherein: The back contact cell further comprises an anti-reflection layer disposed on the light-receiving surface, and the anti-reflection layer extends from the light-receiving surface to the side surface; On the side surface, the anti-reflection layer is disposed between the second doped silicon layer and the transparent conductive layer along a direction away from the side surface.

18. The solar cell according to claim 13 or 16, wherein: The first interface passivation layer and the first doped silicon layer disposed on the side surface are only located on a local area of ​​the side surface and close to the backlight surface; Wherein, along the thickness direction of the silicon substrate, the ratio between the maximum extension length of the first interface passivation layer and the first doped silicon layer on the side and the thickness of the silicon substrate is greater than or equal to 70%; and / or, the surface of the area of ​​the side not covered by the first interface passivation layer and the first doped silicon layer is a velvet surface, and the ratio between the maximum extension length of the velvet surface on the side and the thickness of the silicon substrate is less than or equal to 30%; and / or, in the side surface, the surface reflectivity of the region not covered by the first interface passivation layer and the first doped silicon layer is less than the surface reflectivity of the region covered by the first interface passivation layer and the first doped silicon layer; And / or, the surface of the area of ​​the side surface not covered by the first interface passivation layer and the first doped silicon layer is a velvet surface; and / or, the surface of the area of ​​the side surface covered by the first interface passivation layer and the first doped silicon layer is a polished surface.

19. The solar cell according to claim 13 or 16, wherein: The thickness of each part of the first interface passivation layer and / or the first doped silicon layer is the same; And / or, on the side surfaces of the silicon substrate, the thickness of the surface passivation layer is equal, or the thickness of the surface passivation layer gradually increases along the direction from the backlight surface to the light-receiving surface; And / or, on the side surface of the silicon substrate, the thickness of at least one of the intrinsic silicon layer, the second doped silicon layer and the transparent conductive layer gradually increases along the direction from the light-receiving surface to the backlight surface.

20. The solar cell according to claim 13 or 16, wherein: The surface passivation layer arranged on the side is located on a local area of ​​the side and close to the light receiving surface; along the thickness direction of the silicon substrate, the ratio between the maximum extension length of the surface passivation layer on the side and the thickness of the silicon substrate is less than or equal to 80%.

21. The solar cell according to claim 13 or 16, wherein: The material of the surface passivation layer includes at least one of aluminum oxide, intrinsic amorphous silicon, and doped silicon glass; and / or, The thickness of the first doped silicon layer is greater than or equal to 30 nm and less than or equal to 140 nm; and / or, The thickness of the intrinsic silicon layer is greater than or equal to 8 nm and less than or equal to 14 nm.

22. The solar cell according to claim 13 or 16, wherein: In the side surface of the silicon substrate, the region where the first interface passivation layer and the first doped silicon layer are arranged has a tower base-shaped texture structure; The thickness of the first interface passivation layer at the bottom surface of the tower-shaped texture structure is smaller than the thickness of the first interface passivation layer at the side wall of the tower-shaped texture structure.

23. The solar cell according to claim 13 or 16, wherein: The side surface of the silicon substrate has a tower base-shaped texture structure; Wherein, the thickness of the first interface passivation layer located on the bottom surface of the tower base-shaped texture structure is less than the thickness of the first interface passivation layer located on the side wall of the tower base-shaped texture structure; The thickness of the intrinsic silicon layer at the bottom surface of the tower-shaped texture structure is greater than the thickness of the intrinsic silicon layer at the side wall of the tower-shaped texture structure; and / or the thickness of the second doped silicon layer at the bottom surface of the tower-shaped texture structure is greater than the thickness of the second doped silicon layer at the side wall of the tower-shaped texture structure.

24. The solar cell according to claim 13 or 16, wherein: A doping layer is formed in the side surface of the silicon substrate; the dopant in the doping layer includes the dopant in the first doped silicon layer.

25. A photovoltaic module, wherein: The photovoltaic module comprises a solar cell according to any one of claims 1-24.

Images