Solar cell, preparation method thereof and cell module

Abstract

The invention discloses a solar cell which comprises a silicon substrate, and one side surface of the silicon substrate comprises a first region and a second region which are adjacent to each other along a first direction; on the first region, a first doping layer and a first electrode are sequentially stacked on the silicon substrate; the first doping layer extends to the second region; the first doping layer in the first region is provided with a crystallization region; the projection of the crystallization region on the silicon substrate and the projection of the first electrode on the silicon substrate are at least partially overlapped; and in the second region, at least one part of the first doped layer is an amorphous region. The solar cell can reduce the contact resistance and avoid the electric leakage phenomenon at the same time.

Description

[0001] This application claims the priority of the Chinese patent application filed with the Chinese Patent Office on January 23, 2024, with application number 202410092536.4 and application name “A solar cell, a method for preparing the same and a battery assembly”, the entire contents of which are incorporated by reference in this application. Technical Field

[0002] The present application relates to the photovoltaic field, and in particular to a solar cell and a preparation method thereof and a solar cell assembly. Background Art

[0003] The types of solar cells using crystalline silicon-amorphous silicon heterojunction structure include front-back contact crystalline silicon amorphous silicon heterojunction cells (SHJ) and interdigitated back contact crystalline silicon amorphous silicon heterojunction cells (SHJ-IBC). However, the contact resistance of crystalline silicon amorphous silicon structure is higher than that of tunneling oxide silicon passivation contact structure (TOPCon) and high-temperature diffusion homojunction. Therefore, reducing the contact resistance is the current research and development focus of crystalline silicon amorphous silicon heterojunction. In order to improve the contact resistance of the n-end (c-Si / ia-Si:H / na-Si:H / TCO) and p-end (c-Si / ia-Si:H / pa-Si:H / TCO), in the prior art, the phosphorus-doped amorphous (na-Si:H) and boron-doped amorphous film (pa-Si:H) layers are replaced with phosphorus- or boron-doped microcrystalline / nanocrystalline film layers (n-nc-Si:H, p-nc-Si:H), thereby increasing the effective doping concentration of the phosphorus-doped film layer (hereinafter referred to as n-Si) and the boron-doped film layer (hereinafter referred to as p-Si). However, the process of forming microcrystalline silicon or nanocrystalline silicon thin films requires a large amount of hydrogen and has a slow deposition rate, which increases costs. In addition, due to the small square resistance and strong lateral conductivity of the microcrystalline n and microcrystalline p film layers, the SHJ-IBC battery has severe leakage at the junction of the n-region and p-region film layers. Summary of the invention

[0004] In order to solve the above problems, the present application provides a solar cell, which can reduce contact resistance and avoid leakage.

[0005] The present application provides a solar cell, comprising a silicon substrate, wherein a surface of one side of the silicon substrate comprises a first region and a second region adjacent to each other along a first direction; wherein:

[0006] On the first region, a first doping layer and a first electrode are sequentially stacked on the silicon substrate; the first doping layer extends to the second region;

[0007] The first doped layer in the first region has a crystallized region; a projection of the crystallized region on the silicon substrate at least partially overlaps with a projection of the first electrode on the silicon substrate;

[0008] In the second region, at least a portion of the first doped layer is an amorphized region.

[0009] Furthermore, a third region is further included on one side surface of the silicon substrate, and along the first direction, the third region is located on a side of the second region away from the first region;

[0010] On the third region, a second doping layer and a second electrode are stacked in sequence on the silicon substrate; the second doping layer extends to the second region, and in the second region, the second doping layer is located on a side of the first doping layer close to the silicon substrate; the conductivity of the first doping layer is opposite to that of the second doping layer.

[0011] Furthermore, the second doped layer includes doped polysilicon.

[0012] Further, the second doped layer in the third region has a crystallized region; a projection of the crystallized region on the silicon substrate at least partially overlaps with a projection of the second electrode on the silicon substrate;

[0013] In the second region, at least a portion of the second doped layer is an amorphized region.

[0014] Further, in the first region, the first doped layer includes a first crystallized region and a first amorphized region A;

[0015] At least a portion of the first crystallized region away from the silicon substrate has crystals.

[0016] Furthermore, a third region is further included on one side surface of the silicon substrate, and along the first direction, the third region is located on a side of the second region away from the first region; on the third region, a second doping layer and a second electrode are sequentially stacked on the silicon substrate; the first doping layer and the second doping layer have opposite conductivity;

[0017] In the second region, the first doped layer is stacked on a side of the second doped layer away from the silicon substrate;

[0018] The first amorphized region A includes side portions located at two ends of the first region along the first direction, and the side portions are stacked on side surfaces of the second doping layer close to the first region.

[0019] Further, along the first direction, the first amorphized region A includes a middle portion located between the side portions and the first crystallized region, one end of the middle portion is connected to one of the side portions, and the other end of the middle portion is connected to the first crystallized region.

[0020] Furthermore, the sum of the lengths of the middle portion and the portion of the side portion connected thereto stacked on the silicon substrate is L≥5 μm.

[0021] Further, in the first region, along the thickness direction from the surface of one side far from the silicon substrate to the side close to the silicon substrate, the crystallization rate of the crystallization area of ​​the first doping layer gradually decreases; or

[0022] In the first region, along the thickness direction from a side surface away from the silicon substrate to a side surface close to the silicon substrate, the crystallization rates of the crystallized regions of the first doping layer are equal.

[0023] Further, the first doped layer in the amorphous region is an amorphous silicon layer, and the first doped layer in the crystallized region includes nanocrystalline silicon and / or microcrystalline silicon; and / or

[0024] The crystallization rate of the first doping layer in the crystallization region is 0.01-100%; and / or

[0025] The first doping layer in the crystallized region is distributed in a continuous or discrete manner; and / or

[0026] The first doping layer in the crystallized region is formed by laser irradiation.

[0027] Furthermore, it also includes a first passivation layer located between the silicon substrate and the first doped layer; and / or, it also includes a first conductive layer located between the first doped layer and the first electrode; and / or, it also includes a second passivation layer located between the silicon substrate and the second doped layer; and / or, it also includes a second conductive layer located between the second doped layer and the second electrode.

[0028] A method for preparing a solar cell, comprising the following steps:

[0029] Providing a silicon substrate, wherein a surface of one side of the silicon substrate includes a first region and a second region adjacent to each other along a first direction;

[0030] forming a first doping layer in the first region and the second region of the silicon substrate;

[0031] performing a crystallization process on at least a portion of the first doped layer in the first region, so that at least a portion of the first doped layer in the first region forms a crystallized region;

[0032] A first electrode is formed in the first region so that a projection of the crystallized region on the silicon substrate at least partially overlaps with a projection of the first electrode on the silicon substrate.

[0033] Furthermore, a third region is further included on one side surface of the silicon substrate, and along the first direction, the third region is located on a side of the second region away from the first region;

[0034] The method for preparing the solar cell further comprises the steps of:

[0035] forming a second doping layer in the third region and the second region of the silicon substrate; in the second region, the second doping layer is located on a side of the first doping layer close to the silicon substrate; the first doping layer and the second doping layer have opposite conductivity;

[0036] A second electrode is formed in the third region.

[0037] Furthermore, the second doped layer is a polysilicon doped layer.

[0038] Furthermore, the method for preparing the solar cell further comprises the steps of:

[0039] performing a crystallization process on at least a portion of the second doped layer in the third region, so that at least a portion of the second doped layer in the third region forms a crystallized region;

[0040] A projection of the crystallized region in the third area on the silicon substrate at least partially overlaps with a projection of the second electrode on the silicon substrate.

[0041] Furthermore, after crystallizing at least a portion of the first doped layer in the first region and before forming a first electrode in the first region, the method further includes forming a first conductive layer in the first region.

[0042] Furthermore, the first doped layer in the first region is crystallized by irradiating the first doped layer in the first region with laser.

[0043] Furthermore, the prepared solar cell is the aforementioned solar cell.

[0044] The present application also provides a battery assembly, comprising the aforementioned solar cell.

[0045] The solar cell provided by the present application, because the photogenerated carriers will migrate and diffuse horizontally (perpendicular to the thickness direction of the doping layer) and longitudinally (parallel to the thickness direction of the doping layer) in the doping layers of different doping types, the first doping layer in the first region of the present application has a crystallized region, and the crystallized region has good conductivity, which is conducive to carrier collection. In addition, in the second region, at least a portion of the first doping layer is an amorphous region, and the amorphous region has a lower carrier mobility than the crystal region, and the sheet resistance is low, which can greatly reduce the leakage current. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The accompanying drawings are used to better understand the present application and do not constitute an improper limitation on the present application.

[0047] Figure 1 This is one of the structural schematic diagrams of the solar cell provided in this application.

[0048] Figure 2 A schematic diagram of a portion of the structure of the solar cell provided in this application.

[0049] Figure 3 A schematic diagram of a portion of the structure of the solar cell provided in this application.

[0050] Figure 4 A schematic diagram of a portion of the structure of the solar cell provided in this application.

[0051] Figure 5 A schematic diagram of a portion of the structure of the solar cell provided in this application.

[0052] Figure 6 A schematic diagram of a portion of the structure of the solar cell provided in this application.

[0053] Figure 7 A schematic diagram of a portion of the structure of the solar cell provided in this application.

[0054] Figure 8 A schematic diagram of a portion of the structure of the solar cell provided in this application.

[0055] Fig. 9 A schematic diagram of a portion of the structure of the solar cell provided in this application.

[0056] Fig.10 A schematic diagram of a portion of the structure of the solar cell provided in this application.

[0057] Fig.11 This is one of the structural schematic diagrams of the solar cell provided in this application.

[0058] Fig.12 This is one of the structural schematic diagrams of the solar cell provided in this application.

[0059] Fig.13 1 and 2 are Raman spectra of the first amorphized region A of Example 1 and Comparative Example 1 of the present application.

[0060] Fig.14 This is a transmission electron microscope image of the solar cell prepared in Example 1 of the present application after laser crystallization.

[0061] Fig.15 Parallel resistance diagram of the normalized battery structure provided in this application.

[0062] Fig.16A graph of the series resistance of a normalized battery structure provided for this application.

[0063] Fig.17 This is one of the structural schematic diagrams of the solar cell provided in this application.

[0064] Fig.18 This is one of the structural schematic diagrams of the solar cell provided in this application.

[0065] Description of Reference Numerals

[0066] 1-first electrode, 2-second electrode, 3-silicon substrate, 4-second passivation layer, 5-second crystallized region, 6-second conductive layer, 7-second doped layer, 8-insulating layer, 9-laser absorption layer, 10-first doped layer, 11-first conductive layer, 12-first crystallized region, 13-light incident surface passivation layer, 14-anti-reflection layer, 15-first passivation layer, 16-first amorphized region A, 17-second amorphized region B, 18-first amorphized region B. DETAILED DESCRIPTION

[0067] The following is a description of the exemplary embodiments of the present application, including various details of the embodiments of the present application to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present application. Similarly, for clarity and conciseness, the description of well-known functions and structures is omitted in the following description.

[0068] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, in the description of the present application, the stacked layers are not necessarily in direct contact, and therefore cannot be understood as a limitation on the present application.

[0069] The present application provides a solar cell, comprising a silicon substrate 3, wherein a first region and a second region adjacent to each other along a first direction are provided on one side surface of the silicon substrate 3. In the first region, a first doping layer 10 and a first electrode 1 are sequentially stacked on the silicon substrate 3; the first doping layer 10 extends to the second region; the first doping layer 10 in the first region has a crystallized region, and a projection of the crystallized region on the silicon substrate 3 at least partially overlaps with a projection of the first electrode 1 on the silicon substrate 3.

[0070] The solar cell provided by the present application has a first doping layer 10 in the first region of the present application having a crystallized region, and the crystallized region has good conductivity, which is conducive to carrier collection. In addition, in the second region, at least a portion of the first doping layer 10 is an amorphized region, and the amorphized region has a lower carrier mobility than the crystal region, and the sheet resistance is low, which can greatly reduce the leakage current.

[0071] The specific structure of the solar cell is described in detail below through several embodiments.

[0072] Embodiment 1:

[0073] A surface on one side of the silicon substrate 3 includes a first region, a second region and a third region adjacent to each other along a first direction. In the third region, a second doping layer 7 and a second electrode 2 are sequentially stacked on the silicon substrate 3; the first doping layer 10 and the second doping layer 7 extend to the second region; the second doping layer 7 in the third region has a crystallized region; the projection of the crystallized region of the third region on the silicon substrate 3 at least partially overlaps with the projection of the second electrode 2 on the silicon substrate 3; in the second region, at least a portion of the second doping layer 7 is an amorphous region; the conductivity of the first doping layer 10 is opposite to that of the second doping layer 7.

[0074] The solar cell provided by the present application, because the photogenerated carriers will migrate and diffuse horizontally (perpendicular to the thickness direction of the doping layer) and migrate and diffuse vertically (parallel to the thickness direction of the doping layer) in the doping layers of different doping types, the present application sets a second region with high resistivity between the first doping layer 10 in the first region and the second doping layer 7 in the third region for isolation, which can reduce the lateral migration of carriers and reduce leakage, and at least one of the first doping layer 10 in the first region and the second doping layer 7 in the third region has a crystallized region, and the crystallized region has good conductivity, which is conducive to carrier collection. In addition, in the second region, at least a part of the first doping layer 10 is an amorphized region, and at least a part of the second doping layer 7 is an amorphized region. The amorphized region has lower carrier mobility and lower sheet resistance than the crystal region, which can greatly reduce leakage current.

[0075] In the first embodiment, the second doping layer 7 in the amorphous region is an amorphous silicon layer, and the second doping layer 7 in the crystallized region includes nanocrystalline silicon and / or microcrystalline silicon. In this embodiment, when the solar cell further includes a second passivation layer 4, the second passivation layer 4 is located on a side of the second doping layer 7 close to the silicon substrate 3. The second passivation layer 4 can be one or more of intrinsic amorphous silicon, intrinsic microcrystalline silicon, and intrinsic nanocrystalline silicon.

[0076] In some embodiments, the first doping layer 10 in the first region and the second doping layer 7 in the third region are isolated by the second passivation layer 4 in the second region, the second doping layer 7 which is at least partially an amorphized region, the insulating layer 8, the first passivation layer 15, and the first doping layer 10 which is at least partially an amorphized region, and the first doping layer 10 in the first region and the second doping layer 7 in the third region both have crystallized regions. Therefore, the solar cell not only avoids the risk of leakage at the junction between the first region and the third region, but also reduces the contact resistance between the first region and the third region, thereby improving the performance of the solar cell.

[0077] In some embodiments, in the first region, the first doping layer 10 includes a first crystallized region 12 and a first amorphized region A16;

[0078] In the first crystallized region 12 , at least a portion away from the silicon substrate 3 has crystals.

[0079] In some embodiments, Figure 1 As shown, in the first region, the first doped layer 10 includes a first crystallized region 12 and a first amorphized region A16; the first amorphized region A16 includes side portions located at both ends of the first region, and the side portions are stacked on the second doped layer 7 and the side of the insulating layer close to the first region. The first amorphized region A16 also includes an intermediate portion located between the side portion and the first crystallized region, one end of the intermediate portion is connected to a side portion, and the other end of the intermediate portion is connected to the first crystallized region 12. In the case where the first amorphized region A16 includes two intermediate portions, the first crystallized region 12 is arranged between the two intermediate portions. That is, the first amorphized region A extends along the horizontal surface of the first conductive layer 11 away from the first electrode 1 in the direction close to the second region, passes through the side of the first conductive layer 11 close to the second region, until it is connected to the first amorphized region B in the second region. Because the first doped layer 10 and the second doped layer 7 in the prior art are separated by a passivation layer at the junction of the second region (GAP region) and the first region. The passivation layer at the junction is thin, and the first doping layer 10 and the second doping layer 7 are easily overlapped, resulting in leakage. At least part of the first doping layer 10 and the second doping layer 7 in the second region of the present application is an amorphous region. The amorphous part can increase the square resistance of the first doping layer 10 and the second doping layer 7 at the overlap, increase the parallel resistance of the battery, and only partially crystallize the first doping layer 10 and / or the second doping layer 7, which improves the conductivity of the doping layer at the crystallized location. The non-crystallized area can further reduce the risk of leakage at the overlap of the first doping layer 10 and the second doping layer 7.

[0080] Furthermore, the sum of the lengths of the middle portion and the side portion connected thereto stacked on the silicon substrate 3 is L≥5μm, for example, L can be 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, 11μm, 12μm, 13μm, 14μm, 15μm, 16μm, 17μm, 18μm, 19μm, 20μm, etc. If L is too small, the risk of leakage will increase; if L is larger, the risk of leakage will decrease, but at the same time, the area of ​​the crystallization region will decrease, and the degree to which crystallization reduces the series resistance of the battery will also decrease.

[0081] In some embodiments, Fig.17 As shown, the first doped layer 10 includes a first crystallized region 12 and a first amorphized region A16; the first amorphized region A16 includes side portions located at both ends of the first region, and the side portions are stacked on the second doped layer 7 and the side of the insulating layer close to the first region. One end of the two side portions close to the silicon substrate 3 is connected to the two ends of the first crystallized region 12 respectively.

[0082] In some embodiments, in the first region, the first doping layer 10 only includes the first amorphized region A16 , that is, the first doping layer 10 in the entire first region is the first amorphized region A16 .

[0083] In some embodiments, in the first region, the first doping layer 10 includes only the first crystallized region 12 , that is, the first doping layer 10 in the entire first region is the first crystallized region 12 .

[0084] In the present application, in the third region, the second doping layer 7 includes a second crystallized region 5 and / or a second amorphized region A, and at least a portion of the second crystallized region 5 away from the silicon substrate 3 has crystals.

[0085] In some embodiments, in the third region, the second doping layer 7 includes a second crystallized region 5 and a second amorphized region A.

[0086] In some embodiments, in the third region, the second doping layer 7 includes only the second crystallized region 5 .

[0087] In some embodiments, in the third region, the second doping layer 7 includes only the second amorphized region A.

[0088] In some embodiments, in the first region, the first doping layer 10 includes only the first amorphized region, and in the third region, the second doping layer 7 includes only the second crystallized region 5 .

[0089] In some embodiments, in the first region, the first doping layer 10 includes only the first amorphized region, and in the third region, the second doping layer 7 includes the second crystallized region 5 and the second amorphized region.

[0090] In some embodiments, in the first region, the first doping layer 10 includes a first crystallized region 12 and a first amorphized region, and in the third region, the second doping layer 7 includes only a second amorphized region.

[0091] In some embodiments, in the first region, the first doping layer 10 includes a first crystallized region 12 and a first amorphized region, and in the third region, the second doping layer 7 includes only a second crystallized region 5 .

[0092] In some embodiments, in the first region, the first doping layer 10 includes a first crystallized region 12 and a first amorphized region, and in the third region, the second doping layer 7 includes a second crystallized region 5 and a second amorphized region.

[0093] In some embodiments, in the first region, the crystallization rate in the crystallization zone of the first doped layer gradually decreases along the thickness direction from the surface of one side away from the silicon substrate 3 to the side close to the silicon substrate 3; that is, in the first crystallization zone 12, in the direction from the first conductive layer 11 to the silicon substrate 3, the crystallization rate of the first crystallization zone 12 gradually decreases.

[0094] In some embodiments, within the first region, the crystallization rate within the crystallization zone of the first doped layer is equal from the side surface away from the silicon substrate 3 to the side surface close to the silicon substrate 3 along the thickness direction; that is, in some embodiments, within the first crystallization zone 12, the crystallization rate of the first crystallization zone 12 is the same in the direction from the first conductive layer 11 to the silicon substrate 3.

[0095] In some embodiments, in the second crystallization region 5, the crystallization rate in the second crystallization region 5 gradually decreases along the thickness direction from the side surface away from the silicon substrate 3 to the side close to the silicon substrate 3; that is, in the direction from the second conductive layer 6 to the second passivation layer 4, the crystallization rate of the second crystallization region 5 gradually decreases.

[0096] In some embodiments, in the second crystallization region 5, the crystallization rate in the second crystallization region 5 is equal from the surface of one side away from the silicon substrate 3 to the side close to the silicon substrate 3 along the thickness direction; that is, the crystallization rate of the second crystallization region 5 is the same in the direction from the second conductive layer 6 to the second passivation layer 4.

[0097] In the present application, in the second region, at least one side of the first doping layer 10 close to the first region is a first amorphized region B18. The length of the first amorphized region B18 is ≥50 μm, for example, 50 μm, 55 μm, 60 μm, 65 μm, 70 μm, etc.

[0098] At least one side of the second doping layer 7 close to the first region is a second amorphized region B17. The length of the second amorphized region B17 is ≥50 μm, for example, 50 μm, 55 μm, 60 μm, 65 μm, 70 μm, etc.

[0099] In some embodiments, in the second region, the first doped layer 10 includes only the first amorphized region B18. The length of the first amorphized region B18 is ≥50 μm, for example, 50 μm, 55 μm, 60 μm, 65 μm, 70 μm, etc. The first doped layer 10 in the second region is not crystallized at all, which can further reduce the risk of leakage.

[0100] In some embodiments, in the second region, the first doping layer 10 includes a first amorphized region B18 and a first crystallized region B, the first amorphized region B18 is close to the first region, and the first crystallized region B is close to the third region.

[0101] In some embodiments, in the second region, the second doped layer 7 includes only the second amorphized region B17. The length of the second amorphized region B17 is ≥50 μm, for example, 50 μm, 55 μm, 60 μm, 65 μm, 70 μm, etc. The first doped layer 10 in the second region is entirely an amorphous region, which can further reduce the risk of leakage.

[0102] In some embodiments, in the second region, the length of the first amorphized region B18 is ≥50 μm. When the length of the first amorphized region B18 is too short, the isolation effect of the second region on the first region is poor. When the length of the first amorphized region B18 is too long, the conductive region will become smaller, affecting the battery efficiency.

[0103] The length of the second amorphous region B17 is ≥50 μm. When the length of the second amorphous region B17 is too short, the isolation effect of the second region on the third region is poor. When the length of the second amorphous region B17 is too long, the conductive region will become smaller, affecting the battery efficiency.

[0104] In some embodiments, the length of the first amorphized region B18 may be 50 μm-200 μm. The length of the second amorphized region B17 may be 50 μm-200 μm.

[0105] In some embodiments, in the second region, the second doping layer 7 includes a second amorphized region B17 and a second crystallized region B, the second amorphized region B17 is close to the first region, and the second crystallized region B is close to the third region.

[0106] In the present application, the projection of the first electrode 1 on the silicon substrate 3 is smaller than or equal to the projection of the first crystallized region 12 on the silicon substrate 3 . The projection of the second electrode 2 on the silicon substrate 3 is smaller than or equal to the projection of the second crystallized region 5 on the silicon substrate 3 .

[0107] In the present application, the projection of the first crystallized region 12 on the silicon substrate 3 at least partially overlaps with the projection of the first electrode 1 on the silicon substrate 3 .

[0108] In some embodiments, a projection of the first electrode 1 on the silicon substrate 3 crosses and overlaps with a projection of the first crystallized region 12 on the silicon substrate 3 .

[0109] In some embodiments, the projection of the first electrode 1 on the silicon substrate 3 completely overlaps with the projection of the first crystallized region 12 on the silicon substrate 3 .

[0110] In some embodiments, the projection of the first electrode 1 on the silicon substrate 3 coincides with the projection of the first crystallized region 12 on the silicon substrate 3 , and the area of ​​the projection of the first electrode 1 on the silicon substrate 3 is smaller than the area of ​​the projection of the first crystallized region 12 on the silicon substrate 3 .

[0111] In some embodiments, the projection of the first electrode 1 on the silicon substrate 3 coincides with the projection of the first crystallized region 12 on the silicon substrate 3 , and the area of ​​the projection of the first electrode 1 on the silicon substrate 3 is smaller than the area of ​​the projection of the first crystallized region 12 on the silicon substrate 3 .

[0112] In the present application, the projection of the second crystallized region 5 on the silicon substrate 3 at least partially overlaps with the projection of the second electrode 2 on the silicon substrate 3 .

[0113] In some embodiments, a projection of the second electrode 2 on the silicon substrate 3 crosses and overlaps with a projection of the second crystallized region 5 on the silicon substrate 3 .

[0114] In some embodiments, the projection of the second electrode 2 on the silicon substrate 3 completely overlaps with the projection of the second crystallized region 5 on the silicon substrate 3 .

[0115] In some embodiments, the projection of the second electrode 2 on the silicon substrate 3 coincides with the projection of the second crystallized region 5 on the silicon substrate 3 , and the area of ​​the projection of the second electrode 2 on the silicon substrate 3 is smaller than the area of ​​the projection of the second crystallized region 5 on the silicon substrate 3 .

[0116] In some embodiments, the projection of the second electrode 2 on the silicon substrate 3 coincides with the projection of the second crystallized region 5 on the silicon substrate 3 , and the area of ​​the projection of the second electrode 2 on the silicon substrate 3 is smaller than the area of ​​the projection of the second crystallized region 5 on the silicon substrate 3 .

[0117] In some embodiments, the concentration of the doping element in the first crystallized region 12 is greater than the concentration of the doping element in the first amorphized region A16.

[0118] In some embodiments, the concentration of the doping element in the second crystallized region 5 is greater than the concentration of the doping element in the second amorphized region A.

[0119] In the present application, the first crystallized region 12 is a first microcrystalline doping layer, a first polycrystalline doping layer or a first nanocrystalline doping layer.

[0120] The second crystallized region 5 is a second microcrystalline doping layer, a second polycrystalline doping layer or a second nanocrystalline doping layer.

[0121] The first amorphized region A16 and the first amorphized region B18 are both selected from one of a first amorphous silicon doping layer, a first amorphous silicon carbide (SiCx) doping layer or a first amorphous silicon oxide (SiOx) doping layer.

[0122] The second amorphized region A and the second amorphized region B17 are both selected from one of a second amorphous silicon doping layer, a second amorphous silicon carbide (SiCx) doping layer or a second amorphous silicon oxide (SiOx) doping layer.

[0123] The first crystallized region 12 is selected from one of a first crystalline silicon doped layer, a first crystalline silicon carbide (SiCx) doped layer, or a first crystalline silicon oxide (SiOx) doped layer.

[0124] The second crystallized region 5 is selected from one of a second crystalline silicon doped layer, a second crystalline silicon carbide (SiCx) doped layer, or a second crystalline silicon oxide (SiOx) doped layer.

[0125] The thickness of the first amorphized region A16 and the first amorphized region B18 are both 5nm-200nm, for example, can be 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, 65nm, 70nm, 75nm, 80nm, 85nm, 90nm, 95nm, 100nm, 110nm, 120nm, 130nm, 140nm, 150nm, 160nm, 170nm, 180nm, 190nm or 200nm.

[0126] The thickness of the second amorphous region A and the second amorphous region B17 are both 5nm-200nm, for example, can be 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, 65nm, 70nm, 75nm, 80nm, 85nm, 90nm, 95nm, 100nm, 110nm, 120nm, 130nm, 140nm, 150nm, 160nm, 170nm, 180nm, 190nm or 200nm.

[0127] The thickness of the first crystallized region 12 is 5nm-200nm, for example, it can be 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, 65nm, 70nm, 75nm, 80nm, 85nm, 90nm, 95nm, 100nm, 110nm, 120nm, 130nm, 140nm, 150nm, 160nm, 170nm, 180nm, 190nm or 200nm.

[0128] The thickness of the second crystallized region 5 is 5nm-200nm, for example, it can be 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, 65nm, 70nm, 75nm, 80nm, 85nm, 90nm, 95nm, 100nm, 110nm, 120nm, 130nm, 140nm, 150nm, 160nm, 170nm, 180nm, 190nm or 200nm.

[0129] In the present application, in the first region, the crystallization rate of the first doping layer in the crystallization zone is 0.01%-100%, for example, it can be 3%, 5%, 10%, 20%, 25%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, 75%, 80%, 90%, etc.

[0130] In the third region, the crystallization rate of the second doping layer in the crystallization zone is 0.01-100%, for example, it can be 3%, 5%, 10%, 20%, 25%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, 75%, 80%, 90%, etc.

[0131] The crystallization rate can be measured by Raman spectroscopy. Amorphous silicon / silicon carbide / silicon oxide, microcrystalline silicon / silicon carbide / silicon oxide and crystalline silicon / silicon carbide / silicon oxide have different wave numbers, such as amorphous silicon is about 480 / cm, microcrystalline silicon is about 510 / cm, and crystalline silicon is 520.7 / cm. The amount of components affects the Raman spectrum intensity of the corresponding peak, and the crystallization rate is obtained by integral conversion. The crystallization rate is a parameter that characterizes the degree of crystallization. As the crystallization rate increases, the mobility of carriers increases, the effective doping concentration also increases, and the conductivity of the doped layer increases. Microcrystalline silicon has a short-range ordered atomic structure, while amorphous silicon is amorphous silicon. Therefore, the crystallized area, grain size, etc. can be observed by transmission electron microscopy.

[0132] The grain size of the first crystallized region 12 is nanometer-scale and does not exceed 100 nm, for example, it may be 100 nm, 90 nm, 80 nm, 70 nm, 60 nm, 50 nm, 40 nm or 30 nm.

[0133] The grain size of the second crystallized region 5 is nanometer-scale and does not exceed 100 nm, for example, it may be 100 nm, 90 nm, 80 nm, 70 nm, 60 nm, 50 nm, 40 nm or 30 nm.

[0134] The grain size can be observed by transmission electron microscopy.

[0135] In the present application, in the first region, the first crystallized regions 12 are distributed in a continuous or discrete manner.

[0136] In the third region, the second crystallized regions 5 are distributed in a continuous or discrete manner.

[0137] In some embodiments, Figure 1 In the first region, the first crystallized regions 12 are distributed in a continuous manner. In the third region, the second crystallized regions 5 are distributed in a continuous manner.

[0138] In this application, if Figure 1 and Fig.11 As shown, in the first region, the surface where the side portion is located is at an angle α to the surface where the first crystallized region 12 is located, and the value range of α is 0-180°, excluding 0° and 180°.

[0139] Specifically, α can be 10°, 20°, 30°, 40°, 50°, 60°, 70°, 80°, 90°, 100°, 110°, 120°, 130°, 140°, 150°, 160°, 170°, etc.

[0140] In this application, if Fig.12 As shown, in the first region, the side portion may be arc-shaped, and the tangent of the arc surface where the side portion is located is at an angle of α to the surface where the first crystallized region 12 is located, and the value range of α is 0-180°, excluding 0° and 180°.

[0141] Specifically, α can be 10°, 20°, 30°, 40°, 50°, 60°, 70°, 80°, 90°, 100°, 110°, 120°, 130°, 140°, 150°, 160°, 170°, etc.

[0142] In the present application, the first crystallized region 12 and the second crystallized region 5 are both formed by laser irradiation, that is, the first crystallized region 12 and the second crystallized region 5 are both formed by laser irradiation of an amorphous film layer, and a part of the amorphous film layer is converted into crystals under the action of the laser.

[0143] In the present application, the selective effect of the laser can avoid crystallizing the amorphous n / p film layer at the edge of the amorphous n film layer and the amorphous p film layer, maintain its high resistivity, and limit the lateral leakage current. At the same time, the first crystallized region 12 and the second crystallized region 5 can be crystallized to increase the effective doping concentration and reduce the contact resistance, which is beneficial to reduce the resistance loss of the battery.

[0144] The wavelength of the laser will affect its absorption depth in the amorphous film and the longitudinal range of action in the film layer. The longer the wavelength of the laser, the deeper the absorption depth, and the easier it is for the amorphous to transform into a crystal in the longitudinal or thickness direction. In practical applications, the wavelength of the laser can be determined according to actual needs.

[0145] The greater the laser power, the greater the energy generated by the laser, and the easier it is to transform amorphous materials into crystals.

[0146] Laser power, laser spot overlap rate, laser pulse width, and laser irradiation times affect the laser energy received per unit area, the crystallization range, the crystallization rate, and the degree of passivation damage to the silicon wafer surface under the film layer. The greater the laser energy, the easier it is for amorphous to be converted into crystal, but the higher the degree of passivation damage to the silicon wafer surface. Therefore, in the application, the various parameters of the laser can be designed according to the actual situation.

[0147] In the present application, the single spot energy density of the functional laser can be used to characterize the laser energy, and those skilled in the art can control the laser energy by adjusting the above parameters.

[0148] In the method of the present application, for example, the following single spot energy density of the laser can be used, for example, the single spot energy density of the laser> 60mJ / cm 2 . For example, it can be 61mJ / cm 2 、65mJ / cm 2 、70mJ / cm 2 、75mJ / cm 2 、80mJ / cm 2 、85mJ / cm 2 、90mJ / cm 2 、100mJ / cm 2 、110mJ / cm 2 、120mJ / cm 2 、130mJ / cm 2 、140mJ / cm 2 、150mJ / cm 2 、160mJ / cm 2 、170mJ / cm 2 、180mJ / cm 2 、190mJ / cm2 、200mJ / cm 2 wait.

[0149] Embodiment 2:

[0150] The silicon substrate 3 further includes a third region on one side of the surface. Along the first direction, the third region is located on the side of the second region away from the first region. That is, the silicon substrate 3 includes the first region, the second region and the third region which are adjacent to each other in sequence along the first direction.

[0151] On the third region, a second doping layer 7 and a second electrode 2 are sequentially stacked on the silicon substrate 3;

[0152] The second doped layer 7 extends to the second region; and in the second region, the second doped layer 7 is located on the side of the first doped layer 10 close to the silicon substrate 3; the conductivity of the first doped layer 10 is opposite to that of the second doped layer 7, so as to respectively collect and export electrons and holes, thereby facilitating the formation of photocurrent.

[0153] In some embodiments, the second doped layer 7 includes doped polysilicon. Doped polysilicon has a high current transmission capacity, so when the second doped semiconductor layer is a doped polysilicon layer, the carrier recombination rate can be further reduced, which is beneficial to improving the photoelectric conversion efficiency of the hybrid solar cell.

[0154] like Fig.18 As shown, the solar cell further includes a second passivation layer 4, and the second passivation layer 4 is located on a side of the second doped layer 7 close to the silicon substrate 3. That is, the second passivation layer 4 is located between the second doped layer 7 and the silicon substrate 3. For example, when the second doped layer 7 is doped polycrystalline silicon, the second passivation layer 4 may be a tunneling oxide layer, so that the second doped layer 7 and the second passivation layer 4 form a tunneling oxide layer passivation contact. The tunneling oxide layer passivation technology can form a tunneling film between the second electrode 2 and the silicon substrate 3, isolating the second electrode 2 from contacting the silicon substrate 3, reducing contact recombination losses, and electrons can tunnel through the film without affecting current transfer. At the same time, passivation can bend the surface energy band, reduce the surface recombination losses of the silicon wafer, and effectively improve the front passivation and metal contact problems.

[0155] In some embodiments, the first doping layer 10 in the amorphous region may be an amorphous silicon layer, and the first doping layer 10 in the crystallized region includes nanocrystalline silicon and / or microcrystalline silicon. Fig.18 As shown, the solar cell also includes a first passivation layer, which is located between the silicon substrate 3 and the first doping layer 10, that is, the first passivation layer is located on the side of the first doping layer 10 close to the silicon substrate 3, and the first passivation layer can be one or more of intrinsic amorphous silicon, intrinsic microcrystalline silicon and intrinsic nanocrystalline silicon.

[0156] In some embodiments, in the first region, the first doping layer 10 includes a first crystallized region 12 and a first amorphized region A16;

[0157] In the first crystallized region 12 , at least a portion away from the silicon substrate 3 has crystals.

[0158] like Figure 1 As shown, in the first region, the first doped layer 10 includes a first crystallized region 12 and a first amorphized region A16; the first amorphized region A16 includes side portions located at both ends of the first region, and the side portions are stacked on the side of the second doped layer 7 close to the first region. The first amorphized region A16 also includes a middle portion located between the side portions and the first crystallized region, one end of the middle portion is connected to a side portion, and the other end of the middle portion is connected to the first crystallized region 12. The passivation layer at the junction is thin, and it is easy for the first doped layer 10 and the second doped layer 7 to overlap, resulting in leakage. In this way, the side portion belongs to the amorphized region, which can avoid the first doped layer 10 and the second doped layer 7 from overlapping, resulting in leakage.

[0159] like Fig.18 As shown, the sum of the lengths of the middle portion and the side portion connected thereto stacked on the silicon substrate 3 is L≥5μm, for example, L can be 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, 11μm, 12μm, 13μm, 14μm, 15μm, 16μm, 17μm, 18μm, 19μm, 20μm, etc. If L is too small, the risk of leakage will increase; the larger L is, the smaller the risk of leakage, but at the same time, the area of ​​the crystallization action region is reduced, and the degree to which crystallization reduces the series resistance of the battery is also smaller.

[0160] In the second embodiment, the features of the first doping layer 10 and the first electrode, and the features of the silicon substrate can refer to those of the first embodiment, and will not be described in detail here.

[0161] The following contents are applicable to Embodiment 1 to Embodiment 2 and other embodiments.

[0162] In some embodiments, Fig.18 As shown, the solar cell further includes a first conductive layer 11, which is located between the first doped layer and the first electrode 1. In addition, the solar cell may further include a second conductive layer 6, which is located between the second doped layer and the second electrode 2. The conductive layer has a high electrical conductivity, and can timely guide the collected carriers to reduce the carrier recombination rate.

[0163] In some embodiments, in the first region, a first passivation layer 15 is further provided between the silicon substrate 3 and the first doped layer 10, and a first conductive layer 11 is further provided between the first doped layer 10 and the first electrode 1; that is, in the first region, the first passivation layer 15, the first doped layer 10, the first conductive layer 11 and the first electrode 1 are sequentially stacked on the silicon substrate 3.

[0164] In the third region, a second passivation layer 4 is further arranged between the silicon substrate 3 and the second doped layer 7, and a second conductive layer 6 is further arranged between the second doped layer 7 and the second electrode 2; that is, in the third region, the second passivation layer 4, the second doped layer 7, the second conductive layer 6 and the second electrode 2 are sequentially stacked on the silicon substrate 3.

[0165] The first passivation layer 15 and the second passivation layer 4 extend to the second region, so that the second passivation layer 4, the second doping layer 7, the first passivation layer 15, and the first doping layer 10 are sequentially stacked on the silicon substrate 3 in the second region. In some embodiments, in the second region, an insulating layer 8 is disposed between the first passivation layer 15 and the second doping layer 7; that is, in the second region, the second passivation layer 4, the second doping layer 7, the insulating layer 8, the first passivation layer 15, and the first doping layer 10 are sequentially stacked on the silicon substrate 3.

[0166] The silicon substrate 3 includes a light-facing surface and a backlight surface, which are arranged relative to each other. The backlight surface of the silicon substrate 3 includes a first region and a second region adjacent to each other along a first direction. Adjacent here means that the first region and the second region are connected in sequence but do not overlap. The relative position and relative size of the first region are not specifically limited.

[0167] In some embodiments, the silicon substrate 3 , the first passivation layer 15 , the first doping layer 10 , the second passivation layer 4 , and the second doping layer 7 all have a textured structure.

[0168] In some embodiments, the silicon substrate 3 , the first passivation layer 15 , the first doping layer 10 , the second passivation layer 4 , and the second doping layer 7 all have smooth surfaces.

[0169] In some embodiments, the silicon substrate 3 , the first passivation layer 15 , and the first doping layer 10 in the first region have a textured surface.

[0170] In some embodiments, the silicon substrate 3 , the first passivation layer 15 , and the first doping layer 10 in the first region are smooth surfaces.

[0171] In the case where one side surface of the silicon substrate further includes the third region, each functional layer in the third region has a smooth surface, or each functional layer in the third region has a suede structure.

[0172] Specifically, the light incident surface passivation layer 13 and the anti-reflection layer 14 are sequentially stacked on the surface of the silicon substrate 3 facing away from the first passivation layer 15 and the second passivation layer 4. That is, the light-facing surface of the silicon substrate 3 is sequentially stacked with the light incident surface passivation layer 13 and the anti-reflection layer 14.

[0173] The silicon substrate 3 may be a p-type doped silicon substrate 3 or an n-type doped silicon substrate 3 .

[0174] The light-entering surface passivation layer 13 is intrinsic hydrogenated amorphous silicon, and its thickness is 1-20nm, for example, it can be 1nm, 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm, 10nm, 11nm, 12nm, 13nm, 14nm, 15nm, 16nm, 17nm, 18nm, 19nm or 20nm.

[0175] The anti-reflection layer 14 is silicon nitride, silicon oxide, magnesium fluoride, etc., or a composite anti-reflection structure composed of silicon nitride, silicon oxide, and magnesium fluoride, and its thickness does not exceed 200nm. For example, it can be 200nm, 190nm, 180nm, 170nm, 160nm, 150nm, 140nm, 130nm, 120nm, 110nm, 100nm, 90nm, 80nm, 70nm, 60nm, 50nm, 40nm, 30nm, etc.

[0176] The insulating layer 8 is a silicon nitride layer, i.e., a SiNx layer, wherein x represents a different silicon-nitrogen ratio. Different SiNx are generally represented by different refractive indices, which are 1.9-2.7. The thickness is 30-200nm, for example, 200nm, 190nm, 180nm, 170nm, 160nm, 150nm, 140nm, 130nm, 120nm, 110nm, 100nm, 90nm, 80nm, 70nm, 60nm, 50nm, 40nm, 30nm, etc.

[0177] The first passivation layer 15 may be intrinsic hydrogenated amorphous silicon with a thickness of 1 nm-20 nm, for example, 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, 16 nm, 17 nm, 18 nm, 19 nm or 20 nm.

[0178] The second passivation layer 4 can be an intrinsic hydrogenated amorphous silicon or a tunneling oxide layer with a thickness of 1nm-20nm, for example, 1nm, 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm, 10nm, 11nm, 12nm, 13nm, 14nm, 15nm, 16nm, 17nm, 18nm, 19nm or 20nm.

[0179] The first passivation layer 15 and the second passivation layer 4 are different layers, and may have different hydrogen contents, thicknesses, and processes, for example.

[0180] The first conductive layer 11 is a TCO layer, and the thickness thereof is 5 nm-200 nm, for example, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, 160 nm, 170 nm, 180 nm, 190 or 200 nm.

[0181] The second conductive layer 6 is a TCO layer, and the thickness thereof is 5 nm-200 nm, for example, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, 160 nm, 170 nm, 180 nm, 190 or 200 nm.

[0182] The first electrode 1 is made of silver, aluminum, copper or alloys thereof.

[0183] The second electrode 2 is made of silver, aluminum, copper or an alloy thereof.

[0184] In some embodiments, the thickness of the first doping layer is phosphorus or boron. Exemplarily, the thickness of the first doping layer is phosphorus, and the element doped in the second doping layer is boron; or, when the element doped in the first doping layer is boron, the element doped in the second doping layer is phosphorus.

[0185] In some embodiments, the thickness of the first doping layer is 5nm-200nm, for example, it can be 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, 65nm, 70nm, 75nm, 80nm, 85nm, 90nm, 95nm, 100nm, 110nm, 120nm, 130nm, 140nm, 150nm, 160nm, 170nm, 180nm, 190nm or 200nm.

[0186] The thickness of the second doping layer is 5nm-200nm, for example, it can be 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, 65nm, 70nm, 75nm, 80nm, 85nm, 90nm, 95nm, 100nm, 110nm, 120nm, 130nm, 140nm, 150nm, 160nm, 170nm, 180nm, 190nm or 200nm.

[0187] The present application further provides a solar cell, comprising a silicon substrate 3, and a first doped layer disposed on a surface of one side of the silicon substrate. The first doped layer comprises a first part and a second part, wherein the first part and the second part are adjacent to each other along a second direction. That is, along the second direction, both sides of the first part are adjacent to the second part, or one side of the first part is adjacent to the second part. The second direction is parallel to the surface of the silicon substrate 3, and the second direction may be parallel to the arrangement direction of the first region, the second region, and the third region. The degree of crystallization of the first part is greater than the degree of crystallization of the second part. The first doped layer may comprise at least one of amorphous silicon, nanocrystalline silicon, and microcrystalline silicon, that is, the first doped layer may be an amorphous silicon layer, a nanocrystalline silicon layer, or a microcrystalline silicon layer. Alternatively, the first doped layer may also be a combination of any two or three of amorphous silicon, nanocrystalline silicon, and microcrystalline silicon, and the degree of crystallization of amorphous silicon, nanocrystalline silicon, and microcrystalline silicon may be improved after laser crystallization.

[0188] In the case of adopting the above technical solution, a crystallized structure is formed in the first part of the first doped layer, so that the first part has a crystallized part and another part that is not crystallized. The first part is not entirely a crystallized structure, but mostly an amorphous structure, and only a part forms a crystallized structure, such as nanocrystal, while the second part of the first doped layer adjacent to the first part along the second direction is not crystallized, retaining the original amorphous structure (it should be noted that when the first doped layer includes nanocrystalline silicon and microcrystalline silicon, the crystallization degree or crystallinity of the nanocrystalline silicon and microcrystalline silicon of the second part remains unchanged), so that the overall crystallization degree of the first part of the first doped layer is greater than the overall crystallization degree of the second part. It can be understood that, under the same other factors, when the crystallization degree of the semiconductor layer is smaller, the grains in the semiconductor layer are smaller, and even present the disorder of amorphous silicon material. The smaller the grains in the semiconductor layer, the more interfaces between the grains in the semiconductor layer, so the resistance of the grain interface will be larger. Therefore, the crystallization structure in the first part of the first doping layer reduces the contact resistance, reduces the contact resistance between the first part and the conductive material (transparent conductive layer or electrode), and thus helps to reduce the transmission loss of the carriers collected in the first doping layer to the conductive material. At the same time, the degree of crystallization of the second part of the first doping layer is less than that of the first part, which ensures the passivation effect of the second part adjacent to the first part along the second direction, and reduces the recombination of the edge of the first doping layer, that is, for the back contact solar cell, the second part of the first doping layer is close to the second semiconductor, and the degree of crystallization of the second part is small to ensure the passivation effect of the second part, and prevent leakage between the second part and the second doping layer 7. It can be seen from the above that by setting a reasonable crystallization area and amorphization area on the first doping layer, the higher degree of crystallization of the first part is used to optimize the overall cell efficiency of the solar cell, thereby improving the cell efficiency, and at the same time, the lower degree of crystallization of the second part is used to ensure the passivation effect of the second part and prevent leakage.

[0189] The present application also provides a method for preparing a solar cell, comprising the following steps:

[0190] Step 1: providing a silicon substrate 3, wherein a surface of one side of the silicon substrate 3 includes a first region and a second region adjacent to each other along a first direction;

[0191] Step 2: forming a first doped layer in the first region and the second region of the silicon substrate 3; the first doped layer 10 is a first amorphous doped layer;

[0192] Step 3: performing crystallization treatment on at least a portion of the first doped layer 1 in the first region, so that at least a portion of the first doped layer 10 in the first region has a crystallized region;

[0193] Step 4: forming a first electrode 1 in the first region so that a projection of the crystallized region on the silicon substrate 3 at least partially overlaps with a projection of the first electrode 1 on the silicon substrate 3 .

[0194] In some embodiments, a third region is further included on one side surface of the silicon substrate 3 . Along the first direction, the third region is located on a side of the second region away from the first region.

[0195] The method for preparing a solar cell further comprises the steps of:

[0196] A second doping layer 7 is formed in the third region and the second region of the silicon substrate 3; in the second region, the second doping layer 7 is located on a side of the first doping layer close to the silicon substrate 3; the first doping layer and the second doping layer 7 have opposite conductivity;

[0197] The second electrode 2 is formed in the third region.

[0198] It can be understood that in the above preparation method, after providing the silicon substrate 3, before forming the first doping layer in the first area and the second area of ​​the silicon substrate 3, it also includes forming a second doping layer 7 in the third area and the second area of ​​the silicon substrate 3; in the second area, the second doping layer 7 is located on the side of the first doping layer close to the silicon substrate 3.

[0199] The second electrode 2 may be formed in the third region at the same time as the first electrode 1 is formed in the first region. Alternatively, the first electrode 1 may be formed first and then the second electrode 2 , or the second electrode 2 may be formed first and then the first electrode 1 .

[0200] Exemplarily, the method for preparing the solar cell comprises the following steps:

[0201] Step 1: providing a silicon substrate 3, wherein a surface of one side of the silicon substrate 3 comprises a first region, a second region and a third region adjacent to each other in sequence;

[0202] Step 2: forming a second doping layer 7 in the first region, the second region and the third region of the silicon substrate 3;

[0203] Step 3: removing the second doping layer 7 in the first region to expose the silicon substrate 3;

[0204] Step 4: forming a first doping layer 10 on the silicon substrate 3 in the first region, the second region and the third region; the first doping layer 10 is a first amorphous doping layer;

[0205] Step 5: performing a crystallization process on the first doped layer 1 in the first region, so that the first doped layer 10 in the first region has a crystallized region;

[0206] Step six: forming a first electrode 1 and a second electrode 2 in the first region and the third region respectively, so that a projection of the crystallized region on the silicon substrate 3 at least partially overlaps with a projection of the first electrode 1 on the silicon substrate 3 .

[0207] In some embodiments, the second doped layer 7 is a polysilicon doped layer. Doped polysilicon has a high current transmission capacity, so when the second doped semiconductor layer is a doped polysilicon layer, the carrier recombination rate can be further reduced, which is beneficial to improving the photoelectric conversion efficiency of the hybrid solar cell.

[0208] In some embodiments, the method for preparing a solar cell further comprises the steps of:

[0209] Performing a crystallization process on at least a portion of the second doped layer 7 in the third region, so that at least a portion of the second doped layer 7 in the third region forms a crystallized region;

[0210] The projection of the crystallized region in the third area on the silicon substrate 3 at least partially overlaps with the projection of the second electrode 2 on the silicon substrate 3 .

[0211] It can be understood that in the above preparation method, after providing the silicon substrate 3, before forming the first doping layer in the first area and the second area of ​​the silicon substrate 3, it also includes forming a second doping layer 7 in the third area and the second area of ​​the silicon substrate; in the second area, the second doping layer 7 is located on the side of the first doping layer close to the silicon substrate.

[0212] The crystallization of at least a portion of the first doped layer in the first region and the crystallization of at least a portion of the second doped layer 7 in the third region can be performed simultaneously or separately. The formation of the second electrode 2 in the third region and the formation of the first electrode 1 in the first region can be performed simultaneously or separately.

[0213] Exemplarily, a method for preparing a solar cell comprises the following steps:

[0214] Step 1: providing a silicon substrate 3, wherein a surface of one side of the silicon substrate 3 comprises a first region, a second region and a third region adjacent to each other in sequence;

[0215] Step 2: forming a second doping layer 7 in the first region, the second region and the third region of the silicon substrate 3; the second doping layer 7 is a second amorphous doping layer;

[0216] Step 3: removing the second doping layer 7 in the first region to expose the silicon substrate 3;

[0217] Step 4: forming a first doping layer 10 on the silicon substrate 3 in the first region, the second region and the third region; the first doping layer 10 is a first amorphous doping layer;

[0218] Step 5: removing the first doped layer 10 in the third region to expose the second doped layer 7;

[0219] Step 6: performing crystallization treatment on the first doping layer 10 in the first region and / or the second doping layer 7 in the third region, so that at least one of the first doping layer 10 in the first region and the second doping layer 7 in the third region has a crystallized region;

[0220] Step 7: forming a first electrode 1 and a second electrode 2 in the first region and the third region respectively, so that a projection of the crystallized region on the silicon substrate 3 at least partially overlaps with a projection of the first electrode 1 on the silicon substrate 3, and / or a projection of the crystallized region on the silicon substrate 3 at least partially overlaps with a projection of the second electrode 2 on the silicon substrate 3;

[0221] The first doped layer 10 has an opposite conductivity to that of the second doped layer 7 .

[0222] In some embodiments, after crystallizing at least a portion of the first doped layer 7 in the first region, before forming the first electrode 1 in the first region, a first conductive layer 11 is further formed in the first region. The first electrode 1 is directly formed on the side of the first conductive layer 11 away from the silicon substrate 3. In the case where the third region also includes the second conductive layer 6, the first conductive layer 11 and the second conductive layer 6 can be formed in the same step, for example: before forming the first electrode 1 in the first region and before forming the second electrode in the third region, a conductive layer is further formed on the surface of one side of the silicon substrate; the portion of the conductive layer corresponding to the first region is the first conductive layer 11, and the portion of the conductive layer corresponding to the second region is the second conductive layer 6, and the conductive layer has an opening running through its thickness to separate the first conductive layer 11 and the second conductive layer 6. The first conductive layer 11 is located between the first doped layer and the first electrode 1, and the second conductive layer 6 is located between the second doped layer 7 and the second electrode, so that the first conductive layer 11 and the second conductive layer 6 can be processed and formed in the same step, thereby improving the processing efficiency.

[0223] In step 1, the silicon substrate 3 may be p-type doped or n-type doped.

[0224] In some embodiments, the front side of the silicon substrate 3 is a velvet surface, and the back side is a flat surface.

[0225] In some embodiments, both the front and back sides of the silicon substrate 3 are velvet surfaces.

[0226] In some embodiments, the back side of the silicon substrate 3 is a velvet surface, and the front side is a flat surface.

[0227] In some embodiments, the front side and the back side of the silicon substrate 3 are both planar.

[0228] In some embodiments, the back side of the silicon substrate 3 has a textured surface.

[0229] When the silicon substrate 3 has a suede structure, the actual contact areas between the silicon substrate 3 and the amorphous film layer, the amorphous film layer and the TCO film layer, and the TCO film layer and the metal electrode grid line can be increased, thereby reducing the battery series resistance.

[0230] In step 2, if Figure 2 A second passivation layer 4 , a second doping layer 7 and an insulating layer 8 are sequentially formed on the backlight surface of the silicon substrate 3 , and a laser absorption layer 9 is formed on the entire surface of the insulating layer 8 .

[0231] There is no further limitation on the formation methods of the second passivation layer 4, the second doping layer 7, the insulating layer 8 and the laser absorption layer 9. For example, the second passivation layer 4 can be prepared by plasma enhanced CVD (PECVD) or hot wire CVD (cat-CVD), the second doping layer 7 can be prepared by PECVD, the insulating layer 8 can be prepared by PECVD, and the laser absorption layer 9 can be prepared by PECVD.

[0232] In step three, if Figure 3-Figure 5 As shown, after the laser absorption layer 9, the insulating layer 8, the second doping layer 7 and the second passivation layer 4 in the first region are removed in sequence to expose the silicon substrate 3, the laser absorption layer 9 in the second region and the third region is removed.

[0233] There is no further limitation on the method of removing the laser absorption layer 9, the insulating layer 8, the second doping layer 7, and the second passivation layer 4. For example, the laser absorption layer 9, the insulating layer 8, the second doping layer 7, and the second passivation layer 4 may be removed as follows:

[0234] Step 3.1: Remove the laser absorption layer 9 in the first region by laser ablation, thereby exposing the insulating layer 8 thereunder.

[0235] Step 3.2: Use a wet process to remove the exposed insulating layer 8 using an acidic solution, thereby exposing the second doping layer 7 thereunder. The acidic solution is not further limited, and may be, for example, a hydrofluoric acid solution.

[0236] Step 3.3: Use an alkaline solution to remove the exposed second doping layer 7 and the second passivation layer 4 under the second doping layer 7, thereby exposing the silicon substrate 3 in the first region and removing the laser absorption layer 9 in the second region and the third region. The alkaline solution is not further limited, and can be, for example, potassium hydroxide, sodium hydroxide, etc.

[0237] The laser absorption layer 9 is used to protect the insulating layer 8 and the second doping layer 7 in the second region and the third region from being damaged when performing steps 3.1-3.2.

[0238] Step 3.4: Texturing is performed on the silicon substrate 3 in the first area.

[0239] In some embodiments, step 3.4 may not be performed.

[0240] In step 4, if Figure 6 As shown, a first passivation layer 15 and a first doping layer 10 are sequentially formed on the silicon substrate 3 in the first region and on the insulating layer 8 in the second region and the third region, and the formation method of the first passivation layer 15 and the first doping layer 10 is not further limited. For example, the first passivation layer 15 is formed by PECVD, and the first doping layer 10 is prepared by PECVD.

[0241] In step five, if Figure 7-Figure 9 As shown, the first doped layer 10, the first passivation layer 15 and the insulating layer 8 in the third region are removed in sequence. The method for removing the first doped layer 10, the first passivation layer 15 and the insulating layer 8 is not further limited. For example, the method for removing the first doped layer 10, the first passivation layer 15 and the insulating layer 8 is as follows:

[0242] Step 5.1: Use laser to remove the first doped layer 10 in the third region, so as to expose the insulating layer 8 thereunder.

[0243] Step 5.2: Use a wet method to remove the exposed insulating layer 8 using an acidic solution, thereby exposing the second doping layer 7 thereunder. The acidic solution is not specifically limited, and can be, for example, a hydrofluoric acid solution.

[0244] Before step 6, step 5.3 may also be included, such as Fig.10 As shown, a light incident surface passivation layer 13 and an anti-reflection layer 14 are sequentially formed on the light-facing surface of the silicon substrate 3. The formation methods of the light incident surface passivation layer 13 and the anti-reflection layer 14 are not specifically limited. For example, the light incident surface passivation layer 13 is prepared by PECVD, and the anti-reflection layer 14 is prepared by PECVD.

[0245] In step six, laser is used to irradiate the first doping layer in the first region and / or the second doping layer in the third region, so that at least one of the first doping layer in the first region and the second doping layer in the third region forms a crystallized region, and the effective doping concentration of the doping element in the first crystallized region 12 and / or the second crystallized region 5 is increased.

[0246] In some embodiments, Fig.10As shown, laser is used to irradiate the first region and the third region. Under the action of the laser, part of the first doped layer in the first region undergoes crystallization transformation, so that the first doped layer 10 in the first region includes a first amorphous region A16 and a first crystallized region 12, and the entire second doped layer in the third region undergoes crystallization transformation, so that the second doped layer 7 in the third region becomes a second crystallized region 5.

[0247] In some embodiments, the third region is irradiated with laser, and under the action of the laser, part of the second doped layer in the third region undergoes crystal transformation.

[0248] In some embodiments, when the first doped layer in the first region has a textured surface, only the raised portions of the textured surface in the laser irradiated region undergo crystal transformation, while the recessed portions do not undergo crystal transformation.

[0249] In some embodiments, when the first doped layer in the first region has a smooth surface, the first doped layer in the laser irradiation region undergoes crystal transformation.

[0250] In some embodiments, when the second doped layer in the third region has a textured surface, only the raised portions of the textured surface in the laser irradiated region undergo crystal transformation, while the recessed portions do not undergo crystal transformation.

[0251] In some embodiments, when the second doped layer in the third region has a smooth surface, the second doped layer in the laser irradiation region undergoes crystal transformation.

[0252] The wavelength of the laser will affect its absorption depth in the amorphous film and the longitudinal range of action in the film layer. The longer the wavelength of the laser, the deeper the absorption depth, and the easier it is for the amorphous to transform into a crystal in the longitudinal or thickness direction. In practical applications, the wavelength of the laser can be determined according to actual needs.

[0253] The greater the laser power, the greater the energy generated by the laser, and the easier it is to transform amorphous materials into crystals.

[0254] Laser power, laser spot overlap rate, laser pulse width, and laser irradiation times affect the laser energy received per unit area, the crystallization range, crystallization rate, and the degree of passivation damage to the silicon wafer surface under the film layer. The greater the laser energy, the easier it is for amorphous to be converted into crystal, but the higher the degree of passivation damage to the silicon wafer surface. Therefore, in the application, the various parameters of the laser can be designed according to the actual situation.

[0255] In step seven, a first electrode 1 and a second electrode 2 are formed on the product obtained in step six, which specifically includes the following steps:

[0256] Step 7.1: Depositing a whole conductive layer on the first region, the second region and the third region.

[0257] Step 7.2: Remove the conductive layer on the second area, for example, by using laser or photolithography to remove the conductive layer on the second area, so that there are conductive layers only in the first area and the third area, the conductive layer in the first area is the first conductive layer 11, and the conductive layer in the third area is the second conductive layer 6.

[0258] The first conductive layer 11 is disposed on a surface of the first doping layer 10 that is away from the first passivation layer 15 .

[0259] The second conductive layer 6 is located on a surface of the second doped layer 7 that is away from the second passivation layer 4 .

[0260] Step 7.3: Form a first electrode 1 and a second electrode 2 on the first conductive layer 11 and the second conductive layer 6 respectively.

[0261] The formation methods of the first conductive layer 11, the first electrode 1, the second conductive layer 6 and the second electrode 2 are not specifically limited. For example, the first conductive layer 11 and the second conductive layer 6 are formed at the same time, and the first conductive layer 11 and the second conductive layer 6 are formed by PVD (Physical Vapor Deposition), RPD (Reactive Plasma Deposition), etc. The first conductive layer 11 and the second conductive layer 6 can be ITO (Indium tin oxide), IWO (tungsten-doped indium oxide), AZO (aluminum-doped zinc oxide), etc. The first electrode 1 and the second electrode 2 are obtained by electroplating or screen printing.

[0262] The solar cell prepared by the preparation method of the present application is the aforementioned solar cell, and the various parts of the solar cell can refer to the aforementioned description.

[0263] The present application also provides a battery assembly, comprising the aforementioned solar cell.

[0264] Example

[0265] The experimental methods used in the following examples are all conventional methods unless otherwise specified.

[0266] Unless otherwise specified, the materials and reagents used in the following examples can be obtained from commercial sources.

[0267] Example 1.1

[0268] The solar cell of this embodiment, and its preparation method, comprises the following steps:

[0269] Step 1: Polish and clean the silicon wafer, and perform texturing on the light-incident surface.

[0270] Step 2: PECVD is used to deposit a 5nm intrinsic hydrogenated amorphous silicon passivation layer, a 30nm amorphous n layer, a 100nm SiNx layer (refractive index 2.5), and a 30nm laser absorption layer on the back of the battery.

[0271] Step 3: Use laser to remove the laser absorption layer in the first region, thereby forming a laser opening to expose the SiNx layer.

[0272] Step 4: Perform a wet process, use 10% concentration hydrofluoric acid to remove the SiNx layer in the laser opening to expose the amorphous n layer, and use 10% concentration potassium hydroxide to remove the exposed amorphous n layer, the intrinsic hydrogenated amorphous silicon passivation layer underneath, and the laser absorption layer in the second and third regions, thereby exposing the silicon wafer in the first region and the silicon nitride layer in the second and third regions.

[0273] Step 5: On the back side of the battery, a 5nm intrinsic hydrogenated amorphous silicon passivation layer and a 30nm amorphous p-layer are sequentially deposited on the silicon wafer in the first area, the silicon nitride layer in the second area, and the silicon nitride layer in the third area using PECVD technology.

[0274] Step 6: Use laser (the energy density of the laser spot is 200mJ / cm 2 ) removing the amorphous p layer and the intrinsic hydrogenated amorphous silicon passivation layer in the third region to form an opening, thereby exposing the SiNx layer in the third region.

[0275] Step 7: Perform a wet treatment and use 10% concentration hydrofluoric acid to remove the SiNx layer in the third region.

[0276] Step 8: Use PECVD to deposit an intrinsic hydrogenated amorphous silicon passivation layer and a SiNx anti-reflection film on the light-incident surface, with a refractive index of 2 and a thickness of 70nm.

[0277] Step 9: Perform laser crystallization treatment, using laser to crystallize the middle area of ​​the amorphous p layer in the first region into a nanocrystalline p region, that is, the first nanocrystalline silicon p-doped region and the first amorphous silicon p-doped region exist in the first region at the same time, the first amorphous silicon p-doped region surrounds the first nanocrystalline silicon p-doped region, and the part of the amorphous n layer and the electrode stack in the third region is crystallized into a nanocrystalline n region.

[0278] Step 10: sequentially depositing a TCO layer and an Ag electrode (first electrode) on the nanocrystalline p-layer; sequentially depositing a TCO layer and an Ag electrode (second electrode) on the nanocrystalline n-layer.

[0279] The Raman spectrum of the second doping layer in the third region of this embodiment is shown in FIG. Fig.13 , and its transmission electron microscope image is shown in Fig.14 .

[0280] The difference between Example 2 and Example 1 is that step 9 is different. In this example, only the middle area of ​​the amorphous p-layer in the first region is laser processed, so that only the middle area of ​​the amorphous p-layer in the first region undergoes crystallization. The normalized parallel resistance of the solar cell in this example is shown in Fig.15 The normalized series resistance of the solar cell in this embodiment is shown in Fig.16 .

[0281] The difference between Example 3 and Example 1 is that step 9 is different. In this embodiment, only the amorphous n-layer in the third region is laser processed, so that only the amorphous n-layer in the third region undergoes crystallization. The normalized parallel resistance of the solar cell in this embodiment is shown in Fig.15 The normalized series resistance of the solar cell in this embodiment is shown in Fig.16 .

[0282] The difference between Comparative Example 1 and Example 1 is that there is no laser treatment step in step 9 in Comparative Example 1, and other parameters are the same as those in Example 1. The Raman spectrum of the first doped layer in the first region of the solar cell of this comparative example is shown in FIG. Fig.13 The normalized parallel resistance of the solar cell in this comparative example is shown in Fig.15 The normalized series resistance of the solar cell in this comparative example is shown in Fig.16 .

[0283] The difference between Comparative Example 2 and Example 1 is that the amorphous p-layer in the first region is not laser treated, that is, the amorphous p-layer in the first region is not crystallized at all, and the second amorphous silicon doped layer in the second region is replaced by a second nanocrystalline silicon doped layer. The normalized parallel resistance of the solar cell in this example is shown in FIG. Fig.15 .

[0284] For the above-mentioned Examples 2-3 and Comparative Examples 1 and 2, the normalized parallel resistance of the solar cells obtained therefrom was tested using the FCT650 machine under standard test conditions. The results are as follows: Fig.15 For the above-mentioned Examples 2-3 and Comparative Example 1, the normalized series resistance of the solar cell obtained was tested under standard test conditions using the FCT650 machine. Fig.16 shown.

[0285] Summary: Fig.13 and Fig.14 It can be seen that in the solar cell of this embodiment, under the action of laser, the amorphous silicon on the side of the first doping layer close to the first conductive layer is converted into crystalline silicon. The characteristic peak of the amorphous silicon film layer is at 480cm -1 Nearby, the characteristic peak of the crystallized silicon film layer is at 510cm -1 Compared with the film without laser treatment, the laser treated film has a-1 A peak appears at , indicating that amorphous silicon is crystallized after the laser action.

[0286] Depend on Fig.15 It can be seen that the parallel resistance of the battery in comparative example 2 is 3-4 orders of magnitude lower than the parallel resistance of the battery in examples 2 and 3. The parallel resistance of the battery in examples 2 and 3 is slightly different from the parallel resistance of comparative example 1. The larger the parallel resistance, the smaller the leakage. It can be seen that the solar cell structure of the present application can avoid the serious leakage problem in the whole surface crystal film structure.

[0287] Depend on Fig.16 It can be seen that the series resistance of the solar cell of the present application is significantly reduced compared with Comparative Example 1. The reduction of contact resistance will increase the fill factor, thereby improving the cell efficiency.

[0288] Although the embodiments of the present application are described above in conjunction with the accompanying drawings, the present application is not limited to the above specific embodiments and application fields, and the above specific embodiments are merely illustrative and instructive, rather than restrictive. A person of ordinary skill in the art can also make many forms under the guidance of this specification and without departing from the scope of protection of the claims of the present application, all of which belong to the protection of the present application.

Claims

1. A solar cell, comprising a silicon substrate, wherein a first region and a second region adjacent to each other along a first direction are provided on a surface of one side of the silicon substrate; wherein: On the first region, a first doping layer and a first electrode are sequentially stacked on the silicon substrate; the first doping layer extends to the second region; The first doped layer in the first region has a crystallized region; a projection of the crystallized region on the silicon substrate at least partially overlaps with a projection of the first electrode on the silicon substrate; In the second region, at least a portion of the first doped layer is an amorphized region.

2. The solar cell according to claim 1, wherein: A third region is further included on one side surface of the silicon substrate, and along the first direction, the third region is located on a side of the second region away from the first region; On the third region, a second doping layer and a second electrode are stacked in sequence on the silicon substrate; the second doping layer extends to the second region, and in the second region, the second doping layer is located on a side of the first doping layer close to the silicon substrate; the conductivity of the first doping layer is opposite to that of the second doping layer.

3. The solar cell according to claim 2, wherein: The second doped layer includes doped polysilicon.

4. The solar cell according to claim 2, wherein: The second doped layer in the third region has a crystallized region; a projection of the crystallized region on the silicon substrate at least partially overlaps with a projection of the second electrode on the silicon substrate; In the second region, at least a portion of the second doped layer is an amorphized region.

5. The solar cell according to claim 1, wherein: In the first region, the first doped layer includes a first crystallized region and a first amorphized region A; At least a portion of the first crystallized region away from the silicon substrate has crystals.

6. The solar cell according to claim 5, wherein: A third region is further included on one side surface of the silicon substrate, and along the first direction, the third region is located on a side of the second region away from the first region; on the third region, a second doping layer and a second electrode are sequentially stacked on the silicon substrate; the first doping layer and the second doping layer have opposite conductivity; In the second region, the first doped layer is stacked on a side of the second doped layer away from the silicon substrate; The first amorphized region A includes side portions located at two ends of the first region along the first direction, and the side portions are stacked on side surfaces of the second doping layer close to the first region.

7. The solar cell according to claim 6, wherein: Along the first direction, the first amorphized region A includes a middle portion located between the side portions and the first crystallized region, one end of the middle portion is connected to one of the side portions, and the other end of the middle portion is connected to the first crystallized region.

8. The solar cell according to claim 7, wherein: The sum of the lengths of the middle portion and the portion of the side portion connected thereto stacked on the silicon substrate is L≥5 μm.

9. The solar cell according to any one of claims 1 to 8, wherein: In the first region, along the thickness direction from the surface of one side far from the silicon substrate to the side close to the silicon substrate, the crystallization rate of the crystallized region of the first doping layer gradually decreases; or In the first region, along the thickness direction from a side surface away from the silicon substrate to a side surface close to the silicon substrate, the crystallization rates of the crystallized regions of the first doping layer are equal.

10. The solar cell according to any one of claims 1 to 8, wherein: The first doped layer in the amorphous region is an amorphous silicon layer, and the first doped layer in the crystallized region includes nanocrystalline silicon and / or microcrystalline silicon; and / or The crystallization rate of the first doping layer in the crystallization region is 0.01-100%; and / or The first doping layer in the crystallized region is distributed in a continuous or discrete manner; and / or The first doping layer in the crystallized region is formed by laser irradiation.

11. The solar cell according to any one of claims 2 to 8, wherein: It also includes a first passivation layer located between the silicon substrate and the first doped layer; and / or, it also includes a first conductive layer located between the first doped layer and the first electrode; and / or, it also includes a second passivation layer located between the silicon substrate and the second doped layer; and / or, it also includes a second conductive layer located between the second doped layer and the second electrode.

12. A method for preparing a solar cell, wherein: The steps include: Providing a silicon substrate, wherein a surface of one side of the silicon substrate includes a first region and a second region adjacent to each other along a first direction; forming a first doping layer in the first region and the second region of the silicon substrate; performing a crystallization process on at least a portion of the first doped layer in the first region, so that at least a portion of the first doped layer in the first region forms a crystallized region; A first electrode is formed in the first region so that a projection of the crystallized region on the silicon substrate at least partially overlaps with a projection of the first electrode on the silicon substrate.

13. The preparation method according to claim 12, wherein: A third region is further included on one side surface of the silicon substrate, and along the first direction, the third region is located on a side of the second region away from the first region; The method for preparing the solar cell further comprises the steps of: forming a second doping layer in the third region and the second region of the silicon substrate; in the second region, the second doping layer is located on a side of the first doping layer close to the silicon substrate; the first doping layer and the second doping layer have opposite conductivity; A second electrode is formed in the third region.

14. The preparation method according to claim 13, wherein: The second doped layer is a polysilicon doped layer.

15. The preparation method according to claim 13, wherein: The method for preparing the solar cell further comprises the steps of: performing a crystallization process on at least a portion of the second doped layer in the third region, so that at least a portion of the second doped layer in the third region forms a crystallized region; A projection of the crystallized region in the third area on the silicon substrate at least partially overlaps with a projection of the second electrode on the silicon substrate.

16. The preparation method according to any one of claims 12 to 15, wherein: After crystallizing at least a portion of the first doped layer in the first region and before forming a first electrode in the first region, the method further includes forming a first conductive layer in the first region.

17. The preparation method according to any one of claims 12 to 15, wherein: The first doping layer in the first region is crystallized by irradiating the first doping layer in the first region with laser.

18. A battery assembly, wherein: A solar cell comprising the solar cell according to any one of claims 1 to 11.

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