Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device. The display panel comprises a substrate; the pixel circuit layer is arranged on one side of the substrate, the pixel circuit layer comprises a conductive connecting layer, and the conductive connecting layer comprises at least one power supply signal line; the first electrode layer is arranged on the side, away from the substrate, of the conductive connecting layer and comprises at least one second wiring structure and a plurality of first electrodes; the isolation structures are arranged on the sides, away from the substrate, of the conductive connecting layers and the first electrode layers, a plurality of isolation openings are defined by the isolation structures, the corresponding first electrodes are exposed by the isolation openings, and the isolation structures are electrically connected with at least one power signal line and at least one second wiring structure so as to reduce the voltage drop of the power signal line.

Description

Technical Field

[0001] The present application relates to the technical field of display equipment, and in particular to a display panel and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and flat panel display devices based on technologies such as Light Emitting Diode (LED) have been widely used in various consumer electronic products such as mobile phones, televisions, laptops, desktop computers, etc. due to their advantages such as high image quality, power saving, thin body and wide application range, becoming the mainstream in display devices.

[0003] However, the performance of current display products needs to be improved. Summary of the invention

[0004] Embodiments of the present application provide a display panel and a display device, aiming to improve the performance of the display panel.

[0005] An embodiment of the first aspect of the present application provides a display panel, comprising: a substrate; a pixel circuit layer, arranged on one side of the substrate, comprising a conductive connection layer, the conductive connection layer comprising at least one power signal line; a first electrode layer, arranged on the side of the conductive connection layer facing away from the substrate, comprising at least one second wiring structure and a plurality of first electrodes; an isolation structure, arranged on the side of the conductive connection layer and the first electrode layer facing away from the substrate, the isolation structure enclosing a plurality of isolation openings, the isolation openings exposing the corresponding first electrodes, the isolation structure electrically connecting at least one power signal line and at least one second wiring structure.

[0006] According to an embodiment of the present application, the pixel circuit layer also includes a source and drain layer and multiple pixel driving units, the pixel driving unit includes a driving transistor, and the first electrode of the driving transistor is located in the source and drain layer, wherein: the conductive connection layer is located on the side of the source and drain layer away from the substrate, and the conductive connection layer also includes multiple first wiring structures; the first electrode is electrically connected to the first electrode of the corresponding driving transistor through the corresponding first wiring structure.

[0007] According to an embodiment of the present application, the display panel includes a display area and a non-display area, wherein: a plurality of first wiring structures and a plurality of first electrodes are located in the display area; at least one power signal line and at least one second wiring structure are located in the non-display area.

[0008] According to an embodiment of the present application, the isolation structure includes an electrically connected isolation portion and a lap portion, the isolation portion is located in the display area, the lap portion is located in the non-display area, and the lap portion is electrically connected to at least one power signal line and at least one second routing structure.

[0009] According to an embodiment of the present application, the isolation portion encloses and forms a plurality of isolation openings.

[0010] According to an embodiment of the present application, the conductive connection layer includes a first insulating layer, the first insulating layer is arranged between the isolation structure and the first electrode layer, and between at least one power signal line and the isolation structure, the at least one power signal line includes a power signal line, wherein: the first insulating layer includes at least one first via hole, and the overlapping portion is electrically connected to the at least one power signal line through the at least one first via hole.

[0011] According to an embodiment of the present application, the conductive connection layer includes a first conductive layer and a second conductive layer stacked in a direction away from the substrate, and at least one power signal line includes: a first power signal line, located in the first conductive layer; and, a second power signal line, located in the second conductive layer; wherein the first power signal line is electrically connected to the second power signal line.

[0012] According to an embodiment of the present application, the conductive connection layer also includes a second insulating layer, which is arranged between the first conductive layer and the second conductive layer. The second insulating layer includes at least one second via hole, and the second power signal line is electrically connected to the first power signal line through the at least one second via hole.

[0013] According to an embodiment of the present application, the conductive connection layer includes a first insulating layer, the first insulating layer is arranged between the isolation structure and the first electrode layer, and between the second conductive layer and the isolation structure, wherein: the first insulating layer includes at least one first via hole, and the overlapping portion is electrically connected to the second conductive layer through the at least one first via hole;

[0014] According to an embodiment of the present application, the orthographic projections of at least one first via hole and at least one second via hole on the substrate are staggered.

[0015] According to an embodiment of the present application, the first vias include a plurality of first vias, the plurality of first vias are spaced apart along the first direction, the first vias are extended along the second direction, and the first direction, the second direction and the substrate thickness direction are perpendicular to each other.

[0016] According to an embodiment of the present application, the second power signal line is provided with at least one first air hole, and an orthographic projection of the at least one first air hole on the substrate is staggered with an orthographic projection of the first via hole on the substrate.

[0017] According to an embodiment of the present application, at least one second air hole is formed in the first power signal line, and an orthographic projection of the at least one second air hole on the substrate is staggered with an orthographic projection of the second via hole on the substrate.

[0018] According to an embodiment of the present application, the first insulating layer includes at least one third via hole, and the overlapping portion is electrically connected to at least one second wiring structure through the at least one third via hole.

[0019] According to an embodiment of the present application, the conductive connection layer further includes a third insulating layer disposed between the first electrode layer and at least one power signal line.

[0020] According to an embodiment of the present application, the third insulating layer includes at least one fourth via, and the second routing structure is electrically connected to at least one power signal line through the fourth via; and / or, the third insulating layer includes at least one fifth via, and the second routing structure extends to the fifth via to electrically connect to the at least one power signal line. According to an embodiment of the present application, the third insulating layer includes at least one fifth via, the conductive connection layer includes a first insulating layer, the first insulating layer is arranged between the isolation structure and the first electrode layer, and is arranged between at least one power signal line and the isolation structure, and the at least one power signal line includes a power signal line; wherein: a portion of the first insulating layer is located in the fifth via, and the first insulating layer includes at least one first via located in the fifth via, and the isolation structure is electrically connected to at least one power signal line through the at least one first via.

[0021] According to an embodiment of the present application, the pixel driving unit includes at least one switching transistor, and the conductive connection layer further includes a plurality of third wiring structures, and the third wiring structures are electrically connected to the driving transistor and the at least one switching transistor.

[0022] According to an embodiment of the present application, the display panel also includes a light-emitting layer and a pixel defining layer, the pixel defining layer is arranged between the first electrode and the isolation structure, the pixel defining layer includes a pixel defining portion and a pixel opening, the pixel opening and the isolation opening are interconnected, and the pixel opening exposes the corresponding first electrode; the light-emitting layer includes a light-emitting unit located in each pixel opening, and the light-emitting unit is arranged on the side of the first electrode away from the substrate.

[0023] According to an embodiment of the present application, the pixel defining portion is made of the same material as the first insulating layer.

[0024] According to an embodiment of the present application, a second electrode is disposed on a side of the light-emitting unit facing away from the substrate.

[0025] According to an embodiment of the present application, the second electrode and the isolation structure are electrically connected.

[0026] According to an embodiment of the present application, the overlapping portions enclose to form a first vent, and an orthographic projection of the first vent on the substrate is staggered with an orthographic projection of the second via on the substrate.

[0027] According to an embodiment of the present application, a second air permeable opening is formed in the first insulating layer, and an orthographic projection of the second air permeable opening on the substrate is located within an orthographic projection of the first air permeable opening on the substrate.

[0028] According to an embodiment of the present application, the isolation structure includes a first sublayer and a second sublayer, the first sublayer is located on a side of the second sublayer facing the substrate, and the orthographic projection of the first sublayer on the substrate is within the orthographic projection of the second sublayer on the substrate.

[0029] According to an embodiment of the present application, the first sub-layer via is connected to at least one power signal line.

[0030] According to an embodiment of the present application, the first sub-layer via is connected to at least one second routing structure.

[0031] An embodiment of the second aspect of the present application further provides a display device, comprising the display panel in any embodiment of the first aspect.

[0032] In an embodiment of the present application, at least one power signal line can be used to access a common voltage signal, and the isolation structure electrically connects at least one power signal line and at least one second wiring structure to reduce the voltage drop of the power signal line, thereby reducing the power consumption of the display panel and improving the performance of the display panel. The first electrode can be formed simultaneously with the second wiring structure in the same preparation process, thereby simplifying the preparation process of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Other features, objects and advantages of the present application will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals represent the same or similar features.

[0034] Figure 1 is a structural schematic diagram of a display panel provided in an embodiment of the present application;

[0035] Figure 2 yes Figure 1 Cross-section at CC;

[0036] Figure 3 is a schematic diagram of the structure of another display panel provided in an embodiment of the present application;

[0037] Figure 4 is a structural schematic diagram of another display panel provided in an embodiment of the present application;

[0038] Figure 5 is a structural schematic diagram of another display panel provided in an embodiment of the present application;

[0039] Figure 6 is a structural schematic diagram of another display panel provided in an embodiment of the present application;

[0040] Figure 7 This is a schematic diagram of the structure of another display panel provided in an embodiment of the present application.

[0041] Explanation of reference numerals: 10, display area; 20, non-display area; 100, substrate; 200, conductive connection layer; 201, power signal line; 202, first wiring structure; 210, first conductive layer; 211, first power signal line; 212, second air hole; 220, second conductive layer; 221, second power signal line; 222, first air hole; 300, first electrode layer; 310, second wiring structure; 320, first electrode; 400, isolation structure; 401, isolation part; 402, overlap part; 410, first sublayer; 420, second sublayer; 430, isolation opening; 440, first air vent; 510, first insulating layer; 511, first via hole; 512, third via hole; 513, second air vent; 520, second insulating layer; 521, second via hole; 530, third insulating layer; 531, fourth via hole; 600, light emitting unit; 610, second electrode; 700, pixel driving unit; 701, driving transistor; 710, semiconductor layer; 720, gate; 730, source and drain layer; 731, first electrode; 800, pixel defining portion; 810, pixel opening; X, first direction; Y, second direction; Z, thickness direction. DETAILED DESCRIPTION

[0042] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In the detailed description below, many specific details are proposed to provide a comprehensive understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating examples of the present application. In the accompanying drawings and the following description, at least some of the known structures and technologies are not shown to avoid unnecessary ambiguity in the present application; and, for clarity, the size of some structures may be exaggerated. In addition, the features, structures or characteristics described below may be combined in one or more embodiments in any suitable manner.

[0043] In the description of the present application, it should be noted that, unless otherwise specified, "multiple" means more than two; the terms "upper", "lower", "left", "right", "inner", "outer", etc., indicating directions or positional relationships, are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0044] The directional words appearing in the following description are all directions shown in the figures, and do not limit the specific structure of the embodiments of the present application. In the description of the present application, it should also be noted that, unless otherwise clearly specified and limited, the terms "installation" and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

[0045] like Figure 1 and Figure 2 As shown, a display panel provided by an embodiment of the first aspect of the present application includes: a substrate 100, a pixel circuit layer, a conductive connection layer 200, a first electrode layer 300 and an isolation structure 400, wherein the pixel circuit layer is arranged on one side of the substrate 100, and includes a conductive connection layer 200, and the conductive connection layer 200 includes at least one power signal line 201; the first electrode layer 300 is arranged on the side of the conductive connection layer 200 away from the substrate 100, and includes at least one second wiring structure 310 and a plurality of first electrodes 320; the isolation structure 400 is arranged on the side of the conductive connection layer 200 and the first electrode layer 300 away from the substrate 100, and the isolation structure 400 encloses a plurality of isolation openings 430, and the isolation openings 430 expose the corresponding first electrodes 320, and the isolation structure 400 is electrically connected to at least one power signal line 201 and at least one second wiring structure 310.

[0046] In this embodiment, at least one power signal line 201 can be used to access a common voltage signal, and the isolation structure 400 electrically connects at least one power signal line 201 and at least one second wiring structure 310 to reduce the voltage drop of the power signal line 201, thereby reducing the power consumption of the display panel. Improve the performance of the display panel. Optionally, the first electrode 320 can be formed simultaneously with the second wiring structure 310 in the same preparation process, thereby simplifying the preparation process of the display panel.

[0047] in, Figure 2 This is a schematic diagram showing the cross-section of the panel and does not represent the actual cross-sectional structure.

[0048] Optional, such as Figure 2 As shown, the isolation openings 430 are used to prepare the light-emitting units 600 in each isolation opening 430 to reduce light crosstalk between each light-emitting unit 600 .

[0049] Optionally, the pixel circuit layer may include a semiconductor layer 710, a gate electrode 720, a source-drain electrode layer 730, a first conductive layer 210, and a second conductive layer 220 arranged in sequence in a direction away from the substrate 100. The conductive connection layer 200 includes at least one power signal line 201, and the power signal line 201 may be arranged in the same layer as at least one of the semiconductor layer 710, the gate electrode 720, the source-drain electrode layer 730, the first conductive layer 210, and the second conductive layer 220. Figure 2 , the power signal line 201 is shown to be located in the first conductive layer 210 and the second conductive layer 220 . The power signal line 201 may also be disposed in the same layer as at least one of the semiconductor layer 710 , the gate 720 , and the source-drain layer 730 .

[0050] like Figure 2 As shown, in some optional embodiments, the pixel circuit layer also includes a source-drain layer 730 and a plurality of pixel driving units 700, the pixel driving unit 700 includes a driving transistor 701, and the first electrode 731 of the driving transistor 701 is located in the source-drain layer 730, wherein: the conductive connection layer 200 is located on the side of the source-drain layer 730 away from the substrate 100, and the conductive connection layer 200 also includes a plurality of first wiring structures 202; the first electrode 320 is electrically connected to the first electrode 731 of the corresponding driving transistor 701 through the corresponding first wiring structure 202.

[0051] In these optional embodiments, the conductive connection layer 200 is located on the side of the source-drain layer 730 away from the substrate 100, that is, the power signal line 201 is located on the side of the source-drain layer 730 away from the substrate, so that the power signal line 201 is closer to the second wiring structure 310 and the isolation structure 400, so that the power signal line 201, the second wiring structure 310 and the isolation structure 400 are electrically connected to each other. The pixel driving unit 700 includes a driving transistor 701, and the first electrode 731 of the driving transistor 701 is electrically connected to the corresponding first electrode 320 through the corresponding first wiring structure 202 for driving different light-emitting units 600 to emit light, thereby improving the display effect of the display panel.

[0052] Optionally, in some other embodiments, the pixel circuit layer may include a semiconductor layer 710, a gate 720, and a source-drain electrode layer 730 sequentially arranged in a direction away from the substrate 100. The conductive connection layer 200 includes at least one power signal line 201, and the power signal line 201 may be arranged in the same layer as at least one layer of the semiconductor layer 710, the gate 720, and the source-drain electrode layer 730 (that is, the conductive connection layer 200 is at least one layer of the semiconductor layer 710, the gate 720, and the source-drain electrode layer 730). In these embodiments, the first electrode 731 of the driving transistor 701 of the pixel driving unit 700 is located in the source-drain electrode layer 730, and is electrically connected to the corresponding first electrode 320 through a via hole in the insulating layer between the source-drain electrode layer 730 and the plurality of first electrodes 320.

[0053] like Figure 1 and Figure 2 As shown, in some optional embodiments, the display panel includes a display area 10 and a non-display area 20, wherein: a plurality of first wiring structures 202 and a plurality of first electrodes 320 are located in the display area 10; at least one power signal line 201 and at least one second wiring structure 310 are located in the non-display area 20.

[0054] In these optional embodiments, a plurality of first wiring structures 202 and a plurality of first electrodes 320 are located in the display area 10, and the pixel driving unit 700 is electrically connected to the first electrode 320 through the first wiring structure 202 to drive the light-emitting unit 600 to emit light, thereby improving the display effect of the display panel. At least one power signal line 201 and at least one second wiring structure 310 are located in the non-display area 20, and the second wiring structure 310 is used to reduce the voltage drop of at least one power signal line 201, thereby reducing the power consumption of the display panel.

[0055] Optional, such as Figure 2 As shown, the isolation structure 400 includes an isolation portion 401 and a lap portion 402 which are electrically connected, the isolation portion 401 is located in the display area 10, the lap portion 402 is located in the non-display area 20, and the lap portion 402 is electrically connected to at least one power signal line 201 and at least one second wiring structure 310. The isolation portion 401 is located in the display area 10, and the lap portion 402 is electrically connected to at least one power signal line 201 and at least one second wiring structure 310 so as to transmit the electrical signal in the power signal line 201 to the isolation portion 401.

[0056] Optional, such as Figure 2 As shown, the isolation portion 401 encloses and forms an isolation opening 430 for accommodating the light-emitting unit 600 .

[0057] like Figure 2As shown, in some optional embodiments, the conductive connection layer 200 includes a first insulating layer 510, and the first insulating layer 510 is arranged between the isolation structure 400 and the first electrode layer 300, and is arranged between at least one power signal line 201 and the isolation structure 400, and at least one power signal line 201 includes a power signal line 201, wherein: the first insulating layer 510 includes at least one first via 511, and the overlapping portion 402 is electrically connected to at least one power signal line 201 through at least one first via 511.

[0058] In these optional embodiments, part of the first insulating layer 510 is disposed between the isolation structure 400 and the first electrode layer 300 to isolate and insulate the first electrode layer 300 and the isolation structure 400, and part of the first insulating layer 510 is disposed between at least one power signal line 201 and the isolation structure 400 to isolate and insulate the power signal line 201 and the isolation structure 400. The first insulating layer 510 includes at least one first via hole 511, and the lap portion 402 is electrically connected to at least one power signal line 201 through the at least one first via hole 511, so that the electrical signal in the power signal line 201 is transmitted to the lap portion 402 and then transmitted from the lap portion 402 to the isolation portion 401.

[0059] like Figure 2 As shown, in some optional embodiments, the conductive connection layer 200 includes a first conductive layer 210 and a second conductive layer 220 stacked in a direction away from the substrate 100, and at least one power signal line 201 includes: a first power signal line 211, located in the first conductive layer 210; and, a second power signal line 221, located in the second conductive layer 220; wherein the first power signal line 211 is electrically connected to the second power signal line 221.

[0060] In these optional embodiments, at least one power signal line 201 includes a first power signal line 211 located in the first conductive layer 210 and a second power signal line 221 located in the second conductive layer 220. The first power signal line 211 and the second power signal line 221 are not arranged in the same layer, which can increase the wiring space. The electrical connection between the first power signal line 211 and the second power signal line 221 can further reduce the voltage drop between the first power signal line 211 and the second power signal line 221, thereby reducing the power consumption of the display panel.

[0061] Optional, such as Figure 2As shown, the conductive connection layer 200 further includes a second insulating layer 520, which is disposed between the first conductive layer 210 and the second conductive layer 220. The second insulating layer 520 includes at least one second via hole 521, and the second power signal line 221 is electrically connected to the first power signal line 211 through the at least one second via hole 521. The second insulating layer 520 is disposed between the first conductive layer 210 and the second conductive layer 220 so that the first conductive layer 210 and the second conductive layer 220 are spaced and insulated from each other. The second power signal line 221 is electrically connected to the first power signal line 211 through the at least one second via hole 521 to reduce the voltage drop between the first power signal line 211 and the second power signal line 221.

[0062] Optional, such as Figure 2 As shown, the conductive connection layer 200 includes a first insulating layer 510, and the first insulating layer 510 is disposed between the isolation structure 400 and the first electrode layer 300, and between the second conductive layer 220 and the isolation structure 400, wherein: the first insulating layer 510 includes at least one first via hole 511, and the overlapping portion 402 is electrically connected to the second conductive layer 220 through the at least one first via hole 511. A portion of the first insulating layer 510 is disposed between the second conductive layer 220 and the isolation structure 400 to isolate and insulate the second conductive layer 220 and the isolation structure 400. The first insulating layer 510 includes at least one first via 511, and the overlapping portion 402 is electrically connected to the second conductive layer 220 through at least one first via 511. Optionally, the overlapping portion 402 is electrically connected to the second power signal line 221 through at least one first via 511, so that the electrical signal in the first power signal line 211 and the second power signal line 221 is transmitted to the overlapping portion 402 and then transmitted from the overlapping portion 402 to the isolation portion 401.

[0063] Optional, such as Figure 2 As shown, the orthographic projections of at least one first via hole 511 and at least one second via hole 521 on the substrate 100 are staggered, thereby preventing the first via hole 511 and the second via hole 521 from being connected to each other and causing the via hole depth to be too large.

[0064] Optional, such as Figure 3 and Figure 4 As shown, the first via 511 includes a plurality of first vias 511, and the plurality of first vias 511 are spaced apart along the first direction X. The first vias 511 are extended along the second direction Y. The first direction X, the second direction Y and the thickness direction Z of the substrate 100 are arranged perpendicular to each other in pairs, which is beneficial to reducing the spacing between the first vias 511. The first vias 511 are extended along the second direction Y, thereby increasing the aperture of the first vias 511 and improving the connection area between the second power signal line 221 and the overlapping portion 402.

[0065] like Figure 4As shown, in some optional embodiments, the second power signal line 221 is provided with at least one first air hole 222 , and the orthographic projection of the at least one first air hole 222 on the substrate 100 is staggered with the orthographic projection of the first via hole 511 on the substrate 100 .

[0066] In these optional embodiments, the first air hole 222 is used to discharge the gas from the second power signal line 221 toward the side of the substrate 100 through the first air hole 222. The orthographic projection of the first air hole 222 on the substrate 100 is offset from the orthographic projection of the first via 511 on the substrate 100, that is, the first air hole 222 and the first via 511 are not connected to each other. Since no conductive material is provided at the position of the first air hole 222, electrical connection cannot be made. The first air hole 222 and the first via 511 are offset to ensure that the second power signal line 221 can contact the overlapping portion 402, thereby reducing the risk of circuit breakage between the second power signal line 221 and the overlapping portion 402.

[0067] Optional, such as Figure 4 As shown, the first power signal line 211 is provided with at least one second air hole 212, and the orthographic projection of the at least one second air hole 212 on the substrate 100 is staggered with the orthographic projection of the second via hole 521 on the substrate 100. The second air hole 212 is used to discharge the gas from the first power signal line 211 toward the side of the substrate 100 through the second air hole 212, and the orthographic projection of the second air hole 212 on the substrate 100 is staggered with the orthographic projection of the second via hole 521 on the substrate 100, that is, the second air hole 212 and the second via hole 521 are not connected to each other. Since no conductive material is provided at the position of the second air hole 212, electrical connection cannot be performed. The second air hole 212 and the second via hole 521 are staggered to ensure that the second power signal line 221 can contact the first power signal line 211, thereby reducing the risk of disconnection between the first power signal line 211 and the second power signal line 221.

[0068] like Figure 4 As shown, in some optional embodiments, the first insulating layer 510 includes at least one third via hole 512 , and the overlapping portion 402 is electrically connected to at least one second wiring structure 310 through the at least one third via hole 512 .

[0069] In these optional embodiments, the overlapping portion 402 is electrically connected to at least one second routing structure 310 through at least one third via 512, and the overlapping portion 402 is electrically connected to the second power signal line 221 and the first power signal line 211, thereby further reducing the voltage drop between the first power signal line 211 and the second power signal line 221.

[0070] like Figure 2 and Figure 5As shown, in some other optional embodiments, the conductive connection layer 200 further includes a third insulating layer 530 disposed between the first electrode layer 300 and at least one power signal line 201 .

[0071] In these optional embodiments, the third insulating layer 530 is disposed between the first electrode layer 300 and at least one power signal line 201, the third insulating layer 530 is disposed on the side of the first electrode 320 and the second wiring structure 310 facing the substrate 100, and the third insulating layer 530 is located between at least one second wiring structure 310 and at least one power signal line 201, so that the second wiring structure 310 and at least one power signal line 201 are spaced and insulated from each other.

[0072] Optional, such as Figure 5 As shown, the third insulating layer 530 includes at least one fourth via hole 531, and the second wiring structure 310 is electrically connected to at least one power signal line 201 through the fourth via hole 531. The at least one second wiring structure 310 is electrically connected to at least one power signal line 201 through the fourth via hole 531, thereby reducing the voltage drop of the at least one power signal line 201. Different from the above embodiment, the at least one second wiring structure 310 in this embodiment does not need to be connected to the power signal line 201 through the overlapping portion 402.

[0073] Optionally, the second wiring structure 310 is electrically connected to the first power signal line 211 or the second power signal line 221 through a fourth via 531 .

[0074] In other embodiments, Figure 6 As shown, the third insulating layer 530 includes at least one fifth via hole 532, and the second wiring structure 310 extends to the fifth via hole 532 to be electrically connected to at least one power signal line 201. Optionally, as Figure 2 As shown, part of the first insulating layer 510 is located in the fifth via hole 532, and the first insulating layer 510 includes at least one first via hole 511 located in the fifth via hole 532, and the isolation structure 400 is electrically connected to at least one power signal line 201 through the at least one first via hole 511. Optionally, the overlapping portion 402 is located in the fifth via hole 532 and is electrically connected to at least one power signal line 201 through the first via hole 511.

[0075] Optional, such as Figure 6 As shown, a portion of the second wiring structure 310 is located between the first insulating layer 510 and at least one power signal line 201 .

[0076] In these optional embodiments, part of the first insulating layer 510 is located in the fifth via hole 532, and part of the isolation structure 400 is located in the fifth via hole 532 and electrically connected to at least one power signal line 201 through the first via hole 511. The at least one power signal line 201 may be the second power signal line 221.

[0077] like Figure 2 As shown, in some optional embodiments, the pixel driving unit 700 includes at least one switching transistor, and the conductive connection layer 200 further includes a plurality of third wiring structures, and the third wiring structures are electrically connected to the driving transistor 701 and the at least one switching transistor.

[0078] In these optional embodiments, the third wiring structure electrically connects the driving transistor 701 and at least one switching transistor, so that the third wiring structure can provide electrical signals to the driving transistor 701 and the switching transistor to light up different light-emitting units 600 through the first electrode 320 .

[0079] The first wiring structure 202 is used to electrically connect the driving transistor 701 to the corresponding first electrode 320, and the third wiring structure is used to electrically connect the driving transistor 701 and at least one switching transistor to provide an electrical signal. The driving transistor 701 includes a semiconductor layer 710, a gate 720, and a source-drain layer 730 arranged in sequence in a direction away from the substrate 100. Among them, the conductive connection layer 200 is arranged on the side of the source-drain layer 730 away from the substrate 100. The source-drain layer 730 includes a source and a drain, wherein the source is a first electrode 731, the first wiring structure 202 is electrically connected between the source and the first electrode 320, and the third wiring structure is electrically connected between the driving transistor 701 and the source and drain of the switching transistor.

[0080] Optionally, the display panel may be any one of a 2T1C circuit, a 7T1C circuit, a 7T2C circuit, or a 9T1C circuit. Herein, a "2T1C circuit" refers to a circuit including two transistors and one capacitor, and other "7T1C circuits", "7T2C circuits", "9T1C circuits", and so on.

[0081] like Figure 2 As shown, in some optional embodiments, the display panel further includes a light-emitting layer and a pixel defining layer, the pixel defining layer is disposed between the first electrode 320 and the isolation structure 400, the pixel defining layer includes a pixel defining portion 800 and a pixel opening 810, the pixel opening 810 is interconnected with the isolation opening 430, and the pixel opening 810 exposes the corresponding first electrode 320. The light-emitting layer includes a light-emitting unit 600 located in each pixel opening 810, and the light-emitting unit 600 is disposed on the side of the first electrode 320 away from the substrate 100.

[0082] In these optional embodiments, the pixel defining layer includes a pixel defining portion 800 and a pixel opening 810, the pixel opening 810 is interconnected with the isolation opening 430, the light-emitting layer includes a light-emitting unit 600 located in each pixel opening 810, the light-emitting unit 600 is arranged on the side of the first electrode 320 away from the substrate 100, and the isolation structure 400 and the pixel defining portion 800 are used to reduce light crosstalk between different light-emitting units 600.

[0083] Optionally, the pixel defining portion 800 and the first insulating layer 510 are made of the same material, so they can be simultaneously manufactured and formed in the same manufacturing process, thereby reducing the difficulty of manufacturing.

[0084] Optional, such as Figure 2 As shown, a second electrode 610 is disposed on the side of the light-emitting unit 600 facing away from the substrate 100 , and the first electrode 320 and the second electrode 610 jointly drive the light-emitting unit 600 to emit light.

[0085] Optional, such as Figure 2 As shown, the second electrode 610 is electrically connected to the isolation structure 400 . Specifically, the second electrode 610 is electrically connected to the isolation portion 401 , so that the electrical signal in at least one power signal line 201 is transmitted to the second electrode 610 .

[0086] like Figure 7 As shown, in some optional embodiments, the overlapping portion 402 encloses to form a first vent 440 , and the orthographic projection of the first vent 440 on the substrate 100 is staggered with the orthographic projection of the second via 521 on the substrate 100 .

[0087] In these optional embodiments, the first vent 440 is used to pass gas from the overlapping portion 402 toward the substrate 100. Since there is no overlapping portion 402 material at the first vent 440, the first vent 440 and the second via 521 are staggered to ensure that the overlapping portion 402 is electrically connected to at least one power signal line 201.

[0088] Optional, such as Figure 7 As shown, the first insulating layer 510 is provided with a second vent 513, and the orthographic projection of the second vent 513 on the substrate 100 is located within the orthographic projection of the first vent 440 on the substrate 100. The first insulating layer 510 is provided with a second vent 513 located within the first vent 440, thereby ensuring that gas can be discharged through the second vent 513 and the first vent 440.

[0089] like Figure 2As shown, in some optional embodiments, the isolation structure 400 includes a first sublayer 410 and a second sublayer 420, the first sublayer 410 is located on the side of the second sublayer 420 facing the substrate 100, and the orthographic projection of the first sublayer 410 on the substrate 100 is located within the orthographic projection of the second sublayer 420 on the substrate 100.

[0090] In these optional embodiments, the orthographic projection size of the first sublayer 410 on the substrate 100 is smaller than the orthographic projection size of the second sublayer 420 on the substrate 100, so as to form a recess under the second sublayer 420. During the preparation of the light-emitting unit 600, the material of the light-emitting layer can be separated into mutually independent light-emitting units 600 by the isolation structure 400, and the precision mask evaporation process can be omitted, thereby reducing the preparation cost.

[0091] Optional, such as Figure 2 As shown, the first sub-layer 410 is connected to at least one power signal line 201 through a via, thereby reducing the voltage drop of at least one power signal line 201 and connecting the electrical signal to the isolation structure 400 .

[0092] Optional, such as Figure 2 As shown, the first sub-layer 410 is connected to at least one second wiring structure 310 through a via, thereby further reducing the voltage drop of at least one power signal line 201 .

[0093] Optionally, the specific design of the isolation structure 400 may refer to existing patents, such as application numbers CN118251982A, 202410864269.8, PCT / CN2024 / 098407, PCT / CN2024 / 102783, PCT / CN2024 / 098217, PCT / CN2024 / 099419, and PCT / CN2024 / 099072, which record relevant contents of the isolation structure 400 (or partition structure or isolation column).

[0094] The embodiment of the second aspect of the present application also provides a display device, including the display panel of any of the above-mentioned embodiments of the first aspect. Since the display device provided by the embodiment of the second aspect of the present application includes the display panel of any of the above-mentioned embodiments of the first aspect, the display device provided by the embodiment of the second aspect of the present application has the beneficial effects of the display panel of any of the above-mentioned embodiments of the first aspect, which will not be repeated here.

[0095] The display device in the embodiments of the present application includes but is not limited to mobile phones, personal digital assistants (PDAs), tablet computers, e-books, televisions, access control systems, smart landline phones, consoles, and other devices with display functions.

[0096] Although the present application has been described with reference to preferred embodiments, various modifications may be made thereto and parts thereof may be replaced with equivalents without departing from the scope of the present application. In particular, the various technical features mentioned in the various embodiments may be combined in any manner as long as there are no structural conflicts. The present application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A display panel, characterized in that: include: substrate; A pixel circuit layer, disposed on one side of the substrate, comprises a conductive connection layer, wherein the conductive connection layer comprises at least one power signal line; A first electrode layer, disposed on a side of the conductive connection layer away from the substrate, comprising at least one second wiring structure and a plurality of first electrodes; An isolation structure is arranged on the side of the conductive connection layer and the first electrode layer away from the substrate, the isolation structure encloses a plurality of isolation openings, the isolation openings expose the corresponding first electrodes, and the isolation structure electrically connects the at least one power signal line and the at least one second routing structure.

2. The display panel according to claim 1, characterized in that: The pixel circuit layer further includes a source-drain electrode layer and a plurality of pixel driving units, wherein the pixel driving unit includes a driving transistor, and a first electrode of the driving transistor is located in the source-drain electrode layer, wherein: The conductive connection layer is located on a side of the source and drain electrode layer away from the substrate, and the conductive connection layer further includes a plurality of first wiring structures; The first electrode is electrically connected to the first electrode of the corresponding driving transistor through the corresponding first wiring structure.

3. The display panel according to claim 2, characterized in that: The display panel includes a display area and a non-display area, wherein: The plurality of first wiring structures and the plurality of first electrodes are located in the display area; The at least one power signal line and the at least one second wiring structure are located in the non-display area; Preferably, the isolation structure comprises an isolation portion and a lap portion which are electrically connected, the isolation portion is located in the display area, the lap portion is located in the non-display area, and the lap portion is electrically connected to the at least one power signal line and the at least one second wiring structure; Preferably, the isolation portion encloses and forms the plurality of isolation openings.

4. The display panel according to claim 3, characterized in that: The conductive connection layer includes a first insulating layer, the first insulating layer is arranged between the isolation structure and the first electrode layer, and is arranged between the at least one power signal line and the isolation structure, the at least one power signal line includes one power signal line, wherein: The first insulating layer includes at least one first via hole, and the overlapping portion is electrically connected to the at least one power signal line through the at least one first via hole.

5. The display panel according to claim 3, characterized in that: The conductive connection layer includes a first conductive layer and a second conductive layer stacked in a direction away from the substrate, and the at least one power signal line includes: A first power signal line is located in the first conductive layer; and A second power signal line, located in the second conductive layer; Wherein, the first power signal line is electrically connected to the second power signal line; Preferably, the conductive connection layer further includes a second insulating layer disposed between the first conductive layer and the second conductive layer, the second insulating layer includes at least one second via hole, and the second power signal line is electrically connected to the first power signal line through the at least one second via hole; Preferably, the conductive connection layer comprises a first insulating layer, and the first insulating layer is arranged between the isolation structure and the first electrode layer, and between the second conductive layer and the isolation structure, wherein: The first insulating layer comprises at least one first via hole, and the overlapping portion is electrically connected to the second conductive layer through the at least one first via hole; Preferably, the orthographic projections of the at least one first via hole and the at least one second via hole on the substrate are staggered; Preferably, the first via holes include a plurality of holes, the plurality of the first via holes are spaced apart along a first direction, the first via holes are extended along a second direction, and the first direction, the second direction and the substrate thickness direction are perpendicular to each other.

6. The display panel according to claim 5, characterized in that: The second power signal line is provided with at least one first air hole, and an orthographic projection of the at least one first air hole on the substrate is staggered with an orthographic projection of the first via hole on the substrate; Preferably, the first power signal line is provided with at least one second air hole, and the orthographic projection of the at least one second air hole on the substrate is staggered with the orthographic projection of the second via hole on the substrate.

7. The display panel according to claim 4, characterized in that: The first insulating layer includes at least one third via hole, and the overlapping portion is electrically connected to the at least one second wiring structure through the at least one third via hole.

8. The display panel according to claim 1, characterized in that: The conductive connection layer further includes a third insulating layer disposed between the first electrode layer and the at least one power signal line; Preferably, the third insulating layer includes at least one fourth via hole, and the second wiring structure is electrically connected to the at least one power signal line through the fourth via hole; And / or, the third insulating layer includes at least one fifth via hole, and the second wiring structure extends to the fifth via hole to be electrically connected to the at least one power signal line; Preferably, the third insulating layer includes at least one fifth via hole, the conductive connection layer includes a first insulating layer, the first insulating layer is arranged between the isolation structure and the first electrode layer, and between the at least one power signal line and the isolation structure, and the at least one power signal line includes one power signal line; Part of the first insulating layer is located in the fifth via hole, and the first insulating layer includes at least one first via hole located in the fifth via hole, and the isolation structure is electrically connected to the at least one power signal line through the at least one first via hole.

9. The display panel according to claim 2, characterized in that: The pixel driving unit includes at least one switching transistor, and the conductive connection layer further includes a plurality of third wiring structures, and the third wiring structures are electrically connected to the driving transistor and the at least one switching transistor.

10. The display panel according to claim 5, characterized in that: The display panel further includes a light-emitting layer and a pixel defining layer, wherein the pixel defining layer is disposed between the first electrode and the isolation structure, the pixel defining layer includes a pixel defining portion and a pixel opening, the pixel opening is interconnected with the isolation opening, and the pixel opening exposes the corresponding first electrode; The light-emitting layer includes a light-emitting unit located at each pixel opening, and the light-emitting unit is arranged on a side of the first electrode away from the substrate; Preferably, the pixel defining portion is made of the same material as the first insulating layer; Preferably, a second electrode is provided on a side of the light-emitting unit facing away from the substrate; Preferably, the second electrode is electrically connected to the isolation structure.

11. The display panel according to claim 10, characterized in that: The overlapping portions are combined to form a first vent, and an orthographic projection of the first vent on the substrate and an orthographic projection of the second via on the substrate are arranged in a staggered manner; Preferably, the first insulating layer is provided with a second air permeable opening, and the orthographic projection of the second air permeable opening on the substrate is located within the orthographic projection of the first air permeable opening on the substrate.

12. The display panel according to claim 1, characterized in that: The isolation structure comprises a first sublayer and a second sublayer, the first sublayer is located on a side of the second sublayer facing the substrate, and an orthographic projection of the first sublayer on the substrate is located within an orthographic projection of the second sublayer on the substrate; Preferably, the first sub-layer via is connected to the at least one power signal line; Preferably, the first sub-layer via is connected to the at least one second routing structure.

13. A display device, characterized in that: A display panel comprising any one of claims 1 to 12.

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