Semiconductor device

Abstract

A novel semiconductor device is provided. The semiconductor device includes a flip-flop group having n flip-flops and a plurality of memory cells. The flip-flop group has a function of holding n-bit data. One of the plurality of memory cells has a function of holding n-bit data. Another one of the plurality of memory cells has a function of holding p-bit data. When the data held in the flip-flop group is n bits, the n-bit data held in the flip-flop group is written to one of the memory cells in the first operation. When the data held in the flip-flop group is p bits, the data of the p bits is written to the other of the memory cells in the second operation. N is any one of integers greater than 2, and p is any one of integers greater than 1 and less than n.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device and the like.

[0002] Note that one embodiment of the present invention is not limited to the above-mentioned technical field. The technical field of the invention disclosed in this specification and the like relates to an object, a method or a manufacturing method. In addition, one embodiment of the present invention relates to a process, a machine, a product or a composition of matter. Therefore, specifically, as examples of the technical field of one embodiment of the present invention disclosed in this specification, semiconductor devices, display devices, light-emitting devices, power storage devices, storage devices, driving methods of these devices or manufacturing methods of these devices can be cited.

[0003] In this specification, etc., a semiconductor device refers to a device that utilizes semiconductor characteristics and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.) and a device having the circuit. In addition, a semiconductor device refers to all devices that can work by utilizing semiconductor characteristics. For example, as examples of semiconductor devices, there are integrated circuits, chips with integrated circuits, and electronic components that contain chips in packages. In addition, sometimes storage devices, display devices, light-emitting devices, lighting devices, and electronic devices themselves are semiconductor devices, or include semiconductor devices. Background Art

[0004] The technical development of semiconductor devices that can hold charges corresponding to data by combining a transistor using an oxide semiconductor for a semiconductor layer forming a channel (also called an "OS transistor") and a transistor using silicon for a semiconductor layer forming a channel (also called a "Si transistor") is becoming increasingly popular.

[0005] By providing the semiconductor device with a structure for saving (also referred to as "reserving", "storing" or "backing up") or loading (also referred to as "regenerating", "restoring" or "rebuilding") the program or data held in a trigger or the like, low power consumption can be achieved by using power gating or the like. Therefore, it has been applied to semiconductor devices such as CPUs (central processing units) (for example, see Patent Document 1). [Prior technical literature] [Patent Document]

[0006] [Patent Document 1] Japanese Patent Application Publication No. 2013-9297 Summary of the invention Technical problem to be solved by the invention

[0007] In semiconductor devices such as CPUs, when an exception processing (also called "interrupt processing") request occurs, the exception processing is performed after the data held in the register is backed up (written) to the external memory. In addition, after the exception processing is completed, the data backed up in the external memory needs to be written back to the register. For example, in the event of an exception processing request such as an emergency stop, if the data backup time is long, major problems may occur. In addition, when the frequency of occurrence of exception processing requests is high, the time required for data backup and the time required for write-back cannot be ignored. Therefore, it is necessary to shorten the time required for data backup and write-back. In addition, when the frequency of occurrence of exception processing requests is high, a lot of energy is consumed when data is backed up and written back between the external memory and the register, and power consumption increases.

[0008] One of the purposes of one embodiment of the present invention is to provide a novel semiconductor device, etc. Another purpose of one embodiment of the present invention is to provide a semiconductor device with a reduced footprint, etc. Another purpose of one embodiment of the present invention is to provide a semiconductor device with reduced power consumption, etc. Another purpose of one embodiment of the present invention is to provide a semiconductor device with high reliability, etc. Another purpose of one embodiment of the present invention is to provide a semiconductor device with excellent computing performance, etc.

[0009] Note that the purpose of one embodiment of the present invention is not limited to the above-mentioned purpose. The above-mentioned purposes do not prevent the existence of other purposes. In addition, other purposes are purposes that are not mentioned above but will be described in the following description. A person skilled in the art can derive and appropriately extract purposes other than the above-mentioned from the description of the specification or drawings, etc. Note that one embodiment of the present invention achieves at least one of the above-mentioned purposes and / or other purposes. Solutions to technical problems

[0010] One embodiment of the present invention is a semiconductor device, comprising: a trigger group of n (n is any integer greater than 2) triggers; a first storage unit arranged on the trigger group and comprising n storage circuits; and a second storage unit arranged on the first storage unit and comprising p (p is an integer greater than 1 and less than n) storage circuits, wherein the trigger includes a first transistor including silicon in a semiconductor layer forming a channel, the n storage circuits and the p storage circuits both include a second transistor including an oxide semiconductor in a semiconductor layer forming a channel, and the above-mentioned semiconductor device has the following functions: when the data held by the trigger group is n-bit first data, the first data is held in the first storage unit in a first operation; and when the data held by the trigger group is p-bit second data, the second data is held in the second storage unit in a second operation.

[0011] For example, n storage circuits and p storage circuits each include two second transistors and a capacitor. Preferably, both second transistors have a region overlapping with the capacitor. Preferably, a vertical channel transistor is used as the second transistor. The trigger group has a function of retaining data of more than 1 bit and less than n bits.

[0012] The first operation is, for example, an operation associated with power gating, and the second operation is, for example, an operation associated with interrupt processing. Effects of the Invention

[0013] According to one embodiment of the present invention, a novel semiconductor device can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with a reduced footprint can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with high reliability can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with excellent computing performance can be provided.

[0014] Note that the description of these effects does not prevent the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of the above effects. Note that effects other than the above can be known and extracted from the description of the specification, drawings, claims, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1A and Figure 1B A diagram illustrating a structural example of a semiconductor device. Figure 2A and Figure 2B A diagram illustrating a structural example of a semiconductor device. Figure 3A and Figure 3B A diagram illustrating a structural example of a semiconductor device. Figure 4A A diagram illustrating a structural example of a semiconductor device. Figure 4B It is a timing chart for explaining an operation example of a semiconductor device. FIG. 5A to FIG. 5E It is a diagram for explaining an operation example of a semiconductor device. Figure 6 It is a diagram for explaining an operation example of a semiconductor device. Fig. 7A and Figure 7B A diagram illustrating a structural example of a semiconductor device. Fig. 8A and Figure 8B A diagram illustrating a structural example of a semiconductor device. Fig. 9 A diagram illustrating a structural example of a semiconductor device. Fig.10 A diagram illustrating a structural example of a semiconductor device. Fig.11 It is a diagram for explaining an operation example of a semiconductor device. Fig.12 It is a diagram for explaining an operation example of a semiconductor device. FIG. 13A to FIG. 13C is a diagram showing a structural example of a semiconductor device. FIG. 14A to FIG. 14E is a diagram showing a structural example of a semiconductor device. Fig.15A and Fig. 15B is a diagram showing a structural example of a semiconductor device. Fig.16A and Fig. 16B is a diagram showing a structural example of a semiconductor device. 17A to 17D is a diagram showing a structural example of a semiconductor device. Fig.18 is a diagram showing a structural example of a semiconductor device. Fig.19 is a diagram showing a structural example of a semiconductor device. Fig. 20A and Fig. 20B is a diagram showing a structural example of a semiconductor device. Fig.21A and Fig.21B is a diagram showing a structural example of a semiconductor device. Fig.22A and Fig. 22B is a diagram showing a structural example of a semiconductor device. Fig.23A and Fig. 23B is a diagram showing a structural example of a semiconductor device. Fig.24A and Fig. 24B is a diagram showing a structural example of a semiconductor device. Fig.25 A diagram illustrating a structural example of a semiconductor device. Fig.26 A diagram illustrating a structural example of a semiconductor device. FIG. 27A to FIG. 27J It is a diagram for explaining an example of an electronic device. FIG. 28A to FIG. 28C It is a diagram for explaining an example of an electronic device. Fig.29 is a diagram showing an example of space equipment. Modes for Carrying Out the Invention

[0016] The following describes the embodiments with reference to the accompanying drawings. It should be noted that a person skilled in the art can easily understand that the embodiments can be implemented in a variety of different ways, and the methods and details can be transformed into various forms without departing from the purpose and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the following embodiments.

[0017] In the drawings, the size, thickness of the layer or the area are sometimes exaggerated for the sake of clarity. Therefore, the present invention is not limited to the dimensions in the drawings. In addition, in the drawings, ideal examples are schematically shown, so the present invention is not limited to the shapes or numerical values ​​shown in the drawings.

[0018] In addition, in particular, in a plan view (also referred to as a top view) or a perspective view, description of some components may be omitted to facilitate understanding of the invention. Also, description of some hidden lines may be omitted.

[0019] In addition, unless otherwise specified, the transistors shown in this specification, etc. are enhancement-type (normally closed) field-effect transistors. In addition, when the transistors shown in this specification, etc. are n-channel transistors and there is no special description, the threshold voltage (also referred to as "Vth") of the transistor is greater than 0V. In addition, when the transistors shown in this specification, etc. are p-channel transistors and there is no special description, the threshold voltage (also referred to as "Vth") of the transistor is less than 0V. In addition, when there is no special description, the Vth of multiple transistors of the same conductivity type are equal.

[0020] In this specification, etc., unless otherwise specified, the on-state current refers to the drain current (also referred to as "Id") when the transistor is in the on state (also referred to as the "on state"). Unless otherwise specified, the on state in an n-channel transistor refers to a state where the voltage between the gate and the source (also referred to as "Vg" or "Vgs") is greater than Vth, and the on state in a p-channel transistor refers to a state where Vg is less than Vth. For example, the on-state current of an n-channel transistor sometimes refers to the drain current when Vg is greater than Vth.

[0021] In addition, in this specification, etc., unless otherwise specified, the off-state current refers to the Id when the transistor is in the off state (also called the non-conducting state or the blocking state). Unless otherwise specified, in an n-channel transistor, the off state refers to a state where Vg is lower than Vth (in a p-channel transistor, higher than Vth). In this specification, etc., the off-state current is sometimes referred to as the leakage current.

[0022] In this specification, etc., metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (Oxide Semiconductor, also referred to as OS), etc. For example, when a metal oxide is used for a semiconductor layer of a transistor, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, an OS transistor can be referred to as a transistor containing an oxide or an oxide semiconductor.

[0023] Ordinal numerals such as "first" and "second" in this specification, etc. are added to avoid confusion between constituent elements, and do not indicate a certain order or sequence such as process sequence or stacking sequence. In addition, for terms that are not added with ordinal numerals in this specification, etc., ordinal numerals are sometimes added to the terms in the claims to avoid confusion between constituent elements. Note that the ordinal numerals added in this specification, etc. are sometimes different from the ordinal numerals added in the claims. Note that for terms that are added with ordinal numerals in this specification, etc., their ordinal numerals are sometimes omitted in the claims, etc.

[0024] In this specification, etc., "electrode", "wiring" and "terminal" do not limit the functions of constituent elements. For example, sometimes an "electrode" is used as a part of a "wiring", and vice versa. Furthermore, "electrode" and "wiring" also include a case where a plurality of "electrodes" and "wiring" are provided as one body, etc. In addition, for example, sometimes a "terminal" is used as a part of a "wiring" or an "electrode", and vice versa. Furthermore, "terminal" also includes a case where a plurality of "electrodes", "wiring", "terminals", etc. are formed as one body, etc. Therefore, for example, an "electrode" can be a part of a "wiring" or a "terminal", for example, a "terminal" can be a part of a "wiring" or an "electrode". In addition, "electrode", "wiring" and "terminal" etc. can sometimes be replaced by "area" etc.

[0025] In this specification, the supply of a signal refers to the supply of a predetermined potential to a wiring, etc. Therefore, sometimes "signal" can be replaced by "potential", etc. In addition, sometimes "potential", etc. can be replaced by "signal". "Signal" can be a variable potential or a fixed potential. For example, it can also be a power supply potential.

[0026] In addition, depending on the situation or state, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film" in some cases. Also, "insulating film" may be replaced with "insulating layer" in some cases.

[0027] In this specification, etc., "capacitor" can be, for example, a circuit element having an electrostatic capacitance value higher than 0F, a region of wiring having an electrostatic capacitance value higher than 0F, a parasitic capacitance, or a gate capacitance of a transistor. In addition, "capacitor", "parasitic capacitance" or "gate capacitance" can sometimes be replaced by "capacitor". In contrast, "capacitor" can sometimes be replaced by "capacitor", "parasitic capacitance" or "gate capacitance". In addition, "capacitor" (including "capacitor" with more than three terminals) has a structure including an insulator and a pair of conductors sandwiching the insulator. Therefore, the "pair of conductors" of "capacitor" can be replaced by "a pair of electrodes", "a pair of conductive areas", "a pair of areas" or "a pair of terminals". In addition, sometimes "one of a pair of terminals" is referred to as "a terminal" or "a first terminal". In addition, sometimes "the other of a pair of terminals" is referred to as "another terminal" or "a second terminal". The electrostatic capacitance value can be, for example, more than 0.05fF and less than 10pF. In addition, for example, it can also be more than 1pF and less than 10μF.

[0028] When using transistors with different polarities or when the current direction of a circuit changes, the functions of the transistor's "source" and "drain" are sometimes interchanged. Therefore, in this specification, "source" and "drain" may be interchanged.

[0029] In this specification, "gate" refers to a part or all of a gate electrode and a gate wiring. A gate wiring is a wiring for electrically connecting a gate electrode of at least one transistor to another electrode or another wiring.

[0030] In this specification, etc., "source" refers to a part or all of a source region, a source electrode, and a source wiring. A source region refers to a region in a semiconductor layer whose resistivity is less than a certain value. A source electrode refers to a conductive layer including a portion connected to a source region. A source wiring refers to wiring for electrically connecting a source electrode of at least one transistor to other electrodes or other wiring.

[0031] In this specification, etc., "drain" refers to a part or all of a drain region, a drain electrode, and a drain wiring. The drain region refers to a region in a semiconductor layer whose resistivity is less than a certain value. The drain electrode refers to a conductive layer including a portion connected to the drain region. The drain wiring refers to a wiring used to electrically connect the drain electrode of at least one transistor to other electrodes or other wirings.

[0032] In this specification, etc., for the sake of convenience, words and phrases indicating configurations such as "upper", "lower", "above" or "below" are sometimes used to explain the positional relationship of constituent elements with reference to the drawings. In addition, the positional relationship of constituent elements is appropriately changed according to the direction in which each structure is described. Therefore, the words and phrases described in the specification, etc. are not limited, and the words and phrases can be appropriately replaced according to the situation. For example, if it is an expression of "an insulator located on the top surface of a conductor", by rotating the direction of the illustrated drawing by 180 degrees, it can be replaced with "an insulator located below the conductor".

[0033] In addition, the words "above" and "below" are not limited to the case where the positional relationship of the components is "directly above" or "directly below" and in direct contact. For example, if it is an expression "electrode B on insulating layer A", it is not necessarily necessary that electrode B is formed on insulating layer A in direct contact, and the case where other components are included between insulating layer A and electrode B may also be included.

[0034] In this specification, etc., the words "overlap" and the like do not limit the state of the stacking order of the constituent elements. For example, "electrode B overlapping with insulating layer A" is not limited to the state where electrode B is formed on insulating layer A, but also includes the state where electrode B is formed under insulating layer A or the state where electrode B is formed on the right side (or left side) of insulating layer A, etc.

[0035] In this specification, the words "adjacent" and "close to" do not limit the state of direct contact between components. For example, if it is an expression "electrode B adjacent to insulating layer A", it does not necessarily mean that insulating layer A and electrode B are in direct contact, and it may also include the case where other components are included between insulating layer A and electrode B.

[0036] In this specification, etc., "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°. Therefore, a state where the angle is greater than -5° and less than 5° is also included. "Approximately parallel" refers to a state where the angle formed by two straight lines is greater than -30° and less than 30°. In addition, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°. Therefore, a state where the angle is greater than 85° and less than 95° is also included. In addition, "approximately perpendicular" refers to a state where the angle formed by two straight lines is greater than 60° and less than 120°.

[0037] In this specification, etc., unless otherwise stated, the case where count values ​​or measurement values ​​are "same", "identical", "equal", or "uniform" (including synonyms of these words) includes a variation of ±20% as an error.

[0038] In addition, arrows indicating the X direction, Y direction, and Z direction are sometimes attached in the drawings and the like according to this specification. In this specification and the like, the "X direction" refers to the direction along the X axis, and unless otherwise stated, the forward direction and the reverse direction are sometimes not distinguished. The "Y direction" and the "Z direction" are also the same as the "X direction". In addition, the X direction, the Y direction, and the Z direction are directions that intersect each other. More specifically, the X direction, the Y direction, and the Z direction are directions that are orthogonal to each other. In this specification and the like, one of the X direction, the Y direction, and the Z direction is sometimes referred to as the "first direction". In addition, the other one is sometimes referred to as the "second direction". In addition, the remaining one is sometimes referred to as the "third direction".

[0039] In this specification, when the same symbol is used for multiple components and it is necessary to distinguish them, a symbol such as "A", "b", "_1", "[n]", "[m, n]" is sometimes added to the symbol for identification. For example, in order to clearly indicate a specific storage unit 255 among the multiple storage units 255, it is sometimes described as storage unit 255[1], storage unit 255[2], and storage unit 255[3].

[0040] (Implementation Method 1) In this embodiment, a structural example of a semiconductor device according to one embodiment of the present invention is described. Figure 1A is a block diagram showing a structural example of the semiconductor device 100 .

[0041] Figure 1A The semiconductor device 100 shown includes a CPU core 110, a bus 120, a PMU (Power Management Unit) 130, an input / output IF 140, a cache memory 150, and a state control unit 160. The CPU core 110 includes a calculation unit 111 and a register group 200.

[0042] Note that the components of the semiconductor device 100 are not limited to Figure 1A The components shown in the figure may also include other components. Figure 1A A portion of the components shown. In addition, one component may have the function of another component.

[0043] The register group 200 has a function of temporarily storing data used by the CPU core 110. In addition, the CPU core 110 has a function of performing arithmetic processing in the operation unit 111 based on the data held in the register group 200. The operation unit 111 can perform various arithmetic operations such as four arithmetic operations and logical operations. The operation unit 111 is also called an ALU (Arithmetic Logic Unit). The CPU core 110 is sometimes referred to as a processor core. The CPU core 110 can have a structure in which one is provided in one semiconductor device 100 (single core) or a structure in which two or more are provided (multi-core such as dual core or many cores).

[0044] The register group 200 includes a plurality of registers 201 (register 201 [1], register 201 [2], register 201 [3], register 201 [4], register 201 [5], and register 201 [6]). Note that the register 201 is a type of storage device and also a type of semiconductor device.

[0045] Register 201[1] is used, for example, as a program counter. The program counter has a function of storing a memory address indicating the instruction to be executed next. Register 201[2] is used, for example, as an instruction register. The instruction register has a function of storing instructions read from the memory. Register 201[3] is used, for example, as a base register. The base register has a function of storing the header address of the program and data stored in the memory. Register 201[4] is used, for example, as an index register. The index register has a function of storing the size of data. Register 201[5] is used, for example, as an accumulator. The accumulator has a function of temporarily storing the result of the operation performed by the operation unit 111. Register 201[6] is used, for example, as a general register. A general register is not limited to a specific purpose and is used for various purposes. For example, register 201[6] can be used as an accumulator.

[0046] Note that the registers 201 included in the register group 200 may not include all of the above registers 201, but may include other registers 201. In addition, it may also include a part or all of a plurality of these registers 201. For example, it may also include a plurality of registers 201 used as general registers [6].

[0047] The bus 120 has a function of controlling transmission and reception of data among the CPU core 110 , the PMU 130 , the input / output IF 140 , the cache memory 150 , and the state control circuit 160 .

[0048] The PMU 130 includes a control circuit 131 and a register 201 [7], and has a function of controlling the start and stop of power gating. In addition, the register 201 [7] is also a type of register 201. The register 201 [7] is used as a setting register, for example. The setting register has a function of temporarily storing data used by the control circuit 131.

[0049] The input / output IF 140 has a function of controlling the transmission and reception of data between an external device such as a main memory (not shown) and the semiconductor device 100. Data output from an external device is input to the semiconductor device 100 via the input / output IF 140. In addition, data output from the semiconductor device 100 is input to an external device via the input / output IF 140. The cache memory 150 has a function of storing frequently used instructions and data, etc., and reducing the access frequency to the main memory to increase the operating speed of the semiconductor device 100.

[0050] Figure 1B 2 is a block diagram showing a configuration example of the register 201. The register 201 includes n (n is any integer greater than or equal to 2) OSFFs 210. Figure 1B In the figure, the first OSFF210 is represented as OSFF210[1], and the nth OSFF210 is represented as OSFF210[n]. OSFF210 has the function of holding 1-bit data. Therefore, n is equivalent to the length of data that register 201 can store at one time. For example, in register 201 that can store 64-bit data at one time, n is 64. Note that one OSFF210 can also be referred to as a register 201 that can store 1-bit data.

[0051] Figure 2A A three-dimensional block diagram of OSFF210 is shown. Figure 2B FIG. 2 shows an example of a circuit structure of OSFF 210. OSFF 210 includes a data holding circuit 230 on a scan flip-flop 220 (volatile register). The data holding circuit 230 includes a plurality of storage circuits 231. In this embodiment, three storage circuits 231 (storage circuit 231[1] to storage circuit 231[3]) are shown overlappingly, but the number of storage circuits 231 is not limited to three. In addition, all scan flip-flops 220 included in the register 201 are collectively referred to as a flip-flop group 250 (see FIG. 250 ). Figure 1B ). In addition, all the data holding circuits 230 included in the register 201 are collectively referred to as a group memory 260. Therefore, the group memory 260 includes a plurality of storage circuits 231.

[0052] The scan flip-flop 220 includes a selector 221 and a flip-flop 222. The data holding circuit 230 includes a storage circuit 231. In addition, the OSFF 210 includes a transistor 232.

[0053] The state control unit 160 is a circuit that outputs control signals for switching interrupt processing (also called "exceptional processing") and power gating based on an interrupt signal input from the outside, a sleep signal generated by the CPU core 110, and the like. The state control unit 160 generates, for example, a clock signal CLK and various signals (signal BK, signal RE, signal SE). The clock signal CLK and various signals are input to the CPU core 110.

[0054] The signal BK is a signal for controlling the storage of data held in the flip-flop 222 in the scan flip-flop 220. By storing the data, the data held by the flip-flop 222 is held in any one of the plurality of storage circuits 231 in the data holding circuit 230. Figure 2B In the figure, the signal BK supplied to the storage circuit 231[1] is represented as the signal BK[1], the signal BK supplied to the storage circuit 231[2] is represented as the signal BK[2], and the signal BK supplied to the storage circuit 231[3] is represented as the signal BK[3].

[0055] The signal RE is a signal for controlling the loading of data held in any one of the plurality of storage circuits 231 in the data holding circuit 230. By loading the data, the data held in any one of the plurality of storage circuits 231 in the data holding circuit 230 is held in the flip-flop 222 in the scan flip-flop 220. Figure 2B , the signal RE supplied to the storage circuit 231[1] is represented as the signal RE[1], the signal RE supplied to the storage circuit 231[2] is represented as the signal RE[2], and the signal RE supplied to the storage circuit 231[3] is represented as the signal RE[3].

[0056] The signal SE is a switching signal of the selector 221. The clock signal CLK is a signal that determines the operation timing of the flip-flop 222.

[0057] The OSFF 210 has a function of holding data input from the terminal D or data input from the terminal SD of the scan flip-flop 220 in the scan flip-flop 220 and outputting the data from the terminal Q according to the clock signal CLK. The data of the scan flip-flop 220 output from the terminal Q is held by any one of the plurality of storage circuits 231 included in the data holding circuit 230 according to the signal BK. The data of any one of the plurality of storage circuits 231 included in the data holding circuit 230 is loaded from the terminal SD of the scan flip-flop 220 to the scan flip-flop 220 according to the signal RE.

[0058] The selector 221 has a function of transmitting one of the signals input to the terminal D or the terminal SD to the flip-flop 222 according to the signal SE. The terminal D is input with data supplied from the outside of the OSFF 210. The terminal SD is input with data input from the data holding circuit 230 or scan test data supplied through the terminal SD_IN. The scan test data supplied through the terminal SD_IN is input to the terminal SD through the transistor 232. The conduction state or the non-conduction state of the transistor 232 is controlled by the signal BK[0].

[0059] exist Figure 2B In the figure, a D flip-flop is shown as the flip-flop 222, but the present invention is not limited to this. As the flip-flop 222, a flip-flop in a standard circuit library can be used. The transistor included in the flip-flop 222 is a Si transistor that can constitute a CMOS circuit, and a circuit such as an inverting loop can hold a data. The flip-flop 222 holds the input terminal D according to the clock signal CLK. F The data is stored in the output terminal Q F Output to terminal Q.

[0060] Each of the plurality of storage circuits 231 is connected to a terminal Q and a terminal SD. In each of the plurality of storage circuits 231, a terminal electrically connected to the terminal Q is referred to as an input terminal, and a terminal electrically connected to the terminal SD is referred to as an output terminal. F The input terminal D of the flip-flop 222 is electrically connected to the input terminal of the data holding circuit 230 (storage circuit 231). F The data holding circuit 230 (storage circuit 231 ) is electrically connected to an output terminal of the data holding circuit 230 via the terminal SD and the selector 221 .

[0061] Each of the plurality of storage circuits 231 includes a transistor 233, a transistor 234, and a capacitor 235. The transistor 233 is provided between one electrode of the capacitor 235 and the terminal Q. The transistor 234 is provided between one electrode of the capacitor 235 and the terminal SD. In addition, the other electrode of the capacitor 235 is connected to the wiring CL. In each of the plurality of storage circuits 231, one electrode of the capacitor 235 is represented as a node SN.

[0062] Transistor 233 and transistor 234 preferably use OS transistors. Since the off-state current of the OS transistor is very small, the charge held in the node SN is not easy to decrease, so the voltage drop of the node SN can be suppressed for a long time. In addition, almost no power is required to hold the data (charge) written to the node SN. Therefore, the storage circuit 231 included in the data holding circuit 230 can also be said to be a non-volatile memory. In addition, the storage circuit 231 rewrites data by charging and discharging the capacitor 235, so in principle there is no limit to the number of rewrites. In addition, data can be written and read at high speed and low energy.

[0063] A memory circuit configured using OS transistors is also referred to as an “OS memory.” Therefore, the memory circuit 231 is an OS memory.

[0064] Alternatively, transistors including back gates may be used as the transistors 233 and 234. By supplying a constant voltage to the back gates, Vth of the transistors can be controlled.

[0065] In the storage circuit 231, the OS transistor is used as a switch. In the OS transistor, which is an n-channel transistor, by setting the signal supplied to the gate to a high level (hereinafter also referred to as "H"), the source and the drain can be turned on (on), and by setting the signal supplied to the gate to a low level (hereinafter also referred to as "L"), the source and the drain can be turned off (off). In addition, in the selector 221, by setting the signal SE to a high level, the signal of the terminal SD is selected, and by setting the signal SE to a low level, the signal of the terminal D can be selected.

[0066] For example, in the storage circuit 231[1], by setting the signal BK[1] to H, the data held by the flip-flop 222 can be written to the node SN of the storage circuit 231[1]. Similarly, by setting BK[2] to H and BK[3] to H, the data of the flip-flop 222 can be written to the node SN of the storage circuit 231[2] and the node SN of the storage circuit 231[3]. In addition, by setting RE[1] to H and SE to H, the data of the node SN of the storage circuit 231[2] can be written back to the flip-flop 222. Similarly, by setting RE[2] to H and SE to H, the data of the node SN of the storage circuit 231[2] can be written back to the flip-flop 222. Similarly, by setting RE[3] to H and SE to H, the data of the node SN of the storage circuit 231[3] can be written back to the flip-flop 222.

[0067] All transistors of the storage circuit 231 included in the data holding circuit 230 are preferably OS transistors. OS transistors are a type of thin film transistor and can be formed by stacking using existing thin film forming technology. By using OS transistors to form the storage circuit 231, the data holding circuit 230 can be stacked on the scan trigger 220 composed of a CMOS circuit using Si transistors.

[0068] For example, Figure 3A As shown in the OSFF210, a plurality of storage circuits 231 can be stacked as different layers on the scan flip-flop 220 composed of a CMOS circuit using Si transistors. Note that Figure 3A Storage circuits 231 [ 1 ], 231 [ 2 ] to 231 [ k ] (k is any integer greater than or equal to 2) are shown.

[0069] For example, Figure 3A and Figure 3B As shown, the scan flip-flop 220 may be formed in the layer 10 including the Si transistor, and the data holding circuit 230 may be formed in the layer 20 including the OS transistor. That is, the flip-flop group 250 may be formed in the layer 10, and the group memory 260 may be formed in the layer 20. In addition, the layer 20 may be formed in a plurality of layers. Figure 3A and Figure 3B The following example is shown: the memory circuit 231[1] is formed in the layer 20[1], the memory circuit 231[2] is formed in the layer 20[2], and the memory circuit 231[k] is formed in the layer 20[k]. In addition, the signal BK supplied to the memory circuit 231[k] is represented as the signal BK[k], and the signal RE supplied to the memory circuit 231[k] is represented as the signal RE[k].

[0070] By adopting this structure, a plurality of storage circuits 231 can be sequentially overlapped in the region where the scan flip-flop 220 is formed. Therefore, even if a plurality of storage circuits 231 are mounted, the area overhead of the OSFF 210 can be substantially reduced to zero. Therefore, a semiconductor device with a reduced occupied area can be realized.

[0071] To illustrate the working of OSFF210, Figure 4A FIG. 2 shows a structure in which the number of storage circuits 231 included in the data holding circuit 230 is four (k=4). Figure 4A In FIG. 1 , nodes SN[1] to SN[4] are shown as nodes SN for holding data in the storage circuits 231 (storage circuits 231[1] to 231[4]) included in the data holding circuit 230. Figure 4A, signals BK[1] to BK[4] and signals RE[1] to RE[4] that control storage circuits 231[1] to 231[4] are shown.

[0072] Figure 4B Show instructions Figure 4A An example of the timing diagram of the operation of OSFF210 is shown in FIG. Figure 4B In , T0 to T7 represent time. Figure 4B , a clock signal CLK, a terminal D, a terminal Q, a signal BK[1], a signal BK[2], a signal RE[1], a signal RE[2], a node SN[1], a node SN[2], and a signal SE supplied to the selector 221 are shown. The flip-flop 222 stores data of the input terminal D in synchronization with the rising edge of the clock signal CLK (a waveform in which the clock signal CLK switches from the L level to the H level) and outputs the stored data from the output terminal Q.

[0073] also, FIG. 5A to FIG. 5E Shown for illustration Figure 4B The timing diagram is a schematic diagram of the operation of the OSFF210. Figure 5A The scan trigger 220 and the data holding circuit 230 include storage circuits 231[1] to 231[4]. Figure 5B , Figure 5C , Figure 5D as well as Figure 5E Show Figure 4B The inputs and outputs at time T1, time T3, time T5, and time T7 are data from 131 [1] to storage circuit 231 [4] of scan flip-flop 220 and data holding circuit 230.

[0074] At time T0, in synchronization with the rising edge of the clock signal CLK, the scan flip-flop 220 holds data D0 and outputs it from the output terminal Q. The terminal D is supplied with data D1.

[0075] At time T1, in synchronization with the rising edge of the clock signal CLK, the scan flip-flop 220 holds the data D1 supplied to the terminal D and outputs the data D1 from the output terminal Q. At time T1, by setting the signal BK[1] to H, the signal RE[1] to L, and the signal SE to L, the data D1 output from the output terminal Q of the scan flip-flop 220 is held in the storage circuit 231[1] (refer to Figure 5B ). Terminal D is supplied with data D2.

[0076] At time T1 , signals BK[ 2 ] to BK[ 4 ] and signals RE[ 2 ] to RE[ 4 ] are L.

[0077] At time T2, in synchronization with the rising edge of the clock signal CLK, the scan flip-flop 220 holds the data D2 supplied to the terminal D, and outputs the data D2 from the output terminal Q. The terminal D is supplied with data D3.

[0078] At time T3, in synchronization with the rising edge of the clock signal CLK, the scan flip-flop 220 holds the data D3 supplied to the terminal D and outputs the data D3 from the output terminal Q. At time T3, by setting the signal BK[2] to H, the signal RE[2] to L, and the signal SE to L, the data D3 of the scan flip-flop 220 is held in the storage circuit 231[2] (refer to Figure 5C ). Terminal D is supplied with data D4.

[0079] At time T3 , the signals BK[ 1 ], BK[ 3 ], BK[ 4 ], RE[ 1 ], RE[ 3 ], and RE[ 4 ] are L.

[0080] At time T4, in synchronization with the rising edge of the clock signal CLK, the scan flip-flop 220 holds the data D4 supplied to the terminal D, and outputs the data D4 from the output terminal Q. The terminal D is supplied with data D5.

[0081] At time T5, by setting BK[1] to L, RE[1] to H, and SE to H, the data D1 held in the storage circuit 231[1] can be written back to the scan flip-flop 220 (see Figure 5D ). Terminal D is supplied with data D6.

[0082] At time T5 , signals BK[ 2 ] to BK[ 4 ] and signals RE[ 2 ] to RE[ 4 ] are L.

[0083] At time T6, in synchronization with the rising edge of the clock signal CLK, the scan flip-flop 220 holds the data D6 supplied to the terminal D, and outputs the data D6 from the output terminal Q. The terminal D is supplied with data D7.

[0084] At time T7, by setting BK[2] to L, RE[2] to H, and SE to H, the data D3 held by the storage circuit 231[2] can be written back to the scan flip-flop 220 (see Figure 5E ). Terminal D is supplied with data D8.

[0085] At time T7 , the signals BK[ 1 ], BK[ 3 ], BK[ 4 ], RE[ 1 ], RE[ 3 ], and RE[ 4 ] are L.

[0086] like Figure 4B and FIG. 5B to FIG. 5EAs described above, OSFF210 can save the data of the ongoing process before the interrupt process and load the data for restarting the process after the interrupt process ends. In one embodiment of the present invention, the data saved according to the switching of the interrupt process can be maintained in a plurality of storage circuits included in the data holding circuit. By adopting this structure, the data can be saved and loaded according to the switching of the plurality of interrupt processes according to the timing of the input interrupt signal. Therefore, a plurality of interrupt processes can be performed in sequence. Therefore, data processing can be performed more efficiently.

[0087] Figure 6 is to use Figure 4A The OSFF210 and Figure 4B The operation of the OSFF 210 is described as a timing chart of the switching operation of the interrupt processing of the semiconductor device 100, where the horizontal axis represents the passage of time (Time).

[0088] At time Ta, the data of the scan trigger 220 is stored in the storage circuit 231[1] (saved in 231[1]) while the semiconductor device 100 is performing the first process (Ope1), and then the data of the storage circuit 231[2] is written back to the scan trigger 220 (loaded from 231[2]). In this way, the semiconductor device 100 can interrupt the first process and perform the second process (Ope2).

[0089] At time Tb, the data of the scan trigger 220 is stored in the storage circuit 231[2] (saved in 231[2]) while the semiconductor device 100 is performing the second process, and then the data of the storage circuit 231[3] is written back to the scan trigger 220 (loaded from 231[3]). In this way, the semiconductor device 100 can interrupt the second process and perform the third process (Ope3).

[0090] At time Tc, the data of the scan trigger 220 is stored in the storage circuit 231[3] (saved in 231[3]) while the semiconductor device 100 is performing the third process, and then the data of the storage circuit 231[1] is written back to the scan trigger 220 (loaded from 231[1]). Here, the data written back to the scan trigger 220 from the storage circuit 231[1] is the data stored in the storage circuit 231[1] from the scan trigger 220 at time Ta. That is, the above data is the data required to resume the first process that was interrupted at time Ta. In this way, the state of the third process can be stored and the semiconductor device 100 can resume the interrupted first process.

[0091] By using the OSFF 210 according to one embodiment of the present invention, a semiconductor device can be realized that can interrupt a process in progress, perform a high-priority interruption process, and then restart the interrupted process. Therefore, a semiconductor device with improved computing performance can be provided.

[0092] By including a plurality of OSFFs 210 , it is possible to realize a register 201 capable of temporarily backing up a plurality of multi-valued data. Fig. 7A is a three-dimensional block diagram of a register 201A including three OSFF210s. Figure 2A Three storage circuits 231 are shown. Figure 7B It is shown Fig. 7A FIG. 2 is a diagram showing an example of a circuit configuration of a register 201A.

[0093] Fig. 7A and Figure 7B The register 201A shown is a register 201 in which n is 3 and is used as a register 201 capable of storing 3 bits of data at a time. Therefore, the register 201A includes a trigger group 250 having three scan triggers 220 (scan trigger 220[1], scan trigger 220[2], and scan trigger 220[3]). Fig. 7A In FIG. 1 , the data holding circuit 230 provided above the scan flip-flop 220 [ 1 ] is represented as the data holding circuit 230 [ 1 ].

[0094] exist Figure 7B In the example, the terminal D included in the scan trigger 220[1] is represented as the terminal D[1], and the terminal SD is represented as the terminal SD[1]. In addition, the scan trigger 220[2] includes the terminal D[2] (not shown) as the terminal D, and includes the terminal SD[2] (not shown) as the terminal SD. Similarly, the scan trigger 220[3] includes the terminal D[3] (not shown) as the terminal D, and includes the terminal SD[3] (not shown) as the terminal SD.

[0095] In addition, the terminal Q of the scan trigger 220 [1] is represented as the terminal Q [1], the terminal Q of the scan trigger 220 [2] is represented as the terminal Q [2], and the terminal Q of the scan trigger 220 [3] is represented as the terminal Q [3].

[0096] The first layer (eg, layer 20[1]. see Figure 3A and Figure 3B) The gate of the transistor 233 included in each of the storage circuits 231[1,1], 231[1,2] and 231[1,3] is supplied with the signal BK[1], and the gate of the transistor 234 included in each of the storage circuits 231[1,1], 231[1,2] and 231[1,3] is supplied with the signal RE[1]. The storage circuits 231[1,1], 231[1,2] and 231[1,3] are used as a storage circuit capable of storing 3-bit data.

[0097] In addition, a second layer (eg, layer 20[2]. see Figure 3A and Figure 3B ) The gate of the transistor 233 included in each of the storage circuits 231[2,1], 231[2,2] and 231[2,3] is supplied with the signal BK[2], and the gate of the transistor 234 included in each of the storage circuits 231[2,1], 231[2,2] and 231[2,3] is supplied with the signal RE[2]. The storage circuits 231[2,1], 231[2,2] and 231[2,3] are used as a storage circuit capable of storing 3-bit data.

[0098] In addition, the gate of the transistor 233 included in each of the storage circuits 231[3,1], 231[3,2], and 231[3,3] provided in the third layer on the flip-flop group 250 is supplied with the signal BK[3], and the gate of the transistor 234 included in each of the storage circuits 231[3,1], 231[3,2], and 231[3,3] is supplied with the signal RE[3]. The storage circuits 231[3,1], 231[3,2], and 231[3,3] are used as a single storage circuit capable of storing 3-bit data. A circuit including a plurality of storage circuits 231 and used as a single storage circuit is sometimes referred to as a "memory cell".

[0099] therefore, Fig. 7A and Figure 7B The bank memory 260 of the illustrated register 201A includes three memory cells capable of storing 3 bits of data. Fig. 7A and Figure 7B The register 201A shown can back up the data held in the trigger group 250 in any one of the storage units before power gating. In addition, even if the interrupt processing is performed three times in succession, the data of each time can be backed up in sequence in different storage units. In addition, each time the interrupt processing is completed, the backed-up data can be restored to the trigger group 250.

[0100] Fig. 8A The register 201B and Figure 8B The register 201C shown is a register 201 assuming a case where n is 9 or more, and is used as a register 201 capable of storing n-bit data at a time.

[0101] Therefore, the register 201B and the register 201C as a trigger group 250 include n scan triggers 220 (scan trigger 220 [ 1 ] to scan trigger 220 [n]).

[0102] In addition, on the trigger group 250, the first layer includes n storage circuits 231 (storage circuit 231[1, 1] to storage circuit 231[1, n]), the second layer includes n storage circuits 231 (storage circuit 231[2, 1] to storage circuit 231[2, n]), and the third layer includes n storage circuits 231 (storage circuit 231[3, 1] to storage circuit 231[3, n]).

[0103] Fig. 9 A block diagram of the register 201B is shown when viewed from the X direction. Fig.10 FIG. 2 is a block diagram of the register 201C when viewed from the X direction. The signal SE is input to all scan flip-flops 220 included in the register 201B at the same time or substantially at the same time, and the clock signal CLK is input at the same time or substantially at the same time. The register 201C also has the same structure. Both the register 201B and the register 201C are used as registers capable of storing n bits of data in the flip-flop group 250 at a time.

[0104] The register 201C is a modified example of the register 201 B. In order to reduce duplication of descriptions, the descriptions of the register 201B and the register 201C can be interchanged unless otherwise specified.

[0105] The bank memory 260 includes a plurality of storage units 255 formed of a plurality of storage circuits 231. The storage capacities of the plurality of storage units 255 may be the same or different.

[0106] The register 201B includes a storage unit 255[1] having n storage circuits 231 (storage circuit 231[1,1] to storage circuit 231[1,n]) formed in the first layer on the flip-flop group 250. The signal BK[1] and the signal RE[1] are supplied to all the storage circuits 231 included in the storage unit 255[1]. The storage unit 255[1] is used as a storage circuit with a storage capacity of n bits. Note that the storage unit 255 with a storage capacity of n bits is sometimes referred to as an "n-bit storage unit 255".

[0107] In addition, the register 201B includes a storage unit 255 [2] having p storage circuits 231 formed in the second layer on the flip-flop group 250 as a storage unit 255. p is an integer greater than or equal to 1 and less than n. Fig. 8A and Fig. 9In the illustrated storage cell 255[2], the number of storage circuits 231, p, is 8. Therefore, the storage cell 255[2] is used as a storage circuit with a storage capacity of 8 bits. For example, when n is 64 and p is 8, eight storage cells 255[2] with a storage capacity of 8 bits can be formed in the second layer on the flip-flop group 250.

[0108] exist Fig. 8A and Fig. 9 In FIG. 1 , the first storage unit 255[2] is represented as a storage unit 255[2]a. The signal BK[2]a and the signal RE[2]a are supplied to all storage circuits 231 included in the storage unit 255[1]a. The storage unit 255[2]a is used as a storage circuit with a storage capacity of 8 bits.

[0109] The register 201B includes a storage unit 255 [3] having p storage circuits 231 formed in the third layer on the flip-flop group 250 as the storage unit 255. Fig. 8A and Fig. 9 In the illustrated storage cell 255[3], the number of storage circuits 231, p, is 4. Therefore, the storage cell 255[3] is used as a storage circuit with a storage capacity of 4 bits. For example, when n is 64 and p is 4, sixteen storage cells 255[3] with a storage capacity of 4 bits can be formed in the third layer on the flip-flop group 250.

[0110] exist Fig. 9 In the embodiment, the storage circuit 231[3,1] to the storage circuit 231[3,4] (refer to Fig. 8A ) is represented as storage unit 255[3]a, and includes storage circuits 231[3,5] to 231[3,8] (refer to Fig. 8A All storage circuits 231 included in the storage unit 255[3]a of the second storage unit 255[3] represented as the storage unit 255[3]b are supplied with the signal BK[3]a and the signal RE[3]a. All storage circuits 231 included in the storage unit 255[3]b are supplied with the signal BK[3]b and the signal RE[3]b. Both the storage unit 255[2]a and the storage unit 255[2]b are used as storage circuits with a storage capacity of 4 bits.

[0111] In addition, if Figure 8B and Fig.10As in the register 201C shown in FIG. 1 , a plurality of storage cells 255[2] (storage cells 255[2]a and storage cells 255[2]b) in which the number of storage circuits 231 is 4 and which are used as 4-bit storage circuits may be included in the second layer on the flip-flop group 250. In addition, a storage cell 255[3] having two storage circuits 231 may be included in the third layer on the flip-flop group 250.

[0112] exist Figure 8B and Fig.10 In the register 201C shown, the number p of storage circuits 231 included in the storage unit 255[3] is 2. Therefore, the storage unit 255[3] is used as a storage circuit with a storage capacity of 2 bits. For example, when n is 64 and p is 2, thirty-two storage units 255[3] with a storage capacity of 2 bits can be formed in the third layer on the flip-flop group 250.

[0113] exist Fig.10 In the embodiment, the storage circuit 231[3,1] and the storage circuit 231[3,2] (refer to Figure 8B ) is represented as storage unit 255[3]a, and includes storage circuit 231[3,3] and storage circuit 231[3,4] (refer to Figure 8B ) is represented as storage unit 255[3]b, and includes storage circuit 231[3,5] and storage circuit 231[3,6] (refer to Figure 8B ) is represented as storage unit 255[3]c, which includes storage circuit 231[3,7] and storage circuit 231[3,8] (refer to Figure 8B )'s second storage unit 255[3] is represented as storage unit 255[3]d.

[0114] The signal BK[3]a and the signal RE[3]a are supplied to all the storage circuits 231 included in the storage unit 255[3]a, the signal BK[3]b and the signal RE[3]b are supplied to all the storage circuits 231 included in the storage unit 255[3]b, the signal BK[3]c and the signal RE[3]c are supplied to all the storage circuits 231 included in the storage unit 255[3]c, and the signal BK[3]d and the signal RE[3]d are supplied to all the storage circuits 231 included in the storage unit 255[3]d. The storage units 255[3]a to 255[3]d are all used as storage circuits with a storage capacity of 2 bits.

[0115] The storage capacity of the storage unit 255 is not limited to the above storage capacity. The storage capacity of the storage unit 255 may be 32 bits or 16 bits. In addition, it may be 9 bits or 17 bits depending on the purpose and the like.

[0116] In this embodiment, n-bit storage cells 255 are provided in the first layer (for example, layer 20[1]. See Figure 3A and Figure 3B . ) is an example, but it can also be set outside the first layer. For example, it can also be set in layer 20[2] or layer 20[k].

[0117] The number of bits of data represented in binary is sometimes referred to as "bit length" or "data length". Storage cells 255 having different storage capacities may be provided in the same layer. For example, a 32-bit storage cell 255 having p=32, a 16-bit storage cell 255 having p=16, and an 8-bit storage cell 255 may be provided in the same layer. In other words, a plurality of storage cells 255 having different bit lengths of data that can be stored may be provided in the same layer.

[0118] Since the size (bit length) of the data held by the register 201 is sometimes different depending on the processing performed, it is not always the same size. For example, when 32 bits of data are stored in the 64-bit storage unit 255, unnecessary storage work is performed in the remaining 32 bits. Therefore, unnecessary power consumption occurs. By providing storage units 255 with various storage capacities in the group memory 260, data of different sizes can be efficiently stored. Therefore, the power consumption of the register 201 can be reduced.

[0119] Furthermore, by combining storage cells 255 of different storage capacities, data of various sizes can be stored efficiently. For example, by combining a 4-bit storage cell 255 with p=4 and an 8-bit storage cell 255 with p=4, 12-bit data can be stored.

[0120] When power gating is performed, the data (n-bit data) of all scan flip-flops 220 need to be backed up. At this time, the n-bit data stored in the scan flip-flops 220 may be divided into a plurality of data and stored in a plurality of storage units 255 .

[0121] On the other hand, in order to divide the n-bit data into multiple pieces and store them, the following steps are required: a step of finding multiple available storage units 255; a step of confirming the storage capacity of each of the multiple available storage units 255; a step of determining the division positions of the n-bit data to be stored; and a step of actually storing the data, etc. This results in a long time required to start and recover from power gating, resulting in unnecessary power consumption.

[0122] Therefore, at least one of the plurality of storage units 255 is preferably a storage unit 255 having a storage capacity of n bits. That is, at least one of the plurality of storage units 255 preferably includes a storage unit 255 having the same storage capacity as the register 201B.

[0123] As described above, the semiconductor device of this embodiment can restart the original process based on the data immediately before the interruption process occurs, even if the interruption process occurs during the program processing and other interruption processes occur. The data used to restart the interruption process is held by the register group 200 in the CPU core 110. Therefore, it is not necessary to access an external memory such as SRAM or DRAM to save or load data. Therefore, the execution of the interruption process and the saving or loading of data accompanying the recovery of the interruption process can be efficiently performed without generating a time lag.

[0124] The structure described in this embodiment mode can be implemented in combination with the structures described in other embodiment modes as appropriate.

[0125] (Implementation Method 2) In this embodiment, an operation example of the semiconductor device 100 according to one embodiment of the present invention is described. As described above, the semiconductor device 100 includes the register 201 according to one embodiment of the present invention (see FIG. 1 ). The register 201 illustrated in this embodiment is a register capable of storing 64-bit data in the flip-flop group 250 . Fig.11 2 is a timing chart for explaining the operation status of the semiconductor device 100 and the register 201 , and the horizontal axis represents the passage of time (Time).

[0126] [Time] In a state where the semiconductor device 100 is performing the first process ( Ope1 ), at time Ta, a signal for performing power gating is supplied from the CPU core 110 or through the input / output IF 140 to the state control unit 160 .

[0127] The state control unit 160 backs up (saves) the 64-bit data held by the flip-flop group 250 of the register 201 to the storage unit 255 with a storage capacity of 64 bits included in the register 201. For example, the data is saved to the storage unit 255[1] with a storage capacity of 64 bits (save to 255[1]).

[0128] In the register 201 according to one embodiment of the present invention, by setting the signal BK[1] to L, all 64-bit data can be stored in the storage unit 255[1] (see Figure 2B and Fig. 9 ). That is, since data backup can be performed in 1 clock operation, data backup can be performed quickly.

[0129] The state control unit 160 supplies a signal to stop the power supply to the PMU 130. The power supply may be stopped for the entire CPU core 110 or for a part of the CPU core 110. For example, the power supply may be stopped for all the registers 201 of the register group 200 or for a part of the registers 201 of the register group 200.

[0130] In this way, the semiconductor device 100 transitions to the power gating state. Note that in the power gating state, power supply to a circuit or the like required for restarting power supply later is not stopped.

[0131] [Time Tb] At time Tb, a signal indicating that power gating is terminated is supplied to the state control unit 160 from the CPU core 110 or through the input / output IF 140. The state control unit 160 supplies a signal indicating that power supply is resumed to the PMU 130.

[0132] After the power supply is restarted, the state control unit 160 reads the data held by the storage unit 255[1] of the register 201 into the flip-flop group 250 of the register 201 (loads from 255[1]). Then, the semiconductor device 100 restarts the first process interrupted at the time Ta. In this way, the semiconductor device 100 transitions from the power gating state to the normal active state (Active).

[0133] In addition, in the register 201 according to one embodiment of the present invention, by setting the signal RE[1] to H while the signal BK[1] remains at L, and then setting the signal SE to H, all 64 bits of data stored in the storage cell 255[1] can be restored from the storage cell 255[1] to the flip-flop group 250. That is, since the data can be restored in a 2-clock operation, the data can be restored quickly.

[0134] [Time Tc] When the semiconductor device 100 is performing the first process ( Ope1 ), at time Tc, a signal for preparing to perform the second process ( Ope2 ) as an interrupt process is supplied from the CPU core 110 or through the input / output IF 140 to the state control unit 160 .

[0135] The state control unit 160 determines the storage unit 255 to store the data according to the bit length of the data held by the flip-flop group 250 of the register 201. For example, when the bit length of the data is 8 bits, the data is stored in the storage unit 255[2]a having a storage capacity of 8 bits (stored in 255[2]a).

[0136] Note that when there is no space in the storage unit 255 having the same bit length as the stored data, the data may be stored in a storage unit 255 having a larger bit length than the data. Alternatively, the data may be divided and stored in a plurality of storage units 255 having a smaller bit length than the data.

[0137] Next, data required for the second process is read from the storage unit 255[3]a (loaded from 255[3]a). The data required for the second process may be read from the cache memory 150 or supplied from the outside via the input / output IF 140. After reading the data required for the second process, the semiconductor device 100 performs the second process.

[0138] [Time Td] When the semiconductor device 100 is performing the second process, at time Td, a signal for preparing to perform the third process (Ope3) as an interrupt process is supplied from the CPU core 110 or through the input / output IF 140 to the state control unit 160.

[0139] The state control unit 160 determines the storage unit 255 to store the data according to the bit length of the data held by the flip-flop group 250 of the register 201. For example, when the bit length of the data is 4 bits, the data is stored in the storage unit 255[3]a having a storage capacity of 4 bits (stored in 255[3]a).

[0140] Next, data required for the third process is read from storage unit 255[3]b (loaded from 255[3]b). The data required for the third process may be read from cache memory 150 or supplied from the outside via input / output IF 140. After reading the data required for the third process, semiconductor device 100 performs the third process.

[0141] [Time Te] At time Te, the third process ends. After the third process ends, the data held by the flip-flop group 250 of the register 201 may be stored in the storage unit 255 (stored in 255[3]b).

[0142] After the third process is completed, the stored data is read from the storage unit 255[3]a (loaded from 255[3]a) to restart the interrupted second process. After reading the data required for the second process, the semiconductor device 100 restarts the interrupted second process.

[0143] [Time Tf] At time Tf, the second process ends. After the second process ends, the data held by the flip-flop group 250 of the register 201 may be stored in the storage unit 255 (stored in 255[3]a).

[0144] After the second process is completed, the stored data is read from the storage unit 255[2]a (loaded from 255[2]a) to restart the interrupted first process. After reading the data required for the first process, the semiconductor device 100 restarts the interrupted first process.

[0145] In addition, the registers 201[1], 201[2], 201[3], 201[4], 201[5] and 201[6] included in the CPU core 110 may also perform different processing on each register. For example, Fig.12 As shown in the timing diagram, only registers 201[1] and 201[2] may be in the power gating state during the period from time Ta to time Tb. In addition, during the period from time Tb to time Tc, data for performing the second processing may be maintained in registers 201[1] and 201[2], and data for performing the first processing may be maintained in registers 201[5] and 201[6].

[0146] The storage unit 255 is composed of an OS memory, so data can be written and read at high speed and low energy. Therefore, the data held by the flip-flop group 250 just before the power gating state is transferred can be backed up in the storage unit 255 included in the group memory 260 in a short time. In addition, the data backed up in the storage unit 255 can also be retained during the power gating state. And when returning to the active state from the power gating state, the data of the storage unit 255 can be written back to the flip-flop group 250 in a short time, so that the processing can be started again immediately.

[0147] In addition, even when interrupt processing occurs, data backup (writing) and recovery (reading) can be performed at high speed and low energy. By making the group memory 260 include multiple storage units 255 with different storage capacities, data with different bit lengths can be efficiently backed up. That is, the use efficiency of the group memory 260 can be improved.

[0148] The structure described in this embodiment mode can be implemented in combination with the structures described in other embodiment modes as appropriate.

[0149] (Implementation method 3) In this embodiment, an example of a stacked-layer structure of a semiconductor device according to one embodiment of the present invention is described.

[0150] Fig.13AThis is a plan view of a memory circuit 231 which is one of the semiconductor devices, as viewed from the Z direction. Fig. 13B From the Y direction Fig.13A A cross-sectional view of the portion indicated by the dot-dash line A1-A2. Fig. 13C From the X direction Fig.13A A cross-sectional view of the portion indicated by the dashed line A3-A4 in FIG. Fig.13A Note that in this embodiment mode and the like, the stacking direction of layers constituting the semiconductor device is set to the Z direction.

[0151] The memory circuit 231, which is one of the semiconductor devices, includes an insulating layer 353, a conductive layer 351 formed in a manner embedded in the insulating layer 353, and a conductive layer 352. The conductive layer 351 and the conductive layer 352 can be formed simultaneously using the same material and the same manufacturing process. In addition, it is preferable to make the positions (positions in the Z direction) of the top surfaces of the insulating layer 353, the conductive layer 351, and the conductive layer 352 consistent or approximately consistent by using a chemical mechanical polishing (CMP) method or the like. By performing CMP treatment, the unevenness of the sample surface can be reduced, thereby improving the coverage of the insulating layer and the conductive layer to be formed later.

[0152] In addition, an insulating layer 354 is included over the insulating layer 353, the conductive layer 351, and the conductive layer 352, and a conductive layer 355 is included over the insulating layer 354. The conductive layer 351 and the conductive layer 355 have a region where they overlap with each other with the insulating layer 354 interposed therebetween.

[0153] In addition, a region including the conductive layer 351, the conductive layer 355, and the insulating layer 354 and in which the conductive layer 351 and the conductive layer 355 overlap with each other via the insulating layer 354 functions as the capacitor 235. Therefore, the conductive layer 355 functions as one electrode of the capacitor 235. The conductive layer 351 functions as the other electrode of the capacitor 235.

[0154] In addition, the insulating layer 354 used as the dielectric of the capacitor 235 may also use a material with a high relative dielectric constant (also referred to as a "high-k material"). By using a high-k material as the insulating layer 354, the electrostatic capacitance required for the capacitor 235 can be ensured and the insulating layer 354 can be thickened. By thickening the insulating layer 354, the insulation withstand voltage between the conductive layer 351 and the conductive layer 355 is improved and electrostatic breakdown is suppressed. Therefore, the reliability of the capacitor 235 is improved. As a result, the reliability of the semiconductor device using the capacitor 235 is improved.

[0155] Ferroelectrics can also be used for the insulating layer 354 used as the dielectric of the capacitor 235. Ferroelectrics have the property that polarization occurs internally when an electric field is applied from the outside, and polarization remains even when the electric field is reduced to 0. Therefore, by using a capacitor using this material as a dielectric (also called a ferroelectric capacitor), a nonvolatile memory element can be formed.

[0156] in addition, FIG. 13A to FIG. 13C The memory circuit 231 shown includes an insulating layer 357 on the insulating layer 354 and the conductive layer 355, an insulating layer 358 on the insulating layer 357, and an insulating layer 359 on the insulating layer 358. The insulating layer 357, the insulating layer 358, and the insulating layer 359 are sometimes collectively referred to as the insulating layer 356 or the spacer layer. In addition, a conductive layer 361 is included on the insulating layer 359.

[0157] An opening 362 is provided in the conductive layer 361 , the insulating layer 359 , the insulating layer 358 , and the insulating layer 357 in a region overlapping with a portion of the conductive layer 355 . FIG. 13A to FIG. 13C The memory circuit 231 shown includes a semiconductor layer 363 covering the opening 362. The semiconductor layer 363 has a region overlapping with the bottom of the opening 362 and a region overlapping with the side of the opening 362. That is, the semiconductor layer 363 has a region in contact with the insulating layer 356. Fig. 13B and Fig. 13C In the embodiment, the semiconductor layer 363 has a region in contact with a side surface of the insulating layer 357 , a region in contact with a side surface of the insulating layer 358 , and a region in contact with a side surface of the insulating layer 359 .

[0158] In addition, the semiconductor layer 363 has a region in contact with the conductive layer 355 and a region in contact with the conductive layer 361. That is, a portion of the semiconductor layer 363 is electrically connected to the conductive layer 355, and another portion of the semiconductor layer 363 is electrically connected to the conductive layer 361. In addition, the semiconductor layer 363 may have a region extending beyond the end of the conductive layer 361 (see Fig.13A and Fig.14A ).

[0159] An insulating layer 364 is included over the insulating layer 359, the conductive layer 361, and the semiconductor layer 363. In addition, a conductive layer 365 is included over the insulating layer 364. Fig.13A In FIG. 3 , the conductive layer 365 extends in the Y direction.

[0160] Both the insulating layer 364 and the conductive layer 365 have regions overlapping with the opening 362. In the opening 362, the insulating layer 364 has a region overlapping with the side surface of the conductive layer 361 via the semiconductor layer 363 and a region overlapping with the side surface of the insulating layer 356 (the insulating layer 359, the insulating layer 358, and the insulating layer 357). In addition, in the opening 362, the conductive layer 365 has a region overlapping with the side surface of the opening 362 (the side surface of the insulating layer 356) via the insulating layer 364 and the semiconductor layer 363.

[0161] The thickness of the semiconductor layer 363 is preferably 1 nm or more, 3 nm or more, or 5 nm or more and 20 nm or less, 15 nm or less, 12 nm or less, or 10 nm or less. The thickness of the insulating layer 364 is preferably 0.5 nm or more and 15 nm or less, more preferably 0.5 nm or more and 12 nm or less, and further preferably 0.5 nm or more and 10 nm or less. At least a portion of the insulating layer 364 may be a region having the above thickness.

[0162] The insulating layer 364 includes an insulating layer 366 (see Fig. 13B ). In addition, it is preferable to make the top surface positions (positions in the Z direction) of the conductive layer 365 and the insulating layer 366 consistent or approximately consistent. For example, it is preferable to make the top surface positions of the conductive layer 365 and the insulating layer 366 consistent or approximately consistent by performing CMP treatment or the like. By making the top surface positions of the conductive layer 365 and the insulating layer 366 consistent or approximately consistent, the coverage of the insulating layer and the conductive layer to be formed later can be improved.

[0163] An insulating layer 367 is included on the conductive layer 365 and the insulating layer 366. In addition, a conductive layer 368 embedded in the insulating layer 367, the insulating layer 366, the insulating layer 364, the conductive layer 361, the insulating layer 359, the insulating layer 358, the insulating layer 357, and a portion of the insulating layer 354 is included in the region overlapping with the conductive layer 352. The conductive layer 368 is electrically connected to the conductive layer 361 and the conductive layer 352. The conductive layer 368 and the conductive layer 352 function as contact plugs. In addition, the conductive layer 368 formed through a plurality of layers is also referred to as a "through electrode" or "VIA".

[0164] The conductive layer 361 is used as one of the source electrode and the drain electrode of the transistor 234. In addition, the conductive layer 355 is used as the other of the source electrode and the drain electrode of the transistor 234. For example, when the conductive layer 361 is used as the drain electrode of the transistor 234, the conductive layer 355 is used as the source electrode of the transistor 234. The transistor 234 is formed in a region overlapping with the conductive layer 355. The transistor 234 and the capacitor 235 have a region overlapping each other.

[0165] The semiconductor layer 363 is used as a semiconductor layer (a semiconductor layer including a channel formation region) for forming a channel of the transistor 234, the insulating layer 364 is used as a gate insulating layer, and the conductive layer 365 is used as a gate electrode. Therefore, it can be said that the transistor 234 is provided in a region including the opening 362.

[0166] In addition, the transistor 233 is formed in a region that does not overlap with the transistor 234 and overlaps with the conductive layer 355. The transistor 233 and the capacitor 235 have a region that overlaps with each other. The transistor 233 has the same structure as the transistor 234 and is formed at the same time as the transistor 234. Therefore, the description of the transistor 234 can be replaced with the transistor 233 and the transistor 233 can be described.

[0167] In transistor 234, the source electrode and the drain electrode are arranged in the Z direction. That is, the source and the drain of transistor 234 are arranged at different heights. In other words, the source and the drain of transistor 234 are arranged at different positions in the Z direction. This transistor is also called a "vertical channel transistor", "vertical channel transistor", "vertical transistor" or "VFET (Vertical Field Effect Transistor)".

[0168] In a vertical channel transistor according to one embodiment of the present invention, the source electrode and the drain electrode are arranged in the Z direction. That is, the channel formation region, the source region, and the drain region are arranged in the Z direction. Compared with a conventional transistor in which the channel formation region, the source region, and the drain region are separately arranged on the XY plane, when a vertical transistor is used, the occupied area can be reduced.

[0169] Therefore, by using a vertical channel transistor in a semiconductor device, the occupied area of ​​the semiconductor device can be reduced. In addition, by using a vertical channel transistor in a semiconductor device, high integration of the semiconductor device can be achieved. In addition, the storage capacity per unit area of ​​a storage device using the semiconductor device can be increased.

[0170] In addition, the channel length of the existing transistor is set according to the exposure limit of the photolithography method. A vertical channel transistor according to one embodiment of the present invention can set the channel length according to the thickness of the insulating layer 356 or the insulating layer 358. Therefore, the channel length of the transistor 234 can be set to a very fine structure below the exposure limit of the photolithography method (for example, less than 60nm, less than 50nm, less than 40nm, less than 30nm, less than 20nm or less than 10nm and more than 1nm or more than 5nm). As a result, the on-state current of the transistor 234 is increased, and the frequency characteristics can be improved. By using a vertical channel transistor, a semiconductor device with a high operating speed can be provided.

[0171] <Materials Constituting Semiconductor Devices> An example of a material that can be used for a semiconductor device according to one embodiment of the present invention will be described.

[0172] [Substrate] When a semiconductor device is disposed on a substrate, there is no particular restriction on the material used for the substrate. The material can be determined based on the purpose, such as whether it is necessary to have light transmittance and heat resistance to withstand heat treatment. As a substrate, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate can be used. As an insulating substrate, for example, a glass substrate such as barium borosilicate glass and aluminoborosilicate glass, a ceramic substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (yttria stabilized zirconia substrate, etc.) can be used. In addition, a semiconductor substrate, a flexible substrate, a resin substrate, etc. can also be used.

[0173] For example, as the semiconductor substrate, there can be cited a semiconductor substrate composed of silicon or germanium, or a compound semiconductor substrate using silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, etc. as its material. In addition, there can also be cited a semiconductor substrate having an insulator region inside the above semiconductor substrate, such as an SOI (Silicon On Insulator) substrate, etc. In addition, the semiconductor substrate can be a single crystal semiconductor or a polycrystalline semiconductor.

[0174] Examples of the conductive substrate include graphite substrates, metal substrates, alloy substrates, conductive resin substrates, etc. Alternatively, examples include substrates containing metal nitrides, substrates containing metal oxides, etc. In addition, examples include insulator substrates provided with a conductor or a semiconductor, semiconductor substrates provided with a conductor or an insulator, and conductive substrates provided with a semiconductor or an insulator.

[0175] As materials for flexible substrates or substrates, for example, the following materials can be used: polyesters such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), polyacrylonitrile, acrylic resin, polyimide, polymethyl methacrylate, polycarbonate (PC), polyether sulfone (PES), polyamide (nylon, aromatic polyamide, etc.), polysiloxane, cycloolefin resin, polystyrene, polyamide-imide, polyurethane, polyvinyl chloride, polyvinylidene chloride, polypropylene, polytetrafluoroethylene (PTFE), ABS resin, and cellulose nanofibers, etc.

[0176] By using the above materials as the substrate, a lightweight semiconductor device including the transistor 234 can be provided. Also, by using the above materials as the substrate, a semiconductor device with high impact resistance can be provided. Also, by using the above materials as the substrate, a semiconductor device that is not easily damaged can be provided.

[0177] Alternatively, a substrate having an element provided over these substrates may be used. Examples of the element provided over the substrate include a capacitor, a resistor, a switching element, a light emitting element, and a memory element.

[0178] [Insulation layer] As the insulating layer, insulating oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, metal oxynitrides, etc. can be used. For example, as the insulating layer, a single layer or a stack of insulating materials selected from the following can be used: aluminum nitride, aluminum oxide, aluminum nitride oxide, aluminum oxynitride, magnesium oxide, silicon nitride, silicon oxide, silicon nitride oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, aluminum silicate, etc. In addition, a material obtained by mixing multiple types of oxide materials, nitride materials, oxynitride materials, and nitride oxide materials can also be used.

[0179] In this specification, etc., nitrogen oxide refers to a material containing more nitrogen than oxygen. In addition, oxynitride refers to a material containing more oxygen than nitrogen. In addition, for example, the content of each element can be measured using Rutherford Backscattering Spectrometry (RBS).

[0180] When miniaturization and high integration of transistors are carried out, problems such as leakage current sometimes occur due to the thin film of the gate insulating layer. By using a high-k material (a high dielectric constant material. A material with a high relative dielectric constant) as an insulating layer used as a gate insulating layer, the gate potential of the transistor can be reduced while maintaining the physical thickness. In addition, materials with high dielectric constants such as lead zirconate titanate (PZT), strontium titanate (SrTiO3), (Ba, Sr)TiO3 (BST) can sometimes be used as an insulating layer. On the other hand, by using a material with a low relative dielectric constant for an insulating layer used as an interlayer film, the parasitic capacitance generated between the wirings can be reduced. Therefore, it is preferable to select the material according to the function required of the insulating layer.

[0181] In addition, as materials with a high relative dielectric constant, there are gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0182] In addition, as materials with a relatively low dielectric constant, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide having pores, or resins can be cited.

[0183] The method for forming the insulating material is not particularly limited, and various formation methods such as vapor deposition, ALD (Atomic Layer Deposition), CVD (Chemical Vapor Deposition), sputtering, and spin coating can be used.

[0184] In particular, the insulating layer 353 and the insulating layer 367 are preferably formed using an insulating material that is not easily permeable to impurities. For example, a single layer or a stack of insulating materials containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used. For example, as an example of an insulating material that is not easily permeable to impurities, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, silicon nitride, etc. can be cited.

[0185] By using an insulating material that does not easily allow impurities to pass through as the insulating layer 353, diffusion of impurities from below the insulating layer 353 can be suppressed, and the reliability of the transistor 234 can be improved. That is, the reliability of the semiconductor device including the transistor 234 can be improved. By using an insulating material that does not easily allow impurities to pass through as the insulating layer 367, diffusion of impurities from above the insulating layer 367 can be suppressed, and the reliability of the transistor 234 can be improved. That is, the reliability of the semiconductor device including the transistor 234 can be improved.

[0186] In addition, as the insulating layer, an insulating layer used as a planarization layer can also be used. As the material used as the planarization layer, acrylic resin, polyimide, epoxy resin, polyamide, polyimide amide, siloxane resin, benzocyclobutene resin, phenolic resin and precursors of these resins can be cited. In addition, in addition to the above-mentioned organic materials, low-k materials (low dielectric constant materials. Materials with a small relative dielectric constant.), siloxane resins, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), etc. can also be used. In addition, multiple insulating layers formed of these materials can also be stacked.

[0187] Siloxane resin is equivalent to a resin containing Si-O-Si bonds formed from a siloxane material as a starting material. Siloxane resin can also use an organic group (such as an alkyl group or an aryl group) or a fluoro group as a substituent. In addition, the organic group can also have a fluoro group.

[0188] In addition, a three-layer insulating layer (also called "ZAZ") of aluminum oxide sandwiched between two layers of zirconium oxide may be used as the insulating layer 354 serving as the dielectric of the capacitor 235. ZAZ is a material with a high relative dielectric constant, and by using ZAZ as the dielectric of the capacitor 235, the occupied area of ​​the capacitor 235 can be reduced.

[0189] As described above, a material having ferroelectricity can be used as the insulating layer 354 to allow the capacitor 235 to be used as a ferroelectric capacitor.

[0190] As a material having ferroelectricity, for example, hafnium oxide is preferably used. Alternatively, zirconium oxide, HfZrO X (X is a real number greater than 0. Hereinafter, it is also referred to as "HfZrOx") and other metal oxides. Alternatively, as a material that can have ferroelectricity, a material in which an element J1 is added to hafnium oxide (here, the element J1 is one or more selected from zirconium (Zr), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) can be used.

[0191] Here, the atomic ratio of hafnium atoms to element J1 can be appropriately set. For example, the atomic ratio of hafnium atoms to zirconium atoms can be set to 1:1 or thereabouts. Alternatively, as a material that can have ferroelectricity, a material in which element J2 is added to zirconium oxide (here, element J2 is one or more selected from hafnium (Hf), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) can be used. In addition, the atomic ratio of zirconium atoms to element J2 can be appropriately set. For example, the atomic ratio of zirconium atoms to element J2 can be set to 1:1 or thereabouts. In addition, as a material that can have ferroelectricity, lead titanate (PbTiO X ), barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), barium titanate and other piezoelectric ceramics with perovskite structure.

[0192] In addition, as a material that can have ferroelectricity, aluminum scandium nitride (Al 1-a Sc a N b (a is a real number greater than 0 and less than 0.5, and b is a value of 1 or a vicinity thereof. It is hereinafter referred to as AlScN)), Al-Ga-Sc nitride, Ga-Sc nitride, etc.

[0193] [Conductive layer] As conductive materials for conductive layers of various wirings and electrodes constituting semiconductor devices, metal elements selected from aluminum (Al), chromium (Cr), copper (Cu), silver (Ag), gold (Au), platinum (Pt), tantalum (Ta), nickel (Ni), titanium (Ti), molybdenum (Mo), tungsten (W), hafnium (Hf), vanadium (V), niobium (Nb), manganese (Mn), magnesium (Mg), zirconium (Zr), beryllium (Be), etc., alloys containing the above metal elements as components, or alloys combining the above metal elements, etc. can be used.

[0194] For example, tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. are preferably used. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel are conductive materials that are not easily oxidized or materials that maintain conductivity even when absorbing oxygen, so they are preferred. In addition, semiconductors with high conductivity represented by polycrystalline silicon containing impurity elements such as phosphorus and silicides such as nickel silicide can also be used. There is no particular limitation on the method for forming the conductive material, and various formation methods such as evaporation, ALD, CVD, sputtering, and spin coating can be used.

[0195] In addition, as a conductive material, a Cu-X alloy (X is Mn, Ni, Cr, Fe, Co, Mo, Ta or Ti) can also be used. The layer formed using the Cu-X alloy can be processed by a wet etching process, thereby suppressing the manufacturing cost. In addition, as a conductive material, an aluminum alloy containing one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium and scandium can also be used.

[0196] As the conductive material that can be used for the conductive layer, conductive materials containing oxygen such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon oxide, etc. can also be used. In addition, conductive materials containing nitrogen such as titanium nitride, tantalum nitride, tungsten nitride, etc. can also be used. In addition, the conductive layer can also adopt a laminated structure in which conductive materials containing oxygen, conductive materials containing nitrogen, and materials containing the above-mentioned metal elements are appropriately combined.

[0197] For example, the conductive layer can adopt a single-layer structure of an aluminum layer containing silicon, a two-layer structure of a titanium layer stacked on an aluminum layer, a two-layer structure of a titanium layer stacked on a titanium nitride layer, a two-layer structure of a tungsten layer stacked on a titanium nitride layer, a two-layer structure of a tungsten layer stacked on a tantalum nitride layer, and a three-layer structure of a titanium layer, an aluminum layer, and a titanium layer stacked in sequence.

[0198] In addition, a plurality of conductive layers formed of the above-mentioned conductive materials may be stacked. For example, the conductive layer may also adopt a laminated structure in which a material containing the above-mentioned metal element and a conductive material containing oxygen are combined. For example, the conductive layer may also adopt a laminated structure in which a material containing the above-mentioned metal element and a conductive material containing oxygen are combined. For example, the conductive layer may also adopt a laminated structure in which a material containing the above-mentioned metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined.

[0199] For example, the conductive layer may also have a three-layer structure in which a conductive layer containing at least one of indium and zinc and oxygen, a conductive layer containing copper, and a conductive layer containing at least one of indium and zinc and oxygen are sequentially stacked. In this case, it is preferred that the side of the conductive layer containing copper is also covered with a conductive layer containing at least one of indium and zinc and oxygen. In addition, for example, as the conductive layer, a plurality of conductive layers containing at least one of indium and zinc and oxygen may be stacked.

[0200] When the capacitor 235 is used as a ferroelectric capacitor, the conductive layers 351 and 355 in contact with the ferroelectric insulating layer 354 are preferably made of a material that easily polarizes the insulating layer 354. For example, the conductive layers 351 and 355 are preferably made of titanium nitride.

[0201] [Semiconductor layer] As the semiconductor layer 363, a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like can be used alone or in combination. As the semiconductor material, for example, silicon, germanium, or the like can be used. In addition, a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenide, or a nitride semiconductor can also be used. As the compound semiconductor, an organic substance having semiconductor characteristics or a metal oxide having semiconductor characteristics (also referred to as an oxide semiconductor) can be used. Note that these semiconductor materials may also contain impurities as dopants.

[0202] For example, single crystal silicon, polycrystalline silicon, microcrystalline silicon, or amorphous silicon may be used as the semiconductor layer 363. As the polycrystalline silicon, for example, low temperature polycrystalline silicon (LTPS: Low Temperature Poly Silicon) may be used.

[0203] A transistor using amorphous silicon as the semiconductor layer 363 can be formed on a large glass substrate and can be manufactured at low cost. A transistor using polycrystalline silicon as the semiconductor layer 363 has high field effect mobility and can operate at high speed. In addition, a transistor using microcrystalline silicon as the semiconductor layer 363 has high field effect mobility compared to a transistor using amorphous silicon and can operate at high speed.

[0204] The semiconductor layer 363 may also include a layered material used as a semiconductor. A layered material is a general term for a group of materials having a layered crystalline structure. A layered crystalline structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked by bonds such as van der Waals forces that are weaker than covalent bonds and ionic bonds. The layered material has high conductivity in a unit layer, that is, has high two-dimensional conductivity. By using a material used as a semiconductor and having high two-dimensional conductivity in a channel formation region, a transistor with a large on-state current can be provided.

[0205] As the above-mentioned layered material, for example, graphene, silicene, chalcogenides, etc. can be cited. Chalcogenides are compounds containing oxygen group elements (elements belonging to group 16). In addition, as chalcogenides, transition metal chalcogenides, group 13 chalcogenides, etc. can be cited. Transition metal chalcogenides that can be used as semiconductor layers of transistors include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), zirconium selenide (typically ZrSe2), etc.

[0206] In addition, the band gap of the oxide semiconductor is more than 2eV, so the off-state current of the transistor (also called "OS transistor") using an oxide semiconductor of one of the metal oxides in the semiconductor layer in which the channel is formed is extremely small. As a result, the power consumption of the semiconductor device including the OS transistor can be reduced. In addition, the OS transistor operates stably even in a high temperature environment, and the characteristics vary less. For example, even in a high temperature environment, the off-state current hardly increases. Specifically, even at an ambient temperature above room temperature and below 200°C, the off-state current hardly increases. In addition, even in a high temperature environment, the on-state current is not easy to drop. Therefore, the semiconductor device including the OS transistor operates stably even in a high temperature environment and has high reliability.

[0207] In this embodiment and the like, OS transistors are preferably used as the transistors 233 and 234. The insulation withstand voltage between the source and the drain of the OS transistor is high, so the channel length can be reduced. Therefore, the on-state current can be increased. The OS transistor is suitable for a vertical channel transistor.

[0208] As metal oxides that can be used for the semiconductor layer of the OS transistor, for example, indium oxide, gallium oxide, and zinc oxide can be cited. The metal oxide preferably contains at least indium (In) or zinc (Zn). In addition, the metal oxide preferably contains two or three selected from indium, element M, and zinc. Note that element M is a metal element or a semi-metal element with a high bonding energy with oxygen, for example, a metal element or a semi-metal element with a higher bonding energy with oxygen than indium.

[0209] Element M specifically includes aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. Element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and further preferably gallium. Note that in this specification, etc., metal elements and semi-metal elements are sometimes collectively referred to as "metal elements", and sometimes the "metal elements" described in this specification, etc. include semi-metal elements.

[0210] For example, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also referred to as "GZO"), aluminum zinc oxide (Al-Zn oxide, also referred to as "AZO"), indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as "IAZO"), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as "IGZO"), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as "IGZTO"), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as "IGAZO" or "IAGZO"), etc. can be used. Alternatively, indium tin oxide, gallium tin oxide (Ga—Sn oxide), aluminum tin oxide (Al—Sn oxide), or the like containing silicon may be used.

[0211] By increasing the ratio of the number of atoms of indium contained in the metal oxide relative to the total number of atoms of all metal elements, the field effect mobility of the transistor can be increased.

[0212] Note that the metal oxide may also replace indium or contain one or more metal elements with a large period number in addition to indium. Alternatively, the metal oxide may also replace indium or contain one or more metal elements with a large period number in addition to indium. Metal oxides have a tendency that the greater the overlap of the orbits of the metal elements, the greater the carrier conduction in the metal oxide. Therefore, by including a metal element with a large period number, the field effect mobility of the transistor can sometimes be improved. As metal elements with a large period number, metal elements belonging to the 5th period and metal elements belonging to the 6th period can be cited. As the metal element, specifically, yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium and europium can be cited. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium and europium are called light rare earth elements.

[0213] The metal oxide may also contain one or more non-metallic elements. The inclusion of non-metallic elements in the metal oxide may sometimes improve the field effect mobility of the transistor. Examples of the non-metallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0214] By increasing the ratio of the number of zinc atoms in the main component elements contained in the metal oxide to the total number of metal element atoms, a highly crystalline metal oxide is obtained, thereby suppressing the diffusion of impurities in the metal oxide. Therefore, the variation of the electrical characteristics of the transistor is suppressed and the reliability can be improved.

[0215] By increasing the ratio of the number of atoms of the element M in the main component elements contained in the metal oxide relative to the total number of atoms of the metal elements, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, the generation of carriers caused by oxygen vacancies is suppressed, thereby realizing a transistor with a small off-state current. In addition, the variation of the electrical characteristics of the transistor is suppressed, thereby improving reliability.

[0216] The electrical characteristics and reliability of the transistor vary depending on the composition of the metal oxide used for the semiconductor layer. Therefore, by varying the composition of the metal oxide according to the electrical characteristics and reliability required for the transistor, a semiconductor device having both excellent electrical characteristics and high reliability can be realized.

[0217] When In-Zn oxide is used as the semiconductor layer of the OS transistor, a metal oxide in which the atomic ratio of indium is greater than the atomic ratio of zinc may be used. For example, a metal oxide in which the atomic ratio of the metal elements is In:Zn=1:1, In:Zn=2:1, In:Zn=3:1, In:Zn=4:1, In:Zn=5:1, In:Zn=7:1, In:Zn=10:1 or a metal oxide in the vicinity thereof may be used.

[0218] When In-Sn oxide is used as the semiconductor layer of the OS transistor, a metal oxide in which the atomic ratio of indium is greater than the atomic ratio of tin may be used. For example, a metal oxide in which the atomic ratio of the metal elements is In:Sn=1:1, In:Sn=2:1, In:Sn=3:1, In:Sn=4:1, In:Sn=5:1, In:Sn=7:1, In:Sn=10:1 or a metal oxide in the vicinity thereof may be used.

[0219] When In-Sn-Zn oxide is used as the semiconductor layer of the OS transistor, a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of tin may also be used. Furthermore, it is preferred to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of tin. For example, the atomic ratios of metal elements In:Sn:Zn=2:1:3, In:Sn:Zn=3:1:2, In:Sn:Zn=4:2:3, In:Sn:Zn=4:2:4.1, In:Sn:Zn=5:1:3, In:Sn:Zn=5:1:6, In:Sn:Zn=5:1:7, In:Sn:Zn=5:1:8, In:Sn:Zn =6:1:6、In:Sn:Zn=10:1:3、In:Sn:Zn=10:1:6、In:Sn:Zn=10:1:7、In:Sn:Zn=10:1:8、In :Sn:Zn=5:2:5, In:Sn:Zn=10:1:10, In:Sn:Zn=20:1:10, In:Sn:Zn=40:1:10 or metal oxides in their vicinity.

[0220] When In-Al-Zn oxide is used as the semiconductor layer of the OS transistor, a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of aluminum may be used. Furthermore, it is preferred to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of aluminum. For example, the atomic ratios of the metal elements In:Al:Zn=2:1:3, In:Al:Zn=3:1:2, In:Al:Zn=4:2:3, In:Al:Zn=4:2:4.1, In:Al:Zn=5:1:3, In:Al:Zn=5:1:6, In:Al:Zn=5:1:7, In:Al:Zn=5:1:8, In:Al:Zn=5:1:9, In:Al:Zn=5:1:10, In:Al:Zn=5:1:11, In:Al:Zn=5:1:12, In:Al:Zn=5:1:13, In:Al:Zn=5:1:14, In:Al:Zn=5:1:15, In:Al:Zn=5:1:16, In:Al:Zn=5:1:17, In:Al:Zn=5:1:18, In:Al:Zn=5:1:19, In:Al:Zn=5:1:10, In:Al:Zn=5:1:11, In:Al:Zn=5:1:12 n=6:1:6, In:Al:Zn=10:1:3, In:Al:Zn=10:1:6, In:Al:Zn=10:1:7, In:Al:Zn=10:1:8, In:Al:Zn=5:2:5, In:Al:Zn=10:1:10, In:Al:Zn=20:1:10, In:Al:Zn=40:1:10 or metal oxides thereabouts.

[0221] When In-Ga-Zn oxide is used as the semiconductor layer of the OS transistor, a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of gallium relative to the sum of the atomic numbers of metal elements in the In-Ga-Zn oxide may be used. Furthermore, it is preferred to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of gallium. For example, the semiconductor layer may also use a metal element atomic ratio of In:Ga:Zn=2:1:3, In:Ga:Zn=3:1:2, In:Ga:Zn=4:2:3, In:Ga:Zn=4:2:4.1, In:Ga:Zn=5:1:3, In:Ga:Zn=5:1:6, In:Ga:Zn=5:1:7, In:Ga:Zn=5:1:8, In:Ga :Zn=6:1:6, In:Ga:Zn=10:1:3, In:Ga:Zn=10:1:6, In:Ga:Zn=10:1:7, In:Ga:Zn=10:1:8, In:Ga:Zn=5:2:5, In:Ga:Zn=10:1:10, In:Ga:Zn=20:1:10, In:Ga:Zn=40:1:10 or metal oxides thereof.

[0222] When In-M-Zn oxide is used as the semiconductor layer of the OS transistor, a metal oxide in which the atomic ratio of indium relative to the sum of the atomic numbers of metal elements in the In-M-Zn oxide is higher than the atomic ratio of the element M may be used. Furthermore, it is preferred to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of the element M. For example, the semiconductor layer may also use a metal element atomic ratio of In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M: Zn=6:1:6, In:M:Zn=10:1:3, In:M:Zn=10:1:6, In:M:Zn=10:1:7, In:M:Zn=10:1:8, In:M:Zn=5:2:5, In:M:Zn=10:1:10, In:M:Zn=20:1:10, In:M:Zn=40:1:10 or metal oxides thereabouts.

[0223] When In-M-Zn oxide is used as a semiconductor layer, the following metal oxide may be used: the atomic ratio of the metal elements is In:M:Zn=1:3:2 [atomic ratio] or a composition close thereto, In:M:Zn=1:3:4 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:0.5 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:1 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:1.2 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:2 [atomic ratio] or a composition close thereto, or In:M:Zn=4:2:3 [atomic ratio] or a composition close thereto. Note that the nearby composition includes a range of ±30% of the desired atomic ratio. In addition, gallium is preferably used as the element M.

[0224] Note that when a plurality of metal elements are included as the element M, the sum of the atomic ratios of the metal elements may be the atomic ratio of the element M. For example, when an In-Ga-Al-Zn oxide including gallium and aluminum is used as the element M, the sum of the atomic ratio of gallium and the atomic ratio of aluminum may be the atomic ratio of the element M. In addition, the atomic ratio of indium, the element M, and zinc is preferably within the above range.

[0225] It is preferable to use a metal oxide in which the ratio of the number of atoms of indium in the main component elements contained in the metal oxide to the total number of atoms of the metal elements is 30 atomic % or more and 100 atomic % or less, preferably 30 atomic % or more and 95 atomic % or less, more preferably 35 atomic % or more and 95 atomic % or less, more preferably 35 atomic % or more and 90 atomic % or less, more preferably 40 atomic % or more and 90 atomic % or less, more preferably 45 atomic % or more and 90 atomic % or less, more preferably 50 atomic % or more and 80 atomic % or less, more preferably 60 atomic % or more and 80 atomic % or less, more preferably 70 atomic % or more and 80 atomic % or less. For example, in the case of using In-M-Zn oxide as a semiconductor layer, the ratio of the number of atoms of indium to the total number of atoms of indium, element M and zinc is preferably within the above range.

[0226] As described above, when the ratio of the number of atoms of indium in the main component elements contained in the metal oxide to the total number of atoms of the metal elements is increased, the field effect mobility of the transistor can be increased. By using this transistor, a circuit capable of high-speed operation can be manufactured. Furthermore, the area occupied by the circuit can be reduced.

[0227] The composition of metal oxides can be analyzed, for example, using energy dispersive X-ray spectroscopy (EDX), X-ray photoelectron spectroscopy (XPS), inductively coupled plasma mass spectrometry (ICP-MS) or inductively coupled plasma atomic emission spectrometry (ICP-AES). Alternatively, multiple of the above methods can be combined for analysis. Note that the actual content of elements with low content is sometimes different from the content obtained by analysis due to the influence of analysis accuracy. For example, when the content of element M is low, the content of element M obtained by analysis is sometimes lower than the actual content.

[0228] The metal oxide can be formed by sputtering or ALD as appropriate. Note that when the metal oxide is formed by sputtering, the atomic ratio of the target material is sometimes different from the atomic ratio of the metal oxide. In particular, the atomic ratio of zinc in the metal oxide is sometimes smaller than the atomic ratio of zinc in the target material. Specifically, the atomic ratio of zinc is sometimes about 40% or more and 90% or less of the atomic ratio of zinc in the target material.

[0229] Furthermore, when the metal oxide is deposited by sputtering, the above atomic ratio is not limited to the atomic ratio of the deposited metal oxide, but may also be the atomic ratio of the sputtering target used for the deposition of the metal oxide.

[0230] In addition, when the metal oxide is formed by the ALD method, since atoms can be deposited in layers, there are effects such as being able to deposit with fewer defects such as pinholes, being able to deposit with excellent coverage, and being able to deposit at low temperatures. In addition, it is preferred to perform an impurity removal treatment after the metal oxide is formed to remove impurities (here, typically impurities such as water, hydrogen, carbon, and nitrogen) from the film of the metal oxide. In addition, as impurity treatment, for example, plasma treatment, microwave treatment, and heat treatment can be cited.

[0231] Here, the reliability of the transistor is explained. As one of the indicators for evaluating the reliability of the transistor, there is a GBT (Gate Bias Temperature) stress test in which an electric field is applied to the gate. Among them, the test of maintaining the gate at a high temperature while applying a positive potential (positive bias) relative to the source potential and the drain potential is called a PBTS (Positive BiasTemperature Stress) test, and the test of maintaining the gate at a high temperature while applying a negative potential (negative bias) is called an NBTS (Negative Bias Temperature Stress) test. In addition, the PBTS test and the NBTS test performed under the state of irradiation with light are respectively called the PBTIS (Positive Bias Temperature Illumination Stress) test and the NBTIS (Negative Bias Temperature Illumination Stress) test.

[0232] In an n-channel transistor, a positive potential is applied to the gate when the transistor is turned on, so the variation of the threshold voltage in the PBTS test is one of the important factors to be focused on as a reliability index of the transistor.

[0233] By using a metal oxide that does not contain gallium or has a low gallium content in the semiconductor layer, a transistor with high reliability for forward bias application can be realized. In other words, a transistor with a small change in threshold voltage in a PBTS test can be realized. In addition, when a metal oxide containing gallium is used, the gallium content is preferably lower than the indium content. Thus, a transistor with high reliability can be realized.

[0234] One of the reasons for the change in threshold voltage in the PBTS test is the defect state at or near the interface between the semiconductor layer and the gate insulating layer. The greater the defect state density, the more significant the degradation in the PBTS test. The generation of the defect state can be suppressed by reducing the gallium content in the region of the semiconductor layer that contacts the gate insulating layer.

[0235] The reason why the change in threshold voltage in the PBTS test can be suppressed by using a metal oxide that does not contain gallium or has a low gallium content for the semiconductor layer is, for example, as follows. Gallium contained in the metal oxide is more likely to absorb oxygen than other metal elements (such as indium or zinc). Therefore, it can be inferred that at the interface between the metal oxide containing more gallium and the gate insulating layer, carrier (here, electron) trap sites are easily generated by bonding between gallium and excess oxygen in the gate insulating layer. Therefore, when a positive potential is applied to the gate, carriers are captured at the interface between the semiconductor layer and the gate insulating layer, and the threshold voltage will change.

[0236] More specifically, when In-Ga-Zn oxide is used as the semiconductor layer, a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of gallium can be used for the semiconductor layer. It is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of gallium. In other words, a metal oxide in which the atomic ratio of metal elements satisfies In>Ga and Zn>Ga is used for the semiconductor layer.

[0237] For example, the semiconductor layer of the OS transistor may use metal elements with atomic ratios of In:Ga:Zn=2:1:3, In:Ga:Zn=3:1:2, In:Ga:Zn=4:2:3, In:Ga:Zn=4:2:4.1, In:Ga:Zn=5:1:3, In:Ga:Zn=5:1:6, In:Ga:Zn=5:1:7, In:Ga:Zn=5:1:8, In: Ga:Zn=6:1:6, In:Ga:Zn=10:1:3, In:Ga:Zn=10:1:6, In:Ga:Zn=10:1:7, In:Ga:Zn=10:1:8, In:Ga:Zn=5:2:5, In:Ga:Zn=10:1:10, In:Ga:Zn=20:1:10, In:Ga:Zn=40:1:10 or metal oxides thereabouts.

[0238] The semiconductor layer of the OS transistor preferably uses a metal oxide in which the ratio of the number of atoms of gallium to the number of atoms of the metal element contained is higher than 0 atomic % and is less than 50 atomic %, preferably greater than 0.1 atomic % and less than 40 atomic %, more preferably greater than 0.1 atomic % and less than 35 atomic %, more preferably greater than 0.1 atomic % and less than 30 atomic %, more preferably greater than 0.1 atomic % and less than 25 atomic %, more preferably greater than 0.1 atomic % and less than 20 atomic %, more preferably greater than 0.1 atomic % and less than 15 atomic %, more preferably greater than 0.1 atomic % and less than 10 atomic %. By reducing the gallium content in the semiconductor layer, a transistor with high resistance to the PBTS test can be realized. Note that by including gallium in the metal oxide, it is less likely to generate oxygen vacancies (V O : Oxygen Vacancy) effect.

[0239] As the semiconductor layer of the OS transistor, a metal oxide that does not contain gallium can also be used. For example, In-Zn oxide can be used for the semiconductor layer. At this time, when the atomic number ratio of indium contained in the metal oxide relative to the atomic number of the metal element is increased, the field effect mobility of the transistor can be improved. On the other hand, when the atomic number ratio of zinc contained in the metal oxide relative to the atomic number of the metal element is increased, the metal oxide has high crystallinity, so the variation of the electrical characteristics of the transistor is suppressed, and the reliability can be improved. In addition, as the semiconductor layer, a metal oxide such as indium oxide that does not contain gallium and zinc can also be used. By using a metal oxide that does not contain gallium, the variation of the threshold voltage in the PBTS test can be made extremely small, especially.

[0240] For example, an oxide containing indium and zinc can be used as the semiconductor layer. In this case, for example, a metal oxide having an atomic ratio of metal elements of In:Zn=2:3, In:Zn=4:1 or a ratio close to this can be used.

[0241] Note that although gallium is used as an example for the description, the invention can also be applied to the case where element M is used instead of gallium. It is preferable to use a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of element M for the semiconductor layer. It is also preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of element M.

[0242] A transistor having high reliability in case of forward bias application can be realized by using a metal oxide having a low content of element M as a semiconductor layer. A semiconductor device having high reliability can be realized by using this transistor as a transistor that needs to have high reliability in case of forward bias application.

[0243] The semiconductor layer may also have a stacked structure including two or more metal oxide layers. The compositions of the two or more metal oxide layers included in the semiconductor layer may also be the same or substantially the same as each other. By adopting a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used to form it, thereby reducing the manufacturing cost.

[0244] The compositions of the two or more metal oxide layers included in the semiconductor layer may also be different from each other. For example, a stacked structure of a first metal oxide layer having a composition of In:M:Zn=1:3:4 [atomic ratio] or thereabouts and a second metal oxide layer having a composition of In:M:Zn=1:1:1 [atomic ratio] or thereabouts disposed on the first metal oxide layer may be appropriately used. In addition, gallium or aluminum is particularly preferably used as the element M. For example, a stacked structure of any one selected from indium oxide, indium gallium oxide and IGZO and any one selected from IAZO, IAGZO and ITZO (registered trademark) may be used.

[0245] In addition, for example, a stacked structure of a first metal oxide layer with a composition of In:M:Zn=1:1:1 [atomic ratio] or thereabouts and a second metal oxide layer with a composition of In:Zn=4:1 [atomic ratio] or thereabouts provided on the first metal oxide layer can be appropriately used.

[0246] As the semiconductor layer, a crystalline metal oxide layer is preferably used. For example, a metal oxide layer having a CAAC (c-axis aligned crystal) structure, a polycrystalline structure, a microcrystalline (nc: nano-crystal) structure, etc., which will be described later, can be used. By using a crystalline metal oxide layer for the semiconductor layer, the defect state density in the semiconductor layer can be reduced, thereby realizing a display device with high reliability.

[0247] The higher the crystallinity of the metal oxide layer used for the semiconductor layer, the lower the defect state density in the semiconductor layer can be. On the other hand, by using a metal oxide layer with low crystallinity, a transistor capable of passing a large current can be realized.

[0248] When a metal oxide layer is formed by sputtering, the higher the substrate temperature (stage temperature) during formation, the more crystalline the metal oxide layer can be formed. In addition, the higher the flow rate ratio of the oxygen gas relative to the entire deposition gas used during formation (hereinafter also referred to as the oxygen flow rate ratio) is, the more crystalline the metal oxide layer can be formed.

[0249] The semiconductor layer of the OS transistor may also have a stacked structure of two or more metal oxide layers with different crystallinity. For example, a stacked structure may have a first metal oxide layer and a second metal oxide layer disposed on the first metal oxide layer, and the second metal oxide layer may have a region whose crystallinity is higher than that of the first metal oxide layer. Alternatively, the second metal oxide layer may have a region whose crystallinity is lower than that of the first metal oxide layer. The compositions of the two or more metal oxide layers included in the semiconductor layer may also be the same or substantially the same as each other. By adopting a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used to form them, thereby reducing manufacturing costs. For example, by using the same sputtering target to make the oxygen flow ratio different, a stacked structure of two or more metal oxide layers with different crystallinity can be formed. Note that the compositions of the two or more metal oxide layers included in the semiconductor layer may also be different from each other.

[0250] When an oxide semiconductor is used for the semiconductor layer 363, a material containing hydrogen is preferably used for the insulating layer 357 and the insulating layer 359. When the insulating layer containing hydrogen contacts the oxide semiconductor, the oxide semiconductor in the region where the insulating layer contacts is converted to n-type, and can be used as a source region or a drain region. As the insulating layer, for example, a material containing silicon, nitrogen and hydrogen can be used. Specifically, hydrogen-containing silicon nitride or hydrogen-containing silicon nitride oxide can be used.

[0251] The thickness of the insulating layer 357 and the insulating layer 359 is preferably 1 nm or more and 15 nm or less, more preferably 2 nm or more and 10 nm or less, further preferably 3 nm or more and 7 nm or less, and further preferably 3 nm or more and 5 nm or less. When an oxide semiconductor is used as the semiconductor layer 363, a region of the semiconductor layer 363 that contacts the insulating layer 357 containing hydrogen and a region of the semiconductor layer 363 that contacts the insulating layer 359 containing hydrogen are used as a source region or a drain region. By adjusting the thickness of the insulating layer 357 and the insulating layer 359, the size of the source region and the drain region formed in the semiconductor layer 363 can be controlled.

[0252] The thickness of the insulating layer 358 is preferably 1 nm to 50 nm, more preferably 2 nm to 30 nm, and further preferably 3 nm to 20 nm. By adjusting the thickness of the insulating layer 358, the size of the channel formation region of the semiconductor layer 363 can be controlled.

[0253] The thicknesses of the insulating layer 357 , the insulating layer 358 , and the insulating layer 359 can be appropriately set depending on the characteristics required for the transistor 234 .

[0254] In addition, the deposition of insulating layer 357, insulating layer 358, and insulating layer 359 is preferably performed continuously without being exposed to the atmosphere during the deposition. By performing the deposition of insulating layer 357, insulating layer 358, and insulating layer 359 continuously without being exposed to the atmosphere during the deposition, impurities and moisture from the atmosphere can be prevented from adhering to the interface between insulating layer 357 and insulating layer 358 and its vicinity, and the interface between insulating layer 358 and insulating layer 359 and its vicinity.

[0255] In addition, when an oxide semiconductor is used for the semiconductor layer 363, the conductive layer 355 in contact with the semiconductor layer 363 and the conductive layer 361 in contact with the semiconductor layer 363 preferably use a conductive material that converts the oxide semiconductor into an n-type. For example, a conductive material containing nitrogen can be used. For example, a conductive material containing titanium or tantalum and nitrogen can be used. In addition, other conductive materials can be provided in a manner overlapping with the conductive material containing nitrogen.

[0256] On the other hand, the insulating layer 358 preferably uses a material containing oxygen and having reduced hydrogen. For example, a material containing silicon and oxygen may be used. Specifically, silicon oxide or silicon oxynitride is used. Hydrogen is an impurity element in an oxide semiconductor, so when the semiconductor layer 363 of the oxide semiconductor contacts the insulating layer 358 containing reduced hydrogen, the semiconductor layer 363 is not easily converted to an n-type. In addition, when the semiconductor layer 363 of the oxide semiconductor contacts the insulating layer 358 containing oxygen, the oxygen vacancies in the semiconductor layer 363 are reduced, the characteristics of the transistor 234 are stabilized, and the reliability is improved.

[0257] In addition, when an oxide semiconductor is used for the semiconductor layer 363, the insulating layer 358 preferably contains excess oxygen. In this specification, etc., excess oxygen refers to oxygen released by heating. In addition, when a material containing excess oxygen is used in the insulating layer 358, a material that is not easily permeable to oxygen is preferably used for the insulating layer 357 and the insulating layer 359. As a material that is not easily permeable to oxygen, for example, an oxide containing one or both of aluminum and hafnium, a nitride of silicon, and the like can be used. By using a material that is not easily permeable to oxygen for the insulating layer 357 and the insulating layer 359, the excess oxygen contained in the insulating layer 358 is not easily released to the lower layer or the upper layer. Therefore, sufficient oxygen can be supplied to the oxide semiconductor. For example, an insulating layer (insulating layer 358) containing silicon and oxygen can be included between two insulating layers (insulating layer 357 and insulating layer 359) containing silicon and nitrogen.

[0258] In addition, by using an oxide semiconductor as the semiconductor layer 363 and using a material containing hydrogen as the insulating layer 357 and the insulating layer 359, hydrogen is supplied to the region of the semiconductor layer 363 in contact with the insulating layer 357 and the region of the semiconductor layer 363 in contact with the insulating layer 359, and each region in the semiconductor layer 363 is converted to an n-type. Therefore, the region of the semiconductor layer 363 in contact with the conductive layer 361 and the region of the semiconductor layer 363 in contact with the insulating layer 359 are used as one of the source (source region) and the drain (drain region). In addition, the region of the semiconductor layer 363 in contact with the conductive layer 355 and the region of the semiconductor layer 363 in contact with the insulating layer 357 are used as the other of the source (source region) and the drain (drain region).

[0259] Fig.14A Show Fig. 13B In the above structure, in the transistor 234 of the VFET, the length of the side surface of the insulating layer 358 when viewed from the X direction or the Y direction is the channel length L (channel length L1) (refer to Fig.14A ). Therefore, the channel length L of the transistor 234 is determined by the thickness t1 of the insulating layer 358.

[0260] In addition, the insulating layer 357 and the insulating layer 359 may also use a material that does not contain hydrogen or contains very little hydrogen. For example, silicon nitride with very little hydrogen or silicon oxynitride with very little hydrogen may also be used. At this time, the region where the semiconductor layer 363 contacts the insulating layer 357 and the region where the semiconductor layer 363 contacts the insulating layer 359 are not n-typed. Therefore, the region of the semiconductor layer 363 that contacts the conductive layer 361 is used as one of the source (source region) and the drain (drain region). In addition, the region of the semiconductor layer 363 that contacts the conductive layer 355 is used as the other of the source (source region) and the drain (drain region). In addition, the region of the semiconductor layer 363 that contacts the insulating layer 358 is used as a channel formation region.

[0261] In this case, the total length of the side surfaces of the insulating layers 357, 358, and 359 when viewed in the X direction or the Y direction is the channel length L (channel length L2). Therefore, the channel length L of the transistor 234 is determined by the total thickness t2 of the insulating layers 357, 358, and 359.

[0262] Fig.15A and Fig. 15B Show Fig.14A For example, instead of providing the insulating layer 357 and the insulating layer 359, only the insulating layer 358 may be provided so that the insulating layer 358 is in contact with the conductive layer 355 and the conductive layer 361 (see Fig.15A ). In this case, the length of the side surface of the insulating layer 358 when viewed from the X direction or the Y direction is the channel length L. Therefore, the channel length L of the transistor 234 is determined by the thickness t of the insulating layer 358. Fig.15A In the structure shown in FIG. 35A , insulating layer 358 is sometimes referred to as insulating layer 356. Note that Fig.15A The channel length L shown is Fig.14A The channel length L2 shown is synonymous with, Fig.15A The thickness t2 shown is Fig.14A The thickness t2 shown is synonymous.

[0263] When an oxide semiconductor is used as the semiconductor layer 363, a material containing hydrogen is used as the insulating layers 357 and 359, and a material containing excess oxygen is used as the insulating layer 358, hydrogen in the insulating layers 357 and 359 is bonded to excess oxygen in the insulating layer 358, and a region of the semiconductor layer 363 in contact with the insulating layer 357 and a region of the semiconductor layer 363 in contact with the insulating layer 359 are not supplied with sufficient hydrogen and are not easily converted to n-type. Similarly, a region of the semiconductor layer 363 in contact with the insulating layer 358 is not supplied with sufficient oxygen.

[0264] In order to solve the above problem, an insulating layer 371 which is not easily permeable to oxygen and nitrogen may be provided between the insulating layer 357 and the insulating layer 358, and an insulating layer 372 which is not easily permeable to oxygen and nitrogen may be provided between the insulating layer 359 and the insulating layer 358 (see Fig. 15B ). For example, a material that is not easily permeable to oxygen and nitrogen, such as silicon nitride, can be used. Fig. 15B In the structure shown in FIG. 1 , the insulating layer 357 , the insulating layer 371 , the insulating layer 358 , the insulating layer 372 , and the insulating layer 359 are sometimes collectively referred to as the insulating layer 356 .

[0265] When a material that does not easily transmit oxygen is used as the insulating layers 371 and 372, bonding between hydrogen in the insulating layers 357 and 359 and excess oxygen in the insulating layer 358 is blocked. Therefore, a region of the semiconductor layer 363 in contact with the insulating layer 357 and a region of the semiconductor layer 363 in contact with the insulating layer 359 are sufficiently supplied with hydrogen. Similarly, a region of the semiconductor layer 363 in contact with the insulating layer 358 is sufficiently supplied with oxygen.

[0266] In this case, the total length of the side surfaces of the insulating layer 371, the insulating layer 358, and the insulating layer 372 when viewed in the X direction or the Y direction is the channel length L3. Therefore, the channel length L of the transistor 234 is determined by the total thickness t3 of the insulating layer 371, the insulating layer 358, and the insulating layer 372.

[0267] The channel length L of the transistor 234 shown in this embodiment is determined by the thickness of the insulating layer provided between the conductive layer 361 and the conductive layer 355. Therefore, a transistor having a short channel length L can be manufactured with high precision. In addition, the characteristic non-uniformity between the plurality of transistors 234 can be reduced. Therefore, the operation of the semiconductor device including the transistor 234 is stable, and the reliability can be improved. In addition, when the characteristic non-uniformity is reduced, the circuit design freedom of the semiconductor device is improved, and the operating voltage can also be reduced. Therefore, the power consumption of the semiconductor device can be reduced.

[0268] In this embodiment, three insulating layers (insulating layer 357, insulating layer 358, insulating layer 359) or five insulating layers (insulating layer 357, insulating layer 358, insulating layer 359, insulating layer 371, insulating layer 372) are included between conductive layer 355 and conductive layer 361, but the number of insulating layers between conductive layer 355 and conductive layer 361 is not limited thereto. The number of insulating layers between conductive layer 355 and conductive layer 361 may be one, two, four, or six or more.

[0269] In addition, in order to improve the coverage of the semiconductor layer 363, the insulating layer 364, and the conductive layer 365 formed in the opening 362, the taper angle θ of the side of the opening 362, that is, the taper angle θ of the side of each of the insulating layer 357, the insulating layer 358, and the insulating layer 359 is set to be greater than 45 degrees and less than 90 degrees, preferably greater than 50 degrees and less than 75 degrees. The taper angle θ of the side of a layer (insulating layer, conductive layer, or semiconductor layer) refers to the angle between the bottom surface of the layer and the side surface (see Fig.14A ).

[0270] Fig.16A and Fig. 16B Show Fig.14A Examples of deformations. Fig.16A As shown, by reducing the bottom area of ​​the opening 362, the taper angle θ of the side of the opening 362 can be increased without increasing the area occupied by the transistor 234. By increasing the taper angle θ of the side of the opening 362, the coverage of the semiconductor layer 363, the insulating layer 364, and the conductive layer 365 can be improved.

[0271] When the area of ​​the bottom of the opening 362 is reduced, the conductive layer 365 may become thinner toward the bottom of the opening 362 in the opening 362. The shape of the conductive layer 365 may be referred to as "needle-shaped" or "conical".

[0272] like Fig. 16B As shown, if there is no problem with the coverage of the semiconductor layer 363, the insulating layer 364, and the conductive layer 365, the side of the opening 362 can be made vertical or substantially vertical. In other words, the taper angle θ of the side of the opening 362 can also be 90 degrees or substantially 90 degrees. By making the side of the opening 362 vertical or substantially vertical, the occupied area of ​​the transistor 234 can be reduced. Therefore, the occupied area of ​​the semiconductor device including the transistor 234 can be reduced.

[0273] Since the side surface of the opening 362 is made vertical, the channel length L1 is equal to the thickness t1 of the insulating layer 358. Furthermore, since the side surface of the opening 362 is made vertical, the channel length L2 is equal to the thickness t2 of the insulating layer 356.

[0274] Since the semiconductor layer 363 is disposed in the opening 362, the perimeter of the opening 362 when viewed from the Z direction is equal to the channel width W of the transistor 234 (see FIG. Fig. 14B ). As the perimeter, for example, the perimeter at a position where half of the thickness t1 or half of the thickness t2 of the insulating layer 358 may be obtained. Note that the perimeter at any position of the opening 362 may be set as the channel width W as required. For example, the perimeter at the bottom of the opening 362 may be set as the channel width W, or the perimeter at the top of the opening 362 may be set as the channel width W.

[0275] In the memory device of one embodiment of the present invention, the channel length L is preferably at least smaller than the channel width W. The channel length L of one embodiment of the present invention is preferably 0.1 times or more and 0.99 times or less, and preferably 0.5 times or more and 0.8 times or less.

[0276] In addition, Fig. 14B In FIG. 1 , the outline (planar shape) of the opening 362 when viewed from the Z direction is shown as a circle, but the present invention is not limited thereto. For example, the outline of the opening 362 when viewed from the Z direction may also be an ellipse (see FIG. 1 ). Fig. 14C ) or rectangle (refer to Fig.14D ).Notice, Fig.14D In addition, for example, the outline of the opening 362 when viewed from the Z direction may also be a shape including one or both of a straight line portion and a curved line portion (see Fig.14E ).

[0277] In addition, the opening 362 is preferably small. For example, the maximum width of the opening 362 when viewed from the Z direction (the maximum diameter when the opening 362 is circular) is preferably 60 nm or less, more preferably 50 nm or less, further preferably 40 nm or less, and particularly preferably 30 nm or less. The maximum width of the opening 362 when viewed from the Z direction may also be 20 nm or less. In addition, the minimum width of the opening 362 when viewed from the Z direction (the minimum diameter when the opening 362 is circular) is preferably 1 nm or more, more preferably 5 nm or more. In order to form the above-mentioned tiny opening 362, it is preferred to use a photolithography method using short-wavelength light such as EUV light or an electron beam.

[0278] In the transistor 234 according to one embodiment of the present invention, the capacitance value of the parasitic capacitance generated between the gate and the source is different from the capacitance value of the parasitic capacitance generated between the gate and the drain. Specifically, of the capacitor C1 generated between the conductive layer 365 and the conductive layer 361 and the capacitor C2 generated between the conductive layer 365 and the conductive layer 355, the capacitance value of the capacitor C1 is greater than the capacitance value of the capacitor C2.

[0279] Fig.17A and Fig. 17B A plan view of transistor 234 is shown. Fig. 17C 2 shows a cross-sectional view of transistor 234. Note that Fig.17A and Fig. 17B In the example, some of the components are omitted. Fig.17D An equivalent circuit diagram of the transistor 234 is shown.

[0280] When the transistor 234 according to one embodiment of the present invention is viewed from the Z direction, the conductive layer 365 overlaps with the conductive layer 361 around the opening 362 and overlaps with the conductive layer 355 at the bottom of the opening 362. Fig.17A In FIG. 1 , a region serving as the capacitor C1 when viewed from the Z direction is hatched. A region where the conductive layer 365 and the conductive layer 361 overlap with each other via the semiconductor layer 363 and the insulating layer 364 serves as the capacitor C1.

[0281] exist Fig. 17B In FIG. 3 , a region serving as the capacitor C2 when viewed from the Z direction is hatched. A region where the conductive layer 365 and the conductive layer 355 overlap with each other via the semiconductor layer 363 and the insulating layer 364 at the bottom of the opening 362 serves as the capacitor C2.

[0282] from Fig.17A and Fig. 17B It can be seen that the area of ​​the region used as capacitor C2 is larger than the area of ​​the region used as capacitor C1. When the area of ​​the region used as capacitor C2 is larger than the area of ​​the region used as capacitor C1, the capacitance value of capacitor C1 is larger than that of capacitor C2.

[0283] By utilizing this phenomenon, the capacitor C1 and the capacitor C2, which are parasitic capacitors, can be intentionally used as capacitors. When the overlapping area of ​​the conductive layer 365 and the conductive layer 355 is changed in order to change the capacitance value of the capacitor C2, the shape of the opening 362 is changed, thereby changing the perimeter of the opening 362. The perimeter of the opening 362 is the channel width W of the transistor 234. Therefore, since the change in the perimeter p directly affects the change in the electrical characteristics of the transistor 234, it is difficult to adjust the capacitance value of the capacitor C2.

[0284] On the other hand, the overlapping area between the conductive layer 365 and the conductive layer 361 can be easily adjusted, and the electrical characteristics of the transistor 234 are unlikely to be affected. For example, by increasing the overlapping area between the conductive layer 365 and the conductive layer 361, the capacitance value of the capacitor C1 can be increased.

[0285] Fig.18 2 shows a circuit diagram of the memory circuit 231. When VFETs are used as the transistors 233 and 234 constituting the memory circuit 231, it is preferable to form a capacitor C2 between the gate of the transistor and the capacitor 235. In addition, in the transistor 233, it is preferable to form a capacitor C1 between the gate and the terminal Q. In addition, in the transistor 234, it is preferable to form a capacitor C1 between the gate and the terminal SD.

[0286] When the capacitance value between the gate of the transistor 233 and the capacitor 235 is large, the node SN is easily affected by the potential fluctuation of the signal BK. In addition, when the capacitance value between the gate of the transistor 234 and the capacitor 235 is large, the node SN is easily affected by the potential fluctuation of the signal RE. In order to suppress the potential fluctuation of the node SN and make the storage circuit 231 operate more stably, it is preferable that each capacitor C2 of the transistor 233 and the transistor 234 is formed between the node SD and the gate.

[0287] That is, in the transistor 233, the conductive layer 361 is preferably electrically connected to the terminal Q, and the conductive layer 355 is preferably electrically connected to one electrode (node ​​SN) of the capacitor 235. In addition, in the transistor 234, the conductive layer 361 is preferably electrically connected to the terminal SD, and the conductive layer 355 is preferably electrically connected to one electrode (node ​​SN) of the capacitor 235.

[0288] Fig.19 An example of a stacked structure of an OSFF 210 which is one of semiconductor devices is shown. Fig.19 The OSFF 210 shown includes a layer 20 having a k-layer storage circuit 231 above a layer 10 including a scan flip-flop 220. Fig.19 In the embodiment, the memory circuit 231 included in each of the layers 20 as the k-layer is exemplified by the structure shown in Fig. 13. In order to reduce duplicate descriptions, the description of the memory circuit 231 is omitted here.

[0289] in addition, Fig.19 The transistor 400 included in the scan trigger 220 is illustrated. The transistor 400 is provided on a semiconductor substrate 311 and includes: a conductive layer 316 used as a gate, an insulating layer 315 used as a gate insulator, a semiconductor region 313 formed by a portion of the substrate 311; and a low resistance region 314a and a low resistance region 314b used as a source region or a drain region. The transistor 400 can be a p-channel transistor or an n-channel transistor. As the substrate 311, for example, a single crystal silicon substrate can be used.

[0290] Here, in Fig.19In the transistor 400 shown, the semiconductor region 313 (a part of the substrate 311) forming the channel has a convex shape. In addition, the conductive layer 316 covers the side and top surfaces of the semiconductor region 313 via the insulating layer 315. In addition, the conductive layer 316 can also use a material that adjusts the work function. Because the convex portion of the semiconductor substrate is utilized, this transistor 400 is also called a FIN-type transistor. In addition, an insulator having a mask for forming a convex portion in a manner that contacts the top of the convex portion can also be provided. In addition, although a part of the semiconductor substrate is processed to form a convex portion is shown here, an SOI (Silicon on Insulator) substrate can also be processed to form a semiconductor film having a convex shape.

[0291] Notice, Fig.19 The structure of the transistor 400 shown is only an example and is not limited to the above structure. An appropriate transistor may be used according to the circuit structure or driving method.

[0292] A wiring layer including an interlayer film, wiring, and plugs may be provided between the structures. In addition, the wiring layer may be provided in a plurality of layers according to the design. In addition, in this specification, wiring and a plug electrically connected to the wiring may also be one component. That is, a part of the conductor may be used as wiring, and a part of the conductor may be used as a plug.

[0293] For example, an insulating layer 320, an insulating layer 322, an insulating layer 324, and an insulating layer 326 are sequentially stacked as interlayer films on the transistor 400. In addition, conductive layers 328 and 330 electrically connected to the conductive layer 352 are embedded in the insulating layers 320, 322, 324, and 326. In addition, the conductive layers 328 and 330 are used as contact plugs or wirings.

[0294] In addition, the insulator used as the interlayer film can also be used as a planarization film that covers the concavo-convex shape thereunder. For example, in order to improve the flatness of the top surface of the insulating layer 322, CMP treatment or the like may be performed.

[0295] Alternatively, a wiring layer may be provided over the insulating layer 326 and the conductive layer 330. Fig.19 In the embodiment, an insulating layer 350, an insulating layer 382, ​​and an insulating layer 384 are sequentially stacked on the insulating layer 326 and the conductive layer 330. A conductive layer 386 is formed between the insulating layer 350, the insulating layer 382, ​​and the insulating layer 384. The conductive layer 386 is used as a contact plug or wiring. The conductive layer 386 is electrically connected to the conductive layer 352.

[0296] The structure described in this embodiment mode can be implemented in combination with the structures described in other embodiment modes as appropriate.

[0297] (Implementation 4) In this embodiment, a configuration example in which a plurality of storage circuits 231 are arranged in a row on the same layer overlapping the scan flip-flop 220 in one OSFF 210 is described. Note that in order to reduce duplicate descriptions, in this embodiment, mainly the parts different from other embodiments are described. Therefore, for the contents not described in this embodiment, other embodiments can be referred to.

[0298] In the above embodiment, a configuration example in which a plurality of storage circuits 231 are stacked in the Z direction in one OSFF 210 is described. When the area of ​​the storage circuit 231 is sufficiently small relative to the area of ​​the scan flip-flop 220, j (j is any integer greater than or equal to 2) storage circuits 231 can be arranged in a row on the XY plane on the same layer overlapping the scan flip-flop 220.

[0299] In order to reduce the area of ​​the memory circuit 231, it is preferable to use VFET for the transistor constituting the memory circuit 231. By setting the area of ​​the memory circuit 231 to be less than 1 / 2, preferably less than 1 / 5, and more preferably less than 1 / 8 of the area of ​​the scan trigger 220, it is easy to arrange a plurality of memory circuits 231 in a row on the same layer overlapping the scan trigger 220.

[0300] Fig. 20A FIG. 1 is a three-dimensional block diagram of an OSFF 210 in which a plurality of storage circuits 231 are arranged in parallel on the same layer overlapping with a scan flip-flop 220 . Fig.21A An example of the circuit structure of the OSFF 210 is shown. As an example, Fig. 20A The example in which four storage circuits 231 (storage circuit 231 [1] to storage circuit 231 [4]) are arranged in parallel on the scan flip-flop 220 when j is 4 is shown. The scan flip-flop 220 is formed in layer 10, and the four storage circuits 231 are all formed in layer 20 [1].

[0301] In addition, if Fig. 20B As shown, the memory circuit 231 may also be stacked. Fig. 20B The three-dimensional block diagram of shows an example in which four storage circuits 231 are arranged in parallel in each of the layers 20[1] to 20[4]. Fig. 20B The illustrated OSFF 210 includes 16 storage circuits 231 (storage circuit 231 [ 1 ] to storage circuit 231 [ 16 ]). Fig. 20B The OSFF 210 shown is the OSFF 210 when k is 4 and j is 4.

[0302] By providing a plurality of memory circuits 231 in one layer 20, a large number of memory circuits 231 can be provided with a small number of stacked layers. In addition, by reducing the number of stacked layers 20, the productivity of OSFF 210 can be improved. In addition, the productivity of semiconductor devices including OSFF 210 is improved.

[0303] The transistor 232 may be disposed in either layer 10 or layer 20 (see Fig.21A and Fig.21B ). In other words, the transistor 232 can be a Si transistor or an OS transistor.

[0304] As described above, by using VFETs as transistors constituting the memory circuit 231, the area of ​​the memory circuit 231 can be reduced. In addition, if the area of ​​the memory circuit 231 is the same, the number of transistors used for the memory circuit 231 can be increased. For example, by connecting a plurality of VFETs in parallel, the plurality of VFETs can be used as one transistor having a larger channel width W. In addition, the capacitor 235 can be formed overlapping with the VFET when viewed from the Z direction using a photomask for forming the VFET.

[0305] Fig.22A A perspective view schematically showing a structural example of the storage circuit 231. Fig. 22B yes Fig.22A A circuit diagram of the storage circuit 231 is shown. Fig.22A and Fig. 22B The storage circuit 231 shown includes eight transistors (transistor 233a, transistor 233b, transistor 233c, transistor 233d, transistor 234a, transistor 234b, transistor 234c, and transistor 234d). Fig.22A and Fig. 22B The illustrated storage circuit 231 includes eight capacitors (capacitor 235a, capacitor 235b, capacitor 235c, capacitor 235d, capacitor 235e, capacitor 235f, capacitor 235g, and capacitor 235h).

[0306] The transistor 233a, the transistor 233b, the transistor 233c, and the transistor 233d are connected in parallel and used as one transistor 233. The transistor 233a, the transistor 233b, the transistor 233c, and the transistor 233d have their sources electrically connected to one another, their drains electrically connected to one another, and their gates electrically connected to one another.

[0307] The transistors 234a, 234b, 234c, and 234d are connected in parallel and used as one transistor 234. The sources, drains, and gates of the transistors 234a, 234b, 234c, and 234d are electrically connected to each other.

[0308] Capacitors 235a, 235b, 235c, 235d, 235e, 235f, 235g, and 235h are connected in parallel and used as one capacitor 235. One electrodes of capacitors 235a to 235h are electrically connected to each other, and the other electrodes are electrically connected to each other.

[0309] As described above, by connecting a plurality of transistors in parallel, the plurality of transistors are used as a transistor having a larger channel width W. By increasing the channel width W of transistor 233, the speed of writing data to node SN can be increased. By increasing the channel width W of transistor 234, the speed of reading data from node SN can be increased. In addition, by connecting a plurality of capacitors in parallel, the capacitance value of capacitor 235 increases, thereby improving the data retention capability of node SN.

[0310] Fig.23A Show that Fig.22A The storage circuit 231 shown is used to Fig. 20A The OSFF210 shown is a plan view of the OSFF210. Fig. 23B A plan view of the amplifying storage circuit 231[1] is shown. Fig.24A Shown including Fig.23A A three-dimensional schematic diagram of the areas of the storage circuit 231[1] and the storage circuit 231[2] of the OSFF 210 is shown. Fig. 24B Shown including Fig.23A A three-dimensional schematic diagram of the storage circuit 231[1] and the conductive layer 369SD area of ​​the OSFF210 is shown.

[0311] exist Fig.23A In the embodiment, the conductive layer 361Q is electrically connected to the terminal Q of the OSFF 210 through the conductive layer 369Q. In addition, it can also be said that the conductive layer 361Q and the conductive layer 369Q are used as the terminal Q. In addition, the conductive layer 361SD is electrically connected to the terminal SD of the OSFF 210 through the conductive layer 369SD. In addition, it can also be said that the conductive layer 361SD and the conductive layer 369SD are used as the terminal Q.

[0312] Both the conductive layer 361Q and the conductive layer 361SD extend in the X direction. In addition, the conductive layer 347 (conductive layer 347[1]a, conductive layer 347[2]a, conductive layer 347[3]a, conductive layer 347[4]a) to which the signal RE is supplied and the conductive layer 347 (conductive layer 347[1]b, conductive layer 347[2]b, conductive layer 347[3]b, conductive layer 347[4]b) to which the signal BK is supplied extend in the Y direction. In other words, the conductive layer 347 extends in a direction intersecting with the conductive layer 361 (conductive layer 361Q and conductive layer 361SD).

[0313] In addition, the conductive layer 369Q and the conductive layer 369SD both extend in the Z direction (see Fig. 24B ). That is, the conductive layer 369 (the conductive layer 369Q and the conductive layer 369SD) extends in a direction intersecting the conductive layer 347 and the conductive layer 361 .

[0314] The conductive layer 369 is used as a contact plug, a through electrode (VIA), or a wiring. By extending the conductive layer 369Q in the Z direction, the stacked memory circuit 231 (see Fig. 20B ) is electrically connected to the terminal Q of OSFF210 through a conductive layer 369Q. In addition, by extending the conductive layer 369SD in the Z direction, the conductive layer 361SD included in each of the stacked storage circuits 231 can be electrically connected to the terminal SD of OSFF210 through a conductive layer 369SD.

[0315] For example, signal RE[1] is supplied to storage circuit 231[1] through conductive layer 347[1]a, and signal BK[1] is supplied to storage circuit 231[1] through conductive layer 347[1]b. In addition, signal RE[2] is supplied to storage circuit 231[2] through conductive layer 347[2]a, and signal BK[2] is supplied to storage circuit 231[2] through conductive layer 347[2]b. In addition, signal RE[3] is supplied to storage circuit 231[3] through conductive layer 347[3]a, and signal BK[3] is supplied to storage circuit 231[3] through conductive layer 347[3]b. In addition, signal RE[4] is supplied to storage circuit 231[4] through conductive layer 347[4]a, and signal BK[4] is supplied to storage circuit 231[4] through conductive layer 347[4]b.

[0316] Next, we explain Fig.23A An example of a stacked structure of a semiconductor device according to one embodiment of the present invention is shown. Fig.25 It is along Fig.23A The cross-sectional view of the portion along the dot-dash line A1-A2 in FIG. Fig.26 It is along Fig.23A A cross-sectional view of the portion of the dotted line A3-A4 in FIG. Fig.23A The portion indicated by the dotted line A1-A2 and Fig.23A An example of a stacked structure of the portion indicated by the dashed line A3-A4 in FIG.

[0317] Fig.25 is a diagram showing a cross-sectional structure including a storage circuit 231 [1], Fig.26 2 is a diagram showing a cross-sectional structure including a storage circuit 231[1] and a storage circuit 231[2]. The semiconductor device includes an insulating layer 353 (in the Fig.26 The insulating layer 353 is not shown in the figure) and the conductive layer 351 is formed in a manner embedded in the insulating layer 353. The conductive layer 351 is used as the wiring CL. In addition, it is preferable to make the top surface positions (positions in the Z direction) of the insulating layer 353 and the conductive layer 351 consistent or approximately consistent by a CMP method or the like.

[0318] In addition, the semiconductor device includes an insulating layer 341 over the insulating layer 353 and the conductive layer 351. The insulating layer 353 has an opening 342 (opening 342a to opening 342h) in a region overlapping with a portion of the conductive layer 351. Fig.25 and Fig.26 The opening 342c, the opening 342d, and the opening 342g are not shown.

[0319] In addition, the semiconductor device includes a conductive layer 343 on the insulating layer 341. The insulating layer 341 includes a region overlapping with the opening 342 (opening 342a to opening 342h). In each of the openings 342a to 342h, the conductive layer 343 has a region overlapping with the bottom of the opening and a region overlapping with the side of the opening (the side of the insulating layer 341). At the bottom of each of the openings 342a to 342h, the conductive layer 343 is electrically connected to the conductive layer 351.

[0320] In addition, the semiconductor device includes an insulating layer 344 covering the conductive layer 343 on the conductive layer 343. The insulating layer 344 has a region overlapping with the side surface of the opening 342 via the conductive layer 343 and a region overlapping with the bottom surface of the opening 342 via the conductive layer 343. In addition, the semiconductor device includes a plurality of conductive layers 355 on the insulating layer 344. The conductive layer 355 has a region overlapping with the side surface of the opening 342 via the insulating layer 344 and the conductive layer 343 and a region overlapping with the bottom surface of the opening 342 via the insulating layer 344 and the conductive layer 343.

[0321] In the opening 342a, the region where the conductive layer 343 overlaps with the conductive layer 355 (the conductive layer 355[1] or the conductive layer 355[2]) via the insulating layer 344 is used as a capacitor 235a. In the opening 342b, the region where the conductive layer 343 overlaps with the conductive layer 355 via the insulating layer 344 is used as a capacitor 235b. In the opening 342c, the region where the conductive layer 343 overlaps with the conductive layer 355 via the insulating layer 344 is used as a capacitor 235c. In the opening 342d, the region where the conductive layer 343 overlaps with the conductive layer 355 via the insulating layer 344 is used as a capacitor 235d. In the opening 342e, the region where the conductive layer 343 overlaps with the conductive layer 355 via the insulating layer 344 is used as a capacitor 235e. In the opening 342f, the region where the conductive layer 343 overlaps with the conductive layer 355 via the insulating layer 344 is used as a capacitor 235f. In the opening 342g, a region where the conductive layer 343 and the conductive layer 355 overlap with the insulating layer 344 is used as a capacitor 235g. In the opening 342h, a region where the conductive layer 343 and the conductive layer 355 overlap with the insulating layer 344 is used as a capacitor 235h.

[0322] The capacitors 235a to 235h are connected in parallel to each other and function as one capacitor 235. In addition, the insulating layer 344 functioning as a dielectric of the capacitor 235 may also use a material having a high relative dielectric constant (also referred to as a high-k material). In addition, a ferroelectric may be used for the insulating layer 344 functioning as a dielectric of the capacitor 235.

[0323] Conductive layer 355 is used as node SN. In addition, conductive layer 355 is independently provided in each storage circuit 231. For example, conductive layer 355[1] included in storage circuit 231[1] is used as node SN for holding data written to storage circuit 231[1], and conductive layer 355[2] included in storage circuit 231[2] is used as node SN for holding data written to storage circuit 231[2].

[0324] The semiconductor device includes an insulating layer 357 on the insulating layer 341 and the conductive layer 355, an insulating layer 358 on the insulating layer 357, and an insulating layer 359 on the insulating layer 358. The insulating layer 357, the insulating layer 358, and the insulating layer 359 are sometimes collectively referred to as an insulating layer 356 or a spacer. A conductive layer 361 (conductive layer 361SD and conductive layer 361Q) is included on the insulating layer 359.

[0325] In a region overlapping with a portion of the conductive layer 355, openings 362 (openings 362a to 362h) are provided in the conductive layer 361, the insulating layer 359, the insulating layer 358, and the insulating layer 357. Fig.25 and Fig.26The opening 362c, the opening 362d, and the opening 362g are not shown.

[0326] exist Fig.25 , the semiconductor device includes a semiconductor layer 363[1]a covering an opening 362a, an opening 362b, an opening 362c (not shown), and an opening 362d (not shown). The semiconductor layer 363[1]a has a region overlapping with the bottom of the opening 362a, the opening 362b, the opening 362c, and the opening 362d, and a region overlapping with each side surface.

[0327] In addition, Fig.25 and Fig.26 , the semiconductor device includes a semiconductor layer 363[1]b covering opening 362e, opening 362f, opening 362g (not shown), and opening 362h. The semiconductor layer 363[1]b includes a region overlapping with the bottom of opening 362e, opening 362f, opening 362g, and opening 362h and a region overlapping with each side surface.

[0328] The semiconductor device includes an insulating layer 364 on the insulating layer 359, the conductive layer 361, and the semiconductor layer 363 (semiconductor layer 363[1]a, semiconductor layer 363[1]b, semiconductor layer 363[2]a (not shown), and semiconductor layer 363[2]b), and includes a conductive layer 365 (conductive layer 365[1]a, conductive layer 365[1]b, conductive layer 365[2]a (not shown), and conductive layer 365[2]b) on the insulating layer 364. In addition, the semiconductor device includes an insulating layer 366 on the insulating layer 364. In addition, the top surface positions (positions in the Z direction) of the conductive layer 365 and the insulating layer 366 are made consistent or approximately consistent.

[0329] The region including the opening 362a is used as the transistor 234a, and the region including the opening 362b is used as the transistor 234b. In addition, the region including the opening 362c is used as the transistor 234c (not shown), and the region including the opening 362d is used as the transistor 234d (not shown). The transistor 234a, the transistor 234b, the transistor 234c, and the transistor 234d are connected in parallel and used as a transistor 234 with a large channel width W.

[0330] In addition, the region including the opening 362e is used as a transistor 233a, and the region including the opening 362f is used as a transistor 233b. In addition, the region including the opening 362g is used as a transistor 233c (not shown), and the region including the opening 362h is used as a transistor 233d (not shown). The transistor 233a, the transistor 233b, the transistor 233c, and the transistor 233d are connected in parallel and used as a transistor 233 having a large channel width W.

[0331] Note that the above embodiment can be referred to for the description of the transistor 233 and the transistor 234. Therefore, in this embodiment, the description of the transistor 233 and the transistor 234 is omitted.

[0332] In addition, the semiconductor device includes a conductive layer 345 over the conductive layer 365 . Fig.25 Conductive layer 345[1]a on conductive layer 365[1]a is shown. Fig.26 Conductive layer 345[1]b on conductive layer 365[1]b and conductive layer 345[2]b on conductive layer 365[2]b are shown. In addition, the semiconductor device includes insulating layer 346 on insulating layer 366 and conductive layer 365. In addition, the top surface positions (positions in the Z direction) of conductive layer 345 and insulating layer 346 are preferably aligned or substantially aligned.

[0333] In addition, the semiconductor device includes a plurality of conductive layers 347 on the conductive layer 345 and the insulating layer 346. Fig.25 and Fig.26 , conductive layer 347[1]a, conductive layer 347[1]b, conductive layer 347[2]a, and conductive layer 347[2]b are shown as a plurality of conductive layers 347. Conductive layer 347[1]a is electrically connected to conductive layer 365[1]a via conductive layer 345[1]a. Conductive layer 347[1]b is electrically connected to conductive layer 365[1]b via conductive layer 345[1]b. Conductive layer 347[2]a is electrically connected to conductive layer 365[2]a (not shown) via conductive layer 345[2]a (not shown). Conductive layer 347[2]b is electrically connected to conductive layer 365[2]b via conductive layer 345[2]b.

[0334] The semiconductor device includes an insulating layer 348 over the insulating layer 346. The top surfaces of the conductive layer 347 and the insulating layer 348 are preferably aligned or substantially aligned with each other. The semiconductor device includes an insulating layer 349 over the conductive layer 347 and the insulating layer 348.

[0335] As described above, the conductive layer 361SD is used as the terminal SD, and the conductive layer 361Q is used as the terminal Q. In addition, the signal RE[1] is supplied to the storage circuit 231[1] through the conductive layer 347[1]a, and the signal BK[1] is supplied to the storage circuit 231[1] through the conductive layer 347[1]b. In addition, the signal RE[2] is supplied to the storage circuit 231[2] through the conductive layer 347[2]a, and the signal BK[2] is supplied to the storage circuit 231[2] through the conductive layer 347[2]b.

[0336] The structure described in this embodiment mode can be implemented in combination with the structures described in other embodiment modes as appropriate.

[0337] (Implementation 5) In this embodiment, application examples of a semiconductor device according to one embodiment of the present invention are described.

[0338] The semiconductor device of one embodiment of the present invention can be applied to various electronic components in addition to the CPU. For example, it can be applied to registers of microprocessors such as DSP (Digital Signal Processor) and GPU (Graphics Processing Unit). The microprocessor can also be implemented by PLD (Programmable Logic Device) such as FPGA (Field Programmable Gate Array) and FPAA (Field Programmable Analog Array).

[0339] Therefore, the semiconductor device according to one embodiment of the present invention can be applied to various electronic devices (for example, information terminals, computers, smart phones, e-book reader terminals, digital still cameras, video cameras, video playback devices, navigation systems, game consoles, etc.). In addition, it can also be applied to image sensors, IoT (Internet of Things), and medical equipment. Here, computers include tablet computers, laptop computers, desktop computers, and large computers such as server systems.

[0340] An example of an electronic device including a semiconductor device according to one embodiment of the present invention will be described. FIG. 27A to FIG. 27J The electronic component 700 including the semiconductor device is shown as being included in each electronic device.

[0341] [Mobile phone] Fig.27A The information terminal 5500 shown is a mobile phone (smartphone) which is one of the information terminals. The information terminal 5500 includes a housing 5510 and a display portion 5511 . The display portion 5511 includes a touch panel as an input interface, and buttons are provided on the housing 5510 .

[0342] By applying the semiconductor device according to one embodiment of the present invention to the information terminal 5500 , it is possible to promptly handle interrupt processing or the like that occurs while a program is being executed.

[0343] [Wearable terminal] also, Fig.27BAn information terminal 5900 as an example of a wearable terminal is shown. The information terminal 5900 includes a housing 5901, a display portion 5902, an operation switch 5903, an operation switch 5904, a strap 5905, and the like.

[0344] Similar to the above-described information terminal 5500 , by applying the semiconductor device according to one embodiment of the present invention to a wearable terminal, it is possible to promptly handle interrupt processing that occurs while a program is being executed.

[0345] [Information Terminal] Fig.27C 1 shows a desktop information terminal 5300. The desktop information terminal 5300 includes an information terminal body 5301, a display portion 5302, and a keyboard 5303.

[0346] Similar to the above-described information terminal 5500 , by applying the semiconductor device according to one embodiment of the present invention to the desktop information terminal 5300 , it is possible to promptly handle interrupt processing that occurs while a program is being executed.

[0347] Note that in the above description, FIG. 27A to FIG. 27C A smartphone, a wearable terminal, and a desktop information terminal are shown as examples of electronic devices, but information terminals other than smartphones, wearable terminals, and desktop information terminals may also be applied. Examples of information terminals other than smartphones, wearable terminals, and desktop information terminals include PDAs (Personal Digital Assistants), notebook information terminals, and workstations.

[0348] [Electrical products] also, Fig.27D An electric refrigerator-freezer 5800 is shown as an example of an electric appliance. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, etc. For example, the electric refrigerator-freezer 5800 is an electric refrigerator-freezer that supports IoT (Internet of Things).

[0349] The semiconductor device according to one embodiment of the present invention can be applied to electric refrigerator-freezer 5800. Electric refrigerator-freezer 5800 can transmit information such as food stored in electric refrigerator-freezer 5800 or the expiration date of the food to a data terminal by using the Internet.

[0350] Similar to the above-described information terminal 5500 , by applying the semiconductor device according to one embodiment of the present invention to the electric refrigerator-freezer 5800 , it is possible to promptly handle interrupt processing that occurs while a program is being executed.

[0351] In the above example, an electric refrigerator-freezer is described as an electrical appliance, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, IH cookers, water dispensers, air conditioners including heating and cooling units, washing machines, dryers, audio-visual equipment, etc.

[0352] [Game console] also, Fig.27E A portable game machine 5200 as an example of a game machine is shown. The portable game machine 5200 includes a housing 5201, a display portion 5202, buttons 5203, and the like.

[0353] also, Fig.27F The fixed game machine 7500 is an example of a game machine. The fixed game machine 7500 includes a main body 7520 and a controller 7522. The main body 7520 can be connected to the controller 7522 in a wireless manner or a wired manner. Fig.27F Although not shown in the figure, the controller 7522 may include a display unit for displaying game images, a touch panel and a joystick as an input interface other than buttons, a rotating grip or a sliding grip, etc. In addition, the controller 7522 is not limited to Fig.27F The shape of the controller 7522 can be changed according to the type of game. For example, in shooting games such as FPS (First Person Shooter), a controller that imitates the shape of a gun can be used as a trigger button. In addition, for example, in music games, a controller that imitates the shape of a musical instrument or a musical device can be used. Furthermore, a fixed game machine can also be provided with a camera, a depth sensor, a microphone, etc., and the game player's gestures or voice operations can replace the controller operation.

[0354] In addition, the images of the above-mentioned game machines can be output by display devices such as television devices, personal computer monitors, game monitors, head-mounted displays, etc.

[0355] By using the semiconductor device described in the above embodiment mode for the portable game console 5200 or the stationary game console 7500, a low-power portable game console 5200 or a stationary game console 7500 can be realized. In addition, the heat generated by the circuit can be reduced by means of low power consumption, thereby reducing the negative impact of heat on the circuit itself, peripheral circuits, and modules.

[0356] Furthermore, by using the semiconductor device described in the above embodiment mode for the portable game machine 5200 or the stationary game machine 7500, it is possible to promptly handle interrupt processing that occurs during game play.

[0357] exist Fig.27EIn the example of the game console, a portable game console is shown. Fig.27F A home-use fixed game machine is shown. The electronic device of one embodiment of the present invention is not limited thereto. As an electronic device of one embodiment of the present invention, for example, an arcade game machine installed in an entertainment facility (game center, amusement park, etc.), a pitching machine for batting practice installed in a sports facility, etc. can be cited.

[0358] [Mobile body] The semiconductor devices described in the above embodiments can be applied to a vehicle as a moving object and the vicinity of a driver's seat of the vehicle.

[0359] Figure 27G A car 5700 is shown as an example of a moving object.

[0360] A dashboard that can display a speedometer, a tachometer, a travel distance, a refueling amount, a gear state, an air-conditioning setting, etc. to provide various information is provided near the driver's seat of the automobile 5700. In addition, a display device that displays the above information may also be provided near the driver's seat.

[0361] In particular, by displaying the image captured by the camera device (not shown) installed on the automobile 5700 on the above-mentioned display device, the field of vision blocked by pillars, etc., the blind spot of the driver's seat, etc. can be supplemented, thereby improving safety. In other words, by displaying the image captured by the camera device installed outside the automobile 5700, the field of vision can be supplemented to avoid the blind spot, thereby improving safety.

[0362] By applying the semiconductor device according to one embodiment of the present invention to a movable body, it is possible to promptly respond to interruption processing or the like that occurs when the movable body is operating, such as emergency stop measures.

[0363] Although the above examples describe a car as an example of a mobile body, the mobile body is not limited to the car. For example, a tram, a monorail, a ship, a flying object (a helicopter, an unmanned aerial vehicle (UAV), an airplane, a rocket), etc. can also be cited as a mobile body.

[0364] [camera] The semiconductor devices described in the above embodiments can be applied to cameras.

[0365] Fig.27HA digital camera 6240 is shown as an example of an image pickup device. The digital camera 6240 includes a housing 6241, a display unit 6242, an operation switch 6243, a shutter button 6244, etc., and is provided with a detachable lens 6246. Here, the digital camera 6240 has a structure in which the lens 6246 can be removed from the housing 6241, but the lens 6246 may not be detachable. In addition, the digital camera 6240 may further include a flash device and a viewfinder, etc., which are separately provided.

[0366] By using the semiconductor device described in the above embodiment mode for the digital camera 6240, a low-power digital camera 6240 can be realized. In addition, low power consumption can reduce heat generated by the circuit, thereby reducing negative effects on the circuit itself, peripheral circuits, and modules due to heat.

[0367] [Video Camera] The semiconductor devices described in the above embodiments can be applied to video cameras.

[0368] Fig.27I A video camera 6300 as an example of a camera device is shown. The video camera 6300 includes a first housing 6301, a second housing 6302, a display unit 6303, an operation switch 6304, a lens 6305, a connection unit 6306, and the like. The operation switch 6304 and the lens 6305 are provided on the first housing 6301, and the display unit 6303 is provided on the second housing 6302. The first housing 6301 and the second housing 6302 are connected by the connection unit 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connection unit 6306. The image of the display unit 6303 can also be switched according to the angle between the first housing 6301 and the second housing 6302 in the connection unit 6306.

[0369] By using the semiconductor device described in the above embodiment mode for the video camera 6300, a low-power video camera 6300 can be realized. In addition, the low power consumption can extend the shooting time. In addition, the low power consumption can reduce the heat generated by the circuit, thereby reducing the negative impact of the heat on the circuit itself, peripheral circuits and modules.

[0370] [ICD] The semiconductor device described in the above embodiment can be applied to an implantable cardioverter defibrillator (ICD).

[0371] Fig.27J1 is a schematic cross-sectional view showing an example of an ICD. An ICD main body 5400 includes at least a battery 5401, an electronic component 700, a regulator, a control circuit, an antenna 5404, a wire 5402 to the right atrium, and a wire 5403 to the right ventricle.

[0372] The ICD body 5400 is surgically placed in the body, and two metal wires pass through the subclavian vein 5405 and the superior vena cava 5406 of the human body, and the tip of one of the metal wires is placed in the right ventricle, and the tip of the other metal wire is placed in the right atrium.

[0373] ICD main body 5400 has the function of a pacemaker, and paces the heart when the heart rhythm is out of a predetermined range. In addition, when the heart rhythm does not improve even with pacing (ventricular tachycardia, ventricular fibrillation, etc.), treatment using defibrillation is performed.

[0374] In order to perform pacing and defibrillation appropriately, the ICD main body 5400 needs to monitor the heart rhythm frequently. Therefore, the ICD main body 5400 includes a sensor for detecting the heart rhythm. In addition, the ICD main body 5400 can store the heart rhythm data measured by the sensor, the number of times and time of treatment using pacing, etc. in the electronic component 700.

[0375] In addition, since power is received by antenna 5404, the power is charged to battery 5401. In addition, safety can be improved by including a plurality of batteries in ICD main body 5400. Specifically, even if some batteries in ICD main body 5400 fail, other batteries can function and be used as auxiliary power sources.

[0376] In addition, in addition to the antenna 5404 capable of receiving power, an antenna capable of sending physiological signals may also be included. For example, a system for monitoring cardiac activity in which physiological signals such as pulse, respiratory rate, heart rhythm, and body temperature can be confirmed by an external monitoring device may be constructed.

[0377] By applying the semiconductor device described in the above embodiment to the ICD main body 5400, a low-power ICD main body 5400 can be realized. In addition, the battery can be miniaturized and lightweight due to the low power consumption. In addition, the heat generation of the ICD main body 5400 can be reduced due to the low power consumption, thereby reducing the load on the human body.

[0378] [computer] Fig.28AThe computer 5600 shown is an example of a large computer (supercomputer) mainly used for scientific computing. Scientific computing requires huge calculations at high speed, so the power consumption is large and the heat generation of the chip is high. For example, in a data center including multiple supercomputers, the amount of digital data used is very large. Specifically, it is estimated that the amount of digital data in the world exceeds 10 24 (yota) bytes or 10 30 (quetta(Kun)) bytes.

[0379] By using a semiconductor device of one embodiment of the present invention in computer 5600, a low-power supercomputer can be realized. In addition, low power consumption can reduce the heat generated by the circuit, thereby reducing the negative impact of heat on the circuit itself, peripheral circuits, and modules. In addition, by using a semiconductor device of one embodiment of the present invention, a low-power supercomputer can be realized. As a result, it can be expected that reducing the amount of global digital data can greatly contribute to measures to combat global warming.

[0380] In the computer 5600, a plurality of rack-mounted computers 5620 are stored in a rack 5610. The computer 5620 may have, for example, Fig.28B The structure of the stereogram is shown. Fig.28B In the embodiment, the computer 5620 includes a motherboard 5630, and the motherboard 5630 includes a plurality of slots 5631 and a plurality of connection terminals. A personal computer card 5621 is inserted into the slot 5631. The personal computer card 5621 includes connection terminals 5623, 5624, and 5625, which are connected to the motherboard 5630.

[0381] Fig.28C The personal computer card 5621 shown is an example of a processing board including a CPU, a GPU, a storage device, etc. The personal computer card 5621 has a board 5622. In addition, the board 5622 includes a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629. Note that Fig.28C Semiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 are shown. For description of these semiconductor devices, refer to the description of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 described below.

[0382] The connection terminal 5629 has a shape that can be inserted into the slot 5631 of the motherboard 5630, and is used as an interface for connecting the personal computer card 5621 and the motherboard 5630. Examples of the standard of the connection terminal 5629 include PCIe and the like.

[0383] The connection terminals 5623, 5624, and 5625 can be used as interfaces for supplying power to the personal computer card 5621 or inputting signals, for example. In addition, for example, they can be used as interfaces for outputting signals calculated by the personal computer card 5621, for example. Examples of the specifications of the connection terminals 5623, 5624, and 5625 include USB, SATA (Serial ATA), and SCSI (Small Computer System Interface). In addition, when video signals are output from the connection terminals 5623, 5624, and 5625, HDMI (registered trademark) and the like can be cited as the specifications.

[0384] The semiconductor device 5626 includes a terminal (not shown) for inputting and outputting a signal. By inserting the terminal into a socket (not shown) included in the board 5622 , the semiconductor device 5626 and the board 5622 can be electrically connected.

[0385] The semiconductor device 5627 includes a plurality of terminals, and the semiconductor device 5627 and the board 5622 can be electrically connected by soldering the terminals to wiring included in the board 5622 by reflow soldering. As the semiconductor device 5627, for example, an FPGA (Field Programmable Gate Array), a GPU, a CPU, etc. can be cited. As the semiconductor device 5627, for example, the electronic component 700 can be used.

[0386] The semiconductor device 5628 includes a plurality of terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected by soldering the terminals to wirings included in the board 5622 by, for example, reflow soldering. Examples of the semiconductor device 5628 include a memory device and the like.

[0387] The computer 5600 can be used as a parallel computer. By using the computer 5600 as a parallel computer, for example, large-scale calculations required for learning and inference of artificial intelligence can be performed.

[0388] By using a semiconductor device of one embodiment of the present invention in the above-mentioned various electronic devices, etc., it is possible to quickly respond to interrupt processing that occurs when a program is being executed. By using a semiconductor device of one embodiment of the present invention in the above-mentioned various electronic devices, low power consumption of the electronic device can be achieved. With the help of low power consumption, the heat generated by the circuit is reduced, thereby reducing the negative impact on the circuit itself, peripheral circuits and modules. In addition, by using a semiconductor device of one embodiment of the present invention, an electronic device that can also work stably in a high temperature environment can be realized. As a result, the reliability of the electronic device can be improved.

[0389] The structure described in this embodiment mode can be implemented in combination with the structures described in other embodiment modes as appropriate.

[0390] (Implementation 6) A semiconductor device according to one embodiment of the present invention includes an OS transistor. The OS transistor has a small change in electrical characteristics due to radiation exposure. In other words, it has high resistance to radiation, so it can be appropriately used in an environment where radiation may be incident. For example, the OS transistor can be appropriately used when used in outer space. In this embodiment, the OS transistor is used Fig.29 A specific example in which a semiconductor device according to one embodiment of the present invention is applied to space equipment will be described.

[0391] exist Fig.29 In FIG. 6 , an artificial satellite 6800 is shown as an example of a space device. The artificial satellite 6800 includes a main body 6801, a solar cell panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Fig.29 An example is shown in which the outer space includes the planet 6804. Note that the outer space refers to, for example, an altitude of 100 km or more, but the outer space described in this specification may also include the thermosphere, mesosphere, and stratosphere.

[0392] In addition, outer space is an environment where the radiation dose is more than 100 times that of the ground. Examples of radiation include: electromagnetic waves (electromagnetic radiation) represented by X-rays and gamma rays; and particle radiation represented by alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, muon rays, etc.

[0393] When sunlight shines on the solar cell panel 6802, the power required for the artificial satellite 6800 to operate is generated. However, for example, when sunlight does not shine on the solar cell panel or when the amount of sunlight shining on the solar cell panel is small, the amount of power generated is reduced. Therefore, there is a possibility that the power required for the artificial satellite 6800 to operate may not be generated. In order to operate the artificial satellite 6800 even when the generated power is small, it is preferable to provide a secondary battery 6805 in the artificial satellite 6800. In addition, the solar cell panel is sometimes referred to as a solar cell module.

[0394] The artificial satellite 6800 can generate a signal. The signal is transmitted through the antenna 6803, and a receiver on the ground or other artificial satellites can receive the signal. By receiving the signal transmitted by the artificial satellite 6800, the position of the receiver receiving the signal can be measured. Thus, the artificial satellite 6800 can constitute a satellite positioning system.

[0395] In addition, the control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is composed of, for example, one or more selected from a CPU, a GPU, and a storage device. In addition, as the control device 6807, a semiconductor device including an OS transistor of one embodiment of the present invention is preferably used. Compared with Si transistors, the electrical characteristics of OS transistors due to radiation exposure change is small. That is, OS transistors have high reliability and can be used appropriately even in an environment where radiation may be incident.

[0396] In addition, the artificial satellite 6800 may include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 may have a function of detecting sunlight reflected from an object on the ground. Or, by including a thermal infrared sensor, the artificial satellite 6800 may have a function of detecting thermal infrared rays released from the ground. Thus, the artificial satellite 6800 may be used as an earth observation satellite, for example.

[0397] Note that although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited to this. For example, a semiconductor device according to one embodiment of the present invention can be suitably applied to space equipment such as a spacecraft, a space capsule, and a space probe.

[0398] The structure described in this embodiment mode can be implemented in combination with the structures described in other embodiment modes as appropriate. [Explanation of symbols]

[0399] 100: semiconductor device, 110: CPU core, 111: computing unit, 120: bus, 130: PMU, 131: control circuit, 140: input / output IF, 150: cache memory, 160: state control unit, 200: register group, 201: register, 210: OSFF, 220: scan trigger, 221: selector, 222: trigger, 230: data holding circuit, 231: storage circuit, 232: transistor, 233: transistor, 234: transistor, 235: capacitor, 250: trigger group, 255: storage unit, 260: group storage

Claims

1. A semiconductor device comprising: A trigger group of n (n is any integer greater than or equal to 2) triggers; A first storage unit including n storage circuits disposed on the trigger group; as well as a second storage unit provided on the first storage unit and including p (p is an integer greater than 1 and less than n) storage circuits, wherein the trigger comprises a first transistor including silicon in a semiconductor layer forming a channel, The n memory circuits and the p memory circuits each include a second transistor including an oxide semiconductor in a semiconductor layer forming a channel, Furthermore, the semiconductor device has the following functions: When the data held by the flip-flop group is n-bit first data, in a first operation, the first data is held in the first storage unit; and When the data held by the flip-flop group is p-bit second data, the second data is held in the second storage unit in the second operation.

2. The semiconductor device according to claim 1, The n storage circuits and the p storage circuits each include two second transistors and a capacitor.

3. The semiconductor device according to claim 2, The two second transistors both have a region overlapping with the capacitor.

4. The semiconductor device according to claim 1 or 2, The second transistor is a vertical channel transistor.

5. The semiconductor device according to claim 1, wherein the first operation is accompanied by power gating operation, And the second task is a task accompanying interrupt processing.

Images