A multi-mode input / output function board capable of switching the clock level type

Abstract

The present invention discloses a multi-mode input / output function board capable of switching clock level types, comprising: a clock chip supporting multiple paths of clock input and output, including at least Input One, Input Two, Output One, Output Two, Output Three, and Output Four, and both the input and output are differential clocks; at least one input interface is externally connected to the differential clock of the Input One pin, and a crystal is externally connected to the differential clock of the Input Two pin; the differential clocks connected to the four output pins are all connected to output interfaces for outputting differential clock signals, and the output interfaces connected to the four outputs are different, capable of providing clocks of different levels, with flexible use and meeting the usage requirements of various differential clock level types.

Description

Technical Field

[0001] The present invention relates to the field of electronic design, and particularly to a multi-mode input / output function board capable of switching clock level types. Background Art

[0002] The technical application of differential clocks has been relatively perfect and is widely used in high-speed circuit design. However, the current application methods mostly involve the clock design of the circuit board itself or a single clock provided by a test device. The application environment, provision method, and clock type are all relatively single, and cannot meet the complex hardware test environments with multiple functions and multiple scenarios. The disadvantages of the existing technologies include:

[0003] 1. The clock design in the current circuit board has a relatively clear purpose, so it is mostly in a single-level mode. If there is a need to use other clock levels in the test environment, it is very difficult to handle or even requires redesigning the circuit board.

[0004] 2. Although some test devices can provide differential clocks, since the devices themselves are not used for providing clocks, and the types and methods of providing clocks are very single, in the actual application environment, such devices are very difficult to meet the usage conditions. Summary of the Invention

[0005] To achieve the above object and other related objects, the present invention discloses a multi-mode input / output function board capable of switching clock level types, including:

[0006] A clock chip supporting multi-channel clock input and output, at least including Input 1, Input 2, Output 1, Output 2, Output 3, and Output 4, and both the input and output are differential clocks;

[0007] At least one input interface is externally connected to the differential clock of the Input 1 pin, and a crystal is externally connected to the differential clock of the Input 2 pin;

[0008] The differential clocks of Output 1, Output 2, Output 3, and Output 4 are all connected to output interfaces for outputting differential clock signals, and the connected output interfaces are different.

[0009] Further, the clock chip is connected to a DIP switch for switching between Input 1 and Input 2.

[0010] Further, the clock chip is provided with reserved configuration pins for connecting an external host computer, flash, and EEPROM to configure the clock chip.

[0011] Further, adjustable matching resistors are provided for Input 1, Input 2, Output 1, and Output 2.

[0012] Further, the input interface types connected to the first input include 2.4 mm coaxial interface, 2.92 mm coaxial interface or PCIe slot.

[0013] Further, the output interface types connected to the first output, the second output, the third output and the fourth output include 2.4 mm coaxial interface, 2.92 mm coaxial interface, PCIe slot or SATA socket.

[0014] By adopting the above technical solutions, there are various high-speed interfaces for docking the master device and the slave device, which can dock various test interfaces on the current market. Even if there are special high-speed interface requirements, it can be replaced with the required high-speed interface during design, which is convenient and practical; it can provide clocks with different levels, is flexible in use, and can meet the usage requirements of various differential clocks; there are at least two inputs, which can meet the test scenarios of the same-source clock or non-same-source clock in various situations, and is convenient to apply; the configuration is simple. For different differential clocks, different clock levels can be output only by configuring the configuration pins of the clock buffer, which is flexible in application; the matching resistors of various differential clocks are convenient to replace, and the termination resistors can be matched by using the DIP switch, which is simple and easy to use and has strong reusability; the design is simple and the cost is low, which is suitable for use in various high-speed circuit test fields. Description of the Drawings

[0015] In combination with the accompanying drawings and with reference to the following detailed description, the above and other features, advantages and aspects of the various embodiments of the present disclosure will become more apparent. The drawings are used to better understand the solution and do not limit the present disclosure. In the drawings, the same or similar reference numerals denote the same or similar elements, where:

[0016] Figure 1 is the circuit schematic diagram of the present invention;

[0017] Figure 2 is the pin diagram of the four-terminal capacitor used in the present invention;

[0018] Figure 3 is the schematic diagram of Case 1 in the present invention;

[0019] Figure 4 is the schematic diagram of Case 2 in the present invention. Detailed Embodiments

[0020] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of the present invention.

[0021] Refer to Figure 1, an embodiment of the present invention provides a multi-mode input / output function board capable of switching clock level types, including:

[0022] A clock chip 1 that supports multiple channels of clock input and output. There are various chips in the prior art that meet this requirement. In the embodiment of the present invention, the Si5330X chip is preferably used, which supports two inputs and four outputs, namely Input 1, Input 2, Output 1, Output 2, Output 3, and Output 4, and differential clocks are connected to both the input and output.

[0023] Differential clocks of Input 1 are respectively connected to a four-terminal capacitor 4 and a four-terminal capacitor 5. The pin sorting of the four-terminal capacitor refers to Figure 2 , where the a pin of the four-terminal capacitor 4 is connected to the P end of the differential clock of Input 1, and the b, c, and d pins of the four-terminal capacitor 4 are sequentially connected to a 2.4 mm coaxial interface 6, a 2.92 mm coaxial interface 7, and a PCIe slot 8, and other interfaces can also be connected according to actual usage requirements. The a pin of the four-terminal capacitor 5 is connected to the N end of the differential clock of Input 1, and the b, c, and d pins of the four-terminal capacitor 5 are sequentially connected to a 2.4 mm coaxial interface 9, a 2.92 mm coaxial interface 10, and a PCIe slot 8.

[0024] Input 1 is also externally connected with adjustable-resistance matching resistors, including resistor R1, resistor R2, resistor R3, resistor R4, resistor R5, resistor R6, resistor R7, a two-bit DIP switch 12, and a two-bit DIP switch 13. One end of one pin of the DIP switch 12 is connected to the power supply VDD, and the other end is connected to one end of the resistor R1. The other end of the resistor R1 is connected to the a pin of the four-terminal capacitor 4. One end of the other pin of the DIP switch 12 is connected to the power supply VDD, and the other end is connected to one end of the resistor R2. The other end of the resistor R2 is connected to the a pin of the four-terminal capacitor 5. The resistor R3 is located on the P end of the differential clock, and the resistor R3 is connected between the resistor R1 and Input 1. The resistor R5 is located on the N end of the differential clock, and the resistor R5 is connected between the resistor R2 and Input 1. One end of the resistor R4 is connected between the resistor R1 and the resistor R3, and the other end of the resistor R4 is connected between the resistor R5 and Input 1.

[0025] One end of one pin of the DIP switch 13 is connected to the P end, and the connection point is located between the resistor R1 and the resistor R4. The other end of this pin is connected to one end of the resistor R7, and the other end of the resistor R7 is grounded. The other pin of the DIP switch 13 is connected to the N end, and the connection point is located between the resistor R2 and the resistor R5. The other end of this pin is connected to one end of the resistor R6, and the other end of the resistor R6 is grounded.

[0026] The differential clock of Input 2 is connected to Crystal 2. The two pins of Crystal 2 are respectively connected to the P terminal and the N terminal of the differential clock of Input 2. Input 2 is also externally connected with adjustable resistance matching resistors, including Resistor R8, Resistor R9, Resistor R10, Resistor R11, Resistor R12, Resistor R13, Resistor R14, two-position DIP switch 14 and two-position DIP switch 15. One end of one pin of DIP switch 14 is connected to power supply VDD, and the other end is connected to one end of Resistor R8. The other end of Resistor R8 is connected to the P terminal of the differential clock. One end of the other pin of DIP switch 14 is connected to power supply VDD, and the other end is connected to one end of Resistor R9. The other end of Resistor R9 is connected to the N terminal of the differential clock. Resistor R10 is located on the P terminal of the differential clock, and Resistor R10 is connected between Resistor R8 and Input 2. Resistor R12 is located on the N terminal of the differential clock, and Resistor R12 is connected between Resistor R9 and Input 2. One end of Resistor R11 is connected between Resistor R8 and Resistor R10, and the other end of Resistor R11 is connected between Resistor R12 and Input 2.

[0027] One end of one pin of DIP switch 15 is connected to the P terminal, and the connection point is located between Resistor R8 and Resistor R11. The other end of this pin is connected to one end of Resistor R14, and the other end of Resistor R14 is grounded. The other pin of DIP switch 15 is connected to the N terminal, and the connection point is located between Resistor R9 and Resistor R12. The other end of this pin is connected to one end of Resistor R13, and the other end of Resistor R13 is grounded.

[0028] The clock chip is also externally connected with DIP switch 3. DIP switch 3 is a two-position DIP switch and is used to switch between Input 1 and Input 2.

[0029] The clock chip also reserves Configuration Pin 11, which can be externally connected to a host computer, flash, EEPROM, etc. for configuration.

[0030] The output interface types connected to Output 1, Output 2, Output 3 and Output 4 include 2.4mm coaxial interface, 2.92mm coaxial interface, PCIe slot or SATA socket, and other interfaces can also be connected according to actual usage requirements.

[0031] The P terminal of the differential clock of Output 1 is connected to the 2.4 mm coaxial interface 14, and the N terminal is connected to the 2.4 mm coaxial interface 15. Output 1 is also externally connected with adjustable resistance matching resistors, including resistor R15, resistor R16, resistor R17, resistor R18, resistor R19, resistor R20, resistor R21, two-position DIP switch 16 and two-position DIP switch 17. One end of one pin of DIP switch 16 is connected to the power supply VDD, and the other end is connected to one end of resistor R15. The other end of resistor R15 is connected to the P terminal of the differential clock. One end of the other pin of DIP switch 16 is connected to the power supply VDD, and the other end is connected to one end of resistor R16. The other end of resistor R16 is connected to the N terminal of the differential clock. Resistor R17 is located on the P terminal of the differential clock, and resistor R17 is connected between resistor R15 and Output 1. Resistor R19 is located on the N terminal of the differential clock, and resistor R19 is connected between resistor R16 and Output 1. One end of resistor R18 is connected between Output 1 and resistor R17, and the other end of resistor R18 is connected between resistor R19 and resistor R16.

[0032] One end of one pin of DIP switch 17 is connected to the P terminal, and the connection point is located between resistor R15 and the 2.4 mm coaxial interface 14. The other end of this pin is connected to one end of resistor R21, and the other end of resistor R21 is grounded. The other pin of DIP switch 17 is connected to the N terminal, and the connection point is located between resistor R16 and the 2.4 mm coaxial interface 15. The other end of this pin is connected to one end of resistor R20, and the other end of resistor R20 is grounded.

[0033] The P terminal of the differential clock of Output 2 is connected to the 2.92 mm coaxial interface 16, and the N terminal is connected to the 2.92 mm coaxial interface 17. Output 2 is also externally connected with adjustable resistance matching resistors, including resistor R22, resistor R23, resistor R24, resistor R25, resistor R26, resistor R27, resistor R28, two-position DIP switch 18 and two-position DIP switch 19. One end of one pin of DIP switch 18 is connected to the power supply VDD, and the other end is connected to one end of resistor R22. The other end of resistor R22 is connected to the P terminal of the differential clock. One end of the other pin of DIP switch 18 is connected to the power supply VDD, and the other end is connected to one end of resistor R23. The other end of resistor R23 is connected to the N terminal of the differential clock. Resistor R24 is located on the P terminal of the differential clock, and resistor R24 is connected between resistor R22 and Output 2. Resistor R26 is located on the N terminal of the differential clock, and resistor R26 is connected between resistor R23 and Output 2. One end of resistor R25 is connected between Output 2 and resistor R24, and the other end of resistor R25 is connected between resistor R26 and resistor R23.

[0034] One end of one of the pins of the DIP switch 19 is connected to the P terminal, and the connection point is located between the resistor R22 and the 2.92 mm coaxial interface 16. The other end of this pin is connected to one end of the resistor R28, and the other end of the resistor R28 is grounded. The other pin of the DIP switch 19 is connected to the N terminal, and the connection point is located between the resistor R23 and the 2.92 mm coaxial interface 17. The other end of this pin is connected to one end of the resistor R27, and the other end of the resistor R27 is grounded.

[0035] The differential clock of Output Three is connected to the PCIe slot 18. Output Three is also externally connected with adjustable-value matching resistors, including the resistor R29, the resistor R30, the resistor R31, the resistor R32, the resistor R33, the resistor R34, the resistor R35, the two-position DIP switch 20 and the two-position DIP switch 21. One end of one of the pins of the DIP switch 20 is connected to the power supply VDD, and the other end is connected to one end of the resistor R29. The other end of the resistor R29 is connected to the P terminal of the differential clock. One end of the other pin of the DIP switch 20 is connected to the power supply VDD, and the other end is connected to one end of the resistor R30. The other end of the resistor R30 is connected to the N terminal of the differential clock. The resistor R31 is located on the P terminal of the differential clock, and the resistor R31 is connected between the resistor R29 and Output Three. The resistor R33 is located on the N terminal of the differential clock, and the resistor R33 is connected between the resistor R30 and Output Three. One end of the resistor R32 is connected between Output Three and the resistor R31, and the other end of the resistor R32 is connected between the resistor R33 and the resistor R30.

[0036] One end of one of the pins of the DIP switch 21 is connected to the P terminal, and the connection point is located between the resistor R29 and the PCIe slot 18. The other end of this pin is connected to one end of the resistor R35, and the other end of the resistor R35 is grounded. The other pin of the DIP switch 21 is connected to the N terminal, and the connection point is located between the resistor R30 and the PCIe slot 18. The other end of this pin is connected to one end of the resistor R34, and the other end of the resistor R34 is grounded.

[0037] The differential clock connection of Output 4 has a SATA connector 19. Output 4 is also externally connected with adjustable-resistance matching resistors, including resistor R36, resistor R37, resistor R38, resistor R39, resistor R40, resistor R41, resistor R42, two-position DIP switch 22 and two-position DIP switch 23. One end of one pin of DIP switch 22 is connected to power supply VDD, and the other end is connected to one end of resistor R36. The other end of resistor R36 is connected to the P end of the differential clock. One end of the other pin of DIP switch 22 is connected to power supply VDD, and the other end is connected to one end of resistor R37. The other end of resistor R37 is connected to the N end of the differential clock. Resistor R38 is located on the P end of the differential clock, and resistor R38 is connected between resistor R36 and Output 4. Resistor R40 is located on the N end of the differential clock, and resistor R40 is connected between resistor R37 and Output 4. One end of resistor R39 is connected between Output 4 and resistor R38, and the other end of resistor R39 is connected between resistor R40 and resistor R37.

[0038] One end of one pin of DIP switch 23 is connected to the P end, and the connection point is located between resistor R36 and SATA connector 19. The other end of this pin is connected to one end of resistor R42, and the other end of resistor R42 is grounded. The other pin of DIP switch 23 is connected to the N end, and the connection point is located between resistor R37 and SATA connector 19. The other end of this pin is connected to one end of resistor R41, and the other end of resistor R41 is grounded.

[0039] The following is an example of the usage method of the present invention:

[0040] Refer to Figure 3 , when the master device and the test board need to use the same-source clock, the differential clock level type is LVDS, and Input 1 is configured for use. Since it is LVDS level, pull-up and pull-down resistors are not required, so resistors R1, R2, R6, and R7 are removed, resistors R3 and R5 are replaced with 0-ohm resistors, and a 100-ohm resistor is soldered to R4. The connection method between the master device and the multi-level differential clock function board is as follows: If the external interface of the master device is a PCIe slot, then a PCIe extension cable is used to dock the master device with the PCIe slot 8 of Input 1 of this multi-level differential clock function board.

[0041] For the output end, with LVDS level, replace resistors R31 and R33 with 0-ohm resistors and remove resistors R29, R30, R32, R34, and R35. The connection method between the test board and the multi-level differential clock function board is as follows: Use a PCIe extension cable to dock the test board with the PCIe slot 18 of Output 3 of this multi-level differential clock function board.

[0042] Refer to Figure 4, a clock is provided for a certain device or board card alone, the differential clock level type is HCSL, and Configuration Use Input Two is configured:

[0043] At the input end, a crystal is used to provide the HCSL differential clock. The matching resistors R10 and R12 are changed to 33 ohms, and a 50-ohm pull-down resistor is used. Therefore, the resistors R8 and R9 need to be removed, the resistors R13 and R14 are changed to 50 ohms, and the resistor R11 is removed.

[0044] For the output end HCSL differential clock source-end matching resistor, the resistor R18 is removed, the resistors R17 and R19 are changed to 42.2 ohms, and an 86.6-ohm pull-down resistor is used. Therefore, the resistors R15 and R16 need to be removed, and the resistors R20 and R21 are changed to 86.6 ohms. The connection method between the test board and the multi-level differential clock function board card is as follows: Use two RF cables with 2.4mm interfaces to be respectively connected to the 2.4mm coaxial interface 14 and 2.4mm coaxial interface 15 of the output one of the multi-level differential clock function board card and the 2.4mm coaxial interface of the test board.

[0045] This embodiment provides a multi-mode input / output function board card with a switchable clock level type. There are various high-speed interfaces for docking the master device and the slave device, which can dock various test interfaces on the current market. Even if there are special high-speed interface requirements, it can be replaced with the required high-speed interface during design, which is convenient and practical; it can provide clocks with different levels (such as clocks of types LVPECL, LVDS, CML, HCSL, etc.), with flexible use and can meet all the usage requirements of differential clocks; two inputs can meet the test scenarios of the same-source clock or non-same-source clock in various situations, and the application is convenient; the configuration is simple. For different differential clocks, different clock level outputs can be achieved only by configuring through the configuration pins of the clock buffer, and the application is flexible; the matching resistors of various differential clocks are convenient to replace, and the termination resistors can be matched by using a DIP switch, which is simple and easy to use and has strong reusability; the design is simple and the cost is low, which is suitable for use in various high-speed circuit test fields.

[0046] Those skilled in the art of this technology can understand that unless otherwise defined, all terms (including technical terms and scientific terms) used here have the same meaning as the general understanding of those of ordinary skill in the art in the field to which the present invention belongs. It should also be understood that those terms defined in a general dictionary, should be understood to have a meaning consistent with the meaning in the context of the prior art, and will not be interpreted with an idealized or overly formal meaning unless specifically defined.

[0047] For the method embodiments, for the sake of simplicity of description, they are all expressed as a series of combinations of actions. However, those skilled in the art should be aware that the embodiments of the present invention are not limited by the described order of actions, because according to the embodiments of the present invention, some steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily essential for the embodiments of the present invention.

[0048] From the description of the above embodiments, it can be clearly understood by those skilled in the art that the present application can be implemented by means of software plus a necessary general hardware platform. Based on such an understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as ROM / RAM, magnetic disk, optical disc, etc., and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in various embodiments or some parts of the embodiments of the present application.

[0049] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A multi-mode input / output function board capable of switching clock level types, characterized in that, Including: A clock chip supporting multi-channel clock input and output, at least including Input 1, Input 2, Output 1, Output 2, Output 3 and Output 4, and both the input and output are differential clocks; The differential clock of the Input 1 pin is externally connected with at least one input interface, and the differential clock of the Input 2 pin is externally connected with a crystal; The differential clocks of Output 1, Output 2, Output 3 and Output 4 are all connected with output interfaces for outputting differential clock signals, and the connected output interfaces are different; The matching resistors externally connected to Input 1 include: resistor R1, resistor R2, resistor R3, resistor R4, resistor R5, resistor R6, resistor R7, the first two-position DIP switch (12) and the second two-position DIP switch (13). One end of one pin of the first two-position DIP switch (12) is connected to the power supply VDD, and the other end is connected to one end of resistor R1. The other end of resistor R1 is connected to the a pin of the four-terminal capacitor 4. One end of the other pin of the first two-position DIP switch (12) is connected to the power supply VDD, and the other end is connected to one end of resistor R2. The other end of resistor R2 is connected to the a pin of the four-terminal capacitor (5). Resistor R3 is located on the P end of the differential clock, and resistor R3 is connected between resistor R1 and Input 1. Resistor R5 is located on the N end of the differential clock, and resistor R5 is connected between resistor R2 and Input 1. One end of resistor R4 is connected between resistor R1 and resistor R3, and the other end of resistor R4 is connected between resistor R5 and Input 1; One end of one pin of the second two-position DIP switch (13) is connected to the P end, and the connection point is located between resistor R1 and resistor R4. The other end of this pin is connected to one end of resistor R7, and the other end of resistor R7 is grounded. The other pin of the second two-position DIP switch (13) is connected to the N end, and the connection point is located between resistor R2 and resistor R5. The other end of this pin is connected to one end of resistor R6, and the other end of resistor R6 is grounded.

2. The multi-mode input / output function board capable of switching clock level types according to claim 1, characterized in that, The clock chip is connected with a DIP switch for switching between Input 1 and Input 2.

3. The multi-mode input / output function board capable of switching clock level types according to claim 1, wherein The clock chip is provided with reserved configuration pins for connecting an external host computer, flash, EEPROM to configure the clock chip.

4. A multi-mode input / output function board capable of switching clock level types according to claim 1, characterized in that, The Input 1, Input 2, Output 1 and Output 2 are all provided with matching resistors with adjustable resistance values.

5. The multi-mode input / output function board capable of switching clock level types according to claim 1, characterized in that The types of input interfaces connected to Input 1 include 2.4mm coaxial interface, 2.92mm coaxial interface or PCIe slot.

6. The multi-mode input / output function board capable of switching clock level types according to claim 1, characterized in that, The types of output interfaces connected to Output 1, Output 2, Output 3 and Output 4 include 2.4mm coaxial interface, 2.92mm coaxial interface, PCIe slot or SATA socket.

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