Information processing method and device, electronic equipment and storage medium

Abstract

The invention discloses an information processing method and device, electronic equipment and a storage medium. The method comprises the following steps: determining first information of a target processing unit array (PEA), wherein the first information represents a heat effect condition of each processing unit (PE) in the target PEA in a first time range; on the basis of the first information of the target PEA, second information of the target PEA is determined, the second information comprises the predicted available state of each PE in the target PEA within the second time range when the PE meets a first condition, and the first condition represents that the temperature of the PE is smaller than or equal to a first threshold value; and mapping the to-be-mapped algorithm to the target PEA according to the second information so as to execute the to-be-mapped algorithm through the target PEA.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to an information processing method, device, electronic device and storage medium. Background Art

[0002] As chip manufacturing processes continue to improve, the cost of chip manufacturing under advanced processes has also risen exponentially. Traditional system-on-chip (SoC) design technology can integrate modules such as the main control processor, computing power processor, computing power acceleration unit, storage, and interface in a single chip (which can be expressed as a single die in English) to form a system-level chip. It can be seen that with the continuous improvement of chip functions and performance requirements, the area of ​​​​monolithic chips will become larger and larger under the SoC technology route. In view of the soaring chip manufacturing costs and the inevitable process defects in the chip manufacturing process, it will cause problems such as a decrease in the yield of large chips based on the SoC system and the difficulty in controlling the manufacturing costs of monolithic chips.

[0003] The core particle (also called crystal particle or small chip, etc., can be expressed as Chiplet in English) technology in the related art can solve the problems existing in the above-mentioned SoC technology. Figure 1 As shown, core particle technology is a modular design technology based on advanced packaging, which can modularly assemble heterogeneous chips through standardized protocol interfaces (also known as Lego-style assembly). The advantage of this technical route is that it can modularly cut computing units with high process requirements (such as process requirements less than 12 nanometers (nm)). On the one hand, it can avoid the unnecessary increase of high process area in SoC monolithic integration of modules such as main control, interface, power supply, etc. (such as process requirements greater than 55nm); on the other hand, it can increase the data bandwidth (including memory access bandwidth and data interaction bandwidth) between modules (especially between computing modules and storage modules, and between computing modules) through micro-connection technologies such as micro-bumps (uBump) based on 2.5-dimensional (2.5D, 2.5-Dimensional) / 3D (3D, 3-Dimension) packaging, that is, it can realize high bandwidth memory access packaging (HBM, HighBandwidth Memory), thereby improving the overall performance of the packaged chip.

[0004] However, in the related technology, the heat dissipation effect of the chip still needs to be improved. Summary of the invention

[0005] To solve related technical problems, the embodiments of the present application provide an information processing method, device, electronic device and storage medium.

[0006] The technical solution of the embodiment of the present application is implemented as follows:

[0007] The present application provides an information processing method, including:

[0008] Determining first information of a target processing element array (PEA), wherein the first information represents a thermal effect of each processing element (PE) in the target PEA within a first time range;

[0009] Based on the first information, determine second information of the target PEA, the second information comprising a predicted available state of each PE in the target PEA within a second time range when a first condition is satisfied, the first condition indicating that a temperature of the PE is less than or equal to a first threshold;

[0010] According to the second information, the algorithm to be mapped is mapped to the target PEA, so that the algorithm to be mapped is executed by the target PEA.

[0011] In the above solution, the first information for determining the target PEA includes:

[0012] For each PE in the target PEA, in each time unit of at least one time unit within the first time range, a thermal effect of the PE is quantified based on a gray value to obtain a thermal effect gray value corresponding to the PE in each time unit;

[0013] The thermal effect condition of each PE is determined by using the thermal effect grayscale value and driving voltage corresponding to each PE in each time unit to obtain the first information.

[0014] In the above scheme, the quantification of the thermal effect of PE based on gray value includes:

[0015] Determine a first weighted value and a second weighted value of the PE, wherein the first weighted value is associated with a type of algorithm executed by the PE, and the second weighted value is associated with a data bit width when the PE executes the algorithm;

[0016] The thermal effect grayscale value of the PE is determined using the first weighted value and the second weighted value of the PE.

[0017] In the above scheme, the thermal effect condition of each PE is determined by using the thermal effect gray value and driving voltage corresponding to each PE in each time unit, including:

[0018] For each PE in the target PEA, within the first time range, the product of the thermal effect grayscale value corresponding to the PE in each time unit and the third weighted value is accumulated to obtain the thermal effect cumulative value of the PE, the third weighted value is associated with the driving voltage of the PE, and the thermal effect cumulative value can reflect the thermal effect situation of the PE, and the first information includes the thermal effect cumulative value of each PE in the target PEA within the first time range.

[0019] In the above solution, the determining the second information of the target PEA based on the first information includes:

[0020] Based on the first information, determining third information of the target PEA, wherein the third information includes a maximum driving voltage that each PE in the target PEA can withstand within the second time range;

[0021] The second information is determined based on the third information and the fourth information, wherein the fourth information represents the occupancy status of each PE in the target PEA within the second time range.

[0022] In the above scheme, the first information includes the accumulated value of thermal effect of each PE in the target PEA within the first time range, and the accumulated value of thermal effect can reflect the thermal effect of PE. The accumulated value of thermal effect of each PE is obtained by accumulating the product of the thermal effect gray value corresponding to the PE in each time unit within the first time range and the third weighted value, and the third weighted value is determined by using the first function and the driving voltage of the PE; the third information of the target PEA is determined based on the first information, including:

[0023] For each PE in the target PEA, the maximum driving voltage that the PE can withstand within the second time range is determined by using a second function, the accumulated value of the thermal effect of the PE within the first time range, and a second threshold corresponding to the accumulated value of the thermal effect, wherein the second function is an inverse function of the first function, and the second threshold is associated with the fifth information of the target PEA, and the fifth information indicates the PE in the target PEA that does not meet the first condition within the first time range.

[0024] In the above solution, determining the second information based on the third information and the fourth information includes:

[0025] For each PE in the target PEA, when it is determined by using the fourth information that the PE is occupied within the second time range, determining a first identifier associated with the PE, where the first identifier indicates that the PE does not support execution of the algorithm within the second time range because it is occupied; or,

[0026] In the case where it is determined by using the fifth information of the target PEA that the PE does not satisfy the first condition within the first time range, determining that the PE is associated with a second identifier, the second identifier indicating that the PE does not support the execution of the algorithm due to overheating within the second time range, and the fifth information indicates the PE in the target PEA that does not satisfy the first condition within the first time range; or

[0027] When it is determined by using the third information that the maximum driving voltage that the PE can withstand within the second time range is less than a third threshold, determining that the PE is associated with the second identifier, and the third threshold represents the lowest voltage provided by the system to the PE within the second time range; or

[0028] When it is determined by using the third information that the maximum driving voltage that the PE can withstand within the second time range is greater than or equal to the third threshold and less than the fourth threshold, determine that the PE is associated with a third identifier, where the third identifier indicates that the PE supports the execution of the first type of algorithm within the second time range; or,

[0029] In the case where it is determined by using the third information that the maximum driving voltage that the PE can withstand within the second time range is greater than or equal to the fourth threshold, a fourth identifier associated with the PE is determined, and the fourth identifier indicates that the PE supports the execution of a second type of algorithm within the second time range, and the complexity of the second type of algorithm is higher than the complexity of the first type of algorithm; wherein,

[0030] The second information includes an identifier associated with each PE in the target PEA, and the identifier associated with the PE can reflect the available state of the PE when the first condition is met.

[0031] In the above solution, mapping the algorithm to be mapped to the target PEA according to the second information includes:

[0032] When it is determined according to the second information that the target PEA satisfies a second condition, directly mapping the algorithm to be mapped to the target PEA so as to execute the algorithm to be mapped by the target PEA within the second time range, wherein the second condition indicates that computing resources that can be provided by the target PEA within the second time range support the execution of the algorithm to be mapped; or

[0033] In a case where it is determined according to the second information that the target PEA does not satisfy the second condition, mapping the algorithm to be mapped to the target PEA using a first strategy, so as to execute the algorithm to be mapped through the target PEA within a third time range, where the third time range is greater than the second time range; or

[0034] When it is determined based on the second information that the target PEA does not satisfy the second condition, and the target PEA satisfies the third condition, another algorithm to be mapped whose priority is lower than the algorithm to be mapped is mapped to the target PEA, so that the other algorithm to be mapped is executed by the target PEA within the second time range, and the third condition represents the computing resources that can be provided by the target PEA within the second time range to support the execution of the other algorithm to be mapped.

[0035] The present application also provides an information processing device, including:

[0036] A first processing unit, configured to determine first information of a target PEA, wherein the first information represents a thermal effect of each PE in the target PEA within a first time range;

[0037] a second processing unit, configured to determine second information of the target PEA based on the first information, the second information comprising a predicted available state of each PE in the target PEA within a second time range when a first condition is satisfied, the first condition indicating that a temperature of the PE is less than or equal to a first threshold;

[0038] The third processing unit is configured to map the algorithm to be mapped to the target PEA according to the second information, so as to execute the algorithm to be mapped through the target PEA.

[0039] The embodiment of the present application also provides an electronic device, comprising: a communication interface and a processor; wherein:

[0040] The processor is configured to:

[0041] Determine first information of a target PEA, wherein the first information represents a thermal effect of each PE in the target PEA within a first time range;

[0042] Based on the first information, determine second information of the target PEA, the second information comprising a predicted available state of each PE in the target PEA within a second time range when a first condition is satisfied, the first condition indicating that a temperature of the PE is less than or equal to a first threshold;

[0043] According to the second information, the algorithm to be mapped is mapped to the target PEA, so that the algorithm to be mapped is executed by the target PEA.

[0044] The present application also provides an electronic device, including: a processor and a memory for storing a computer program that can be run on the processor.

[0045] Wherein, the processor is used to execute the steps of any of the above methods when running the computer program.

[0046] An embodiment of the present application further provides a storage medium having a computer program stored thereon, wherein the computer program implements the steps of any of the above methods when executed by a processor.

[0047] The information processing method, device, electronic device and storage medium provided in the embodiment of the present application determine the first information of the target PEA, the first information characterizing the thermal effect of each PE in the target PEA within the first time range; based on the first information, determine the second information of the target PEA, the second information includes the predicted available state of each PE in the target PEA within the second time range when the first condition is met, the first condition characterizing that the temperature of the PE is less than or equal to the first threshold; according to the second information, map the algorithm to be mapped to the target PEA to execute the algorithm to be mapped through the target PEA. The scheme provided in the embodiment of the present application predicts the available state of each PE in the future time range (i.e., the second time range) when the temperature does not exceed a specific threshold (i.e., the first threshold) based on the thermal effect of each PE in the target PEA within a specific time range (i.e., the first time range), and then maps the algorithm to be mapped to the target PEA based on the available state of each PE in the future time range when the temperature does not exceed a specific threshold, so as to execute the algorithm to be mapped through the target PEA. In this way, the number of PEs with too high temperature (i.e., the temperature exceeds a specific threshold, i.e., the temperature is greater than the first threshold) can be reduced in the process of executing the algorithm to be mapped through the target PEA, avoiding high-load operation of PEAs. The heat diffusion effect generated by E at full load has a collateral impact on the adjacent PE, effectively ensuring the actual heat dissipation performance of the chip where the target PEA is located in actual work (especially under full load), so that it can achieve active heat dissipation of the chip from a software perspective for some specific packaging scenarios (such as 2.5D / 3D superposition of computing power modules (ie PE)), and achieve reasonable utilization of the computing power resources of the chip while effectively improving the heat dissipation effect of the chip, thereby improving the overall algorithm throughput of the chip and the overall utilization of the chip, and thus providing effective support for the subsequent formation of electronic design automation (EDA, Electronic Design Automation) and / or integrated development environment (IDE, Integrated Development Environment) tools for advanced packaging and hardware and software collaborative design. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 It is a schematic diagram of packaging based on core particle technology in the related art;

[0049] Figure 2 It is a schematic diagram of a PE structure with a driving voltage management function in the related art;

[0050] Figure 3 A schematic diagram of PEA composed of PE in the related art;

[0051] Figure 4 It is a conceptual diagram of PE parallel execution in the related art;

[0052] Figure 5 A flowchart of an information processing method according to an embodiment of the present application;

[0053] Figure 6 This is a schematic diagram of the temperature control optimization architecture of a general purpose graphics processor (GPGPU, General Propose Graphic Processing Unit) based on HBM, which is an application example of this application;

[0054] Figure 7 A schematic diagram of hot marking nodes in a data flow graph (DFG) for the application example of this application;

[0055] Figure 8 A schematic diagram of resource occupancy assessment for this application example;

[0056] Fig. 9 Schematic diagram of the algorithm mapping optimization for the application example of this application;

[0057] Fig.10 This is a schematic diagram of the structure of an information processing device according to an embodiment of the present application;

[0058] Fig.11 This is a schematic diagram of the structure of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0059] The present application is further described in detail below in conjunction with the accompanying drawings and embodiments.

[0060] In the related technology, the heat dissipation of the chip usually depends on the static power consumption and dynamic power consumption, and the dynamic power consumption is particularly prominent in the high-speed computing power module (also known as the computing power unit, etc.). The thermal effect of the chip is the main factor affecting the chip performance, and it is also the main reason for the processor to switch from single-core to multi-core. Excessive on-chip temperature will affect the migration efficiency of electrons and holes in the silicon-based semiconductor field effect tube in the chip, which will directly affect the chip performance under various advanced process technologies. Whether it is 2.5D packaging or 3D packaging, since the chip will be stacked during the packaging stage, the heat dissipation problem of the chip will face greater challenges under the design route of the core particle technology. Among them, the complete stacking design usually occurs between the computing power unit and the storage unit, between the computing power unit and the computing power unit, or between the computing power unit and the storage and computing integrated unit. Generally speaking, the heat dissipation problem caused by 3D stacking of computing power units is the most complex and serious, which may lead to problems such as unreliable and uncontrollable data results.

[0061] In actual applications, the heat dissipation problem of the chip can be solved based on the improvement of materials and structures. For example, the heat dissipation problem under 2.5D / 3D packaging can be improved from the packaging structure through the combination of thermal conductive materials and perforations. However, on the one hand, this heat dissipation solution cannot ensure the actual heat dissipation performance of the chip in actual work (especially under full load), and cannot ensure that the heat dissipation solution can effectively improve the heat dissipation of the chip in the scenario of 2.5D / 3D superposition of computing power modules; on the other hand, this kind of passive heat dissipation solution based on the improvement of materials and structures may not be able to actively avoid the collateral impact of the heat diffusion effect generated by the high-load running module under full load on the adjacent parallel computing units.

[0062] To sum up, in the related technology, for some specific packaging scenarios (such as the scenario of 2.5D / 3D superposition of computing power modules, etc.), the heat dissipation effect of the chip still needs to be improved. In order to improve the heat dissipation effect of the chip, the embodiment of the present application needs to at least solve the heat dissipation and heat diffusion problems of the computing power core unit under the 2.5D / 3D stacked package during operation. Among them, the computing power core unit can refer to the parallel computing power module, storage and computing integrated module, coarse-grained reconfigurable module (CGRA, Coarse-Grained Reconfigurable Architecture), fine-grained reconfigurable module (i.e. field programmable gate array (FPGA, Field-Programmable Gate Array)) of the general purpose graphics processor (GPGPU, General Propose Graphic Processing Unit), etc., and specifically can refer to PE. PE is the basic unit particle of the GPGPU processing unit algorithm, which is composed of an arithmetic logic unit (ALU, Algorithm and Logic Unit) and a supporting memory access and interconnection mechanism. It can process various algorithms dynamically configured by the mapper in unit time, such as completing the following in one clock cycle. Figure 2 The input data sorting, ALU calculation, and data output are shown. The layout of PE in the chip layout needs to meet the corresponding memory access and interconnection requirements, such as Figure 3 As shown, the PE in the chip is usually set in the form of PEA, which can support Figure 4 In most GPGPUs, the interconnection of PEs is limited to the PEs adjacent to the PE and the PEs upstream and downstream.

[0063] Based on this, in various embodiments of the present application, based on the thermal effect of each PE in the target PEA within a specific time range, the available state of each PE within a future time range when the temperature does not exceed a specific threshold is predicted, and then according to the available state of each PE within the future time range when the temperature does not exceed a specific threshold, the algorithm to be mapped is mapped to the target PEA to execute the algorithm to be mapped through the target PEA. In this way, the number of PEs with too high temperature (i.e., the temperature exceeds a specific threshold) can be reduced in the process of executing the algorithm to be mapped through the target PEA, and the heat diffusion effect of the high-load PEs at full load can be avoided. The collateral influence on the adjacent PEs is avoided, and the actual heat dissipation performance of the chip where the target PEA is located in actual work (especially at full load) is effectively guaranteed, so that the active heat dissipation of the chip can be realized from a software perspective for some specific packaging scenarios (such as 2.5D / 3D superposition of the computing power module (i.e., PE), etc., and the reasonable use of the computing power resources of the chip can be realized on the premise of effectively improving the heat dissipation effect of the chip, so as to improve the overall algorithm throughput of the chip, and improve the overall utilization of the chip, and then provide effective support for the subsequent formation of EDA and / or IDE tools for advanced packaging and hardware and software collaborative design.

[0064] Specifically, an embodiment of the present application provides an information processing method, which is applied to an electronic device (such as a server, etc.), such as Figure 5 As shown, the method includes:

[0065] Step 501: determining first information of a target PEA, wherein the first information represents a thermal effect of each PE in the target PEA within a first time range;

[0066] Step 502: Determine second information of the target PEA based on the first information, the second information comprising a predicted available state of each PE in the target PEA within a second time range when a first condition is satisfied, the first condition indicating that a temperature of the PE is less than or equal to a first threshold;

[0067] Step 503: According to the second information, the algorithm to be mapped is mapped (mapping in English) to the target PEA, so as to execute the algorithm to be mapped through the target PEA.

[0068] Here, it can be understood that the target PEA is set on the chip of the electronic device, and can be specifically set on the control chip of the electronic device; in other words, the information processing method provided in the embodiment of the present application can be specifically implemented by the control chip of the electronic device.

[0069] In actual application, the durations corresponding to the first time range and the second time range may be the same or different. For example, the durations corresponding to the first time range and the second time range may both be one unit of time, such as one clock cycle.

[0070] In actual application, the PE in the target PEA can also be called a computing power module, a computing power unit, a computing unit, a parallel computing unit, or a computing power core unit, etc. The embodiment of the present application does not limit the specific name of the PE as long as its function is realized.

[0071] In actual application, in the process of determining the thermal effect of each PE in the target PEA within the first time range, the electronic device can quantify the thermal effect of each PE based on the gray value.

[0072] Based on this, in one embodiment, the first information for determining the target PEA may include:

[0073] For each PE in the target PEA, in each time unit of at least one time unit within the first time range, a thermal effect of the PE is quantified based on a gray value to obtain a thermal effect gray value corresponding to the PE in each time unit;

[0074] The thermal effect condition of each PE is determined by using the thermal effect grayscale value and driving voltage corresponding to each PE in each time unit to obtain the first information.

[0075] In actual application, the time unit may also be referred to as unit time, etc.; the specific duration of the time unit may be set according to demand, such as a clock cycle.

[0076] In actual application, the electronic device can quantify the thermal effect of each PE in the target PEA based on the gray value based on the algorithm executed by each PE in the first time range.

[0077] Based on this, in one embodiment, the quantification of the thermal effect of PE based on the gray value may include:

[0078] Determine a first weighted value and a second weighted value of the PE, wherein the first weighted value is associated with a type of algorithm executed by the PE, and the second weighted value is associated with a data bit width when the PE executes the algorithm;

[0079] The thermal effect grayscale value of the PE is determined using the first weighted value and the second weighted value of the PE.

[0080] In actual application, the electronic device can obtain the data flow graph (DFG) corresponding to the target PEA within the first time range, and identify the calculation type processed by each node (i.e., PE) in the corresponding DFG in each time unit within the first time range, that is, determine the algorithm type executed by each PE, and identify the data bit width when each PE executes the algorithm; for each PE in the target PEA, determine the first weighted value of the PE using the determined algorithm type executed by the PE, and determine the second weighted value of the PE using the determined data bit width when the PE executes the algorithm, and then use the first weighted value and the second weighted value of the PE to determine the thermal effect grayscale value corresponding to the PE in the time unit.

[0081] In actual application, the specific correlation between the type of algorithm executed by PE and the first weighted value, the specific correlation between the data bit width when PE executes the algorithm and the second weighted value, the specific value range and bit width of the thermal effect grayscale value of PE, and the specific correlation between the first weighted value and the second weighted value of PE and the thermal effect grayscale value of PE can be set according to needs. Exemplarily, the specific correlation between the type of algorithm executed by PE and the first weighted value can be as shown in Table 1. When PE runs a general processing algorithm, the weighting factor of the PE can be marked as A1, that is, the first weighted value of the PE is determined to be A1; when PE runs a general calculation algorithm, the weighting factor of the PE can be marked as A2, that is, the first weighted value of the PE is determined to be A2; when PE runs a complex calculation algorithm, the weighting factor of the PE can be marked as A3, that is, the first weighted value of the PE is determined to be A3. The specific correlation between the data bit width and the second weighted value when the PE executes the algorithm can be shown in Table 2. When the number of valid bits corresponding to the PE is [0:7], the weighting factor of the PE can be marked as B1, that is, the second weighted value of the PE is determined to be B1; when the number of valid bits corresponding to the PE is [8:15], the weighting factor of the PE can be marked as B2, that is, the second weighted value of the PE is determined to be B2; when the number of valid bits corresponding to the PE is [16:], the weighting factor of the PE can be marked as B3, that is, the second weighted value of the PE is determined to be B3. In addition, the specific correlation between the first weighted value and the second weighted value of the PE and the thermal effect grayscale value of the PE can be shown in Table 3. The specific value range of the thermal effect grayscale value of the PE can be set to [0:7], and the thermal effect grayscale value of the PE can be represented by a grayscale value with a bit width of 3 bits.

[0082] Computation type (i.e. the type of algorithm executed by the PE) Weighting factor (i.e. first weighting value) General processing, such as delay or shift, etc. A1 General calculations, such as addition, subtraction, or fixed-point algorithms, etc. A2 Complex calculations, such as multiplication or floating-point algorithms A3

[0083] Table 1

[0084] The number of effective bits (i.e. the data bit width when PE executes the algorithm) Weighting factor (i.e. second weighting value) [0:7] B1 [8:15] B2 [16:] B3

[0085] Table 2

[0086] A1 A2 A3 B1 0 1 2 B2 2 4 6 B3 3 5 7

[0087] Table 3

[0088] In actual application, after determining the thermal effect grayscale value corresponding to each time unit of each PE in the target PEA within the first time range, the electronic device can weight the thermal effect grayscale value based on the driving voltage corresponding to the PE in the time unit, and accumulate the weighted thermal effect grayscale values ​​within the first time range to obtain the thermal effect status of the PE within the first time range.

[0089] Based on this, in one embodiment, determining the thermal effect of each PE using the thermal effect grayscale value and driving voltage corresponding to each PE in each time unit may include:

[0090] For each PE in the target PEA, within the first time range, the product of the thermal effect grayscale value corresponding to the PE in each time unit and the third weighted value is accumulated to obtain the thermal effect cumulative value of the PE, the third weighted value is associated with the driving voltage of the PE, and the thermal effect cumulative value can reflect the thermal effect situation of the PE, and the first information includes the thermal effect cumulative value of each PE in the target PEA within the first time range.

[0091] Among them, in actual application, the third weighted value can be determined by using the first function and the driving voltage of PE; the first function can be understood as a mathematical nonlinear mapping, which is used to map the driving voltage of PE to a weighted value (i.e., the third weighted value). Generally, the higher the driving voltage of PE, the more heat is dissipated when the transistor inside the PE is working, and the higher the third weighted value. In addition, it should be noted that the driving voltage of each PE in the embodiment of the present application can be dynamically configured / adjusted, and a higher driving voltage will bring a lower transistor transmission delay, which can be understood as the transistor flipping in the PE is faster, and the PE can carry more complex algorithms per unit time; a lower driving voltage corresponds to a higher transistor transmission delay, and the transistor flipping speed in the PE slows down, and the PE will not be able to complete complex algorithms (such as high-precision multiplication, etc.) within a unit time.

[0092] In actual application, in the process of determining the second information of the target PEA based on the first information, the electronic device can first predict the maximum driving voltage that each PE in the target PEA can withstand within the second time range based on the first information, and then combine the maximum driving voltage that each PE in the target PEA can withstand within the second time range and the occupancy of each PE to predict the available state of each PE in the target PEA within the second time range when the first condition is met.

[0093] Based on this, in one embodiment, determining the second information of the target PEA based on the first information may include:

[0094] Based on the first information, determining third information of the target PEA, wherein the third information includes a maximum driving voltage that each PE in the target PEA can withstand within the second time range;

[0095] The second information is determined based on the third information and the fourth information, wherein the fourth information represents the occupancy status of each PE in the target PEA within the second time range.

[0096] Among them, in actual application, the occupancy status of each PE in the target PEA within the second time range refers to whether each PE is occupied by an algorithm that has not been fully executed within the second time range, and can also be understood as the available status of each PE within the second time range when only considering the algorithm execution angle, without considering whether there is an overheating situation. In addition, the fourth information can be understood as the operating configuration status of the target PEA known by the electronic device itself; in other words, the electronic device can obtain the fourth information locally or obtain (can be understood as determining or generating) the fourth information based on the operating configuration status of the target PEA,

[0097] In one embodiment, the first information may include a thermal effect cumulative value of each PE in the target PEA within the first time range, the thermal effect cumulative value can reflect the thermal effect of the PE, and the thermal effect cumulative value of each PE is obtained by accumulating the product of the thermal effect gray value corresponding to the PE in each time unit within the first time range and the third weighted value, and the third weighted value is determined by using the first function and the driving voltage of the PE; accordingly, the third information of the target PEA determined based on the first information may include:

[0098] For each PE in the target PEA, the maximum driving voltage that the PE can withstand within the second time range is determined by using a second function, the accumulated value of the thermal effect of the PE within the first time range, and a second threshold corresponding to the accumulated value of the thermal effect, wherein the second function is an inverse function of the first function, and the second threshold is associated with the fifth information of the target PEA, and the fifth information indicates the PE in the target PEA that does not meet the first condition within the first time range.

[0099] In actual application, it can be understood that the maximum driving voltage that each PE can withstand corresponds to the fastest clock that the PE can withstand, that is, the high or low driving voltage of the PE corresponds to the speed of the clock, and the speed of the clock can be mapped to the speed of the PE execution algorithm, that is, the speed of the clock can reflect the performance of the PE.

[0100] In actual application, the specific values ​​of the first threshold and the second threshold can be set according to the needs, such as according to the material, packaging, etc. of the chip where the target PEA is located, and the embodiment of the present application does not limit this. In addition, the second threshold is associated with the fifth information of the target PEA, which can be understood as the second threshold being associated with the first threshold. If the actual working temperature of a PE is greater than the first threshold, that is, the PE does not meet the first condition, the normal operation of the transistor inside the PE will be affected, and the accumulated value of the thermal effect of the PE is greater than the second threshold.

[0101] In actual application, after determining the third information and obtaining the fourth information, the electronic device can traverse all PEs of the target PEA based on the third information and the fourth information. When the fourth information is used to determine that a PE is occupied within the second time range, the electronic device can determine that the available state of the PE within the second time range is: the execution of the algorithm is not supported because it is occupied.

[0102] Based on this, in one embodiment, determining the second information based on the third information and the fourth information may include:

[0103] traverse all PEs of the target PEA based on the third information and the fourth information;

[0104] For each PE in the target PEA, when the fourth information is used to determine that the PE is occupied within the second time range, a first identifier associated with the PE is determined, wherein the first identifier indicates that the PE does not support the execution of the algorithm within the second time range because it is occupied, and the second information includes the first identifier associated with the PE.

[0105] In actual application, in the process of traversing all PEs of the target PEA based on the third information and the fourth information, the electronic device can also determine whether the PE is overheated, that is, determine whether the PE meets the first condition; when a PE does not meet the first condition, it means that the PE is overheated, and the electronic device can determine that the available state of the PE within the second time range is: the execution of the algorithm is not supported due to overheating.

[0106] Based on this, in one embodiment, determining the second information based on the third information and the fourth information may include:

[0107] traverse all PEs of the target PEA based on the third information and the fourth information;

[0108] For each PE in the target PEA, when it is determined using the fifth information of the target PEA that the PE does not satisfy the first condition within the first time range, a second identifier associated with the PE is determined, wherein the second identifier indicates that the PE does not support the execution of the algorithm due to overheating within the second time range, the second information includes the second identifier associated with the PE, and the fifth information indicates the PE in the target PEA that does not satisfy the first condition within the first time range.

[0109] In actual application, in the process of traversing all PEs of the target PEA based on the third information and the fourth information, when the third information is used to determine that the maximum driving voltage that a PE can withstand within the second time range is less than the minimum voltage of the PE ALU, the electronic device can determine that the available state of the PE within the second time range is: not supporting the execution of the algorithm due to overheating.

[0110] Based on this, in one embodiment, determining the second information based on the third information and the fourth information may include:

[0111] traverse all PEs of the target PEA based on the third information and the fourth information;

[0112] For each PE in the target PEA, when it is determined by using the third information that the maximum driving voltage that the PE can withstand within the second time range is less than the third threshold, the second identifier associated with the PE is determined, the second information includes the second identifier associated with the PE, and the third threshold represents the lowest voltage provided by the system to the PE within the second time range.

[0113] In actual application, the specific value of the third threshold can be set according to demand, for example, according to the material and packaging of the chip where the target PEA is located, and this embodiment of the present application does not limit this.

[0114] In actual application, a driving voltage threshold (referred to as the fourth threshold in the subsequent description, and the fourth threshold is greater than the third threshold) can be set in advance for the general processing algorithms and general computing algorithms shown in Table 1 above. In the process of traversing all PEs of the target PEA based on the third information and the fourth information, when the third information is used to determine that the maximum driving voltage that a PE can withstand within the second time range is greater than or equal to the third threshold, and less than or equal to the fourth threshold, the electronic device can determine that the available state of the PE within the second time range is: supporting the execution of general processing algorithms and general computing algorithms.

[0115] Based on this, in one embodiment, determining the second information based on the third information and the fourth information may include:

[0116] traverse all PEs of the target PEA based on the third information and the fourth information;

[0117] For each PE in the target PEA, when the third information is used to determine that the maximum driving voltage that the PE can withstand within the second time range is greater than or equal to the third threshold and less than the fourth threshold, the PE-associated third identifier is determined, and the third identifier represents that the PE supports the execution of the first type of algorithm within the second time range, and the second information includes the PE-associated third identifier.

[0118] Among them, in actual application, the first type of algorithm may include the general processing type algorithm and the general calculation type algorithm shown in Table 1 above; the specific value of the fourth threshold value can be set according to needs, such as according to the material, packaging, etc. of the chip where the target PEA is located, and the embodiment of the present application does not limit this.

[0119] In actual application, in the process of traversing all PEs of the target PEA based on the third information and the fourth information, when the third information is used to determine that the maximum driving voltage that a PE can withstand within the second time range is greater than or equal to the fourth threshold, the electronic device can determine that the available state of the PE within the second time range is: supporting the execution of the complex calculation algorithm shown in Table 1 above.

[0120] Based on this, in one embodiment, determining the second information based on the third information and the fourth information may include:

[0121] traverse all PEs of the target PEA based on the third information and the fourth information;

[0122] For each PE in the target PEA, when using the third information to determine that the maximum driving voltage that the PE can withstand within the second time range is greater than or equal to the fourth threshold, determine the PE-associated fourth identifier, the fourth identifier indicates that the PE supports the execution of the second type of algorithm within the second time range, the complexity of the second type of algorithm is higher than the complexity of the first type of algorithm, and the second information includes the PE-associated fourth identifier.

[0123] Among them, in actual application, the second type of algorithm may include the complex calculation type algorithm shown in Table 1 above. In addition, it can be understood that the second information may specifically include an identifier associated with each PE in the target PEA (i.e., the first identifier, the second identifier, the third identifier or the fourth identifier), and the identifier associated with the PE can reflect the available state of the PE when the first condition is met. Here, the specific form of expression of the second information can be set according to demand, such as a binary matrix, etc., and the embodiment of the present application is not limited to this.

[0124] In actual application, after determining the second information, if it can be judged based on the second information that the computing resources that can be provided by the target PEA within the second time range support the execution of the algorithm to be mapped, then the algorithm to be mapped can be directly mapped to the target PEA, and the algorithm to be mapped can be executed through the target PEA within the second time range.

[0125] Based on this, in one embodiment, mapping the algorithm to be mapped to the target PEA according to the second information may include:

[0126] When it is determined according to the second information that the target PEA satisfies the second condition, the algorithm to be mapped is directly mapped to the target PEA so that the algorithm to be mapped is executed by the target PEA within the second time range, and the second condition represents the computing resources that can be provided by the target PEA within the second time range to support the execution of the algorithm to be mapped.

[0127] In actual application, the electronic device may obtain the DFG of the algorithm to be mapped, and map the algorithm to be mapped to the target PEA according to the DFG of the algorithm to be mapped. If the target PEA does not meet the second condition, the electronic device may extend the time for the target PEA to execute the algorithm to be mapped.

[0128] Based on this, in one embodiment, mapping the algorithm to be mapped to the target PEA according to the second information may include:

[0129] When it is determined according to the second information that the target PEA does not satisfy the second condition, the algorithm to be mapped is mapped to the target PEA using a first strategy so as to execute the algorithm to be mapped through the target PEA within a third time range, and the third time range is greater than the second time range.

[0130] Among them, in actual application, the first strategy may include: making each PE in the target PEA convert from executing the algorithm to be mapped in parallel to executing the algorithm to be mapped in serial, so as to extend the time for the target PEA to execute the algorithm to be mapped to the third time range. Exemplarily, when the second time range includes a unit time (such as a clock cycle), the electronic device can map the algorithm to be mapped to the next-level system clock PE of the target PEA, occupying two or more unit times of the PE, that is, the third time range can include at least two unit times; the next-level system clock of the target PEA can also be understood as the next iteration cycle of the target PEA, that is, the algorithm to be mapped can be executed after all PEs in the target PEA have executed the algorithm to be executed, the algorithm mapping is uniformly updated, and the calculation of the next round of mapping is started.

[0131] In actual application, when the target PEA does not meet the second condition, the current algorithm (i.e., the algorithm to be mapped) can also be suspended to the stack, and the second priority algorithm in the mapping queue (i.e., another algorithm to be mapped) can be activated from the stack and mapped to the target PEA when the target PEA meets the second condition later.

[0132] Based on this, in one embodiment, mapping the algorithm to be mapped to the target PEA according to the second information may include:

[0133] When it is determined based on the second information that the target PEA does not satisfy the second condition, and the target PEA satisfies the third condition, another algorithm to be mapped whose priority is lower than the algorithm to be mapped is mapped to the target PEA, so that the other algorithm to be mapped is executed by the target PEA within the second time range, and the third condition represents the computing resources that can be provided by the target PEA within the second time range to support the execution of the other algorithm to be mapped.

[0134] The information processing method provided in the embodiment of the present application determines the first information of the target PEA, the first information characterizing the thermal effect of each PE in the target PEA within a first time range; based on the first information, determines the second information of the target PEA, the second information includes the predicted available state of each PE in the target PEA within the second time range when the first condition is met, the first condition characterizing that the temperature of the PE is less than or equal to the first threshold value; according to the second information, maps the algorithm to be mapped to the target PEA to execute the algorithm to be mapped through the target PEA. The scheme provided in the embodiment of the present application predicts the available state of each PE in a future time range (i.e., the second time range) when the temperature does not exceed a specific threshold value (i.e., the first threshold value) based on the thermal effect of each PE in the target PEA within a specific time range (i.e., the first time range), and then maps the algorithm to be mapped to the target PEA to execute the algorithm to be mapped through the target PEA based on the available state of each PE in the future time range when the temperature does not exceed the specific threshold value. In this way, the number of PEs with too high temperature (i.e., the temperature exceeds the specific threshold value, i.e., the temperature is greater than the first threshold value) can be reduced in the process of executing the algorithm to be mapped through the target PEA, avoiding high The heat diffusion effect generated by the load-running PE at full load has a collateral impact on the adjacent PE, effectively ensuring the actual heat dissipation performance of the chip where the target PEA is located in actual work (especially under full load), so that for some specific packaging scenarios (such as 2.5D / 3D superposition of PE, etc.), active heat dissipation of the chip can be achieved from a software perspective, and the rational use of the chip's computing power resources can be achieved while effectively improving the chip's heat dissipation effect, thereby improving the chip's overall algorithm throughput and the chip's overall utilization rate, and thus providing effective support for the subsequent formation of EDA and / or IDE tools for advanced packaging and hardware and software collaborative design.

[0135] The present application is described in further detail below in conjunction with application examples.

[0136] Based on the characteristics of HBM packaging, this application example designs an active heat dissipation optimization mechanism including modeling, mapping optimization, configuration optimization and other steps, which can actively optimize heat dissipation according to the characteristics of HBM packaging. Figure 6As shown, the HBM-based GPGPU temperature control optimization architecture in this application example may include a PE thermal accumulation statistics module, a PE drive voltage statistics response module, a parallel resource occupancy assessment module (also referred to as an algorithm parallel resource occupancy assessment module or mapper 1) and an algorithm mapping logic optimization module (also referred to as a mapper 2); in addition, the architecture may also selectively include an on-chip temperature sensing module, which may send an overheating alarm signal (i.e., the fifth information) in the form of a high level when the PE is overheated (i.e., the temperature of the PE is greater than the above-mentioned first threshold).

[0137] The PE thermal accumulation statistics module is used to perform weighted accumulation of the algorithm types and running clocks that have been cumulatively executed by each PE in the PEA (i.e., the target PEA) in the previous several unit times (i.e., the first time range), and output the thermal effect of each PE in the current PEA (i.e., the target PEA) (i.e., the first information) to the PE driving voltage statistics response module. Considering the simplicity and ease of implementation of the statistical algorithm, this application example quantifies the thermal effect of the PE based on the gray value, and the quantized value range is between [0:7], and is represented by a gray value with a 3-bit width.

[0138] Specifically, if Figure 7As shown, the PE thermal accumulation statistics module can first obtain the historical DFG, identify the calculation type processed by each node (ie, PE) in the historical DFG, and determine whether the calculation type processed by each PE is a general processing algorithm such as delay or shift, or a general calculation algorithm such as addition, subtraction, or fixed-point algorithm, or a complex calculation algorithm such as multiplication or floating-point algorithm. As shown in Table 1 above, when the PE runs a general processing algorithm, the PE thermal accumulation statistics module can mark the weighting factor of the PE (ie, the first weighted value) as A1; when the PE runs a general calculation algorithm, the PE thermal accumulation statistics module can mark the weighting factor of the PE (ie, the first weighted value) as A2; when the PE runs a complex calculation algorithm, the PE thermal accumulation statistics module can mark the weighting factor of the PE (ie, the first weighted value) as A3. Afterwards, the PE thermal accumulation statistics module can identify the data bit width processed by general computing nodes (i.e., PE) and complex computing nodes. Since the number of transistors required by PE when processing large bit width (the transistor forms a PN junction for charging and discharging due to participation in calculation) is significantly higher than that in the small bit width scenario, as shown in Table 2 above, when the effective number of bits is [0:7], the PE thermal accumulation statistics module can mark the weighting factor of the PE (i.e., the above-mentioned second weighted value) as B1; when the effective number of bits is [8:15], the PE thermal accumulation statistics module can mark the weighting factor of the PE (i.e., the above-mentioned second weighted value) as B2; when the effective number of bits is [16:], the PE thermal accumulation statistics module can mark the weighting factor of the PE (i.e., the above-mentioned second weighted value) as B3. Afterwards, the PE thermal accumulation statistics module can determine the thermal effect grayscale value of each PE based on the above Table 3 and the two types of weighted values ​​determined, and thermally mark each node (i.e., PE) of the DFG, i.e., mark the thermal effect grayscale value, and obtain a thermally marked DFG (which can be expressed as H_DFG). Finally, the PE thermal accumulation statistics module can perform thermal environment analysis on each PE, and calculate the sum of the thermal effects of each PE within a certain unit time (i.e., the above first time range), i.e., use the following formula to weight the thermal effect grayscale value of the algorithm executed by a PE in each unit time and the weighted value of the driving voltage of the PE (such as the driving voltage of the ALU):

[0139] ∑ thermal effect|PE=algorithm thermal effect gray value| t-1 ×ω(VDD_ALU| t-1 )+algorithm thermal effect gray value | t-2 ×ω(VDD_ALU| t-2 )+algorithm thermal effect gray value | t-3 ×ω(VDD_ALU| t-3 ) (1)

[0140] Among them, ∑ thermal effect |PE represents the cumulative value of thermal effect of a PE; algorithm thermal effect gray value | t-1 Indicates the thermal effect grayscale value of the PE in unit time t-1 (i.e. one time unit mentioned above); VDD_ALU| t-1 represents the ALU driving voltage of the PE within the unit time t-1; ω represents the above-mentioned first function, which is used to map the ALU driving voltage of the PE to a weighted value (ie, the third weighted value); algorithm thermal effect gray value | t-2 Indicates the grayscale value of the thermal effect of the PE within the unit time t-2; VDD_ALU| t-2 Indicates the ALU driving voltage of the PE in unit time t-2; algorithm thermal effect gray value | t-3 Indicates the grayscale value of the thermal effect of the PE within unit time t-3; VDD_ALU| t-3 It represents the ALU driving voltage of the PE within the unit time t-3; it can be understood that the above-mentioned first time range includes the unit time t-1, the unit time t-2 and the unit time t-3.

[0141] In this application example, the PE heat accumulation statistics module can output the heat effect of each PE in the current PEA (i.e., the target PEA) calculated by the above formula (1) (i.e., the above first information) to the PE driving voltage statistics response module, that is, the input data of the PE driving voltage statistics response module can include the heat effect accumulation value of each PE in the current PEA output by the PE heat accumulation statistics module. In addition, the input data of the PE driving voltage statistics response module can also selectively include the overheating alarm signal (i.e., the above fifth information) issued in the form of a high level by the on-chip temperature sensing module when the PE is overheated (i.e., the temperature of the PE is greater than the above first threshold). The PE driving voltage statistics response module is used to integrate the outputs of the PE thermal accumulation statistics module and the on-chip temperature sensing module, and estimate the fastest clock that the PE can withstand within the next unit time (that is, the above-mentioned second time range) according to the thermal effect accumulation model corresponding to the above formula (1), combined with the thermal effect failure threshold value (that is, the above-mentioned second threshold value) determined by the current chip material and packaging method, and according to the algorithm with the largest transistor flip rate (the transistor flip rate can reflect the complexity of the algorithm, and the thermal effect gray value corresponding to the algorithm with the largest transistor flip rate in this application example is 7), that is, the following formula is used to estimate the maximum ALU driving voltage that the PE can withstand within the next unit time:

[0142] VDD_ALU| t =f(thermal effect value| Threshold -∑ Thermal Effect|PE) (2)

[0143] Where, VDD_ALU|t represents the maximum ALU driving voltage that a PE can withstand within a unit time t (i.e., the second time range mentioned above); f represents the second function mentioned above, which is the inverse function of ω; thermal effect value | Threshold represents the thermal effect failure threshold value (i.e., the second threshold value) determined by the current chip material and packaging method; ∑ thermal effect | PE is the cumulative value of the thermal effect of PE at unit time t-1, unit time t-2, and unit time t-3 calculated using the above formula (1).

[0144] It should be noted that the driving voltage of each PE in this application example can be dynamically configured / adjusted. A higher driving voltage will result in a lower transistor transmission delay, which can be understood as faster transistor flipping in the PE, and the PE can carry more complex algorithms per unit time; a lower driving voltage corresponds to a higher transistor transmission delay, at which time the transistor flipping speed in the PE slows down, and the PE will be unable to complete complex algorithms (such as high-precision multiplication, etc.) per unit time.

[0145] In this application example, the PE driving voltage statistics response module can output the maximum ALU driving voltage (i.e., the third information) that each PE in the current PEA (i.e., the target PEA) can withstand within the next unit time (i.e., the second time range) calculated using the above formula (2) to the parallel resource occupancy evaluation module. The parallel resource occupancy evaluation module is used to combine the data input by the PE driving voltage statistics response module (i.e., the third information) and the PEA operation configuration status (i.e., the fourth information) mastered by the mapper 1 itself, that is, to integrate the available status (i.e., the occupancy status, i.e., the fourth information) of each PE in the PEA and the maximum ALU driving voltage that can be tolerated (i.e., the third information), and output the following to the algorithm mapping logic optimization module: Figure 8 The resource occupancy evaluation diagram represented by a binary data matrix (ie, the second information mentioned above) is shown,

[0146] Specifically, the parallel resource occupancy evaluation module may traverse all PEs in the current PEA (i.e., the target PEA) and perform resource occupancy analysis according to the following steps:

[0147] Step a: If a PE will still be occupied by an unfinished algorithm within the next unit time (i.e., the second time range), the PE can be marked as "Unavailable (Using / Took)" (i.e., the first mark), and jump to the next PE for resource occupancy analysis;

[0148] Step b: If a PE is marked with an overheat alarm signal output by the on-chip temperature sensing module (the signal is fed back to the parallel resource occupancy evaluation module via the PE driving voltage statistical response module), the PE can be marked as "Unavailable (overheat) (which can be expressed as Unavailable (hot_over / OVER HOT))" (i.e., the second mark mentioned above), and jump to the next PE for resource occupancy analysis;

[0149] Step c: If the expected maximum ALU driving voltage that a PE can withstand is less than the minimum ALU voltage provided by the system to the PE (i.e., the third threshold), it can be determined that the PE is also overheated and cannot perform computing operations in the next unit time, that is, the PE can also be marked as "Unavailable (overheated) (which can be expressed as Unavailable (hot_over / OVERHOT))" (i.e., the second mark), and jump to the next PE for resource occupancy analysis;

[0150] Step d: If the expected maximum ALU driving voltage that a PE can withstand is greater than or equal to the lowest ALU voltage provided by the system to the PE (i.e., the third threshold value mentioned above), and is less than or equal to the execution requirement of the complexity algorithm of the gray value of 5 per unit time (i.e., the fourth threshold value mentioned above), then it can be determined that the PE can be used for the mapping of the general processing class and general computing class algorithms shown in Table 1 for the next unit time, and the PE can be marked as "fixed algorithm (i.e., the general processing class algorithm and the general computing class algorithm shown in Table 1 above) available / slow clock available (which can be expressed as Available_to_Fixed / slow_clk_available in English)" (i.e., the third identifier mentioned above), and jump to the next PE for resource occupancy analysis;

[0151] Step e: If the expected maximum ALU driving voltage that a PE can withstand is greater than the execution requirement of the complexity algorithm for achieving a grayscale value of 5 per unit time (i.e., the fourth threshold),

[0152] Then it can be determined that the PE can be used for the mapping of the complex computing algorithm shown in Table 1 for the next unit time, and the PE can be marked as "floating point algorithm (i.e., the complex computing algorithm shown in Table 1) available / fast clock available (which can be expressed as Available_to_Float / fast_clk_available in English)" (i.e., the fourth identifier above), and jump to the next PE for resource occupancy analysis;

[0153] Step f: After the last PE is analyzed, the parallel resource occupancy evaluation module can output the following to the algorithm mapping logic optimization module: Figure 8The resource occupancy assessment graph (ie, the above-mentioned second information) is represented by a binary data matrix.

[0154] In this application example, the input data of the algorithm mapping logic optimization module includes the resource occupancy evaluation graph (i.e., the second information) output by the parallel resource occupancy evaluation module in the form of a binary data matrix, and the algorithm mapping logic optimization module can evaluate the best mapping solution based on the resource occupancy evaluation graph. Specifically, Fig. 9 As shown, if the resources shown in the current resource occupancy evaluation diagram (i.e., the computing resources that the target PEA can provide within the second time range) meet all the resources required for parallel calculation of the algorithm to be mapped in the same unit time (i.e., the above target PEA meets the second condition), it can be directly mapped according to the characteristics of the algorithm without optimization; if the resources shown in the current resource occupancy evaluation diagram cannot meet all the resources required for parallel calculation of the algorithm to be mapped in the same unit time (i.e., the above target PEA does not meet the second condition), it can be mapped according to the following two optimization compromise schemes (the order of these two schemes can reflect the priority, i.e., the priority of scheme 1 is higher than the priority of scheme 2):

[0155] Solution 1, such as Fig. 9 As shown, the algorithm to be mapped is mapped to the next-level system clock PE, occupying at least two unit times of the PE (i.e., the third time range mentioned above), and converting the parallel processing into serial processing;

[0156] Solution 2: suspend the current algorithm to the stack, map the next priority algorithm in the queue, and immediately activate the suspended algorithm from the stack after the resources meet the computing power requirements of the suspended algorithm.

[0157] The solution provided by this application example proposes an active heat dissipation method based on resource scheduling and dynamic configuration. Through the thermal load mapping model (i.e., the above formula (1)) and dynamic resource scheduling, the rational use of computing resources can be achieved, thereby further improving the overall algorithm throughput of the chip and improving the overall utilization of the chip; further, it can provide effective support for the subsequent formation of EDA and / or IDE tools for advanced packaging and hardware-software collaborative design. In addition, the active heat dissipation optimization mechanism of "modeling, mapping optimization, and configuration optimization" provided by this application example based on the characteristics of the HBM packaging form has strong operability, and can avoid the inherent mechanism limitations of the original passive heat dissipation by combining active heat dissipation methods with hardware and software that adapt to the characteristics of the thermal environment of the architecture.

[0158] In order to implement the method of the embodiment of the present application, the embodiment of the present application also provides an information processing device, such as Fig.10 As shown, the device comprises:

[0159] A first processing unit 1001 is used to determine first information of a target PEA, where the first information represents a thermal effect of each PE in the target PEA within a first time range;

[0160] A second processing unit 1002 is configured to determine second information of the target PEA based on the first information, wherein the second information includes a predicted available state of each PE in the target PEA within a second time range when a first condition is satisfied, wherein the first condition indicates that a temperature of the PE is less than or equal to a first threshold;

[0161] The third processing unit 1003 is configured to map the algorithm to be mapped to the target PEA according to the second information, so as to execute the algorithm to be mapped through the target PEA.

[0162] In one embodiment, the first processing unit 1001 is specifically configured to:

[0163] For each PE in the target PEA, in each time unit of at least one time unit within the first time range, a thermal effect of the PE is quantified based on a gray value to obtain a thermal effect gray value corresponding to the PE in each time unit;

[0164] The thermal effect condition of each PE is determined by using the thermal effect grayscale value and driving voltage corresponding to each PE in each time unit to obtain the first information.

[0165] In one embodiment, the first processing unit 1001 is further configured to:

[0166] Determine a first weighted value and a second weighted value of the PE, wherein the first weighted value is associated with a type of algorithm executed by the PE, and the second weighted value is associated with a data bit width when the PE executes the algorithm;

[0167] The thermal effect grayscale value of the PE is determined using the first weighted value and the second weighted value of the PE.

[0168] In one embodiment, the first processing unit 1001 is further used to accumulate, for each PE in the target PEA, the product of the thermal effect grayscale value corresponding to the PE in each time unit and the third weighted value within the first time range to obtain a thermal effect cumulative value of the PE, wherein the third weighted value is associated with the driving voltage of the PE, and the thermal effect cumulative value can reflect the thermal effect of the PE, and the first information includes the thermal effect cumulative value of each PE in the target PEA within the first time range.

[0169] In one embodiment, the second processing unit 1002 is specifically configured to:

[0170] Based on the first information, determining third information of the target PEA, wherein the third information includes a maximum driving voltage that each PE in the target PEA can withstand within the second time range;

[0171] The second information is determined based on the third information and the fourth information, wherein the fourth information represents the occupancy status of each PE in the target PEA within the second time range.

[0172] In one embodiment, the first information includes a thermal effect accumulation value of each PE in the target PEA within the first time range, the thermal effect accumulation value can reflect the thermal effect of the PE, and the thermal effect accumulation value of each PE is obtained by accumulating the product of the thermal effect gray value corresponding to the PE in each time unit within the first time range and a third weighted value, and the third weighted value is determined by using the first function and the driving voltage of the PE;

[0173] Correspondingly, the second processing unit 1002 is also used to determine, for each PE in the target PEA, the maximum driving voltage that the PE can withstand within the second time range by using a second function, the accumulated value of the thermal effect of the PE within the first time range, and a second threshold corresponding to the accumulated value of the thermal effect, wherein the second function is an inverse function of the first function, and the second threshold is associated with the fifth information of the target PEA, and the fifth information indicates the PE in the target PEA that does not meet the first condition within the first time range.

[0174] In one embodiment, the second processing unit 1002 is further configured to:

[0175] For each PE in the target PEA, when it is determined by using the fourth information that the PE is occupied within the second time range, determining a first identifier associated with the PE, where the first identifier indicates that the PE does not support execution of the algorithm within the second time range because it is occupied; or,

[0176] In the case where it is determined by using the fifth information of the target PEA that the PE does not satisfy the first condition within the first time range, determining that the PE is associated with a second identifier, the second identifier indicating that the PE does not support the execution of the algorithm due to overheating within the second time range, and the fifth information indicates the PE in the target PEA that does not satisfy the first condition within the first time range; or

[0177] When it is determined by using the third information that the maximum driving voltage that the PE can withstand within the second time range is less than a third threshold, determining that the PE is associated with the second identifier, and the third threshold represents the lowest voltage provided by the system to the PE within the second time range; or

[0178] When it is determined by using the third information that the maximum driving voltage that the PE can withstand within the second time range is greater than or equal to the third threshold and less than the fourth threshold, determine that the PE is associated with a third identifier, where the third identifier indicates that the PE supports the execution of the first type of algorithm within the second time range; or,

[0179] In the case where it is determined by using the third information that the maximum driving voltage that the PE can withstand within the second time range is greater than or equal to the fourth threshold, a fourth identifier associated with the PE is determined, and the fourth identifier indicates that the PE supports the execution of a second type of algorithm within the second time range, and the complexity of the second type of algorithm is higher than the complexity of the first type of algorithm; wherein,

[0180] The second information includes an identifier associated with each PE in the target PEA, and the identifier associated with the PE can reflect the available state of the PE when the first condition is met.

[0181] In one embodiment, the third processing unit 1003 is specifically configured to:

[0182] When it is determined according to the second information that the target PEA satisfies a second condition, directly mapping the algorithm to be mapped to the target PEA so as to execute the algorithm to be mapped by the target PEA within the second time range, wherein the second condition indicates that computing resources that can be provided by the target PEA within the second time range support the execution of the algorithm to be mapped; or

[0183] In a case where it is determined according to the second information that the target PEA does not satisfy the second condition, mapping the algorithm to be mapped to the target PEA using a first strategy, so as to execute the algorithm to be mapped through the target PEA within a third time range, where the third time range is greater than the second time range; or

[0184] When it is determined based on the second information that the target PEA does not satisfy the second condition, and the target PEA satisfies the third condition, another algorithm to be mapped whose priority is lower than the algorithm to be mapped is mapped to the target PEA, so that the other algorithm to be mapped is executed by the target PEA within the second time range, and the third condition represents the computing resources that can be provided by the target PEA within the second time range to support the execution of the other algorithm to be mapped.

[0185] Among them, the function of the first processing unit 1001 is equivalent to the function of the PE thermal accumulation statistics module in the above application example; the function of the second processing unit 1002 is equivalent to the function of the PE driving voltage statistics response module and the parallel resource occupancy evaluation module in the above application example; the function of the third processing unit 1003 is equivalent to the function of the algorithm mapping logic optimization module in the above application example.

[0186] In actual application, the first processing unit 1001, the second processing unit 1002 and the third processing unit 1003 can be implemented by a processor in an information processing device.

[0187] It should be noted that: when the information processing device provided in the above embodiment performs information processing, only the division of the above program modules is used as an example. In actual application, the above processing can be assigned to different program modules as needed, that is, the internal structure of the device is divided into different program modules (such as the PE thermal accumulation statistics module, PE drive voltage statistics response module, parallel resource occupancy evaluation module and algorithm mapping logic optimization module in the above application example) to complete all or part of the processing described above. In addition, the information processing device provided in the above embodiment and the information processing method embodiment belong to the same concept, and the specific implementation process is detailed in the method embodiment, which will not be repeated here.

[0188] Based on the hardware implementation of the above program modules, and in order to implement the method of the embodiment of the present application, the embodiment of the present application also provides an electronic device, such as Fig.11 As shown, the electronic device 1100 includes:

[0189] Communication interface 1101, capable of exchanging information with other electronic devices;

[0190] A processor 1102, connected to the communication interface 1101 to implement information interaction with other electronic devices, and used to execute the method provided by one or more of the above technical solutions when running a computer program;

[0191] The memory 1103 stores computer programs that can be executed on the processor 1102 .

[0192] Specifically, the processor 1102 is configured to:

[0193] Determine first information of a target PEA, wherein the first information represents a thermal effect of each PE in the target PEA within a first time range;

[0194] Based on the first information, determine second information of the target PEA, the second information comprising a predicted available state of each PE in the target PEA within a second time range when a first condition is satisfied, the first condition indicating that a temperature of the PE is less than or equal to a first threshold;

[0195] According to the second information, the algorithm to be mapped is mapped to the target PEA, so that the algorithm to be mapped is executed by the target PEA.

[0196] In one embodiment, the processor 1102 is further configured to:

[0197] For each PE in the target PEA, in each time unit of at least one time unit within the first time range, the thermal effect of the PE is quantified based on the gray value to obtain the thermal effect gray value corresponding to the PE in each time unit;

[0198] The thermal effect condition of each PE is determined by using the thermal effect grayscale value and driving voltage corresponding to each PE in each time unit to obtain the first information.

[0199] In one embodiment, the processor 1102 is further configured to:

[0200] Determine a first weighted value and a second weighted value of the PE, wherein the first weighted value is associated with a type of algorithm executed by the PE, and the second weighted value is associated with a data bit width when the PE executes the algorithm;

[0201] The thermal effect grayscale value of the PE is determined using the first weighted value and the second weighted value of the PE.

[0202] In one embodiment, the processor 1102 is further used to accumulate, for each PE in the target PEA, the product of the thermal effect grayscale value corresponding to the PE in each time unit and the third weighted value within the first time range to obtain a thermal effect cumulative value of the PE, wherein the third weighted value is associated with the driving voltage of the PE, and the thermal effect cumulative value can reflect the thermal effect status of the PE, and the first information includes the thermal effect cumulative value of each PE in the target PEA within the first time range.

[0203] In one embodiment, the processor 1102 is further configured to:

[0204] Based on the first information, determining third information of the target PEA, wherein the third information includes a maximum driving voltage that each PE in the target PEA can withstand within the second time range;

[0205] The second information is determined based on the third information and the fourth information, wherein the fourth information represents the occupancy status of each PE in the target PEA within the second time range.

[0206] In one embodiment, the first information includes a thermal effect accumulation value of each PE in the target PEA within the first time range, the thermal effect accumulation value can reflect the thermal effect of the PE, and the thermal effect accumulation value of each PE is obtained by accumulating the product of the thermal effect gray value corresponding to the PE in each time unit within the first time range and a third weighted value, and the third weighted value is determined by using the first function and the driving voltage of the PE;

[0207] Correspondingly, the processor 1102 is also used to determine, for each PE in the target PEA, the maximum driving voltage that the PE can withstand within the second time range by using a second function, the accumulated value of the thermal effect of the PE within the first time range, and a second threshold corresponding to the accumulated value of the thermal effect, wherein the second function is an inverse function of the first function, and the second threshold is associated with the fifth information of the target PEA, and the fifth information indicates the PE in the target PEA that does not meet the first condition within the first time range.

[0208] In one embodiment, the processor 1102 is further configured to:

[0209] For each PE in the target PEA, when it is determined by using the fourth information that the PE is occupied within the second time range, determining a first identifier associated with the PE, where the first identifier indicates that the PE does not support execution of the algorithm within the second time range because it is occupied; or,

[0210] In the case where it is determined by using the fifth information of the target PEA that the PE does not satisfy the first condition within the first time range, determining that the PE is associated with a second identifier, the second identifier indicating that the PE does not support the execution of the algorithm due to overheating within the second time range, and the fifth information indicates the PE in the target PEA that does not satisfy the first condition within the first time range; or

[0211] When it is determined by using the third information that the maximum driving voltage that the PE can withstand within the second time range is less than a third threshold, determining that the PE is associated with the second identifier, and the third threshold represents the lowest voltage provided by the system to the PE within the second time range; or

[0212] When it is determined by using the third information that the maximum driving voltage that the PE can withstand within the second time range is greater than or equal to the third threshold and less than the fourth threshold, determine that the PE is associated with a third identifier, where the third identifier indicates that the PE supports the execution of the first type of algorithm within the second time range; or,

[0213] In the case where it is determined by using the third information that the maximum driving voltage that the PE can withstand within the second time range is greater than or equal to the fourth threshold, a fourth identifier associated with the PE is determined, and the fourth identifier indicates that the PE supports the execution of a second type of algorithm within the second time range, and the complexity of the second type of algorithm is higher than the complexity of the first type of algorithm; wherein,

[0214] The second information includes an identifier associated with each PE in the target PEA, and the identifier associated with the PE can reflect the available state of the PE when the first condition is met.

[0215] In one embodiment, the processor 1102 is further configured to:

[0216] When it is determined according to the second information that the target PEA satisfies a second condition, directly mapping the algorithm to be mapped to the target PEA so as to execute the algorithm to be mapped by the target PEA within the second time range, wherein the second condition indicates that computing resources that can be provided by the target PEA within the second time range support the execution of the algorithm to be mapped; or

[0217] In a case where it is determined according to the second information that the target PEA does not satisfy the second condition, mapping the algorithm to be mapped to the target PEA using a first strategy, so as to execute the algorithm to be mapped through the target PEA within a third time range, where the third time range is greater than the second time range; or

[0218] When it is determined based on the second information that the target PEA does not satisfy the second condition, and the target PEA satisfies the third condition, another algorithm to be mapped whose priority is lower than the algorithm to be mapped is mapped to the target PEA, so that the other algorithm to be mapped is executed by the target PEA within the second time range, and the third condition represents the computing resources that can be provided by the target PEA within the second time range to support the execution of the other algorithm to be mapped.

[0219] It should be noted that the specific processing process of the processor 1102 can be understood by referring to the above method, which will not be repeated here.

[0220] Of course, in actual application, the various components in the electronic device 1100 are coupled together through the bus system 1104. It can be understood that the bus system 1104 is used to realize the connection and communication between these components. In addition to the data bus, the bus system 1104 also includes a power bus, a control bus, and a status signal bus. However, for the sake of clarity, Fig.11 Various buses are labeled as bus system 1104 .

[0221] The memory 1103 in the embodiment of the present application is used to store various types of data to support the operation of the electronic device 1100. Examples of such data include: any computer program used to operate on the electronic device 1100.

[0222] The method disclosed in the above embodiment of the present application can be applied to the processor 1102, or implemented by the processor 1102. The processor 1102 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by an integrated logic circuit of the hardware in the processor 1102 or an instruction in the form of software. The above processor 1102 may be a general-purpose processor, a digital signal processor (DSP, Digital Signal Processor), or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. The processor 1102 can implement or execute the various methods, steps and logic block diagrams disclosed in the embodiments of the present application. The general-purpose processor may be a microprocessor or any conventional processor, etc. In combination with the steps of the method disclosed in the embodiment of the present application, it can be directly embodied as a hardware decoding processor to execute, or it can be executed by a combination of hardware and software modules in the decoding processor. The software module may be located in a storage medium, which is located in the memory 1103, and the processor 1102 reads the information in the memory 1103, and completes the steps of the above method in combination with its hardware.

[0223] In an exemplary embodiment, the electronic device 1100 may be implemented by one or more application specific integrated circuits (ASIC), DSP, programmable logic device (PLD), complex programmable logic device (CPLD), FPGA, general purpose processor, controller, microcontroller (MCU), microprocessor, or other electronic components to execute the aforementioned method.

[0224] It can be understood that the memory 1103 of the embodiment of the present application can be a volatile memory or a non-volatile memory, and can also include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a magnetic random access memory (FRAM), a ferromagnetic random access memory, a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM); the magnetic surface memory can be a disk memory or a tape memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static random access memory (SRAM), synchronous static random access memory (SSRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM, SyncLink Dynamic Random Access Memory), and direct RAMbus random access memory (DRRAM, Direct Rambus Random Access Memory).The memory described in the embodiments of the present application is intended to include, but is not limited to, these and any other suitable types of memory.

[0225] In an exemplary embodiment, the present application also provides a storage medium, namely a computer storage medium, specifically a computer-readable storage medium, for example, a memory 1103 storing a computer program, and the computer program can be executed by a processor 1102 of an electronic device 1100 to complete the steps of the aforementioned method. The computer-readable storage medium can be a memory such as FRAM, ROM, PROM, EPROM, EEPROM, Flash Memory, magnetic surface storage, optical disk, or CD-ROM.

[0226] It should be noted that: "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0227] In addition, the technical solutions described in the embodiments of the present application can be combined arbitrarily without conflict.

[0228] The above description is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application.

Claims

1. An information processing method, characterized in that: include: Determine first information of a target processing unit array PEA, wherein the first information represents a thermal effect of each processing unit PE in the target PEA within a first time range; Based on the first information, determine second information of the target PEA, the second information comprising a predicted available state of each PE in the target PEA within a second time range when a first condition is satisfied, the first condition indicating that a temperature of the PE is less than or equal to a first threshold; According to the second information, the algorithm to be mapped is mapped to the target PEA, so that the algorithm to be mapped is executed by the target PEA.

2. The method according to claim 1, characterized in that The first information for determining the target PEA includes: For each PE in the target PEA, in each time unit of at least one time unit within the first time range, the thermal effect of the PE is quantified based on the gray value to obtain the thermal effect gray value corresponding to the PE in each time unit; The thermal effect condition of each PE is determined by using the thermal effect grayscale value and driving voltage corresponding to each PE in each time unit to obtain the first information.

3. The method according to claim 2, characterized in that The quantification of the thermal effect of PE based on gray value includes: Determine a first weighted value and a second weighted value of the PE, wherein the first weighted value is associated with a type of algorithm executed by the PE, and the second weighted value is associated with a data bit width when the PE executes the algorithm; The thermal effect grayscale value of the PE is determined using the first weighted value and the second weighted value of the PE.

4. The method according to claim 2, characterized in that: The method of determining the thermal effect of each PE by using the thermal effect grayscale value and the driving voltage corresponding to each PE in each time unit includes: For each PE in the target PEA, within the first time range, the product of the thermal effect grayscale value corresponding to the PE in each time unit and the third weighted value is accumulated to obtain the thermal effect cumulative value of the PE, the third weighted value is associated with the driving voltage of the PE, and the thermal effect cumulative value can reflect the thermal effect situation of the PE, and the first information includes the thermal effect cumulative value of each PE in the target PEA within the first time range.

5. The method according to claim 1, characterized in that The determining, based on the first information, second information of the target PEA includes: Based on the first information, determining third information of the target PEA, wherein the third information includes a maximum driving voltage that each PE in the target PEA can withstand within the second time range; The second information is determined based on the third information and the fourth information, wherein the fourth information represents the occupancy status of each PE in the target PEA within the second time range.

6. The method according to claim 5, characterized in that The first information includes a thermal effect cumulative value of each PE in the target PEA within the first time range, the thermal effect cumulative value can reflect the thermal effect of the PE, and the thermal effect cumulative value of each PE is obtained by accumulating the product of the thermal effect gray value corresponding to the PE in each time unit within the first time range and the third weighted value, and the third weighted value is determined by using the first function and the driving voltage of the PE; the third information of the target PEA is determined based on the first information, including: For each PE in the target PEA, the maximum driving voltage that the PE can withstand within the second time range is determined by using a second function, the accumulated value of the thermal effect of the PE within the first time range, and a second threshold corresponding to the accumulated value of the thermal effect, wherein the second function is an inverse function of the first function, and the second threshold is associated with the fifth information of the target PEA, and the fifth information indicates the PE in the target PEA that does not meet the first condition within the first time range.

7. The method according to claim 5, characterized in that The determining the second information based on the third information and the fourth information includes: For each PE in the target PEA, when it is determined by using the fourth information that the PE is occupied within the second time range, determining a first identifier associated with the PE, where the first identifier indicates that the PE does not support execution of the algorithm within the second time range because it is occupied; or, In the case where it is determined by using the fifth information of the target PEA that the PE does not satisfy the first condition within the first time range, determining that the PE is associated with a second identifier, the second identifier indicating that the PE does not support the execution of the algorithm due to overheating within the second time range, and the fifth information indicates the PE in the target PEA that does not satisfy the first condition within the first time range; or When it is determined by using the third information that the maximum driving voltage that the PE can withstand within the second time range is less than a third threshold, determining that the PE is associated with the second identifier, and the third threshold represents the lowest voltage provided by the system to the PE within the second time range; or When it is determined by using the third information that the maximum driving voltage that the PE can withstand within the second time range is greater than or equal to the third threshold and less than the fourth threshold, determine that the PE is associated with a third identifier, where the third identifier indicates that the PE supports the execution of the first type of algorithm within the second time range; or, In the case where it is determined by using the third information that the maximum driving voltage that the PE can withstand within the second time range is greater than or equal to the fourth threshold, a fourth identifier associated with the PE is determined, and the fourth identifier indicates that the PE supports the execution of a second type of algorithm within the second time range, and the complexity of the second type of algorithm is higher than the complexity of the first type of algorithm; wherein, The second information includes an identifier associated with each PE in the target PEA, and the identifier associated with the PE can reflect the available state of the PE when the first condition is met.

8. The method according to claim 1, characterized in that: The mapping of the to-be-mapped algorithm to the target PEA according to the second information includes: When it is determined according to the second information that the target PEA satisfies a second condition, directly mapping the algorithm to be mapped to the target PEA so as to execute the algorithm to be mapped by the target PEA within the second time range, wherein the second condition indicates that computing resources that can be provided by the target PEA within the second time range support the execution of the algorithm to be mapped; or In a case where it is determined according to the second information that the target PEA does not satisfy the second condition, mapping the algorithm to be mapped to the target PEA using a first strategy, so as to execute the algorithm to be mapped through the target PEA within a third time range, wherein the third time range is greater than the second time range; or When it is determined based on the second information that the target PEA does not satisfy the second condition, and the target PEA satisfies the third condition, another algorithm to be mapped whose priority is lower than the algorithm to be mapped is mapped to the target PEA, so that the other algorithm to be mapped is executed by the target PEA within the second time range, and the third condition represents the computing resources that can be provided by the target PEA within the second time range to support the execution of the other algorithm to be mapped.

9. An information processing device, characterized in that: include: A first processing unit, configured to determine first information of a target PEA, wherein the first information represents a thermal effect of each PE in the target PEA within a first time range; a second processing unit, configured to determine second information of the target PEA based on the first information, the second information comprising a predicted available state of each PE in the target PEA within a second time range when a first condition is satisfied, the first condition indicating that a temperature of the PE is less than or equal to a first threshold; The third processing unit is configured to map the algorithm to be mapped to the target PEA according to the second information, so as to execute the algorithm to be mapped through the target PEA.

10. An electronic device, characterized in that: include: A communication interface and a processor; wherein, The processor is configured to: Determine first information of a target PEA, wherein the first information represents a thermal effect of each PE in the target PEA within a first time range; Based on the first information, determine second information of the target PEA, the second information comprising a predicted available state of each PE in the target PEA within a second time range when a first condition is satisfied, the first condition indicating that a temperature of the PE is less than or equal to a first threshold; According to the second information, the algorithm to be mapped is mapped to the target PEA, so that the algorithm to be mapped is executed by the target PEA.

11. An electronic device, characterized in that: include: a processor and a memory for storing a computer program capable of being executed on the processor, Wherein, when the processor is used to run the computer program, it executes the steps of the method described in any one of claims 1 to 8.

12. A storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 8 are implemented.

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