Error source identification method and system
By introducing computer program products into automotive system-on-chip SoC, the problem of poor fault management in complex systems is solved, rapid response and scalable fault management are achieved, and the functional safety of the system is improved.
Patent Information
- Application Number
- CN202411511512.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-10-22
- Filing Date
- 2024-10-28
- Publication Date
- 2025-05-02
AI Technical Summary
In the context of automotive functional safety, it is difficult for the prior art to effectively manage failures, especially in complex systems on chips, which may lead to poor kernel management of failures, which in turn affects the rapid response and security of the system.
By introducing computer program products, including data structures and methods, in the system-on-chip SoC, it is used to retrieve partial information from the FCCU module, custom startup, improve detection of possible input failure combinations, and provide fast response and scalable fault management mechanisms.
Improves the information quality for failures, ensures that the appropriate response is selected among different possibilities, achieves rapid response and scalable fault management, and enhances the functional safety of the system.
Smart Images
Figure CN119917323A_ABST
Abstract
Description
Technical Field
[0001] The present description relates to signal processing circuits and devices, such as microprocessor units (MPUs for short) and / or microcontroller units (MCUs for short).
[0002] One or more embodiments may be applied in an automotive functional safety context, such as that governed by a standard known as ISO 26262. Background Art
[0003] A fault may be defined as an abnormal condition that may cause an element or item to fail (eg, a bit flip in a memory register). A fault may manifest itself as an error that may ultimately lead to system failure.
[0004] In the context of automotive safety standards, once a fault occurs in an external device of a single system or a combination of systems, the fault is routed to a Fault Collector and Control Unit (FCCU for short).
[0005] The FCCU module is configured to send specific reaction codes to the MCU / MPU core to manage faults.
[0006] The FCCU module operates according to a finite state machine (FSM for short), which includes four states: normal, configuration, alarm and fault.
[0007] In complex systems-on-chip (SoCs for short), using multiple safety mechanisms can become cumbersome where a wide range of failure paths may be available.
[0008] For example, in order to comply with the functional safety concept and ASIL-D standard, the fault can be covered by the safety mechanism. ASIL D is the abbreviation of Automotive Safety Integrity Level D, which refers to the classification of the initial danger (risk of harm) defined in ISO 26262 and the standard level of safety measures applied to deal with residual risks. If a fault occurs, each safety mechanism sends a signal to the next level, and these signals are collected by the FCCU in multiple (e.g., 182) multiplexed channels. For example, the core manages the fault based on the received signal.
[0009] Since routing is rarely one-to-one, existing solutions present the disadvantage of risking losing valuable information about the source of the fault, which in turn may lead to poor fault management by the core. Summary of the invention
[0010] It is an object of one or more embodiments to help overcome the above-mentioned disadvantages.
[0011] According to one or more embodiments, the object is achieved via a method having the features set out in the appended claims.
[0012] One or more embodiments may relate to a corresponding system-on-chip (SoC), which may be installed on a vehicle, such as a battery-powered vehicle.
[0013] One or more embodiments may include a computer program product that is loadable in a memory of at least one processing circuit (e.g., a computer) and includes software code portions for performing the steps of the method when the product is run on the at least one processing circuit. As used herein, reference to such a computer program product is understood to be equivalent to reference to a computer-readable medium containing instructions for controlling a processing system to coordinate the implementation of the method according to one or more embodiments. Reference to "at least one computer" is intended to emphasize the possibility that one or more embodiments will be implemented in a modular and / or distributed form.
[0014] The claims are an integral part of the technical teaching provided herein with reference to the embodiments.
[0015] One or more embodiments help enhance the quality of information provided to the kernel to help select an appropriate response among different possibilities in the fastest possible time.
[0016] One or more embodiments facilitate retrieving complete information starting from partial information retrieved from a FCCU module.
[0017] One or more embodiments facilitate customized startup.
[0018] One or more embodiments improve detection of possible input fault combinations.
[0019] One or more embodiments facilitate rapid response.
[0020] One or more embodiments help provide scalable responsiveness because different versions of functionality can be exported for more specialized applications.
[0021] One or more embodiments facilitate testing activities. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] One or more embodiments will now be described, by way of non-limiting example only, with reference to the accompanying drawings, in which:
[0023] Figure 1 is an exemplary diagram of a vehicle equipped with a system according to the present disclosure;
[0024] Figure 2 yes Figure 1 An exemplary diagram of a portion of the system illustrated in ;
[0025] Figure 3 is an exemplary graph of the evolution of a signal over time as exemplified herein;
[0026] Figure 4 is a diagram of a data structure according to the present disclosure;
[0027] Figure 5 is a diagram illustrating a method according to the present disclosure;
[0028] Figure 6 is a diagram illustrating a data structure;
[0029] Figure 7 is a diagram of further operations in a method according to the present disclosure,
[0030] Figures 8 to 10 is an exemplary diagram illustrating a data structure stored in one or more examples according to the present disclosure.
[0031] Corresponding reference numerals in the different figures generally refer to corresponding parts unless otherwise indicated.
[0032] The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.
[0033] The edges of a feature drawn in a figure do not necessarily indicate the end of the extent of the feature. DETAILED DESCRIPTION
[0034] In the following description, one or more specific details are illustrated to provide a deeper understanding of the embodiments of the present description. The embodiments can be obtained without one or more specific details, or using other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so that some aspects of the embodiments are not obscured.
[0035] References to "an embodiment" or "one embodiment" in the framework of this description are intended to indicate that a particular configuration, structure, or characteristic described with respect to the embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment" or "in one embodiment" that may appear in one or more points of the description do not necessarily refer to the same embodiment.
[0036] Furthermore, particular conformations, structures or characteristics may be combined in any suitable manner in one or more embodiments.
[0037] The reference signs used herein are provided for convenience only and therefore do not limit the degree of protection or the scope of the embodiments.
[0038] For simplicity, in the detailed description that follows, the same reference numerals may be used to represent both a node / line in a circuit and a signal that may appear at that node or line.
[0039] For simplicity, one or more embodiments are discussed below mainly with reference to an electric road vehicle (Battery Electric Vehicle, BEV), otherwise it can be understood that such examples are not limiting. One or more embodiments can be applied in a similar manner to theoretically any kind of motor vehicle, such as a hybrid vehicle or an internal combustion engine powered vehicle.
[0040] like Figure 1 As illustrated, the vehicle V includes a central electronic control unit (ECU for short) 10 coupled to a set of auxiliary ECUs 12, and the central ECU 10 is configured to transmit commands from a user (for example, via an accelerator pedal or a steering system of the vehicle V) to the set of actuators via the corresponding auxiliary ECUs of the vehicle V coupled thereto.
[0041] The auxiliary ECU comprises a processing unit for generating control signals for the vehicle systems and a data storage unit for storing data exchanged with the central ECU in a manner known per se.
[0042] like Figure 1 As shown, the central ECU includes a system on chip SoC 10, which includes:
[0043] a plurality of sensing circuits 14 coupled to the auxiliary ECU to provide a set of sensing signals indicative of various status conditions of a system driven by the auxiliary ECU (e.g., a steering actuator) and / or an internal state of the ECU (e.g., a state of data stored in a memory unit);
[0044] a set of collector error modules CEM 16, the CEM 16 being coupled to the plurality of detection circuits 14 to collect a first set of detection signals therefrom, the CEMs of the set of CEMs being configured to apply a (logical) signal processing to the received set of detection signals in order to extract information related to the presence of faults and to reduce the number of total signals, the set of CEMs 16 generating a set of error signals as a result of applying the (logical) signal processing;
[0045] Fault control and collection unit FCCU 18, FCCU 18 is coupled to the set of CEM 16 to receive a second set of detection signals, FCCU is a hardware IP for providing a central capability to control and collect faults reported by the set of CEM 16 of SoC 10; in the case where a recovery mechanism is provided by SoC 10, the faults are reported externally via (multiple) output pins or reported externally from the inside via feedback branch 19.
[0046] Specifically, the FCCU provides a mechanism for aggregating error notifications and a configurable means for placing the SoC in a safe state. For example, error indications are passed from individual detection components 14 to the FCCU 18 via the CEM.
[0047] For example, the feedback circuit 19 triggered by the FCCU 18 may include:
[0048] Internal feedback mechanisms, e.g., alerting any core, and / or
[0049] External feedback mechanisms, for example, shift some GPIO voltage nodes.
[0050] As will be appreciated by those skilled in the art, the FCCU 18 may be equipped with finite state machine FSM logic according to which the unit 18 determines the appropriate action to take in response to a received error signal.
[0051] For simplicity, one or more embodiments are described below mainly with reference to an exemplary case in which the set of CEMs 16 comprises two CEMs 161 , 162 , except that it is understood that such a number of CEMs is merely exemplary and in no way limiting.
[0052] like Figure 2 As illustrated, the collection of CEM 16 includes:
[0053] a first CEM circuit 161, the first CEM circuit 161 comprising a first set of signal processing blocks 1610, 1612, 1614, the signal processing blocks 1610, 1612, 1614 being configured to be coupled to the detection circuit block 14 to receive the detection signal therefrom, the first CEM circuit 161 further comprising a first CEM register 1618, the first CEM register 1618 being configured to store data relating to the manner in which the detection signal is connected and processed by a signal processing block in the first set of signal processing blocks 1610, 1612, 1614;
[0054] A second CEM circuit 162, the second CEM circuit 162 includes a second set of signal processing blocks 1620, 1622, 1624, the signal processing blocks 1620, 1622, 1624 are configured to be coupled to the detection circuit block 14 to receive the detection signal therefrom, and the second CEM circuit 162 also includes a second CEM register 1628, the second CEM register 1628 is configured to store data related to the manner in which the detection signal is connected and processed by the signal processing blocks in the second set of signal processing blocks 1620, 1622, 1624.
[0055] For simplicity, one or more embodiments are discussed below considering an exemplary scenario in which each signal processing circuit module 1610, 1612, 1614, 1620, 1622, 1624 includes three input channels, except that it can be understood that such a number of input channels is merely exemplary and is by no means limiting.
[0056] like Figure 2 As illustrated, the CEM circuits 161 , 162 are designed to process a variable number of signals, for example even a greater number than the number of signals detected from the detection circuit 14 .
[0057] For example, the first CEM register 1618 may include data for configuring:
[0058] The first signal processing circuit block 1610 in the set of signal processing circuit blocks 161 receives a first input signal (at a first input node) at a first input node. Figure 2 ), while keeping the remaining input nodes of the first signal processing circuit block 1610 unconnected (in Figure 2 indicated as “NC” in the
[0059] The second signal processing circuit block 1612 in the set of signal processing circuit blocks 161 receives the first input signal (at the first input node) at the first input node. Figure 2 Indicated as "1" in Figure 2 ), and the third input node of the second signal processing circuit block 1612 is left unconnected (in Figure 2 indicated as “NC” in the
[0060] The third signal processing circuit block 1614 in the set of signal processing circuit blocks 161 receives the first input signal (at the first input node) at the first input node. Figure 2 Indicated as "1" in Figure 2 , and receives a third detection signal (indicated as “2” in FIG. 1 ) at a third input node of the third signal processing circuit block 1614. Figure 2 is indicated as “n” in the figure).
[0061] As will be appreciated by those skilled in the art, the collection of CEMs providing signal processing stages intermediate the detection circuit 14 and the FCCU 18 facilitates pre-processing of signals for provision to the FCCU 18, for example to operate as an "enable" signal for some specific FCCU input channels.
[0062] like Figure 2 As illustrated, the FCCU 18 includes FCCU registers 180 configured to store data relating to how to interpret the combination of signals received at the input. For example, this may take the form of a look-up table that assigns values to the output signal F based on the values of the input signals provided by the CEM 16.
[0063] For example:
[0064] The set of detection circuits 14 includes 990 detection circuits,
[0065] The set of CEMs includes 12 CEM circuit blocks 161, 162,
[0066] Each CEM 16 may include 1761 input nodes, so most of the input nodes of the CEM may be in a "not connected" state.
[0067] For example, the FCCU circuit 18 includes 182 input channels.
[0068] like Figure 3 exemplified, Figure 1 and Figure 2 The operation of the SoC 10 illustrated in FIG. 1 can be divided into different time frames:
[0069] Box 300: The system 10 operates periodically during a normal operation phase;
[0070] Block 310: A fault event is detected; for example, a temperature sensor in the set of sensing circuits 14 generates an output voltage exceeding a defined threshold;
[0071] Block 312: In response to the signal 310 being asserted by the FCCU circuit 18 indicating a fault condition detected by the detection circuit 14, the counter (at Figure 1 and Figure 2 The measurement of the fault tolerance time interval (FTTI, which can last at least 10ms, where 1ms = 10 -3 Seconds = 1 millisecond), as described below, various operations are performed during the fault-tolerant time interval;
[0072] Block 311: A security check may be performed by the application;
[0073] Block 312: Software safety mechanisms are checked; in response to a lapse of block 312, an interrupt service routine (ISR) may be triggered, the ISR comprising:
[0074] Block 314: Detecting the source of the error signal F received by the FCCU 18 (ie, a particular subsystem within the auxiliary ECU 12),
[0075] Block 316: Apply countermeasures to correct the error (e.g., if the failure is an erroneous bit in memory, attempt to rewrite the data bit);
[0076] Block 318: Clear service, ie, reset the FCCU and CEM circuits into the node.
[0077] In a conventional SoC arrangement 10, in response to receiving a signal indicating a fault from the CEM 16, the FCCU 18 may trigger an interrupt to any core via the feedback branch 19. It is of interest to develop methods for identifying the source of an error corresponding to a received error signal, since this information may be "lost" in the CEM pre-processing stage 16.
[0078] The inventors have observed that by using a collection of data structures 402, 404, it is possible to quickly identify Figure 3 The set of data structures 402 , 404 may be accessed (eg, from the memory 180 ) in response to the fault detection 310 , depending on the source of the error during the time frame 314 illustrated in FIG.
[0079] like Figure 4 As illustrated, the first data structure 402, such as a first table, includes:
[0080] a first set of items CEM_CH indicating which signal processing circuit block 1610, 1612, 1614, 1620, 1622, 1624 of the set of CEM circuits 161, 162 is connected to which FCCU input node or channel FCCU_CH; for example, each item of the first set of items CEM_CH may be associated to a respective channel of the set of channels FCCU_CH via its position in the table or alternatively via a further set of items FCCU_CH paired with the first set of items CEM_CH;
[0081] A second set of terms SM, the second set of terms SM indicating that a plurality of input nodes of a signal processing block (eg, 1610) are actually connected (eg, as Figure 2 Only the first input node as illustrated in ); and
[0082] A third set of items KEY, the third set of items KEY includes IDs of other tables in the second set of data structures 404 as described below.
[0083] like Figure 4 As illustrated, a second data structure in the second set of data structures 404, such as a second table KEY1, contains information related to a connection node (e.g., a first node) of a signal processing block 1610, the signal processing block 1610 being identified as being connected to a first FCCU input channel 01, and the second data structure includes an entry for each "active" CEM channel CEM_No connected to the corresponding FCCU channel. Figure 4 As illustrated, the data structure also includes:
[0084] a set of FCC channel numbers FCC_CH (e.g., 01) associated with each CEM channel (e.g., 1) of a particular CEM signal processing circuit block (e.g., 1610);
[0085] A set of numbers (e.g., 161) of CEM circuits where CEM channels (e.g., 1610) are located;
[0086] a set of CEM channel IDs CEM_CH (e.g., 1610),
[0087] A set of IDs of associated external devices (e.g., RAM) of the auxiliary ECU 12,
[0088] Optionally, a set of IDs of associated sub-external devices of the auxiliary ECU 12 (eg, addresses of fault memory units);
[0089] Optionally, an enable signal EN may be used by other user circuits to enable various functions.
[0090] like Figure 5 As illustrated, the method 500 for identifying a source of an error in response to detection 14 of an error signal includes:
[0091] Block 502: Accessing data stored in the FCCU register 180 to detect which of the FCCU input channels 01, 02, 03, 04, 05, 06 has received an error signal;
[0092] Block 504: Using the entry of the first data structure 402 to identify which signal processing circuit block of the set of signal processing circuit blocks 1610, 1612, 1614, 1620, 1622, 1624 of the CEM 16 is coupled to the identified faulty FCCU input channel;
[0093] Block 506: Identify a corresponding data structure (e.g., KEY1) in the second set of data structures 404 by reading the entry “KEY” associated with the entry “CEM_CH” in the first data structure 402, the corresponding data structure storing additional information related to coupling the identified signal processing circuit block (e.g., 1610) and the detection circuit block 14;
[0094] Block 510: Identify a CEM circuit (e.g., 161) corresponding to a CEM numbered entry of a second data structure accessed in a second set of data structures 404, and access a register (e.g., 1628) of the identified CEM circuit;
[0095] Block 512: Accessing a CEM register (e.g., 1618) of the identified CEM circuit (e.g., 161) to determine input nodes and corresponding error sources;
[0096] Block 514: Collecting entries of a second data structure in the set of second data structures 404, the entries corresponding to the CEM channel CEM_CH coupled to the identified error source;
[0097] Block 516 : Providing a second data structure as an output signal, for example, as feedback 19 from the kernel 12 .
[0098] The inventors have observed that Figure 5 The method illustrated in facilitates performing error source identification using time block 314 because it is faster to access multiple small (in terms of memory size) data structures than to scan all entries of a larger data structure.
[0099] like Figure 5 As illustrated, the method may be a computer-implemented method executed by the core 12 in response to receiving the error detection signal.
[0100] As exemplified herein, the method comprises:
[0101] coupling the set of sensing circuits 14 to the set of electronic devices 12;
[0102] sensing, via a sensing circuit, a set of sensing signals S1, S2, the set of sensing signals S1, S2 comprising a sensing signal indicating an operating state of an electronic device in the set of electronic devices;
[0103] via coupling the set of signal processing channels 1610, 1612, 1614, 1620, 1622, 1624 to the set of sensing circuits, applying logical signal processing 16 to the set of sensing signals, and providing as a result a set of logically combined sensing signals,
[0104] Wherein, the logically combined sensing signals indicate whether the operating state of the electronic device in the set of electronic devices is an expected (or correct) operating state or an unexpected (or incorrect) operating state;
[0105] providing the logically combined sensing signal in the set of logically combined sensing signals to an input channel in the set of input channels 01, 02, 03, 04, 05, 06 of the fault collection and control unit FCCU 18;
[0106] storing 180, 1618, 1628 at least one data structure 402, 404, the at least one data structure 402, 404 comprising data related to the manner in which the set of input channels of the FCCU is coupled to the set of sensing circuits via the set of signal processing channels 1610, 1612, 1614, 1620, 1622, 1624;
[0107] In response to at least one combined sensing signal in the set of combined sensing signals indicating an unintended operational state of an electronic device in the set of electronic devices:
[0108] identifying 502 an FCCU input channel of the set of input channels of the FCCU from which at least one combined sensed signal indicative of an unexpected operating state originates;
[0109] accessing 504, 512 data 180, 1618, 1628 stored in at least one data structure;
[0110] Based on the accessed data, identifying 314 , 514 an electronic device in the set of electronic devices that generates an unexpected operating state sensing signal;
[0111] An interrupt request signal F is provided to the identified electronic device of the set of electronic devices.
[0112] For example, the method includes performing a feedback action 19 with respect to the identified electronic device in the set of electronic devices, the feedback action including at least one of: ignoring the unexpected operating state, restoring the expected operating state, and storing the unexpected operating state.
[0113] As illustrated herein, storing at least one data structure includes:
[0114] storing a first data structure 402 comprising an ordered list of signal processing channels 1610, 1612, 1614, 1620, 1622, 1624 associated with input channels of the FCCU and an associated list of pointers to data structures in another set of data structures 404;
[0115] The data structures in the further set of data structures are populated with data relating to the signal processing channels and sensing circuits associated with each input channel of the FCCU.
[0116] As illustrated herein, identifying 502 an FCCU input channel from a set of input channels of the FCCU from which at least one combined sensed signal indicative of an incorrect operating state originates includes:
[0117] storing 180 values of logically combined sensed signals received at corresponding FCCU input channels in the set of FCCU input channels in the set of logically combined sensed signals;
[0118] The stored values of the incorrect operating state signal are accessed 502 and an FCCU input channel of the set of FCCU input channels is identified that is coupled to at least one combined sense signal of the set of combined sense signals indicating an incorrect operating state of an electronic device of the set of electronic devices.
[0119] As illustrated herein, accessing data stored in at least one data structure includes:
[0120] identifying 504, based on the at least one data structure, which signal processing channel of the set of signal processing channels is coupled to a FCCU input channel of the set of FCCU input channels that is coupled to at least one combined sensed signal of the set of combined sensed signals that indicates an improper operating state of an electronic device of the set of electronic devices;
[0121] accessing 512 data related to the manner in which a signal processing channel in the set of signal processing channels is coupled to the set of sensing circuits;
[0122] collecting 514 access data corresponding to a signal processing channel coupled to the identified error source,
[0123] A data structure is provided 516, the data structure indicating coupling of the identified electronic device in the set of electronic devices to the identified error source.
[0124] As illustrated herein, the computer program product includes instructions which, when executed by the electronic device 10 , 12 , cause the electronic device to perform a method according to the present disclosure.
[0125] As illustrated herein, the system on chip SoC 10 includes a set of sensing circuits 14, which are configured to be coupled to a set of electronic devices to sense a set of sensing signals S1, S2 therefrom, the set of sensing signals S1, S2 including sensing signals indicating an operating state of an electronic device in the set of electronic devices. For example, the SoC includes:
[0126] a logic signal processing circuit device 16, the logic signal processing circuit device 16 being coupled to the set of sense signals via the set of signal processing channels 1610, 1612, 1614, 1620, 1622, 1624, the logic signal processing circuit device 16 being configured to provide a set of logically combined sense signals,
[0127] wherein the logically combined sensing signals indicate whether the operating state of an electronic device in the set of electronic devices 12 is a correct operating state or an incorrect operating state;
[0128] a fault collection and control unit FCCU coupled to the logic signal processing circuit arrangement to receive the logically combined sensed signal of the set of logically combined sensed signals at a FCCU input channel of the set of FCCU input channels;
[0129] at least one set of registers 180, 1618, 1628 storing at least one data structure 402, 404 including data related to the manner in which the set of input channels of the FCCU is coupled to the set of sensing circuits via the set of signal processing channels;
[0130] processing circuitry configured to indicate an incorrect operating state of an electronic device in the set of electronic devices in response to at least one combined sensing signal in the set of combined sensing signals:
[0131] identifying 502 an FCCU input channel of the set of input channels of the FCCU from which at least one combined sensed signal indicative of an incorrect operating state originates;
[0132] accessing 504, 512 data stored in at least one data structure;
[0133] identifying, based on the accessed data, an electronic device from the set of electronic devices that generates an incorrect operating state sensing signal;
[0134] An interrupt request signal F is provided 516 to the identified electronic device of the set of electronic devices.
[0135] As illustrated herein, the processing circuit device is also configured to perform a feedback action 19 relative to the identified electronic device in the set of electronic devices, the feedback action including at least one of: ignoring the unexpected operating state, restoring the expected operating state, and storing the unexpected operating state.
[0136] As illustrated herein, at least one data structure stored in at least one set of registers includes:
[0137] a first data structure 402 comprising an ordered list of signal processing channels associated with input channels of the FCCU and an associative list of pointers to data structures in a further set of data structures,
[0138] The data structures in the further set of data structures 404 are populated with data related to the signal processing channels and sensing circuits associated with each FCCU input channel in the set of FCCU input channels.
[0139] As illustrated herein, the processing circuitry is further configured to indicate an incorrect operating state of an electronic device in the set of electronic devices in response to at least one combined sensing signal in the set of combined sensing signals:
[0140] Identifying 502 an FCCU input channel of a set of input channels of the FCCU from which at least one combined sensed signal indicative of an incorrect operating state originates, comprises:
[0141] storing 180 values of logically combined sensed signals received at corresponding FCCU input channels in the set of FCCU input channels in the set of logically combined sensed signals;
[0142] The stored values of the incorrect operating status signals are accessed 502 and an FCCU input channel of the set of FCCU input channels is identified that is coupled to at least one combined sense signal of the set of combined sense signals indicating an incorrect operating status of an electronic device of the set of electronic devices.
[0143] As illustrated herein, the processing circuitry is further configured to indicate an incorrect operating state of an electronic device in the set of electronic devices in response to at least one combined sensing signal in the set of combined sensing signals:
[0144] Based on the at least one data structure 402, 404, identifying 504 which signal processing channel of the set of signal processing channels is coupled to a FCCU input channel of the set of FCCU input channels that is coupled to at least one combined sensed signal of the set of combined sensed signals that indicates an improper operating state of an electronic device of the set of electronic devices;
[0145] accessing 512 data related to the manner in which a signal processing channel in the set of signal processing channels is coupled to the set of sensing circuits;
[0146] collecting 514 access data corresponding to a signal processing channel coupled to the identified error source,
[0147] A data structure is provided 516 that indicates coupling of the identified electronic device in the set of electronic devices to the identified error source.
[0148] As exemplified herein, the vehicle V comprises:
[0149] According to the system on chip SoC 10 of the present disclosure,
[0150] A collection of electronic devices 12 coupled to the SoC;
[0151] A set of actuators configured to operate the vehicle based on signals F, D exchanged between the set of electronic devices and the SoC.
[0152] As will be appreciated by those skilled in the art, the signals provided by the set of CEM circuits 16 at the corresponding FCCU input channels 01, 02, 03, 04, 05, 06 may be stored in corresponding entries in the FCCU registers 180 according to a particular data structure as they may be classified as belonging to a category selected from normal, alarm and fault.
[0153] like Figure 6 As illustrated, the data structure for data entries stored in the FCCU registers 180 may include multiple sections (or registers), such as, for example:
[0154] a set of register sections N2A, N2F, F2A, A2F, also referred to as "frozen registers", including a normal to alarm section N2A, a normal to fault section N2F, a fault to normal section F2A, an alarm to fault section A2F;
[0155] a set of timer registers AT1, AT2, AT3, AT4, for example including a first timer register AT1, a second timer register AT2, a third timer register AT3, and a fourth timer register AT4, the timer registers in the set of timer registers AT1, AT2, AT3, AT4 being configured to be activated if the normal-to-alarm portion N2A includes an "unassigned" state (for example, fixed to be equal to a hexadecimal string 0xFF);
[0156] The RF register section includes a sub-register for each input channel of the FCCU.
[0157] like Figure 7 As illustrated, a method of accessing the FCCU registers 180 to identify the channel source that triggered the error signal detected at the FCCU 18 includes:
[0158] Block 700: Accessing the freeze registers N2A, N2F, F2A, A2F and checking whether only one of the registers stores data related to the faulty channel or whether more than one register includes data related to multiple faults;
[0159] Block 704: In response to detecting that a plurality of register portions among the register portions in the set of register portions N2A, N2F, F2A, A2F store error-related data, accessing data stored in the first timer register AT1 and the second timer register AT2, and identifying the register portion with the lower timer count (e.g., the second register indicates that data stored in the normal to fault portion N2F was stored earlier than data stored in the fault to alarm portion A2F);
[0160] Block 706: In the case where the timers show the same timing, or the data stored in the register cannot be directly assigned to one of the faulty channels, there is a priority mechanism based on the index numbers associated with the respective channels, for example, in the case of decreasing the alarm timer register count, a higher priority is assigned to a lower index number;
[0161] Block 710: The channels detected by reading the register portions according to the different scenarios 702, 706 are provided to the user circuit.
[0162] Figures 8 to 10 It is an example Figure 7 Schematic diagram of example data structures 180A, 180B, 180C in various scenarios of the method illustrated in .
[0163] like Figure 8 As illustrated, in the case where a single fault is detected, register N2A in data structure 180A stores information about the channel from which the fault originates, and the method includes Figure 7 The operations in blocks 700, 702, and 710 illustrated in FIG.
[0164] like Fig. 9 and Fig.10 As shown, in the case where multiple faults are detected, Figure 7 The freeze register of data structure 180B accessed in block 700 of the method illustrated in does not provide a clear indication of which channel caused the fault.
[0165] like Fig. 9 As shown, the alarm timer registers AT1, AT2, AT3, AT4 in the data structure 180B are Figure 7 is accessed in block 706 as illustrated.
[0166] For example, since the second alarm timer AT2 includes a greater value than the first alarm timer AT1 , in the exemplary scenario of decreasing the count or reverse counting timer, the channel considered to have generated a fault is the channel linked to the first alarm timer AT1 .
[0167] like Fig.10 As illustrated, if, on the contrary, the accessed alarm timer registers AT1, AT2, AT3, AT4 cannot be relied upon to determine the priority order of the detected multiple faults, as shown in data structure 180C, the method includes in Figure 7 RF registers are accessed at step 708 of the method illustrated in . For example, priority may be assigned to the "lowest" channel value 10 found in the RF registers because the hardware may be configured to associate higher thresholds with faults having lower FCCU channel numbers.
[0168] Otherwise, it is understood that the various individual implementation options illustrated in the figures attached throughout this specification are not necessarily intended to be employed in the same combination illustrated in the figures. One or more embodiments may therefore employ these (non-mandatory) options individually and / or in a combination different from the combination illustrated in the figures.
[0169] The details and embodiments may vary, even significantly, with respect to what has been described purely by way of example, without prejudice to the essential principles and without departing from the scope of protection.
[0170] The method (500) is summarized as comprising: coupling a set of sensing circuits (14) to a set of electronic devices (12); sensing a set of sensing signals (S1, S2) via the sensing circuits (14), the set of sensing signals (S1, S2) comprising sensing signals indicating an operating state of an electronic device in the set of electronic devices (12); applying logical signal processing (16) to the set of sensing signals (S1, S2) via coupling a set of signal processing channels (1610, 1612, 1614, 1620, 1622, 1624) to the set of sensing circuits (14); The method comprises the steps of: providing a set of logically combined sensing signals and providing a set of logically combined sensing signals as a result, wherein the logically combined sensing signals indicate whether the operating state of the electronic device in the set of electronic devices (12) is an expected operating state or an unexpected operating state; providing the logically combined sensing signals in the set of logically combined sensing signals to an input channel in a set of input channels (01, 02, 03, 04, 05, 06) of a fault collection and control unit FCCU (18); storing (180, 1618, 1628) at least one data structure (402, 404), the at least one data structure The structure (402, 404) includes data related to the manner in which a set of input channels (01, 02, 03, 04, 05, 06) of the FCCU (18) is coupled to a set of sensing circuits (14) via a set of signal processing channels (1610, 1612, 1614, 1620, 1622, 1624); in response to at least one of the set of combined sensing signals indicating an unexpected operating state of an electronic device in the set of electronic devices (12): identifying (502) the input channels (01, 02, 03, 04, 05, 06) of the FCCU (18) 04, 05, 06), at least one combined sensing signal indicating an unexpected operating state originating from the FCCU input channel; accessing (504, 512, 512) data (180, 1618, 1628) stored in at least one data structure (402, 404); based on the accessed data, identifying (314, 514) an electronic device in the set of electronic devices (12) that generates an unexpected operating state sensing signal; and providing an interrupt request signal (F) to the identified electronic device in the set of electronic devices (12).
[0171] The method includes performing a feedback action (19) relative to an identified electronic device in a set of electronic devices (12), the feedback action (19) including at least one of: ignoring an unexpected operating state, restoring an expected operating state, and storing an unexpected operating state.
[0172] Storing (180, 1618, 1628) at least one data structure (402, 404) includes: storing a first data structure (402), the first data structure (402) including an ordered list of signal processing channels (1610, 1612, 1614, 1620, 1622, 1624) associated with input channels (01, 02, 03, 04, 05, 06) of the FCCU (18), and an associated list of pointers to data structures in another set (404) of data structures; and populating the data structures in the other set of data structures (404) with data associated with the signal processing channels (1610, 1612, 1614, 1620, 1622, 1624) and sensing circuits (14) associated with each input channel (01, 02, 03, 04, 05, 06) of the FCCU (18).
[0173] Identifying (502) an FCCU input channel from which at least one combined sensing signal indicative of an unexpected operating state in a set of input channels (01, 02, 03, 04, 05, 06) of an FCCU (18) originates, comprising: storing (180) values of logically combined sensing signals in the set of logically combined sensing signals received at corresponding FCCU input channels in the set of FCCU input channels (01, 02, 03, 04, 05, 06); and accessing (502) the stored values (180) of the unexpected operating state signals, and identifying an FCCU input channel in the set of FCCU input channels (01, 02, 03, 04, 05, 06) that is coupled to at least one combined sensing signal indicative of an unexpected operating state of an electronic device in the set of electronic devices (12).
[0174] Accessing (504, 512, 512) data (180, 1618, 1628) stored in at least one data structure (402, 404) includes: based on the at least one data structure (402, 404), identifying (504) which of a set of signal processing channels (1610, 1612, 1614, 1620, 1622, 1624) can be coupled to a set of FCCU input channels (01, 02, 03, 04, 05, 06) coupled to a set of indicating electronic devices (12) in a set of combined sensed signals accessing (512) data related to the manner in which a signal processing channel in a set of signal processing channels (1610, 1612, 1614, 1620, 1622, 1624) is coupled to a set of sensing circuits (14); collecting (514) access data corresponding to a signal processing channel coupled to an identified error source; and providing (516) a data structure indicating coupling of an identified electronic device in the set of electronic devices (12) to an identified error source.
[0175] The computer program product is generally described as comprising instructions which, when the program is executed by an electronic device (10, 12), cause the electronic device (10, 12) to perform a method.
[0176] A system on chip (SoC) (10) is summarized as comprising: a set of sensing circuits (14), the set of sensing circuits (14) being configured to be coupled to a set of electronic devices (12) to sense a set of sensing signals (S1, S2) from the set of electronic devices (12), the set of sensing signals (S1, S2) comprising sensing signals indicating an operating state of an electronic device in the set of electronic devices (12); and a logic signal processing circuit device (16), the logic signal processing circuit device (16) being coupled to the set of sensing signals (S1, S2) via a set of signal processing channels (1610, 1612, 1614, 1620, 1622, 1624 ...) The processing circuit device (16) is configured to provide a set of logically combined sensing signals, wherein the logically combined sensing signals indicate whether the operating state of the electronic device in the set of electronic devices (12) is an expected operating state or an unexpected operating state; a fault collection and control unit FCCU (18), the fault collection and control unit FCCU (18) is coupled to the logic signal processing circuit device (16) to receive the logically combined sensing signals in the set of logically combined sensing signals at an FCCU input channel in the set of FCCU input channels (01, 02, 03, 04, 05, 06); at least one of the registers (180, 1618, 1628) a set of registers (180, 1618, 1628) storing at least one data structure (402, 404), the at least one data structure (402, 404) including data related to the manner in which a set of input channels (01, 02, 03, 04, 05, 06) of the FCCU (18) is coupled to a set of sensing circuits (14) via a set of signal processing channels (1610, 1612, 1614, 1620, 1622, 1624); and a processing circuit device configured to indicate an electronic device in the set of electronic devices (12) in response to at least one of the set of combined sensing signals. An unexpected operating state of an electronic device is detected by: identifying (502) an FCCU input channel from which at least one combined sensing signal indicating an unexpected operating state originates from a set of input channels (01, 02, 03, 04, 05, 06) of the FCCU (18); accessing (504, 512, 512) data stored (180, 1618, 1628) in at least one data structure (402, 404); based on the accessed data, identifying (314, 514) an electronic device from a set of electronic devices (12) that generates an unexpected operating state sensing signal; and providing an interrupt request signal (F) to the identified electronic device from the set of electronic devices (12).
[0177] The processing circuit device is also configured to perform a feedback action (19) relative to the identified electronic device in the set of electronic devices (12), the feedback action (19) comprising at least one of: ignoring the unexpected operating state, restoring the expected operating state, and storing the unexpected operating state.
[0178] At least one data structure (402, 404) stored in at least one set of registers (180, 1618, 1628) includes: a first data structure (402), the first data structure (402) including an ordered list of signal processing channels (1610, 1612, 1614, 1620, 1622, 1624) associated with input channels (01, 02, 03, 04, 05, 06) of the FCCU (18), and an associated list of pointers to data structures in another set of data structures (404); wherein the data structures in the other set of data structures (404) are populated with data associated with the signal processing channels (1610, 1612, 1614, 1620, 1622, 1624) and sensing circuits (14) associated with each FCCU input channel in the set of FCCU input channels (01, 02, 03, 04, 05, 06).
[0179] The processing circuit device is also configured to: in response to at least one combined sensing signal in the set of combined sensing signals indicating an unexpected operating state of an electronic device in the set of electronic devices (12): identify (502) an FCCU input channel from which at least one combined sensing signal in the set of input channels (01, 02, 03, 04, 05, 06) of the FCCU (18) originates, including: storing (180) values of the logically combined sensing signals in the set of logically combined sensing signals received at corresponding FCCU input channels in the set of FCCU input channels (01, 02, 03, 04, 05, 06); and accessing (502) the stored values (180) of the unexpected operating state signals, and identifying the FCCU input channel in the set of FCCU input channels (01, 02, 03, 04, 05, 06) that is coupled to at least one combined sensing signal in the set of combined sensing signals indicating an unexpected operating state of an electronic device in the set of electronic devices (12).
[0180] The processing circuit device may also be configured to, in response to at least one of the combined sensing signals indicating an unexpected operating state of an electronic device in the set of electronic devices (12), identify (504) which of the set of signal processing channels (1610, 1612, 1614, 1620, 1622, 1624) is coupled to the indicating electronic device (12) in the set of FCCU input channels (01, 02, 03, 04, 05, 06) based on at least one data structure (402, 404). accessing (512) data related to the manner in which a signal processing channel in a set of signal processing channels (1610, 1612, 1614, 1620, 1622, 1624) is coupled to a set of sensing circuits (14); and collecting (514) access data corresponding to a signal processing channel coupled to an identified error source; and providing (516) a data structure indicating coupling of an identified electronic device in a set of electronic devices (12) to an identified error source.
[0181] A vehicle (V) is summarized as comprising: a system on a chip SoC (10), a set of electronic devices (12) coupled to the SoC (10); and a set of actuators, the set of actuators being configured to operate the vehicle (V) based on signals (F, D) exchanged between the set of electronic devices (12) and the SoC (10).
[0182] The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments can be modified, as necessary, to employ the concepts of the various patents, applications and publications to provide further embodiments.
[0183] These and other changes can be made to the embodiments in light of the above detailed description. In general, in the appended claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full range of equivalents to which such claims are entitled. Therefore, the claims are not limited by this disclosure.
Claims
1. A method comprising: coupling the set of sensing circuits to the set of electronic devices; sensing, via the sensing circuit, a set of sensing signals, the set of sensing signals indicating an operating state of an electronic device in the set of electronic devices; applying logical signal processing to the set of sense signals via coupling the set of signal processing channels to the set of sense circuits, and providing a set of logically combined sense signals as a result, wherein the logically combined sensing signals indicate whether the operating state of the electronic device in the set of electronic devices is an expected operating state or an unexpected operating state, wherein the signal processing channels are each included in one of a plurality of collector error module (CEM) circuits, each CEM circuit including a corresponding CEM register; providing the logically combined sensing signals in the set of the logically combined sensing signals to an input channel in the set of input channels of a fault collection and control unit FCCU; storing at least one data structure including data related to the manner in which the set of input channels of the FCCU are coupled to the set of sensing circuits via the set of signal processing channels; as well as In response to at least one combined sensing signal in the set of combined sensing signals indicating the unintended operating state of the electronic device in the set of electronic devices: identifying the FCCU input channel of the set of input channels of the FCCU from which at least one combined sensed signal indicative of the unexpected operating state originates; accessing said data stored in said at least one data structure; identifying, based on the accessed data, the electronic device of the set of electronic devices that generates at least one combined sensing signal indicative of the unintended operating state; as well as An interrupt request signal is provided to the identified electronic device of the set of electronic devices.
2. The method according to claim 1, further comprising: A feedback action is performed with respect to the identified electronic device in the set of electronic devices, the feedback action comprising at least one of: ignoring an unexpected operating state, restoring an expected operating state, and storing the unexpected operating state.
3. The method of claim 1 , wherein storing the at least one data structure comprises: storing a first data structure comprising an ordered list of signal processing channels associated with the input channels of the FCCU and an associative list of pointers to data structures in another set of data structures; as well as The data structures in the further set of data structures are populated with data relating to signal processing channels and sensing circuits of each input channel in the set of input channels associated to the FCCU.
4. The method of claim 1 , wherein identifying the FCCU input channel of the set of input channels of the FCCU from which at least one combined sensed signal indicative of the unexpected operating state originates comprises: storing values of the logically combined sensed signals received at corresponding ones of the set of FCCU input channels in the set of FCCU input channels; as well as Accessing stored values of the unexpected operating state signals and identifying the FCCU input channel in the set of FCCU input channels that is coupled to at least one of the combined sensing signals in the set of combined sensing signals indicating an unexpected operating state of the electronic device in the set of electronic devices.
5. The method of claim 1 , wherein accessing the data stored in the at least one data structure comprises: identifying, based on the at least one data structure, which of the set of signal processing channels is coupled to the FCCU input channel of the set of FCCU input channels that is coupled to at least one of the combined set of sensed signals indicating an unintended operating state of the electronic device of the set of electronic devices; accessing data related to the manner in which signal processing channels in the set of signal processing channels are coupled to the set of sensing circuits; collecting the accessed data corresponding to the signal processing channel coupled to the identified error source; as well as A data structure is provided that indicates coupling of the identified electronic device in the set of electronic devices to the identified error source.
6. The method of claim 1, wherein the at least one data structure comprises: a set of register sections, the set of register sections comprising a normal to alarm section, a normal to fault section, a fault to normal section, and an alarm to fault section; as well as A set of timer registers that are activated when the normal-to-alarm portion includes an unassigned state.
7. A system comprising: a set of sensing circuits coupled to the set of electronic devices to sense a set of sensing signals indicative of an operational state of an electronic device in the set of electronic devices; a logic signal processing circuit arrangement coupled to the set of sense signals via a set of signal processing channels, the logic signal processing circuit arrangement being configured to provide a set of logically combined sense signals, the logic signal processing circuit arrangement comprising a plurality of collector error module (CEM) circuits, each CEM circuit comprising a corresponding CEM register, and a signal processing channel of the set of signal processing channels; wherein the logically combined sensing signals indicate whether the operating state of the electronic device in the set of electronic devices is an expected operating state or an unexpected operating state; a fault collection and control unit FCCU coupled to the logic signal processing circuit arrangement to receive the logically combined sensed signal of the set of logically combined sensed signals at a FCCU input channel of the set of FCCU input channels; at least one set of registers storing at least one data structure including data related to the manner in which the set of FCCU input channels are coupled to the set of sensing circuits via the set of signal processing channels; as well as processing circuitry configured to indicate an unintended operational state of an electronic device in the set of electronic devices in response to at least one combined sensing signal in the set of combined sensing signals: identifying the FCCU input channel of the set of input channels of the FCCU from which at least one combined sensed signal indicative of the unexpected operating state originates; accessing said data stored in said at least one data structure; Based on the accessed data, identifying the electronic device in the set of electronic devices that generates the unexpected operating state sensing signal; and An interrupt request signal is provided to the identified electronic device of the set of electronic devices.
8. A system according to claim 7, wherein the processing circuit device is also configured to perform a feedback action relative to the identified electronic device in the set of electronic devices, and the feedback action includes at least one of the following: ignoring the unexpected operating state, restoring the expected operating state, and storing the unexpected operating state.
9. The system of claim 7, wherein the at least one data structure stored in the at least one set of registers comprises: a first data structure comprising an ordered list of signal processing channels associated with the input channels of the FCCU and an associative list of pointers to data structures in a second set of data structures, and Wherein the data structures in the second set of the data structures are populated with data relating to the signal processing channel and the sensing circuit associated to each FCCU input channel in the set of FCCU input channels.
10. The system of claim 7, wherein the processing circuitry is further configured to, in response to at least one combined sensing signal in the set of combined sensing signals indicating an unintended operating state of the electronic device in the set of electronic devices: identifying the FCCU input channel of the set of input channels of the FCCU from which at least one combined sensed signal indicative of the unexpected operating state originates; storing values of the logically combined sensed signals received at corresponding FCCU input channels in the set of FCCU input channels in the set of logically combined sensed signals; and Accessing stored values of the unexpected operating state signals and identifying the FCCU input channel in the set of FCCU input channels that is coupled to at least one of the combined sensing signals in the set of combined sensing signals indicating an unexpected operating state of the electronic device in the set of electronic devices.
11. The system of claim 7, wherein the processing circuit device is further configured to indicate the unintended operating state of the electronic device in the set of electronic devices in response to at least one combined sensing signal in the set of combined sensing signals: identifying, based on the at least one data structure, which of the set of signal processing channels is coupled to the FCCU input channel of the set of FCCU input channels that is coupled to at least one of the combined sensed signals of the set of combined sensed signals indicating the unintended operating state of the electronic device of the set of electronic devices; accessing data related to the manner in which signal processing channels in the set of signal processing channels are coupled to the set of sensing circuits; collecting the accessed data corresponding to the signal processing channel coupled to the identified error source; and A data structure is provided that indicates coupling of the identified electronic device in the set of electronic devices to the identified error source. 12 . The system of claim 7 , wherein the logically combined sensed signals in the set of logically combined sensed signals are assigned a classification between a normal category, an alarm category, and a fault category.
13. The system of claim 7, wherein the at least one data structure comprises a set of register sections and a set of timer registers.
14. The system of claim 13, wherein the set of register sections includes a normal to alarm section, a normal to fault section, a fault to normal section, and an alarm to fault section.
15. The system of claim 14, wherein the set of timer registers is activated when the normal to alarm portion includes an unassigned state.
16. A device comprising: System on chip SoC, the SoC comprising: A collection of detection circuits; a set of collector error modules CEM, the set of CEMs being coupled to the plurality of detection circuits, each CEM comprising a plurality of signal processing blocks, each signal processing block being coupled to the set of detection circuits, and CEM registers; a fault control and collection unit FCCU, said FCCU being coupled to said set of collector error modules, said FCCU comprising FCCU registers; A first data structure in the FCCU register and a first data structure in each CEM register, the first data structure comprising: a first set of data, the first set of data comprising which of the plurality of signal processing blocks is associated with which of the plurality of inputs of the FCCU; a second set of data comprising a number of input nodes of each of the plurality of signal processing blocks connected to an input of the FCCU; and a third set of data, the third set of data comprising identifications of a plurality of tables in the second data structure; and A plurality of auxiliary electronic control units are coupled to the SoC.
17. The apparatus of claim 16, wherein each of the plurality of auxiliary electronic control units comprises a processing unit and a data storage unit, the processing unit being configured to generate a control signal for a vehicle system, the data storage unit being configured to store data exchanged with the SoC.
18. The apparatus of claim 16, wherein each CEM comprises: a first signal processing block of the plurality of signal processing blocks, the first signal processing block comprising a first input node configured to receive a first input signal, an unconnected second input node, and an unconnected third input node; a second signal processing block of the plurality of signal processing blocks, the second signal processing block comprising a first input node configured to receive the first input signal, a second input node configured to receive a second detection signal, and a third input node that is not connected; as well as A third signal processing block of the plurality of signal processing blocks, the third signal processing block comprising a first input node configured to receive the first input signal, a second input node configured to receive the second detection signal, and a third input node configured to receive a third detection signal.
19. The apparatus of claim 18, wherein the FCCU register comprises a lookup table that assigns a value to an output signal based on a value of the first input signal, a value of the second detection signal, and a value of the third detection signal.
20. The apparatus of claim 16, wherein the second data structure comprises: a table key including data about a plurality of connection nodes of each signal processing block; a set of multiple FCC channel numbers, the set of multiple FCC channel numbers being associated with each CEM channel of the corresponding CEM signal processing block; a set of numbers corresponding to the positions of the CEM channels in each CEM; A collection of multiple CEM channel identifiers; as well as A set of multiple identifications of multiple external devices of the auxiliary electronic control unit.