Anomaly recovery method, apparatus and electronic device

Abstract

Embodiments of the present application provide an exception recovery method, device and electronic equipment, which are applied to a binary translation system, the binary translation system is used for translating a source program in a client into a target program in a host, and the method comprises the following steps: in the case of an exception, determining a source instruction corresponding to a target instruction triggering the exception and a basic block in the source program, and marking a target position corresponding to the source instruction in the source program; determining an offset value corresponding to a target register according to the target position and a register delay calculation algorithm; the target register comprises registers corresponding to each instruction between a start position of the basic block and the target position and within a correction range of the register delay calculation algorithm; and correcting a value of the target register according to the offset value. Embodiments of the present application can solve problems such as incorrect register values caused by register delay optimization in the binary translation process in the case of exceptions, self-modifying code and other special cases, and improve the exception recovery efficiency.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, and in particular, to an exception recovery method and device and electronic equipment. BACKGROUND

[0002] Register delay computation is mainly proposed to solve the timing problem in hardware design and optimize the performance of instruction execution. It also has important application in binary translation, which can help optimize the instruction translation process and improve the translation efficiency.

[0003] The optimization of the register delay computation class faces a problem: dynamic binary translation cannot always be executed completely when executing the translated basic block. In some special cases, the execution flow may be transferred to the exception handling function at an instruction in the middle of a basic block. These special cases include but are not limited to the generation of exceptions, the occurrence of self-modifying code, etc. In this case, the exception handling program needs to restore the scene at this time, including the values of various registers. However, the principle of the optimization of the register delay computation class is to reduce or merge the calculation of the values of some registers in a basic block, and only guarantee that the values of all registers are consistent with the expected values after the complete execution of a basic block. Therefore, if an exception occurs when executing an instruction, a corresponding mechanism is needed to restore the values of the registers to avoid errors in future program execution. SUMMARY

[0004] The embodiment of the present application provides an exception recovery method, device and electronic equipment, which can solve the problem of incorrect register values caused by optimization in the binary translation system in the prior art in special cases such as the generation of exceptions and the occurrence of self-modifying code.

[0005] In order to solve the above problem, the embodiment of the present application discloses an exception recovery method applied to a binary translation system, wherein the binary translation system is used to translate a source program in a client into a target program in a host, and the method comprises the following steps:

[0006] In the case of an exception, determining the source instruction and the basic block corresponding to the target instruction triggering the exception in the source program, and marking the target position of the source instruction in the source program;

[0007] According to the target position and the register delay computation algorithm, determining the offset value corresponding to the target register; the target register includes the registers corresponding to each instruction between the start position of the basic block and the target position in the register delay computation algorithm modification range;

[0008] According to the offset value, modifying the value of the target register.

[0009] In another aspect, the embodiments of the present application disclose an exception recovery apparatus applied to a binary translation system, wherein the binary translation system is used to translate a source program in a guest machine into a target program in a host machine, and the apparatus comprises:

[0010] a determining unit, configured to determine a source instruction and a basic block corresponding to a target instruction triggering an exception in the source program and mark a target position corresponding to the source instruction in the source program in a case where the exception occurs, and determine an offset value corresponding to a target register according to the target position and a register delay calculation algorithm, wherein the target register comprises registers corresponding to instructions between a start position of the basic block and the target position in a correction range of the register delay calculation algorithm;

[0011] a correcting unit, configured to correct a value of the target register according to the offset value.

[0012] In still another aspect, the embodiments of the present application further disclose an electronic device, which comprises a memory and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by one or more processors to implement the foregoing exception recovery method.

[0013] The embodiments of the present application further disclose a readable storage medium, which enables an electronic device to implement the foregoing exception recovery method when instructions in the storage medium are executed by a processor of the electronic device.

[0014] The embodiments of the present application have the following advantages:

[0015] In the process of implementing the exception recovery, the embodiments of the present application can first determine a source instruction and a basic block corresponding to a target instruction triggering an exception in a source program and mark a target position corresponding to the source instruction in the source program in a case where the exception occurs, and then determine an offset value corresponding to a target register according to the target position and a register delay calculation algorithm, wherein the target register comprises registers corresponding to instructions between a start position of the basic block and the target position in a correction range of the register delay calculation algorithm, and finally correct a value of the target register according to the offset value. Thus, the embodiments of the present application can solve the problem of incorrect register values caused by register delay optimization in the process of binary translation in a special case such as an exception or self-modifying code, and improve the exception recovery efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the description of the embodiments of the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and all other drawings obtained by those of ordinary skill in the art without creative labor based on these drawings are within the protection scope of the present application.

[0017] Figure 1 is a dynamic binary translator running flow of the present application Figure 1 ;

[0018] Figure 2 is a dynamic binary translation flow diagram of the present application Figure 2 ;

[0019] Figure 3 is a step flow diagram of an embodiment of the exception recovery method of the present application

[0020] Figure 4 is a flow diagram of the instruction sequence execution in an exception of the present application

[0021] Figure 5 is a flow diagram of the instruction sequence execution in a normal case of the present application

[0022] Figure 6 is a flow diagram of the register delay calculation optimization recovery in an exception of the present application

[0023] Figure 7 is a structure block diagram of an exception recovery device of the present application

[0024] Figure 8 is a structure block diagram of an electronic device for exception recovery of the present application DETAILED DESCRIPTION

[0025] The technical solutions in the embodiments of the present application will be described clearly and completely below with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor are within the protection scope of the present application.

[0026] There are many differences in the instructions supported by the hardware design of different Instruction Set Architecture (ISA), which leads to the incompatibility of the executable file compiled based on one ISA and other platforms.

[0027] Binary translation technology enables a program compiled based on one architecture to run on another architecture hardware platform, and achieves the function of making executable files cross-ISA compatible. Figure 1 As shown in Figure 1 A flowchart of dynamic binary translation provided by an embodiment of the present application is shown in Figure 1 Dynamic binary translation adopts the mode of "translation while running", and translates instructions of a guest architecture into host architecture instructions and runs them at runtime. After the translator reads a binary file, it usually translates and executes according to the granularity of a translation block (TB). Before executing a basic block, it first searches in a code cache area. If a translated basic block is found, the code block can be executed. If the basic block is not found in the code cache area, translation is performed, the translated code is put into the code cache area, and then the basic block is executed. After a basic block is executed, the next basic block is searched in the code cache area, and the cycle continues until the program execution ends.

[0028] With the continuous improvement of microprocessor performance, the feasibility of running a source program of another CPU architecture under a certain central processing unit (CPU) architecture through binary translation is getting stronger and stronger, which makes the binary translation technology develop more. However, the technology still has technical problems such as low translation efficiency and too many redundant operations. When translating from a complex instruction set computer (CISC) to a reduced instruction set computer (RISC), the instruction function of the CISC architecture is powerful, and a single instruction can perform complex operations such as memory access arithmetic operations and logical operations. The RISC architecture tends to use simple fixed-length instructions, and each instruction usually only performs a simple operation. In order to achieve complex functions, multiple instructions need to be combined to achieve them under the RISC architecture. Therefore, for binary translators from CISC architecture to RISC, the instructions of the original instruction set will be converted into more instructions. In order to solve the problem of low efficiency of binary translators, many optimization methods have been proposed from various angles, such as flag information delay generation, instruction elimination, and register value delay calculation, to reduce the generation of instructions as much as possible.

[0029] Binary translation technology can enable programs compiled based on one architecture to run on another architecture hardware platform, enabling executable files to cross ISA compatibility, which is of great significance for migrating the software ecosystem of mature CPU architecture to new CPU architecture, promoting the software ecosystem construction and promoting the development of new architecture. In binary translation, the architecture hardware platform actually running the program is referred to as the HOST platform, and the platform of the architecture simulated by the binary translator is referred to as the GUEST platform, such as running x86 programs on the LoongArch platform. In the embodiments of the present application, the HOST platform is LoongArch, and the GUEST platform is x86.

[0030] As shown in Figure 2 , Figure 2 A flowchart of a dynamic binary translation process provided by an embodiment of the present application is shown in Figure 2 , which specifically includes steps 201 to 204.

[0031] Step 201, the target program reads the executable program of the client platform.

[0032] In the embodiments of the present application, in the dynamic binary translation process, the target program reads the executable program of the client platform.

[0033] Step 202, basic block lookup is performed in the code cache area.

[0034] After the target program reads the executable program of the client platform, basic block lookup is performed in the code cache area.

[0035] Step 203, in the case where there is an already translated basic block, the code block is executed through the translated basic block.

[0036] After the basic block lookup in the code cache area, in the case where there is an already translated basic block, the code block is executed through the translated basic block.

[0037] Step 204, in the case where there is no already translated basic block, basic block code translation is performed, the translated basic block is stored in the code cache area, and the code block is executed.

[0038] After the basic block lookup in the code cache area, in the case where there is no already translated basic block, basic block code translation is performed, the translated basic block is stored in the code cache area, and the code block is executed.

[0039] The optimization of the register delay computation class faces a problem, because the dynamic binary translation cannot always complete the execution of a basic block completely when executing the translated basic block. Some special cases can cause the execution flow to jump to an exception handling function at an instruction in the middle of a basic block, including but not limited to the generation of an exception, the occurrence of self-modification, and the like. The exception handling function needs to restore the context at this time, including the values of the registers. However, the principle of the optimization of the register delay computation class is to reduce / merge the computation of the values of some registers in a basic block, and it only guarantees that the values of all the registers are consistent with the expected values after the complete execution of a basic block. Therefore, if an exception occurs when an instruction is executed, a corresponding mechanism is needed to restore the values of the registers to avoid errors in future program execution.

[0040] The prior art exception recovery method includes reserving the difference information generated by the instruction optimization in the instruction optimization process, and implementing instruction correction according to the recorded difference information when an exception occurs or the like, so as to improve the correctness of the execution of the translated program. In the process of translating a basic block, difference information generated between the optimized instruction sequence and the instruction sequence before optimization is recorded in a specified area of the basic block, and position information corresponding to the difference information is recorded, the position information including the entry address of the optimized instruction and the like.

[0041] However, the exception recovery method reserves the difference information generated by the instruction optimization in the instruction optimization process for each TB, but not every TB will have an exception, which wastes time and space.

[0042] In order to solve the problem that the binary translation system in the prior art has incorrect register values caused by optimization in special cases such as exceptions and self-modification code, with reference to Figure 3 , a step flowchart of an embodiment of an exception recovery method of the present application is shown, which is applied to a binary translation system, and the method can specifically include the following steps:

[0043] Step 101, in the case of an exception, determining the source instruction and the basic block corresponding to the target instruction triggering the exception in the source program, and marking the target position of the source instruction in the source program.

[0044] Step 102, determining the offset value of the target register according to the target position and the register delay computation algorithm; the target register includes the registers corresponding to each instruction between the start position of the basic block and the target position in the range of the modification of the register delay computation algorithm.

[0045] Step 103, modifying the value of the target register according to the offset value.

[0046] The abnormality recovery method provided by the embodiment of the present application can be applied to a binary translation system, and the binary translation system is used for translating a source program in a guest into a target program in a host.

[0047] It should be noted that the source program is a binary code. In the translation process, the binary translation system can only obtain the binary code (i.e., the source program) after the compilation processing, and the binary code is subjected to the disassembly processing to obtain the code at the assembly level. At this time, the code cannot be cut into units based on the functions in the source program. Generally, the binary translation system cuts the obtained source program into one basic block after another, and the last instruction of each basic block is generally a jump instruction in the source program. The binary translation system works based on the basic block as the basic unit.

[0048] The corresponding source instruction in the source program refers to the instruction before the translation, and the source instruction is a basic unit in the source program, which can be an assignment statement, a function call, a conditional judgment, etc.

[0049] The source instruction is a basic component for building the source program, and developers can create a program with complex functions and rigorous logic by combining these instructions.

[0050] It should be noted that the specific form and meaning of the source instruction can be different in different programming languages and programming paradigms. For example, in a functional programming language, the source instruction can involve more function definitions and calls, and in an object-oriented programming language, it can involve more class and object operations.

[0051] The target program refers to the program generated after the translation of the source program in the guest, which can be directly executed on the host.

[0052] In the embodiment of the present application, the abnormal situation can include the generation of an exception, the occurrence of self-modification, etc.

[0053] The technical problem to be solved by the present application is that, in the binary translation system, due to the instruction optimization, especially the instruction optimization of the register delay calculation, the register value is incorrect due to the optimization in the special situation such as the occurrence of the exception and the self-modification code.

[0054] In view of the problem of high instruction inflation rate when translating from a complex instruction set to a reduced instruction set, the binary translator often adopts some instruction optimization algorithms to reduce the number of translated instructions, for example, performing delay calculation on a certain register in a basic block to reduce the number of generated code instructions after the translation, thereby improving the running efficiency of the binary translator. However, the value of the delay calculation register cannot provide an accurate register value in some special situations, resulting in program errors.

[0055] In abnormal cases, the control flow of the instructions is transferred to the logic of exception handling for execution, and after the exception handling is completed, the original instruction sequence can not be returned to continue execution. Therefore, the translator needs to accurately restore the register state at the time when the special case occurs.

[0056] As shown in Figure 4 , Figure 4 A flowchart of the execution of an instruction sequence in an abnormal case is shown, and the instructions are executed in order according to the instruction sequence.

[0057] As shown in Figure 5 , Figure 5 A flowchart of the execution of an instruction sequence in a normal case is shown, and in the process of executing the instruction sequence, when an exception handling case is encountered, the control flow of the instruction c is transferred to the exception handling, and after the exception handling is completed, the instruction d below the instruction c is not continued to be executed, but jumps to the instruction x for subsequent execution. If the basic block is optimized by the register delay calculation algorithm, the value of the register can not be calculated in real time when the instruction c is executed, and when the instruction x sequence is executed subsequently, an error register state is obtained, which in turn causes the program execution error.

[0058] Due to the register delay calculation optimization, the value of the register at the time of the exception can not be calculated in real time, and if the current one possible error register state is directly used, the program execution error will be caused.

[0059] The target instruction triggering the exception refers to the host instruction triggering the exception in the target program. It can be understood that in the case of an exception, the basic block corresponding to the target instruction can be determined by obtaining the instruction address of the target instruction triggering the exception.

[0060] Exemplarily, the binary translation system can capture the exception handling, and determine the address required to modify the instruction triggering the exception through the signal processing function corresponding to the segmentation violation signal (SIGSEGV).

[0061] Note that the instruction address refers to the address of the CPU instruction that triggered the exception, which is usually stored in the program counter (PC) of the CPU. When a signal is sent to a user program, the instruction address itself is not directly passed through the data structure used by the Linux system to store signal-related details. However, the user program can obtain the instruction address through other means, for example, in the signal handling function, the current context information can be obtained through a structure used to save the context information of the user thread, such as the ucontext_t structure, which contains the value of the program counter (PC).

[0062] If a system call for handling signals is used, such as the sigaction system call, a signal handling function is registered, and a flag for specifying whether the signal handling function receives detailed information about the signal is enabled, such as the SA_SIGINFO flag in the sigaction system call, then the signal handling function will receive a parameter containing context information from which the instruction address of the exception can be extracted.

[0063] When the CPU detects an exception, the execution of the current program is suspended, and the operating system kernel saves the CPU context at the time of the exception, such as the register state, program counter (PC), etc. Further, the kernel will call the corresponding exception handling program according to the exception type. The kernel usually returns the instruction address of the exception (i.e., the value of the program counter PC) to the user program for debugging or processing.

[0064] When an exception occurs, the corresponding TB basic block can be found according to the target instruction address that triggered the exception. Specifically, the operating system kernel first returns the target instruction address that triggered the exception, which is the virtual address of the Guest, and then converts the Guest virtual address to the Host virtual address, which is usually done by the memory management module in the binary translation system. The binary translation system maintains a TB cache for storing translated TB basic blocks. Through the Host virtual address, the corresponding TB basic block can be found in the TB cache.

[0065] Exemplarily, it is assumed that a Guest program runs in a binary translation system, and the CPU triggers an exception in the case that the Guest program executes an illegal instruction. At this time, the operating system kernel saves the context and returns the exception instruction address (such as 0x4000). The binary translation system converts the virtual address 0x4000 of the Guest into the virtual address of the Host; and searches for a TB basic block containing 0x4000 in the TB cache. It is assumed that the start address of the found TB basic block is 0x3FF0, and the end address is 0x4010. The instructions in the TB basic block are analyzed, and the illegal instruction is found and repaired. In this way, the exception can be efficiently handled in the virtualization environment, and the correct execution of the Guest program is ensured.

[0066] In the embodiment of the present application, the offset values of the instructions between the first instruction in the basic block corresponding to the target instruction triggering the exception and the target position can be calculated based on the register delay calculation algorithm, and the offset values corresponding to the instructions between the first instruction in the basic block and the target position are accumulated to obtain the target offset value corresponding to the target register.

[0067] Finally, the value of the target register corresponding to the target instruction triggering the exception is corrected by using the target offset value. For example, the value of the target register is obtained by adding the register value and the target offset value, such as: the optimization of the sp register, that is, sp = sp + the register optimization operation in set A.

[0068] In the embodiment of the present application, the process of determining the offset value of each instruction in the basic block according to the register delay calculation algorithm can be described by Table 1, as shown in Table 1:

[0069] Table 1

[0070]

[0071] As shown in Table 1, taking the source program including x86 instructions and the target program including RISC-V instructions as an example, the instruction sequence in x86 in the table includes: poprbx; poprbp; popr12; ret; this instruction sequence usually appears at the tail of a function, and is used to restore the previously saved register values before the function returns. First, the value of the rbx register is restored from the stack. Then, the value of the rbp register is restored from the stack, which usually means that the stack frame of the current function will be destroyed, because rbp is the stack frame pointer. Next, the value of the r12 register is restored from the stack. Finally, the ret instruction is executed, the return address is popped from the stack and jumps to the address, thereby returning to the caller.

[0072] The translation of the above x86 instruction sequence into a RISC-V instruction sequence is: lw x10, 0(x2) for loading data from the top of the stack into register x10 (corresponding to rbx); addi x2, x2, 4 for moving the stack pointer up by 4 bytes; lw x8, 0(x2) for loading data from the top of the stack into register x8 (corresponding to rbp); addi x2, x2, 4 for moving the stack pointer up by 4 bytes; lw x12, 0(x2) for loading data from the top of the stack into register x12 (corresponding to r12); addi x2, x2, 4 for moving the stack pointer up by 4 bytes; and jr x1 for returning to the address in the link register.

[0073] The instruction sequence optimized by the register delay calculation is: lw x10, 0(x2) for loading data from the top of the stack into register x10; lw x8, 4(x2) for loading data from the top of the stack into register x8; lw x12, 8(x2) for loading data from the top of the stack into register x12; addi x2, x2, 12 for moving the stack pointer up by 12 bytes; and jr x1 for returning to the address in the link register.

[0074] For example, according to the register delay calculation algorithm, it can be determined that the offset values of the stack pointer sp of the three pop instructions are all 4, that is, when the ret instruction is reached, the offset value of the stack pointer sp is 12, and the semantics of the ret instruction itself requires shifting the stack pointer, that is, sp+4, so the stack pointer sp+16 needs to be added in the ret instruction.

[0075] In the embodiment of the present application, in the process of performing exception recovery, in the case of an exception, the target instruction triggering the exception, the corresponding source instruction and the basic block in the source program are first determined, and the target position corresponding to the source instruction in the source program is marked; then, according to the target position and the register delay calculation algorithm, the offset value corresponding to the target register is determined; the target register includes the registers corresponding to each instruction between the start position and the target position of the basic block within the correction range of the register delay calculation algorithm; finally, the value of the target register is corrected according to the offset value. Thus, in the case of an exception, self-modifying code, etc., the problem of incorrect register values caused by register delay optimization during binary translation can be solved, and the efficiency of exception recovery can be improved.

[0076] Further, in the embodiment of the present application, when the offset value corresponding to the target register is determined according to the target position and the register delay calculation algorithm, the exception recovery method further includes steps 1021 to 1022:

[0077] Step 1021, according to the target position and the register delay calculation algorithm, determining the offset value corresponding to each instruction between the first instruction of the basic block corresponding to the source instruction and the target position.

[0078] Step 1022, accumulating the offset value corresponding to each instruction between the starting position of the basic block and the first source instruction, to obtain the offset value of the first register corresponding to the first source instruction; the first source instruction is any instruction between the starting position of the basic block and the target position.

[0079] The basic block corresponding to the source instruction refers to the basic block to which the target instruction triggering the exception belongs, which can be determined according to the address of the host instruction, for example: the TB basic block corresponding to the host instruction can be determined according to the address of the host instruction.

[0080] Exemplarily, starting from the first instruction (starting position) of the basic block, to the Nth instruction, each Guest instruction is scanned one by one, that is, all instructions between the first instruction of the basic block and the target position are traversed.

[0081] The offset value corresponding to each instruction can be determined by the register delay calculation algorithm.

[0082] The accumulation process refers to accumulating the offset value corresponding to each instruction between the starting position of the basic block and the first source instruction.

[0083] Exemplarily, assuming that the offset value corresponding to the starting position of the basic block is A, the offset value corresponding to the second instruction is B,..., and the offset value corresponding to the first source instruction is X, then the offset value corresponding to each instruction between the first instruction of the basic block and the first source instruction is accumulated, and the target offset value corresponding to the target register can be obtained as A+B+…+X.

[0084] The offset value of the first register corresponding to the first source instruction can be obtained by accumulating the offset value corresponding to each instruction between the starting position of the basic block and the first source instruction.

[0085] In the embodiment of the application, in the process of determining the target offset value, the binary translation system can first determine the basic block corresponding to the target instruction triggering the exception, and then analyze and process each instruction between the first instruction of the basic block and the target position by the register delay calculation algorithm, to obtain the offset value corresponding to each instruction between the first instruction of the basic block and the target position; and then accumulating the offset value corresponding to each instruction, and the target offset value corresponding to the target register can be determined.

[0086] Further, in the embodiment of the present application, when the offset values corresponding to each instruction between the first instruction of the basic block corresponding to the source instruction and the target position are determined according to the target position and the register delay calculation algorithm, the abnormal recovery method further comprises steps 10211 to 10212:

[0087] Step 10211, judging whether there is a repair identifier at the target position of the basic block; the repair identifier is used to indicate that the register delay calculation algorithm has triggered the repair processing of the registers corresponding to each instruction between the first instruction of the basic block and the target position.

[0088] Step 10212, in the case that there is no repair identifier between the first instruction of the basic block and the target position, determining the offset values corresponding to each instruction between the first instruction of the basic block and the target position according to the register delay calculation algorithm.

[0089] The position of the current instruction contains a repair identifier for recovering a certain register delay calculation value, which means that the register delay calculation algorithm can recover the value of a certain register at any instruction in the TB, for example, in the case that there is a repair identifier in the current instruction, the register delay calculation value corresponding to the instruction can be recovered based on the repair identifier.

[0090] In the embodiment of the present application, in the process of determining the offset values corresponding to each instruction between the first instruction of the basic block corresponding to the source instruction and the target position according to the target position and the register delay calculation algorithm, since the register delay calculation algorithm itself can also recover the value of a certain register at a certain instruction in the basic block, in the process of analyzing and processing each instruction between the first instruction of the basic block and the target position, the binary translation system can also judge whether there is a repair identifier at the target position of the basic block; in the case that there is no repair identifier between the first instruction of the basic block and the target position, the binary translation system can determine the offset values corresponding to each instruction between the first instruction of the basic block corresponding to the source instruction and the target position according to the register delay calculation algorithm.

[0091] Further, the abnormal recovery method provided by the embodiment of the present application can further comprise the following steps:

[0092] Step 10213, in the case that there is a repair identifier between the first instruction of the basic block and the target position, clearing the offset values corresponding to the registers corresponding to each instruction between the first instruction of the basic block and the target position, and analyzing the next instruction of the target instruction.

[0093] Exemplarily, in the case that there is a repair identifier between the first instruction of the basic block and the target position, the offset values corresponding to each instruction between the first instruction of the basic block stored in set A and the instruction with the repair identifier are cleared.

[0094] In the embodiment of the present application, in the process of determining the offset values corresponding to each instruction between the first instruction of the basic block and the target position of the source instruction according to the target position and the register delay calculation algorithm, since the register delay calculation algorithm itself can also restore the value of a certain register at a certain instruction in the basic block, in the process of analyzing and processing each instruction between the first instruction of the basic block and the target position one by one, the binary translation system can also determine whether there is a repair identifier at the target position of the basic block; in the case that there is a repair identifier between the first instruction of the basic block and the target position, the binary translation system can first clear the offset values corresponding to the repair identifier positions within the modification range of the register delay calculation algorithm; and then determine the offset values corresponding to each instruction between the instruction with the repair identifier and the target position according to the register delay calculation algorithm.

[0095] Further, in the embodiment of the present application, in the process of determining the offset values corresponding to each instruction between the first instruction of the basic block and the target position of the source instruction according to the target position and the register delay calculation algorithm, the exception restoration method further comprises steps 10214 to 10217:

[0096] Step 10214, for the basic block corresponding to the target instruction triggering the exception, determining the serial number corresponding to each instruction in the basic block according to the arrangement order of the instructions in the basic block, and determining the target serial number corresponding to the instruction in the target position.

[0097] Step 10215, determining whether the serial number corresponding to the ith instruction in the basic block is less than or equal to the target serial number; the initial value of i is 1, and i is a positive integer.

[0098] Step 10216, in the case that the serial number corresponding to the ith instruction in the basic block is less than or equal to the target serial number, determining the offset value corresponding to the ith instruction through the register delay calculation algorithm.

[0099] The arrangement order of the instructions in the basic block refers to the instruction sequence, for example, the instruction sequence is inst a, inst b, inst c, …, etc., which is not limited in the embodiment of the present application.

[0100] Exemplarily, the serial number corresponding to each instruction in the basic block refers to that the serial number corresponding to inst a is 1, the serial number corresponding to inst b is 2, the serial number corresponding to inst c is 3, …, which is not limited in the embodiment of the present application.

[0101] The target sequence number corresponding to the instruction in the target position refers to a target sequence number corresponding to the target instruction triggering the exception, for example, in a case where the target instruction triggering the exception is inst c, the target sequence number corresponding to the target instruction triggering the exception is 3, and in an embodiment of the present application, no limitation is made.

[0102] The sequence number corresponding to the ith instruction in the basic block refers to a sequence number determined by the arrangement order of the ith instruction in the basic block, for example, the sequence number corresponding to the ith instruction in the basic block can be 5, or 10, etc.

[0103] The offset value corresponding to the ith instruction can be determined by the register delay calculation algorithm.

[0104] In a case where the sequence number corresponding to the ith instruction in the basic block is greater than the target sequence number, it is determined that the offset values corresponding to the target registers are all calculated.

[0105] In an embodiment of the present application, in the process of determining the offset values corresponding to each instruction between the first instruction of the basic block corresponding to the source instruction and the target position according to the target position and the register delay calculation algorithm, the binary translation system can first determine the sequence number corresponding to each instruction in the basic block, and determine the target sequence number corresponding to the instruction in the target position; and then by comparing the sequence number corresponding to the ith instruction in the basic block with the target sequence number, the offset values corresponding to each instruction are determined; in a case where the sequence number corresponding to the ith instruction in the basic block is less than or equal to the target sequence number, the offset value corresponding to the ith instruction can be determined by the register delay calculation algorithm; in a case where the sequence number corresponding to the ith instruction in the basic block is greater than the target sequence number, it is determined that the offset values corresponding to the target registers are all calculated.

[0106] Further, in an embodiment of the present application, when the value of the target register is modified according to the offset value, the exception recovery method further includes steps 1031 to 1033:

[0107] Step 1031, obtaining the register values corresponding to each instruction between the starting position of the basic block and the target position.

[0108] Step 1032, adding the register value and the offset value to obtain the modified register value for the first register; the first register is any register in the target register.

[0109] Step 1033, replacing the register value corresponding to the first register with the modified register value.

[0110] In the process of modifying the value of the target register according to the offset value, the binary translation system can obtain the register values corresponding to the instructions between the start position and the target position of the basic block, and then add the register value and the offset value to obtain the modified register value for the first register, the first register being any register in the target register, and finally replace the register value corresponding to the first register with the modified register value.

[0111] For example, the process of adding the register value and the offset value to obtain the modified register value for the first register refers to the process of adding the value of a certain register to the offset value stored in set A, for example, the optimization of the sp register, which is sp = sp + the register optimization operation in set A.

[0112] For example, replacing the register value corresponding to the first register with the modified register value refers to replacing the register value corresponding to the first register with the value of the sp + the register optimization in set A.

[0113] In the embodiment of the application, in the process of modifying the value of the target register according to the offset value, the binary translation system can add the register value and the offset value to obtain the modified register value for the first register, and replace the register value corresponding to the first register with the modified register value.

[0114] For example, the processing process of the binary translation system for the optimization of the sp register can be sp = sp + the register optimization operation in set A.

[0115] Further, in the embodiment of the application, when the abnormality occurs, the source instruction corresponding to the target instruction triggering the abnormality in the source program and the basic block are determined, and the target position corresponding to the source instruction in the source program is marked, the abnormality recovery method further includes steps 1011 to 1013:

[0116] Step 1011, when the abnormality occurs, the instruction address triggering the abnormality is determined.

[0117] Step 1012, based on the instruction address, the basic block corresponding to the target instruction triggering the abnormality is determined.

[0118] Step 1013, based on the instruction address, the source instruction corresponding to the target instruction triggering the abnormality in the source program is determined in the basic block, and the target position corresponding to the source instruction in the source program is marked.

[0119] For example, the address of the target instruction triggering the abnormality can be the address of the host instruction.

[0120] The basic block corresponding to the target instruction that triggered the exception refers to the basic block to which the target instruction that triggered the exception belongs, determined by the address of the host instruction.

[0121] For example, the source instruction that triggers the exception corresponds to the Guest instruction in the source program.

[0122] For example, marking the target location corresponding to the source instruction in the source program can be a process of marking the position number of the Guest instruction.

[0123] In this embodiment of the invention, when an exception occurs, in the process of determining the source instruction and basic block corresponding to the target instruction that triggered the exception in the source program, and marking the target position corresponding to the source instruction in the source program, the binary translation system can first determine which source instruction in the basic block is abnormal based on the address of the target instruction that triggered the exception, and finally mark the target position corresponding to the source instruction in the source program.

[0124] In another embodiment of the present invention, at the moment of an anomaly, starting from the first instruction in TB and ending with the instruction in which the anomaly occurred, an algorithm that optimizes the register delay calculation is used to scan the instruction interval to obtain a value of the register that was delayed and not calculated, and then the register value at the moment of the anomaly is corrected.

[0125] like Figure 6 As shown, Figure 6 The figure illustrates a flowchart of register delay calculation optimization and recovery in the event of an anomaly, according to an embodiment of this application. As shown, when an anomaly occurs, the relevant register delay calculation (TB) is first obtained based on the instruction that triggered the anomaly. Starting with the first instruction in the TB and ending with each instruction that triggered the anomaly, the Guest instructions are processed one by one to obtain the offset value for the delay calculation of each register at the time of the anomaly. Then, the registers are corrected. This register delay calculation optimization and recovery process specifically includes steps 301 to 308:

[0126] Step 301: In the event of an exception, determine the basic block corresponding to the target instruction that triggered the exception.

[0127] Obtain the exception TB based on the host command that triggered the exception.

[0128] When an exception occurs, the corresponding TB basic block is determined based on the address specified by the host instruction.

[0129] Step 302: Obtain the instruction number in the basic block that triggered the exception, and mark it as N.

[0130] The host instruction triggering the exception is the i-th Guest instruction in the TB, and the number is marked as N.

[0131] Step 303, initialize the register delay computation offset value set A to 0.

[0132] Initialize the register delay computation offset value set to 0, assuming that the set is marked as A.

[0133] Step 304, start traversing from the first instruction in the basic block corresponding to the target instruction triggering the exception.

[0134] Starting from the first instruction in the basic block, to the N-th instruction, scan each Guest instruction one by one, since the optimization algorithm itself can also restore the value of a register at a certain instruction in the TB.

[0135] Step 305, determine whether the sequence number corresponding to the i-th instruction in the basic block is less than or equal to the sequence number of the instruction triggering the exception.

[0136] If yes, execute step 306, otherwise execute step 307.

[0137] Step 306, call the optimization algorithm to scan the instruction to obtain the offset value of all register delay computations corresponding thereto.

[0138] Step 307, restore the offset value corresponding to the target instruction triggering the exception according to set A.

[0139] After scanning all instructions, restore the values of all registers according to the delay computation offset values of the respective registers recorded in set A.

[0140] Step 308, add the set of offset values to set A.

[0141] It should be noted that the register delay computation algorithm further includes: it can be determined whether there is a repair identifier in each instruction; the repair identifier is used to indicate that the register delay computation algorithm has triggered the repair processing of the registers corresponding to the instructions between the first instruction of the basic block and the target position, and the repair identifier can be in any instruction between the first instruction of the basic block and the target position. If the repair identifier exists, the value of the corresponding register in set A is cleared, and then the next instruction is scanned; otherwise, the register delay computation offset value of the current instruction is calculated and added to the corresponding register offset in set A.

[0142] The present application aims at the problem of incorrect register values caused by optimization of instructions, especially register delay calculation, in a binary translation system, especially in special cases such as occurrence of exceptions and self-modifying code. A scanning method is proposed. The method starts from the first instruction in a TB at the time of occurrence of an exception, ends at the instruction of occurrence of the exception, and uses the algorithm of the optimization of register delay calculation itself to scan the instruction interval to obtain a value of a register that is not calculated due to delay, and then corrects the register value at the time of the exception.

[0143] The present application provides a scanning algorithm for restoring a register field at the time of occurrence of an exception of a register delay calculation type optimization algorithm. The algorithm takes a basic block as a unit, starts from the first instruction in a TB at the time of occurrence of an exception, ends at the instruction of occurrence of the exception, and uses the algorithm of the optimization of register delay calculation itself to scan the instruction interval to obtain a value of a register that is not calculated due to delay, and then corrects the register value at the time of the exception.

[0144] In summary, the embodiment of the present application provides an exception recovery method. In the process of performing exception recovery, in the case of occurrence of an exception, the source instruction and the basic block corresponding to the target instruction triggering the exception in the source program can be determined first, and the target position of the source instruction in the source program is marked. Then, the offset value corresponding to the target register can be determined according to the target position and the register delay calculation algorithm. The target register includes the registers corresponding to each instruction between the start position of the basic block and the target position in the register delay calculation algorithm correction range. Finally, the value of the target register can be corrected according to the offset value. Thus, in special cases such as occurrence of an exception and self-modifying code, the problem of incorrect register values caused by register delay optimization in the binary translation process can be solved, and the exception recovery efficiency can be improved.

[0145] It should be noted that, for the method embodiment, in order to simply describe, all are described as a series of action combinations, but those skilled in the art should know that the embodiment of the present application is not limited by the action sequence described, because according to the embodiment of the present application, certain steps can be performed in other order or simultaneously. Secondly, those skilled in the art should know that the embodiments described in the specification all belong to preferred embodiments, and the actions involved are not necessarily necessary for the embodiment of the present application.

[0146] Device embodiment

[0147] Reference Figure 7 Fig. 1 shows a structure block diagram of an exception recovery device of the present application, which is applied to a binary translation system for translating a source program in a client into a target program in a host machine. The exception recovery device 60 can specifically include:

[0148] The determining unit 601 is configured to, in the case where an exception occurs, determine a target instruction triggering the exception corresponding source instructions and a basic block in the source program, and mark a target position corresponding to the source instructions in the source program; determine offset values corresponding to target registers according to the target position and a register delay calculation algorithm; the target registers include registers corresponding to each instruction between a start position of the basic block and the target position within a correction range of the register delay calculation algorithm.

[0149] The correcting unit 602 is configured to correct values of the target registers according to the offset values.

[0150] In an optional embodiment of the present application, the determining unit is specifically configured to:

[0151] determine offset values corresponding to each instruction between a first instruction of the basic block corresponding to the source instructions and the target position according to the target position and the register delay calculation algorithm;

[0152] accumulate the offset values corresponding to each instruction between the start position of the basic block and the first source instruction to obtain an offset value of a first register corresponding to the first source instruction; the first source instruction is any instruction between the start position of the basic block and the target position.

[0153] In an optional embodiment of the present application, the determining unit is specifically configured to:

[0154] determine whether a repair identifier exists at the target position of the basic block; the repair identifier is used to indicate that the register delay calculation algorithm has triggered repair processing of registers corresponding to each instruction between the first instruction of the basic block and the target position;

[0155] in the case where no repair identifier exists between the first instruction of the basic block and the target position, determine offset values corresponding to each instruction between the first instruction of the basic block and the target position according to the register delay calculation algorithm.

[0156] In an optional embodiment of the present application, the determining unit is further configured to:

[0157] in the case where the repair identifier exists between the first instruction of the basic block and the target position, clear the offset values corresponding to the registers corresponding to each instruction between the first instruction of the basic block and the target position, and analyze a next instruction of the target instruction.

[0158] In an optional embodiment of the present application, the determining unit is further configured to:

[0159] determining a serial number corresponding to each instruction in the basic block according to the arrangement order of the instructions in the basic block, and determining a target serial number corresponding to the instruction in the target position;

[0160] determining whether the serial number corresponding to the ith instruction in the basic block is less than or equal to the target serial number; the initial value of i is 1, and i is a positive integer;

[0161] in the case that the serial number corresponding to the ith instruction in the basic block is less than or equal to the target serial number, determining the offset value corresponding to the ith instruction through a register delay calculation algorithm;

[0162] in the case that the serial number corresponding to the ith instruction in the basic block is greater than the target serial number, determining that the offset values corresponding to the target registers are all calculated.

[0163] In an optional embodiment of the present application, the correction unit is further configured to:

[0164] obtaining the register value corresponding to each instruction between the start position and the target position of the basic block;

[0165] adding the register value and the offset value to obtain a corrected register value for the first register; the first register is any register in the target register;

[0166] replacing the register value corresponding to the first register with the corrected register value.

[0167] In an optional embodiment of the present application, the determination unit is further configured to:

[0168] in the case that an exception occurs, determining the instruction address of the instruction that triggers the exception;

[0169] based on the instruction address, determining the basic block corresponding to the target instruction that triggers the exception;

[0170] based on the instruction address, determining the source instruction corresponding to the target instruction that triggers the exception in the source program in the basic block, and marking the target position corresponding to the source instruction in the source program.

[0171] In summary, the embodiment of the present application provides an abnormality recovery device, which can, in the process of performing abnormality recovery, in the case of abnormality, first determine the source instruction and the basic block corresponding to the target instruction triggering the abnormality in the source program, and mark the target position corresponding to the source instruction in the source program; then determine the offset value corresponding to the target register according to the target position and the register delay calculation algorithm; the target register includes the registers corresponding to each instruction between the starting position of the basic block and the target position in the range of correction of the register delay calculation algorithm; finally, the value of the target register is corrected according to the offset value. Thus, in the case of abnormality, self-modifying code, etc., the problem of incorrect register value caused by register delay optimization in the binary translation process can be solved, and the abnormality recovery efficiency is improved.

[0172] For the embodiment of the abnormality recovery device, it is basically similar to the method embodiment, so the description is relatively simple, and the related parts are described in the part of the method embodiment.

[0173] Each embodiment in the present specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same and similar parts between the embodiments can be referred to each other.

[0174] The embodiment of the present application provides an electronic device for abnormality recovery, which is applied to a binary translation system for translating a source program in a client into a target program in a host computer. The electronic device comprises a memory and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by one or more processors. The one or more programs include instructions for determining the source instruction and the basic block corresponding to the target instruction triggering the abnormality in the source program, and marking the target position corresponding to the source instruction in the source program in the case of abnormality; determining the offset value corresponding to the target register according to the target position and the register delay calculation algorithm; the target register includes the registers corresponding to each instruction between the starting position of the basic block and the target position in the range of correction of the register delay calculation algorithm; and correcting the value of the target register according to the offset value.

[0175] Figure 8 Fig. 1 is a structural block diagram of an electronic device 300 for abnormality recovery according to an exemplary embodiment. For example, the electronic device 300 can be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0176] Reference Signs List Figure 8The electronic device 300 can include one or more of the following components: a processing component 302, a memory 304, a power supply component 306, a multimedia component 308, an audio component 310, an input / output (I / O) interface 312, a sensor component 314, and a communication component 316.

[0177] The processing component 302 usually controls overall operations of the electronic device 300, such as operations associated with displaying, making phone calls, data communications, camera operations and recording operations. The processing component 302 can include one or more processors 320 to execute instructions to complete all or part of steps of the above methods. In addition, the processing component 302 can include one or more modules to facilitate

[0178] The memory 304 is configured to store various types of data to support operations of the electronic device 300. Examples of these data include instructions for any application or method operating on the electronic device 300, contact data, phonebook data, messages, pictures, videos, etc. The memory 304 can be implemented by any type of volatile or non-volatile storage devices or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic or optical disk.

[0179] The power supply component 306 supplies electrical power for the various components of the electronic device 300. The power supply component 306 can include a power supply management system, one or more power supplies, and other components associated with generating, managing and distributing electrical power for the electronic device 300.

[0180] The multimedia component 308 includes a screen to provide an output interface between the electronic device 300 and a user. In some embodiments, the screen can include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen can be implemented as a touch screen to receive input signals from a user. The touch panel includes one or more touch sensors to sense touch, slide and gesture on the touch panel. The touch sensor can not only sense a boundary of a touching or sliding action, but also detect duration and pressure related to the touching or sliding action. In some embodiments, the multimedia component 308 includes a front camera and / or a rear camera. When the electronic device 300 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera can receive external multimedia data. Each of the front camera and the rear camera can be a fixed optical lens system or have a focal length and optical zoom capability.

[0181] The audio component 310 is configured to output and / or input audio signals. For example, the audio component 310 includes a microphone (MIC) to receive an external audio signal when the electronic device 300 is in an operating mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signal can be further stored in the memory 304 or transmitted via the communication component 316. In some embodiments, the audio component 310 further includes a speaker to output audio signals.

[0182] The I / O interface 312 provides an interface between the processing component 302 and peripheral interface modules, which can be a keypad, a click wheel, buttons, and the like. The buttons can include, but are not limited to, a home button, a volume button, a start button, and a lock button.

[0183] The sensor component 314 includes one or more sensors to provide various state assessments for the electronic device 300. For example, the sensor component 314 can detect an open / closed state of the electronic device 300, relative positioning of components, such as a display and a keypad of the electronic device 300, a change in position of the electronic device 300 or a component of the electronic device 300, presence or absence of user contact with the electronic device 300, an orientation or acceleration / deceleration of the electronic device 300, and a temperature change of the electronic device 300. The sensor component 314 can include a proximity sensor configured to detect presence of a nearby object without any physical touch. The sensor component 314 can further include a light sensor such as a CMOS or CCD image sensor for use in an imaging application. In some embodiments, the sensor component 314 can further include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0184] The communication component 316 is configured to facilitate wired or wireless communication between the electronic device 300 and other devices. The electronic device 300 can access a wireless network based on a communication standard, such as WiFi, 2G, or 3G, or a combination thereof. In an exemplary embodiment, the communication component 316 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 316 further includes a Near Field Communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on Radio Frequency Identification (RFID) technology, Infrared Data Association (IrDA) technology, Ultra-WideBand (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0185] In an exemplary embodiment, the electronic device 300 can be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, micro-controllers, microprocessors, or other electronic elements, for performing the above-described methods.

[0186] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions, such as the memory 304 including instructions, is also provided, which can be executed by the processor 320 of the electronic device 300 to perform the above-described methods. For example, the non-transitory computer-readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disc, and an optical data storage device, etc.

[0187] A non-transitory computer-readable storage medium, when instructions in the storage medium are executed by a processor of an electronic device (a server or a terminal), enables the processor to perform Figure 2 the illustrated abnormality recovery method.

[0188] Each of the above-described embodiments is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. Therefore, the same or similar parts among the embodiments can be mutually referred to.

[0189] Those skilled in the art should understand that the embodiments of the present embodiments can be provided as a method, device, or computer program product. Therefore, the embodiments of the present embodiments can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the embodiments of the present embodiments can take the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0190] The embodiments of the present application are described with reference to the flowchart illustrations and / or block diagrams of the methods, terminal devices (systems) and computer program products according to the embodiments of the present application. It is understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal devices to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal devices, create means for implementing the functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams.

[0191] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal devices to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the function specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams.

[0192] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal devices, such that a series of operational steps are performed on the computer or other programmable terminal devices to produce a computer implemented process so that the instructions which execute on the computer or other programmable terminal devices provide steps for implementing the functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams.

[0193] Although preferred embodiments of the present application have been described, those skilled in the art will be able to make additional modifications and variations to these embodiments without departing from the scope of the present application. Accordingly, the appended claims are intended to encompass all such modifications and variations as falling within the scope of the present application.

[0194] Finally, it is to be understood that the phraseology or terminology such as "first" and "second" etc. used herein is merely intended to differentiate one entity or operation from another entity or operation, without necessarily requiring or implying any actual such relationship or order between such entities or operations. Moreover, the terms "comprising", "including", or any other closure, are intended to cover the non-exclusive inclusion such that a process, method, article, or apparatus that comprises a list of elements does not include those elements alone but can include other elements not expressly listed or even include elements inherent in such process, method, article, or apparatus. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of additional identical elements in the process, method, article, or apparatus including the element.

[0195] The above describes in detail the abnormal recovery method, device and electronic equipment provided by the present application. The principles and implementation modes of the present application are described by using specific examples. The above description of the embodiments is only used to help understand the method of the present application and its core idea. Meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation mode and application range can be changed. In summary, the content of the specification should not be understood as a limitation of the present application.

Claims

1. An abnormality recovery method characterized by comprising: The method is applied to a binary translation system for translating a source program in a client into a target program in a host, and comprises: In the case of an exception, determining the corresponding source instruction and basic block of the target instruction triggering the exception in the source program, and marking the corresponding target position of the source instruction in the source program; According to the target position and the register delay calculation algorithm, determining the offset value corresponding to the target register, comprising: according to the target position and the register delay calculation algorithm, determining the offset value corresponding to each instruction between the first instruction of the basic block corresponding to the source instruction and the target position; accumulating the offset values corresponding to each instruction between the starting position of the basic block and the first source instruction to obtain the offset value of the first register corresponding to the first source instruction; the first source instruction is any instruction between the starting position of the basic block and the target position; the target register includes the registers corresponding to each instruction between the starting position of the basic block and the target position within the correction range of the register delay calculation algorithm; According to the offset value, correcting the value of the target register.

2. The method of claim 1, wherein, The method further comprises: In the case that there is no repair identifier between the first instruction of the basic block and the target position, determining the offset value corresponding to each instruction between the first instruction of the basic block and the target position according to the register delay calculation algorithm. The method further comprises:

3. The method of claim 2, wherein, In the case that there is the repair identifier between the first instruction of the basic block and the target position, clearing the offset values corresponding to the registers corresponding to each instruction between the first instruction of the basic block and the target position, and analyzing the next instruction of the target instruction. The method further comprises:

4. The method of claim 1, wherein, For the basic block corresponding to the target instruction triggering the exception, determining the serial number corresponding to each instruction in the basic block according to the arrangement order of the instructions in the basic block, and determining the target serial number corresponding to the instruction in the target position; Determining whether the serial number corresponding to the ith instruction in the basic block is less than or equal to the target serial number; the initial value of i is 1, and i is a positive integer; In the case that the serial number corresponding to the ith instruction in the basic block is less than or equal to the target serial number, determining the offset value corresponding to the ith instruction through the register delay calculation algorithm; In the case that the serial number corresponding to the ith instruction in the basic block is less than or equal to the target serial number, determining the offset value corresponding to the ith instruction through the register delay calculation algorithm; In a case where a sequence number corresponding to an i-th instruction in the basic block is greater than the target sequence number, it is determined that the offset values corresponding to the target registers are all calculated.

5. The method of claim 1, wherein, The modifying the values of the target registers according to the offset values comprises: obtaining register values corresponding to each instruction between the starting position and the target position of the basic block; for a first register, adding the register value and the offset value to obtain a modified register value; the first register is any register in the target registers; replacing a register value corresponding to the first register with the modified register value.

6. The method of claim 1, wherein, In a case where an exception occurs, the source instruction and the basic block corresponding to the target instruction triggering the exception in the source program are determined, and a target position corresponding to the source instruction in the source program is marked, comprising: In a case where an exception occurs, an instruction address triggering the exception is determined; based on the instruction address, a basic block corresponding to the target instruction triggering the exception is determined; based on the instruction address, a source instruction corresponding to the target instruction triggering the exception in the source program is determined in the basic block, and a target position corresponding to the source instruction in the source program is marked.

7. An abnormality recovery apparatus characterized by comprising: The apparatus is applied to a binary translation system for translating a source program in a client into a target program in a host, and the apparatus comprises: a determination unit configured to, in a case where an exception occurs, determine a source instruction and a basic block corresponding to a target instruction triggering the exception in the source program, and mark a target position corresponding to the source instruction in the source program; and determine offset values corresponding to target registers according to the target position and a register delay calculation algorithm; the target registers comprise register values corresponding to each instruction between a starting position of the basic block and the target position in a modification range of the register delay calculation algorithm; a modification unit configured to modify values of the target registers according to the offset values. The determination unit is specifically configured to: determine offset values corresponding to each instruction between a first instruction of the basic block corresponding to the source instruction and the target position according to the target position and the register delay calculation algorithm; add the offset values corresponding to each instruction between the starting position of the basic block and the first source instruction to obtain an offset value of a first register corresponding to the first source instruction; the first source instruction is any instruction between the starting position of the basic block and the target position.

8. An electronic device, comprising: The electronic device includes a memory, and one or more programs stored in the memory and configured to be executed by one or more processors to perform the exception recovery method of any one of claims 1 to 6.

9. A readable storage medium, characterized by, When instructions in the storage medium are executed by a processor of an electronic device, the processor can perform the exception recovery method of any one of claims 1 to 6.

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