Multi-channel parallel test system and method based on memory

Abstract

The invention relates to the technical field of memory channel testing, in particular to a multi-channel parallel testing system and method based on a memory. The method comprises the following steps: acquiring original data of a memory test channel; performing topology analysis on the original data of the memory test channel to generate node distribution data of the memory channel; performing dynamic weight calculation on the storage channel node distribution data to obtain channel priority data; performing resource competition arbitration on the storage channel node distribution data according to the channel priority data to generate channel resource allocation data; performing control plane mapping on the channel resource allocation data to generate network topology virtualization data; and performing routing strategy optimization processing on the network topology virtualization data to generate dynamic routing table data. By optimizing channel resource allocation, topology virtualization management, elastic scheduling synchronization, fault prediction and data matching, the multi-channel parallel test efficiency and accuracy of the memory are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of storage channel testing, and in particular to a storage-based multi-channel parallel testing system and method thereof. Background Art

[0002] With the rapid development of computer technology and semiconductor technology, memory, as an important component of computing systems, has been continuously improving in capacity, speed and complexity. However, the growth of memory scale and the complexity of structure have also brought about a significant increase in testing difficulty. Traditional single-channel memory testing methods have been unable to meet the needs of modern memory manufacturing in terms of test efficiency and coverage. Early memory testing mainly relied on sequential read and write test methods to determine whether the memory is normal by detecting the functional status of memory cells one by one. However, this method shows significant time consumption on large-capacity memories, which seriously restricts test efficiency. With the emergence of multi-channel memory architectures, such as DDR and HBM (high bandwidth memory), traditional test methods cannot fully utilize the parallel characteristics of multiple channels, resulting in low resource utilization. In order to solve these problems, multi-channel parallel testing methods have emerged. This method can significantly improve the test speed and effectively cover complex fault modes by activating multiple channels at the same time to run test tasks in parallel. However, current traditional technologies lack in-depth analysis of storage channel node distribution and resource competition in multi-channel testing, which can easily lead to uneven or conflicting channel resource allocation. At the same time, pipeline scheduling and cache synchronization mechanisms are often inflexible, which can easily cause data inconsistencies and performance bottlenecks, resulting in low efficiency and accuracy of multi-channel parallel testing of memory. Summary of the invention

[0003] Based on this, it is necessary to provide a memory-based multi-channel parallel testing system and method thereof to solve at least one of the above technical problems.

[0004] To achieve the above object, a memory-based multi-channel parallel testing method is provided, the method comprising the following steps: Step S1: acquiring original data of a memory test channel; performing topological analysis on the original data of the memory test channel to generate storage channel node distribution data; performing dynamic weight calculation on the storage channel node distribution data to obtain channel priority data; performing resource competition arbitration on the storage channel node distribution data according to the channel priority data to generate channel resource allocation data; Step S2: Control plane mapping is performed on the channel resource allocation data to generate network topology virtualization data; routing strategy optimization is performed on the network topology virtualization data to generate dynamic routing table data; elastic pipeline concurrent scheduling is performed on the dynamic routing table data to generate parallel test pipeline data; adaptive cache synchronization is performed on the parallel test pipeline data to generate channel parallel cache consistency state data; Step S3: extracting timing features of parallel test pipeline data based on cache consistency state data to obtain parallel test timing feature data; performing streaming calculation on the parallel test timing feature data to obtain real-time abnormal index data; constructing a model based on the real-time abnormal index data to generate a memory multi-channel fault probability distribution prediction model; importing the parallel test timing feature data into the memory multi-channel fault probability distribution prediction model to perform test fault prediction and generate fault probability prediction data; Step S4: collect test data for the parallel test pipeline data according to the fault probability prediction data to obtain channel parallel actual test data; match the channel parallel actual test data with the fault probability prediction data to generate a memory multi-channel parallel test matching report to perform parallel test detection operations.

[0005] The present invention effectively improves the efficiency and fairness of channel resource allocation through topology analysis, dynamic weight calculation and resource competition arbitration, avoids resource conflicts and uneven allocation problems, and provides an efficient channel scheduling basis for subsequent parallel testing. Through control plane mapping, network topology virtualization is realized, and the network management flexibility of memory testing is improved; routing strategy optimization and elastic pipeline concurrent scheduling improve the efficiency and throughput of parallel testing, and adaptive cache synchronization ensures data consistency, reducing data delays and errors during testing. Based on the extraction of timing features of cache consistency state data, real-time abnormal index data is generated in combination with streaming computing, and a fault probability distribution prediction model is constructed to achieve early prediction and positioning of potential faults, significantly improving the accuracy of testing and fault detection efficiency. By collecting parallel test data and matching it with fault probability prediction data, a multi-channel parallel test matching report is generated, the credibility of the test results is comprehensively improved, and accurate decision support is provided for parallel test detection operations, ensuring the efficiency and reliability of detection operations. The above steps are closely linked, from resource allocation to network optimization, and then to fault prediction and result verification, which comprehensively improves the efficiency, accuracy and intelligence level of multi-channel parallel testing of memory. Therefore, the present invention improves the efficiency and accuracy of multi-channel parallel testing of memory by optimizing channel resource allocation, topology virtualization management, elastic scheduling synchronization, fault prediction and data matching.

[0006] Preferably, step S1 comprises the following steps: Step S11: obtaining original data of the memory test channel; Step S12: performing data preprocessing on the original data of the memory test channel to generate standard memory test channel data, wherein the data preprocessing includes data cleaning, data denoising, data missing value filling and data standardization; performing NUMA topology analysis on the standard memory test channel data to generate storage channel node distribution data; Step S13: performing node edge computing resource evaluation on the storage channel node distribution data to generate node computing load distribution data; performing dynamic weight calculation on the storage channel nodes through the node computing load distribution data to obtain channel priority data; Step S14: performing resource competition arbitration on the storage channel node distribution data according to the channel priority data to generate channel resource allocation data.

[0007] The present invention accurately collects the original data of the memory test channel to ensure that the basic data for subsequent analysis is comprehensive and accurate, providing reliable input for the entire process. Through data cleaning, denoising, missing value filling and standardization, the data quality and consistency are improved, and the interference of noise and outliers on the analysis is eliminated. NUMA (non-uniform memory access) topology analysis is performed to clarify the distribution of storage channel nodes and optimize the physical and logical structure analysis of the memory. Through edge computing resource evaluation, the computing load status of each node is identified to provide accurate node load distribution information. The dynamic weight calculation mechanism optimizes the priority configuration of storage channel nodes based on load distribution to ensure the fairness and efficiency of resource scheduling. Through resource competition arbitration of channel priority, storage resources are reasonably allocated, resource utilization is maximized, and potential conflicts and performance bottlenecks are reduced. Provide dynamic and accurate channel resource allocation strategies to improve the overall efficiency and responsiveness of the system.

[0008] Preferably, step S14 includes the following steps: Step S141: performing resource competition identification on the storage channel node distribution data to obtain channel node resource competition data; Step S142: defining arbitration rules for channel node resource competition data based on the first-in-first-out principle to obtain node resource competition arbitration rule data; Step S143: performing local resource allocation on the channel node resource competition data according to the node resource competition arbitration rule data to generate node resource allocation data; Step S144: using the channel priority data to adjust the node resource allocation data for global channel resource allocation, and generating channel resource allocation data.

[0009] The present invention can accurately locate competition hotspots, clarify the resource contention of each node, and reduce blind spots and uneven resource allocation problems by identifying resource competition for storage channel node distribution data. The generated channel node resource competition data provides a scientific basis for subsequent arbitration and improves the pertinence of resource allocation. Based on the first-in-first-out (FIFO) principle, resource competition arbitration rules are formulated to ensure the fairness of resource allocation and prevent high-priority nodes from occupying resources for a long time, resulting in starvation of low-priority nodes. The standardization and automation of arbitration rules improve the efficiency and transparency of the resource allocation decision-making process. According to the arbitration rules, resource competition data is locally allocated to effectively reduce the complexity of resource competition and avoid overload of a single node or a single area. The generated node resource allocation data optimizes the resource utilization rate at the node level and balances the resource distribution. The node-level allocation results are globally adjusted using channel priority data to achieve dynamic optimization of resources across nodes and regions. It ensures that the resource requirements of high-priority channels are fully met while taking into account the overall performance and stability of the system. Through a global and local allocation method, resource utilization is optimized to avoid resource waste and unnecessary conflicts. Resource arbitration and dynamic adjustment mechanisms reduce delays and bottlenecks caused by resource competition and improve the overall performance of the system. Resource allocation strategies based on node priority and dynamic adjustment rules enable the system to flexibly adapt to different workloads and application scenario requirements. Through fair arbitration rules and efficient resource allocation mechanisms, the long-term impact of resource imbalance on system operation is reduced, and the stable operation cycle of the system is extended.

[0010] Preferably, step S2 comprises the following steps: Step S21: performing resource data abstraction on the channel resource allocation data to obtain channel resource allocation abstract data, wherein the resource data abstraction includes device type abstraction, connection relationship abstraction and address information abstraction; performing topology modeling on the channel resource allocation abstract data to generate resource allocation physical network topology data; Step S22: performing control plane mapping on the resource allocation physical network topology data through the SDN controller to generate network topology virtualization data; performing routing demand analysis on the network topology virtualization data to generate routing demand data; performing routing strategy optimization processing on the network topology virtualization data based on the routing demand data to generate dynamic routing table data; Step S23: performing link aggregation analysis on the dynamic routing table data to generate bandwidth allocation strategy data; performing topology adaptive processing on the bandwidth allocation strategy data to generate channel interconnection topology data; performing elastic pipeline concurrent scheduling on the channel interconnection topology data to generate parallel test pipeline data; Step S24: performing adaptive cache synchronization on the parallel test pipeline data to generate channel parallel cache consistency state data.

[0011] The present invention reduces direct dependence on physical resources through the abstraction of device types, connection relationships and address information, and realizes the standardization and modular management of channel resources. Topology modeling provides a clear physical network view for resource allocation, improves the accuracy and dynamic adjustment capability of resource scheduling, and reduces resource waste and conflicts. Network topology virtualization and control plane mapping based on SDN controller enable resource allocation to change from a static mode to a dynamic and intelligent direction, adapting to dynamic demand changes in complex network environments. Routing strategy optimization not only reduces the path overhead of data transmission, but also improves the network load balancing capability, thereby enhancing the stability and efficiency of transmission. Link aggregation analysis combined with bandwidth allocation strategy effectively improves the overall bandwidth utilization of the system and ensures the smooth operation of high-throughput test scenarios. Elastic pipeline concurrent scheduling realizes dynamic resource allocation and multi-task collaborative processing, reducing resource competition and waiting time between test tasks. Adaptive cache synchronization technology ensures the data consistency state in multi-channel parallel processing, avoiding the occurrence of data loss, duplication or delay. The data consistency monitoring mechanism improves the system's fault tolerance to sudden anomalies and ensures the accuracy and traceability of test results. Dynamic routing tables and topology adaptive processing mechanisms enable the system to adapt to changes in business needs in real time, reduce human intervention, and improve the level of automation. The modular design of the process provides high compatibility and flexibility for subsequent functional expansion and strategy optimization, meeting the requirements of test scenarios of different scales and complexities.

[0012] Preferably, performing elastic pipeline concurrent scheduling on channel interconnection topology data includes: Extract key channel features from the channel interconnection topology data to obtain channel interconnection key feature data, wherein the channel interconnection key feature data includes key node data and channel interconnection link data; perform dependency analysis on the key node data and the channel interconnection link data to generate channel interconnection dependency data; According to the channel interconnection dependency data, the channel interconnection topology data is divided into service units to generate independent service unit data; based on the independent service unit data, the channel interconnection topology data is segmented into microservices to generate service unit division data; Perform service unit containerization on the service unit division data to generate containerized service unit data; perform container network orchestration on the containerized service unit data to generate unit container network orchestration data; perform container orchestration mapping on the containerized service unit data through the unit container network orchestration data to generate container scheduling strategy data; Concurrency optimization is performed on the container scheduling strategy data to generate task parallelism data; pipeline synchronization is performed on the task parallelism data to generate parallel test pipeline data.

[0013] The present invention accurately identifies the core factors affecting channel performance through feature extraction and dependency analysis of key nodes and interconnected link data, provides a reliable basis for subsequent service division, and reduces redundancy and resource waste. Service unit division deconstructs complex channel topology data into independent modules, significantly improving the modular management capabilities of the system. Microservice segmentation ensures that each service unit has good collaboration while running independently, reducing the complexity of global resource scheduling. The containerized service unit provides a unified operating environment, ensures compatibility and isolation between different service units, and reduces conflicts and debugging costs in deployment. Container network orchestration realizes efficient connection and communication between service units, optimizes network performance and operating efficiency. The scheduling strategy data generated by container orchestration mapping fully considers the dependency and load characteristics of the service unit, realizes dynamic allocation and optimal utilization of resources, and improves scheduling efficiency. The concurrent optimization strategy maximizes resource utilization based on task parallelism data, effectively reduces task execution time, and improves overall parallel processing performance. The pipeline synchronization mechanism ensures data consistency and process orderliness between tasks, avoiding conflicts and bottlenecks in processing. By combining containerization with elastic scheduling, the system can maintain efficient operation under different load conditions, and its adaptability and scalability are significantly enhanced. The automated process of data processing and task scheduling reduces human intervention, reduces operation and maintenance costs, and improves the reliability and stability of system operation.

[0014] Preferably, concurrent optimization of container scheduling policy data includes: Perform policy execution on the container scheduling policy data to generate container scheduling policy execution data; perform scheduling node screening on the storage channel node distribution data based on the container scheduling policy execution data to obtain the policy execution scheduling node; perform scheduling timestamp analysis on the policy execution scheduling node to generate the node scheduling timestamp; According to the node scheduling timestamp, the strategy execution scheduling nodes are divided into nodes with timestamp differences, and concurrent synchronous timestamp node data and concurrent asynchronous timestamp node data are generated; node task batch processing is performed on the concurrent synchronous timestamp node data to generate a concurrent synchronous node task batch processing strategy; Perform concurrent timestamp calibration on the data of concurrent non-synchronous timestamp nodes and concurrent synchronous timestamp nodes to obtain concurrent timestamp calibration data; perform transaction rollback within the difference timestamp on the concurrent non-synchronous timestamp nodes based on the concurrent timestamp calibration data to generate a non-concurrent synchronous node task rollback strategy; The concurrent synchronization node task batch processing strategy and the non-concurrent synchronization node task rollback strategy are used to concurrently optimize the container scheduling strategy data and generate task parallelism data.

[0015] The present invention accurately screens the distribution of storage channel nodes by executing data based on container scheduling strategies, ensuring that the selected scheduling nodes have high adaptability and priority, thereby reducing the occupation of invalid resources and optimizing the scheduling path. Timestamp analysis and difference division are performed on the scheduling nodes, the characteristics of synchronous and asynchronous nodes are clarified, the timing consistency in the execution of concurrent tasks is ensured, and conflicts and delays caused by time differences are effectively avoided. For synchronous timestamp node data, a task batch processing strategy is generated to efficiently allocate resources, reduce the switching and waiting time required for task execution, and significantly improve the system processing throughput. Timestamp calibration is performed on asynchronous nodes to eliminate task errors caused by node timing differences, and ensure data consistency and accuracy of operation logic between tasks. A timestamp rollback mechanism is introduced in asynchronous node transaction processing to effectively deal with transaction anomalies caused by timing differences, enhance the system's fault tolerance and task recovery capabilities, and improve the robustness of overall scheduling. By combining the synchronous node batch processing strategy with the asynchronous node rollback strategy, the task parallel execution process is further optimized, while ensuring task consistency, the task parallelism is maximized and the overall task execution time is shortened. The whole process optimization fully utilizes system resources, avoids performance degradation caused by resource waste or conflicts, and ensures that the container scheduling system can maintain stable and efficient operation under high load. Through the comprehensive implementation of concurrency optimization, the scheduling system has high flexibility and can quickly respond to task priority adjustments and operating environment changes while maintaining stability, providing reliable protection for containerized task management in complex scenarios.

[0016] Preferably, performing adaptive cache synchronization on parallel test pipeline data includes: Perform distributed cache stratification on parallel test pipeline data to generate cache hierarchy data; perform memory queue optimization on cache hierarchy data to generate queue scheduling strategy data; The queue scheduling policy data is processed by a consistency protocol to generate synchronization state machine data; conflict detection is performed on the synchronization state machine data, and when a conflict is detected in the synchronization state machine data, the conflicting data is merged to generate cache consistency state data.

[0017] The present invention forms a structured cache hierarchy by performing cache hierarchical design on parallel test pipeline data, making data storage and access more efficient and reducing data retrieval delay. The cache hierarchical structure data is optimized for memory queues to generate scientific and efficient queue scheduling strategy data, significantly improving the task distribution and execution efficiency of the cache queue and reducing the ineffective occupation of system resources. The consistency protocol processing is introduced on the queue scheduling strategy data to ensure the synchronous update of cache data in multi-node or distributed environments, effectively avoiding the problem of data inconsistency and improving the stability and reliability of task execution. The introduction of the synchronization state machine provides dynamic monitoring capabilities for cache synchronization, and eliminates task blocking and resource waste caused by data competition by detecting conflicting data in real time and performing reasonable merging. In the process of conflicting data merging, the data integrity and consistency between different cache nodes are guaranteed, and the reliable interaction of data under high-concurrency tasks is effectively supported to avoid the risk of data loss or repeated processing. The adaptive cache synchronization mechanism fully optimizes the system's memory and computing resource allocation, makes cache management more efficient, maximizes system resource utilization, and provides strong support for system operation. In the high-intensity task processing of the parallel test pipeline, the optimization strategy of adaptive cache synchronization greatly improves the task throughput of the pipeline, enabling the system to quickly respond to high-concurrency requests and improve task execution efficiency. This optimization solution enhances the robustness of the system while achieving data consistency, enabling it to adapt to the needs of diverse scenarios, and has good scalability to support future functional upgrades and performance improvements.

[0018] Preferably, step S3 comprises the following steps: Step S31: extracting timing characteristics of parallel test pipeline data based on cache consistency state data to obtain parallel test timing characteristic data; Step S32: Perform streaming calculation on the parallel test time series feature data to obtain real-time abnormal index data; divide the real-time abnormal index data into data sets to generate a model training set and a model test set; Step S33: training the model training set by using a long short-term memory neural network algorithm to generate a memory multi-channel fault probability distribution prediction pre-model; optimizing and iterating the memory multi-channel fault probability distribution prediction pre-model by using a model test set to generate a memory multi-channel fault probability distribution prediction model; Step S34: Importing the parallel test timing feature data into the memory multi-channel fault probability distribution prediction model to perform test fault prediction and generate fault probability prediction data.

[0019] The present invention extracts time series features from parallel test pipeline data based on cache consistency state data, effectively captures the dynamic characteristics of data changes, provides a high-precision input basis for subsequent fault prediction, and improves the accuracy and reliability of data analysis. Streaming calculations are performed on parallel test time series feature data to generate abnormal indicators in real time, quickly identify potential abnormalities in the test process, ensure that faults can be discovered and handled in time at an early stage, and reduce the risk of problem spread. The data set partitioning strategy ensures the diversity of the model training set and the representativeness of the model test set, provides a scientific sample distribution basis for the training and optimization of the neural network model, and improves the generalization ability and prediction effect of the model. The long short-term memory (LSTM) neural network algorithm is applied to make full use of the time correlation of the time series feature data, and an efficient fault probability distribution prediction model is constructed, which improves the ability to accurately predict multi-channel faults. By optimizing and iterating the pre-model for predicting the probability distribution of multi-channel faults in the memory, the performance and stability of the model are significantly enhanced, ensuring that the model's prediction of the fault mode is closer to the actual scenario. Importing parallel test timing feature data into the prediction model to generate fault probability prediction data can monitor and predict potential system failures in real time, provide forward-looking guidance for system operation and maintenance, and avoid performance degradation or interruption risks caused by failures. With the help of automated fault prediction, the time for problem diagnosis and troubleshooting is shortened, and the frequency and complexity of manual intervention are reduced, thus effectively saving manpower and time costs in the testing process.

[0020] Preferably, step S4 comprises the following steps: Step S41: Generate test signals for parallel test pipeline data according to the fault probability prediction data to obtain channel parallel test signals; collect test data for the channel parallel test signals to obtain channel parallel actual test data; Step S42: Perform data matching calculation on the channel parallel actual test data and the fault probability prediction data to obtain channel parallel test matching data; perform data visualization on the channel parallel test matching data to generate a memory multi-channel parallel test matching report to execute parallel test detection operations.

[0021] The present invention automatically generates channel parallel test signals according to fault probability prediction data, realizes dynamic adaptation of test signals, reduces the complexity of manual intervention, and improves test operation efficiency. Test data collection is performed on channel parallel test signals to fully obtain actual test data of multiple channels, ensure the diversity and integrity of data, and provide a rich data basis for subsequent analysis. Matching and calculating the channel parallel actual test data with the fault probability prediction data, accurately comparing the prediction and actual results, and significantly improving the credibility of the test results and the accuracy of fault location. Data visualization is performed based on the matching calculation results to generate an intuitive and clear memory multi-channel parallel test matching report, providing engineers and operation and maintenance teams with intuitive data display and problem analysis tools, and improving decision-making efficiency. Combining test signal generation with data matching analysis, deep optimization of multi-channel parallel testing is achieved, and the concurrent processing capability of the test system in large-scale test scenarios is significantly improved. Through matching verification of actual test data and predicted data, the error range in fault detection is effectively reduced, ensuring the accuracy of fault location and the reliability of diagnostic results. The dynamic generation of test signals and the automated processing of data matching significantly improve the intelligence level of the test system, laying a foundation for further expanding the automated detection process. The generation of memory multi-channel parallel test matching reports provides a transparent display of the entire process, provides a traceable basis for fault detection and optimization, and meets the high-standard audit requirements for test operations. Automated test signal generation, data collection, and report output shorten the test cycle, while reducing dependence on human resources, saving costs, and improving overall operational efficiency.

[0022] In this specification, a memory-based multi-channel parallel testing system is provided, which is used to execute the above-mentioned memory-based multi-channel parallel testing method. The memory-based multi-channel parallel testing system includes: A channel resource allocation module is used to obtain the original data of the memory test channel; perform topological analysis on the original data of the memory test channel to generate storage channel node distribution data; perform dynamic weight calculation on the storage channel node distribution data to obtain channel priority data; perform resource competition arbitration on the storage channel node distribution data according to the channel priority data to generate channel resource allocation data; The concurrent scheduling module is used to perform control plane mapping on the channel resource allocation data to generate network topology virtualization data; perform routing strategy optimization processing on the network topology virtualization data to generate dynamic routing table data; perform elastic pipeline concurrent scheduling on the dynamic routing table data to generate parallel test pipeline data; perform adaptive cache synchronization on the parallel test pipeline data to generate channel parallel cache consistency state data; A fault prediction module is used to extract timing features of parallel test pipeline data based on cache consistency state data to obtain parallel test timing feature data; perform streaming calculations on the parallel test timing feature data to obtain real-time abnormal indicator data; construct a model based on the real-time abnormal indicator data to generate a memory multi-channel fault probability distribution prediction model; import the parallel test timing feature data into the memory multi-channel fault probability distribution prediction model to perform test fault prediction and generate fault probability prediction data; The parallel test module is used to collect test data for the parallel test pipeline data according to the fault probability prediction data to obtain the actual channel parallel test data; match the actual channel parallel test data with the fault probability prediction data to generate a memory multi-channel parallel test matching report to execute parallel test detection operations.

[0023] The beneficial effect of the present invention is that through topology analysis and dynamic weight calculation, resources can be accurately allocated to each storage channel, resource conflicts and unnecessary delays can be avoided, high-priority channels can be ensured to get faster responses, and overall system performance can be improved. Through network topology virtualization and route optimization, efficient data transmission and fluency are ensured, the risk of network congestion is reduced, and the reliability of data transmission is improved. By performing adaptive cache synchronization in a parallel test pipeline, data consistency between multiple test channels is ensured, test errors caused by cache inconsistency are avoided, and the stability of parallel testing is improved. Through timing feature extraction and streaming computing, potential faults in the system can be detected and predicted in real time. By constructing a multi-channel fault probability distribution prediction model for a memory, potential faults can be warned in advance, thereby improving the reliability of the system. By matching the fault probability prediction data with the actual test data, a parallel test matching report is generated, which provides an accurate execution basis for the parallel test operation of the memory, helps to reduce test time and cost, and improves the accuracy of fault detection. Therefore, the present invention improves the efficiency and accuracy of multi-channel parallel testing of the memory by optimizing channel resource allocation, topology virtualization management, elastic scheduling synchronization, fault prediction and data matching. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A schematic diagram of a step flow of a memory-based multi-channel parallel testing method; Figure 2 for Figure 1 Detailed implementation steps of step S2 in the flowchart; Figure 3 for Figure 1 Detailed implementation steps of step S3 in FIG. The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0025] The technical method of the present invention is described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by technicians in this field without creative work are within the scope of protection of the present invention.

[0026] In addition, the accompanying drawings are only schematic illustrations of the present invention and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities. The functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor methods and / or microcontroller methods.

[0027] It should be understood that, although the terms "first", "second", etc. may be used herein to describe various units, these units should not be limited by these terms. These terms are used only to distinguish one unit from another unit. For example, without departing from the scope of the exemplary embodiments, the first unit may be referred to as the second unit, and similarly the second unit may be referred to as the first unit. The term "and / or" used herein includes any and all combinations of one or more of the listed associated items.

[0028] To achieve this, please refer to Figures 1 to 3 , a memory-based multi-channel parallel testing method, the method comprising the following steps: Step S1: acquiring original data of a memory test channel; performing topological analysis on the original data of the memory test channel to generate storage channel node distribution data; performing dynamic weight calculation on the storage channel node distribution data to obtain channel priority data; performing resource competition arbitration on the storage channel node distribution data according to the channel priority data to generate channel resource allocation data; Step S2: Control plane mapping is performed on the channel resource allocation data to generate network topology virtualization data; routing strategy optimization is performed on the network topology virtualization data to generate dynamic routing table data; elastic pipeline concurrent scheduling is performed on the dynamic routing table data to generate parallel test pipeline data; adaptive cache synchronization is performed on the parallel test pipeline data to generate channel parallel cache consistency state data; Step S3: extracting timing features of parallel test pipeline data based on cache consistency state data to obtain parallel test timing feature data; performing streaming calculation on the parallel test timing feature data to obtain real-time abnormal index data; constructing a model based on the real-time abnormal index data to generate a memory multi-channel fault probability distribution prediction model; importing the parallel test timing feature data into the memory multi-channel fault probability distribution prediction model to perform test fault prediction and generate fault probability prediction data; Step S4: collect test data for the parallel test pipeline data according to the fault probability prediction data to obtain channel parallel actual test data; match the channel parallel actual test data with the fault probability prediction data to generate a memory multi-channel parallel test matching report to perform parallel test detection operations.

[0029] The present invention effectively improves the efficiency and fairness of channel resource allocation through topology analysis, dynamic weight calculation and resource competition arbitration, avoids resource conflicts and uneven allocation problems, and provides an efficient channel scheduling basis for subsequent parallel testing. Through control plane mapping, network topology virtualization is realized, and the network management flexibility of memory testing is improved; routing strategy optimization and elastic pipeline concurrent scheduling improve the efficiency and throughput of parallel testing, and adaptive cache synchronization ensures data consistency, reducing data delays and errors during testing. Based on the extraction of timing features of cache consistency state data, real-time abnormal index data is generated in combination with streaming computing, and a fault probability distribution prediction model is constructed to achieve early prediction and positioning of potential faults, significantly improving the accuracy of testing and fault detection efficiency. By collecting parallel test data and matching it with fault probability prediction data, a multi-channel parallel test matching report is generated, the credibility of the test results is comprehensively improved, and accurate decision support is provided for parallel test detection operations, ensuring the efficiency and reliability of detection operations. The above steps are closely linked, from resource allocation to network optimization, and then to fault prediction and result verification, which comprehensively improves the efficiency, accuracy and intelligence level of multi-channel parallel testing of memory. Therefore, the present invention improves the efficiency and accuracy of multi-channel parallel testing of memory by optimizing channel resource allocation, topology virtualization management, elastic scheduling synchronization, fault prediction and data matching.

[0030] In the embodiment of the present invention, reference Figure 1 FIG. 1 is a schematic diagram of a step flow chart of a memory multi-channel parallel testing method according to the present invention. In this example, the memory multi-channel parallel testing method includes the following steps: Step S1: acquiring original data of a memory test channel; performing topological analysis on the original data of the memory test channel to generate storage channel node distribution data; performing dynamic weight calculation on the storage channel node distribution data to obtain channel priority data; performing resource competition arbitration on the storage channel node distribution data according to the channel priority data to generate channel resource allocation data; In an embodiment of the present invention, the original data of the channel in the memory test process is collected through the interface protocol, including the test results, delay, bandwidth, data throughput and other key performance indicators of each channel. The collected original data is stored in a unified format to form a memory test channel original data set. The topology analysis algorithm is used to analyze the structural relationship of the storage channel and construct the node network topology diagram of the channel. The node can represent a storage controller, a switch, a data cache module, etc., and the edge represents the data path and communication relationship between the nodes. The output topology analysis result is the storage channel node distribution data, which includes: the connection relationship of each node, channel bandwidth distribution, delay distribution and other indicators. The storage channel node distribution data is dynamically weighted according to the channel performance index. The weight calculation process determines the priority of each channel node by comprehensively considering multiple performance indicators such as bandwidth, delay, throughput and reliability of the channel. The specific calculation method is as follows: the bandwidth value of the current node is compared with the maximum bandwidth value of all nodes, and the proportion thereof is calculated. A higher bandwidth proportion indicates that the transmission capacity of the node is stronger. The minimum delay value of all nodes is compared with the delay value of the current node to obtain its delay priority. A lower delay value has a higher priority. Compare the throughput value of the current node with the maximum throughput value of all nodes and calculate their proportion. A higher throughput indicates that the node has stronger data processing capabilities. Directly use the reliability index value of the current node. The node with higher reliability has higher priority. Calculate the final comprehensive weight of each node by assigning weight coefficients to bandwidth, delay, throughput and reliability factors respectively. The weight coefficient is used to balance the importance of different performance indicators. Finally, sort the node priorities according to the comprehensive weight value of each node and generate channel priority data. Perform resource competition arbitration based on the channel priority data and determine the resource allocation scheme: dynamically allocate resources according to the priority of the node, and high-priority nodes get resources first. Use resource allocation algorithms (such as the improved maximum flow algorithm or fair scheduling algorithm) to resolve resource conflicts. Ensure that the arbitration results meet performance constraints such as bandwidth, delay, and throughput. Organize the allocation results after arbitration into structured data, including: the resource allocation amount of each node, the final priority ranking between channels, and form the final channel resource allocation data to guide subsequent storage resource scheduling and optimization.

[0031] Step S2: Control plane mapping is performed on the channel resource allocation data to generate network topology virtualization data; routing strategy optimization is performed on the network topology virtualization data to generate dynamic routing table data; elastic pipeline concurrent scheduling is performed on the dynamic routing table data to generate parallel test pipeline data; adaptive cache synchronization is performed on the parallel test pipeline data to generate channel parallel cache consistency state data; In the embodiment of the present invention, by mapping the channel resource allocation data to the control plane, the mapping relationship between the resource node and the logical network is established by associating the control plane of the storage network, thereby generating network topology virtualization data, which includes the distribution of virtual nodes and virtual links. Subsequently, the network topology virtualization data is optimized for routing strategy, and based on the rules of shortest path priority, load balancing and fault recovery, the routing strategy is dynamically adjusted using a heuristic algorithm (such as Dijkstra or improved Bellman-Ford algorithm) to generate dynamic routing table data. On this basis, tasks are elastically scheduled for pipeline concurrency according to the dynamic routing table data, and the data transmission task is decomposed into multiple stages by using pipeline concurrency. Resources are allocated and adjusted through priority scheduling and real-time load monitoring to form parallel test pipeline data. Finally, adaptive cache synchronization is implemented for the parallel test pipeline data, and an independent cache area is allocated for each pipeline. By dynamically adjusting the cache size, resolving cache read-write conflicts, and synchronizing the cache status of each pipeline in real time, the cache status is checked for consistency using a hash check mechanism, and the inconsistent status is processed to restore the correct data version, thereby generating channel parallel cache consistency status data.

[0032] Step S3: extracting timing features of parallel test pipeline data based on cache consistency state data to obtain parallel test timing feature data; performing streaming calculation on the parallel test timing feature data to obtain real-time abnormal index data; constructing a model based on the real-time abnormal index data to generate a memory multi-channel fault probability distribution prediction model; importing the parallel test timing feature data into the memory multi-channel fault probability distribution prediction model to perform test fault prediction and generate fault probability prediction data; In an embodiment of the present invention, by extracting the timing features of the parallel test pipeline data based on the cache consistency state data, by analyzing the time changes of the cache state, key timing features such as data transmission delay, read and write rate fluctuations, and cache conflict frequency are extracted. Then, these timing feature data are streamed, and the streaming computing framework is used to process the data in real time, and real-time abnormal indicators such as delay excess rate and throughput reduction rate are calculated. Subsequently, based on the real-time abnormal indicator data, a model is constructed, and a suitable machine learning algorithm (such as random forest, XGBoost, etc.) is selected to train the memory multi-channel fault probability distribution prediction model, and the abnormal indicator data is used to generate a fault prediction model. Finally, the parallel test timing feature data is imported into the prediction model, the fault probability prediction is performed, the fault probability of each channel is calculated, and the prediction result is output to identify the possibility of the occurrence of the memory multi-channel fault.

[0033] Step S4: collect test data for the parallel test pipeline data according to the fault probability prediction data to obtain channel parallel actual test data; match the channel parallel actual test data with the fault probability prediction data to generate a memory multi-channel parallel test matching report to perform parallel test detection operations.

[0034] In the embodiment of the present invention, test data is collected for parallel test pipeline data according to the fault probability prediction data, and actual test data of the channels is collected to obtain actual test data of the channels in parallel. Then, the actual test data of the channels in parallel is matched with the fault probability prediction data, and data comparison is performed to ensure the consistency of the test data and the prediction results. Finally, a memory multi-channel parallel test matching report is generated, which includes the correspondence between the actual test results of each channel and the predicted fault probability, providing support for subsequent parallel test detection operations.

[0035] Preferably, step S1 comprises the following steps: Step S11: obtaining original data of the memory test channel; Step S12: performing data preprocessing on the original data of the memory test channel to generate standard memory test channel data, wherein the data preprocessing includes data cleaning, data denoising, data missing value filling and data standardization; performing NUMA topology analysis on the standard memory test channel data to generate storage channel node distribution data; Step S13: performing node edge computing resource evaluation on the storage channel node distribution data to generate node computing load distribution data; performing dynamic weight calculation on the storage channel nodes through the node computing load distribution data to obtain channel priority data; Step S14: performing resource competition arbitration on the storage channel node distribution data according to the channel priority data to generate channel resource allocation data.

[0036] In an embodiment of the present invention, the original data of 10 test channels are collected from the memory test system, and each channel records the data of the most recent 100 operations, including operation time, resource usage, and access times. In the original data, 5 records are found to have obvious errors (for example, the resource usage is negative), and these abnormal records are directly removed. The resource usage data of each channel is denoised using the average smoothing method. For example, the original resource usage data of channel 1 is [20, 22, 18, 100, 21], which becomes [20, 22, 20, 21, 21] after denoising, and the obvious abnormal point 100 is eliminated. In the record of channel 2, there are 2 missing values ​​in resource usage, which are filled with the average value (25) of the resource usage of the same channel. The resource usage data is normalized to the range of [0,1]. For example, the resource usage data of channel 1 [20, 22, 20, 21, 21] becomes [0.0, 1.0, 0.0, 0.5, 0.5] after standardization. After data preprocessing, standard memory test channel data is generated. Subsequently, NUMA topology analysis is performed based on these data to determine the distribution relationship between nodes. For example, channel 1 includes 3 nodes, numbered N1, N2 and N3, and the topological connection relationship is N1→N2→N3. The computing load of each node is evaluated. Assuming that the total resource of node N1 is 100 units and the actual usage is 60 units, the node load is calculated as: node load = usage ÷ total resource = 0.6, and the loads of nodes N2 and N3 are calculated as 0.7 and 0.5 respectively. According to the node load value, the dynamic weight of the node is calculated, and the weight is the inverse of the load value. For example: the weight of N1 is 1 / 0.6=1.67, the weight of N2 is 1 / 0.7=1.43, and the weight of N3 is 1 / 0.5=2.00. The priorities are arranged from high to low according to the weight, and the channel priority data is obtained: N3>N1>N2. According to the channel priority, the resource allocation method for each node is weighted. Assume that there are currently 300 units of resources to be allocated: the allocation amount of N1 is 1.67 / (1.67+1.43+2.00)×300≈91 units, and the allocation amount of N2 is 1.43 / (1.67+1.43+2.00)×300≈78 units. The allocation amount of N3 is 2.00 / (1.67+1.43+2.00)×300≈131 units. The final allocation result is: N1: 91 units of resources, N2: 78 units of resources, N3: 131 units of resources. Output results: channel resource allocation data, providing a basis for subsequent resource scheduling.

[0037] Preferably, step S14 includes the following steps: Step S141: performing resource competition identification on the storage channel node distribution data to obtain channel node resource competition data; Step S142: defining arbitration rules for channel node resource competition data based on the first-in-first-out principle to obtain node resource competition arbitration rule data; Step S143: performing local resource allocation on the channel node resource competition data according to the node resource competition arbitration rule data to generate node resource allocation data; Step S144: using the channel priority data to adjust the node resource allocation data for global channel resource allocation, and generating channel resource allocation data.

[0038] In an embodiment of the present invention, by performing competition analysis on the node resource usage information in the storage channel node distribution data, resource conflicts are identified, and channel node resource competition data is generated. Assume that the storage channel includes 3 nodes (N1, N2, and N3), and the resource request situation is as follows: N1 requests 50 units of resources, and the actual available resources are 30 units (the amount of competition is 20 units), N2 requests 40 units of resources, and the actual available resources are 20 units (the amount of competition is 20 units), and N3 requests 60 units of resources, and the actual available resources are 50 units (the amount of competition is 10 units). Based on the first-in-first-out (FIFO) principle, arbitration rules are defined for resource competition situations, and node resource competition arbitration rule data is generated. According to the request order of the nodes, resource priorities are allocated: the first requesting node (N1) is allocated first; the second requesting node (N2) is allocated second best; and the third requesting node (N3) is allocated last. The node resource competition arbitration rule data is: N1: priority 1, N2: priority 2, N3: priority 3. According to the arbitration rules, the resources of the competing nodes are locally allocated, and the node resource allocation data is generated. Assuming that the total amount of current contention resources is 50 units, they are allocated in sequence according to the arbitration rules: N1 (priority 1) allocates 40% (i.e., 20 units) of the remaining contention resources. N2 (priority 2) allocates 40% (i.e., 20 units) of the remaining contention resources. N3 (priority 3) allocates 20% (i.e., 10 units) of the remaining contention resources. The channel priority data is used to globally adjust the node resource allocation data to ensure that the allocated resources meet the channel priority requirements and generate channel resource allocation data. Assuming that the channel priority data is: channel 1 (N1): weight 1.5, channel 2 (N2): weight 1.2, channel 3 (N3): weight 1.0. Adjust the resources allocated to each node according to the weight: N1: the allocated resources are adjusted to 20×1.5=30 units, N2: the allocated resources are adjusted to 20×1.2=24 units, N3: the allocated resources are adjusted to 10×1.0=10 units, and the final output channel resource allocation data results are used for the optimization decision of resource scheduling.

[0039] As an example of the present invention, refer to Figure 2 As shown, in this example, step S2 includes: Step S21: performing resource data abstraction on the channel resource allocation data to obtain channel resource allocation abstract data, wherein the resource data abstraction includes device type abstraction, connection relationship abstraction and address information abstraction; performing topology modeling on the channel resource allocation abstract data to generate resource allocation physical network topology data; Step S22: performing control plane mapping on the resource allocation physical network topology data through the SDN controller to generate network topology virtualization data; performing routing demand analysis on the network topology virtualization data to generate routing demand data; performing routing strategy optimization processing on the network topology virtualization data based on the routing demand data to generate dynamic routing table data; Step S23: performing link aggregation analysis on the dynamic routing table data to generate bandwidth allocation strategy data; performing topology adaptive processing on the bandwidth allocation strategy data to generate channel interconnection topology data; performing elastic pipeline concurrent scheduling on the channel interconnection topology data to generate parallel test pipeline data; Step S24: performing adaptive cache synchronization on the parallel test pipeline data to generate channel parallel cache consistency state data.

[0040] In an embodiment of the present invention, channel resource allocation abstract data is generated by abstracting device information, connection relationship and address information in channel resource allocation data. Specific devices (such as storage nodes, switches, etc.) are abstracted into device categories (such as "storage", "network", etc.). Physical connections (such as cables or wireless) are abstracted into logical connections. Address information is normalized, for example, from specific IP addresses to subnet level information. Assume that the channel resource allocation data contains the following information: Device: N1 (storage node), S1 (switch). Connection relationship: N1↔S1 (physical connection). Address information: N1 address is 192.168.1.10, S1 address is 192.168.1.1. After abstraction: Device type abstraction: N1→"storage", S1→"network". Connection relationship abstraction: N1↔S1→logical connection. Address information abstraction: 192.168.1.10→subnet 192.168.1.0 / 24. Based on the channel resource allocation abstract data, the resource allocation physical network topology data is constructed, including node and connection weights. Nodes: storage (N1), network (S1). Weight: The storage node weight is 1.5, and the network node weight is 1.2. The SDN controller is used to map the physical network topology data to the virtualization control plane to generate network topology virtualization data. The SDN controller identifies the N1 and S1 nodes and assigns virtual node numbers V1 and V2. Based on the network topology virtualization data, the data traffic and transmission path requirements are analyzed to generate routing demand data. 100MB of data is transmitted between nodes V1 and V2, with a traffic requirement of 10MB per second and a delay of less than 5ms. According to the routing demand data, the virtualized topology is optimized and the dynamic routing table data is generated. The path selection is: V1→S1→V2, which meets the rate and delay requirements. Link aggregation is performed on the dynamic routing table data to optimize bandwidth allocation and generate bandwidth allocation policy data. The total bandwidth is: 100MB / s. Allocation: 20MB / s is allocated to the path V1→S1→V2, and the remaining bandwidth is allocated to other paths. According to the bandwidth allocation strategy, the network topology is adjusted to generate channel interconnection topology data. Dynamically adjust the path: Add a redundant path V1→S2→V2 to improve reliability. Use the topology data to design a parallel test pipeline and generate parallel test pipeline data. The test tasks are divided into 4 parallel pipelines, and the scheduling strategy is the task priority queue. Output: Parallel test pipeline data: Pipeline 1-4: Tasks are allocated in parallel, and high-priority tasks are given priority. Cache synchronization is performed on the parallel test pipeline data to ensure the consistency of concurrent tasks, generate channel parallel cache consistency status data, and use a distributed lock mechanism to ensure task status synchronization.

[0041] Preferably, performing elastic pipeline concurrent scheduling on channel interconnection topology data includes: Extract key channel features from the channel interconnection topology data to obtain channel interconnection key feature data, wherein the channel interconnection key feature data includes key node data and channel interconnection link data; perform dependency analysis on the key node data and the channel interconnection link data to generate channel interconnection dependency data; According to the channel interconnection dependency data, the channel interconnection topology data is divided into service units to generate independent service unit data; based on the independent service unit data, the channel interconnection topology data is segmented into microservices to generate service unit division data; Perform service unit containerization on the service unit division data to generate containerized service unit data; perform container network orchestration on the containerized service unit data to generate unit container network orchestration data; perform container orchestration mapping on the containerized service unit data through the unit container network orchestration data to generate container scheduling strategy data; Concurrency optimization is performed on the container scheduling strategy data to generate task parallelism data; pipeline synchronization is performed on the task parallelism data to generate parallel test pipeline data.

[0042] In an embodiment of the present invention, by extracting key node data and channel interconnection link data from the channel interconnection topology data, nodes that have an important impact on network communication (such as high-traffic nodes and low-latency nodes) are identified, and link information connecting key nodes, including bandwidth, delay, stability, etc., is recorded. The channel interconnection topology data is as follows: Nodes: A, B, C, D, E. Links: AB (10ms, 1Gbps), BC (20ms, 500Mbps), CD (15ms, 800Mbps), DE (5ms, 2Gbps). Through feature extraction: key node data: B, D (due to large impact of traffic and delay), channel interconnection link data: AB, BC, CD, DE (record the delay and bandwidth of each link). The key node data and channel interconnection link data are analyzed to generate channel interconnection dependency data for describing the logical relationship between nodes and links. Node dependency: B is a relay node for C and A, and D is a relay node for C and E. Link dependency: AB and BC depend on the relay capability of B. According to the channel interconnection dependency data, the channel interconnection topology data is divided into independent service units, and the service units are divided as follows: Unit 1: nodes A and B (including link AB). Unit 2: nodes C and D (including links BC, CD). Unit 3: node E (including link DE). The independent service unit data is further segmented to generate service unit division data, and the service unit division data is encapsulated into containers to generate containerized service unit data. Unit 1→Container C1, Unit 2→Container C2, Unit 3→Container C3. Based on the containerized service unit data, the communication rules and data transmission paths between containers are defined to generate unit container network orchestration data. Container communication rules: C1→C2: priority channel, bandwidth limit 500Mbps. C2→C3: redundant path, delay <15ms. Through the unit container network orchestration data, the container scheduling policy data is generated, including task allocation priority and execution strategy. Priority tasks: tasks with high bandwidth requirements are assigned to the C1→C2 channel. Ordinary tasks: tasks with low latency requirements are assigned to the C2→C3 channel. According to the container scheduling strategy data, optimize the parallelism of task allocation and generate task parallelism data. High priority task parallelism: 4. Ordinary task parallelism: 2. Perform pipeline synchronization on task parallelism data to ensure data consistency and generate parallel test pipeline data. Pipeline structure: Stage 1: C1→C2. Stage 2: C2→C3, stage parallel synchronization completed, task allocation consistency check passed.

[0043] Preferably, concurrent optimization of container scheduling policy data includes: Perform policy execution on the container scheduling policy data to generate container scheduling policy execution data; perform scheduling node screening on the storage channel node distribution data based on the container scheduling policy execution data to obtain the policy execution scheduling node; perform scheduling timestamp analysis on the policy execution scheduling node to generate the node scheduling timestamp; According to the node scheduling timestamp, the strategy execution scheduling nodes are divided into nodes with timestamp differences, and concurrent synchronous timestamp node data and concurrent asynchronous timestamp node data are generated; node task batch processing is performed on the concurrent synchronous timestamp node data to generate a concurrent synchronous node task batch processing strategy; Perform concurrent timestamp calibration on the data of concurrent non-synchronous timestamp nodes and concurrent synchronous timestamp nodes to obtain concurrent timestamp calibration data; perform transaction rollback within the difference timestamp on the concurrent non-synchronous timestamp nodes based on the concurrent timestamp calibration data to generate a non-concurrent synchronous node task rollback strategy; The concurrent synchronization node task batch processing strategy and the non-concurrent synchronization node task rollback strategy are used to concurrently optimize the container scheduling strategy data and generate task parallelism data.

[0044] In an embodiment of the present invention, by executing the container scheduling policy data, the specific scheduling situation of each node is recorded, and the container scheduling policy execution data is generated. The container scheduling policy includes the following rules: priority tasks are assigned to the node group {N1, N2}. Ordinary tasks are assigned to the node group {N3, N4}. Based on the container scheduling policy execution data, the storage channel node distribution data is screened to determine the execution scheduling node, and the screening results are: policy execution scheduling nodes: N1, N2, N3, N4. Timestamp analysis is performed on the policy execution scheduling node, and the task start time, end time, delay and other information of each node are recorded to generate node scheduling timestamp data. N1: start time T1, end time T2, delay 5ms. N2: start time T3, end time T4, delay 3ms. N3: start time T5, end time T6, delay 7ms. N4: start time T7, end time T8, delay 6ms. According to the difference of node scheduling timestamps, it is divided into concurrent synchronous timestamp nodes and concurrent asynchronous timestamp nodes. Synchronous timestamp nodes: N1, N2 (delay difference less than 2ms), asynchronous timestamp nodes: N3, N4 (delay difference greater than 2ms). Batch processing of concurrent synchronous timestamp node data, optimization of node task execution efficiency, and generation of concurrent synchronous node task batch processing strategy. Batch processing strategy: merge the tasks of N1 and N2, uniformly process high priority tasks, and merge the task execution priority queue: {N1, N2}. Timestamp calibration of concurrent asynchronous timestamp node data and concurrent synchronous timestamp node data to ensure the uniformity of task execution and generate concurrent timestamp calibration data. The calibration method is to adjust the execution time of N3 and N4 to synchronize with N1 and N2. For concurrent asynchronous timestamp nodes, roll back tasks to a safe state based on calibration data, generate a non-concurrent synchronous node task rollback strategy, and the rollback range is: task status of N3 and N4. Rollback strategy: reset tasks to T5 and T7. Use batch processing strategy and rollback strategy to comprehensively optimize container scheduling strategy data and generate task parallelism data. The parallelism of synchronous execution tasks is 4 (including N1 and N2), and the parallelism of asynchronous execution tasks is 2 (including N3 and N4).

[0045] Preferably, performing adaptive cache synchronization on parallel test pipeline data includes: Perform distributed cache stratification on parallel test pipeline data to generate cache hierarchy data; perform memory queue optimization on cache hierarchy data to generate queue scheduling strategy data; The queue scheduling policy data is processed by a consistency protocol to generate synchronization state machine data; conflict detection is performed on the synchronization state machine data, and when a conflict is detected in the synchronization state machine data, the conflicting data is merged to generate cache consistency state data.

[0046] In an embodiment of the present invention, distributed cache stratification is performed on parallel test pipeline data, and cache hierarchies are divided according to data access frequency and characteristics to generate cache hierarchical structure data. Level 1 cache: high-frequency access data (task metadata, status data). Level 2 cache: medium-frequency access data (intermediate result data). Level 3 cache: low-frequency access data (historical test pipeline data). Load analysis is performed on queues at each layer of the cache hierarchical structure data to evaluate the read and write pressure and occupancy of the queues. Level 1 cache queue: frequent reads and fewer writes, level 2 cache queue: balanced read and write, and level 3 cache queue: fewer reads and more writes. Based on the load analysis results, the priority and allocation strategy of the memory queue are adjusted to generate queue scheduling strategy data. Level 1 cache queue: prioritize allocating more memory and enable asynchronous write strategy. Level 2 cache queue: evenly allocate memory and enable read-write balance strategy. Level 3 cache queue: enable delayed write strategy to reduce real-time occupancy. Perform consistency protocol processing on the queue scheduling policy data, build a synchronization mechanism, generate synchronization state machine data, use distributed consistency protocols (such as Paxos or Raft) to ensure that each cache level is synchronized and consistent among multiple nodes, and record transaction logs of state changes to support rollback. Detect the synchronization state machine data to determine whether there is conflicting data caused by concurrent writing of multiple nodes. Conflict conditions: more than two nodes modify the same cache key at the same time or the order of state changes is inconsistent. When a conflict is detected in the synchronization state machine data, merge the conflicting data based on the timestamp priority or the final write rule to generate cache consistency state data. Conflict merge rule: Use data with a newer timestamp. If the timestamps are the same, select according to the write priority (node ​​ID). Output: Cache consistency state data: Key_1 merge completed, Key_2 merge completed.

[0047] As an example of the present invention, refer to Figure 3 As shown, in this example, step S3 includes: Step S31: extracting timing characteristics of parallel test pipeline data based on cache consistency state data to obtain parallel test timing characteristic data; Step S32: Perform streaming calculation on the parallel test time series feature data to obtain real-time abnormal index data; divide the real-time abnormal index data into data sets to generate a model training set and a model test set; Step S33: training the model training set by using a long short-term memory neural network algorithm to generate a memory multi-channel fault probability distribution prediction pre-model; optimizing and iterating the memory multi-channel fault probability distribution prediction pre-model by using a model test set to generate a memory multi-channel fault probability distribution prediction model; Step S34: Importing the parallel test timing feature data into the memory multi-channel fault probability distribution prediction model to perform test fault prediction and generate fault probability prediction data.

[0048] In an embodiment of the present invention, the parallel test pipeline data is cleaned and normalized based on the cache consistency state data, invalid or missing data points are removed, and the data is standardized to a unified range (such as [0, 1]). The time series features of the parallel test are extracted using the sliding window mechanism to generate parallel test time series feature data, and the features include: task delay, queue length, read and write rate, data consistency update frequency, etc. Specifically, the sliding window size is 10 seconds. Extracted features: queue length mean: 20, delay standard deviation: 2 milliseconds. Real-time streaming calculation is performed on the parallel test time series feature data to generate real-time abnormal indicator data, and abnormal fluctuations are detected using sliding mean and standard deviation calculation. Threshold conditions: delay> mean + 3× standard deviation, queue length> 95th percentile. Anomaly detected: timestamp 2024-12-12T12:00:15, indicator: delay 50 milliseconds (abnormal). The real-time abnormal indicator data is divided into a training set and a test set: model training set: 80%, model test set: 20%. The model training set is trained using a long short-term memory neural network (LSTM) to generate a memory multi-channel fault probability distribution prediction pre-model. Network structure: 3-layer LSTM, 128 units, optimization algorithm: Adam, learning rate 0.001. The pre-model is optimized and iterated using the model test set: the learning rate and model parameters are adjusted to reduce overfitting, and the stop condition is that the test set loss converges (change < 0.001). The parallel test timing feature data is imported into the prediction model to perform test fault prediction, generate fault probability prediction data, and output the multi-channel fault probability distribution for each time step. Input data: delay 10 milliseconds, queue length 15, read and write rate 5MB / s, output prediction: Time step 1 (next 1 second): channel 1 fault probability 0.01, channel 2 fault probability 0.03. Time step 2 (next 2 seconds): channel 1 fault probability 0.02, channel 2 fault probability 0.05.

[0049] Preferably, step S4 comprises the following steps: Step S41: Generate test signals for parallel test pipeline data according to the fault probability prediction data to obtain channel parallel test signals; collect test data for the channel parallel test signals to obtain channel parallel actual test data; Step S42: Perform data matching calculation on the channel parallel actual test data and the fault probability prediction data to obtain channel parallel test matching data; perform data visualization on the channel parallel test matching data to generate a memory multi-channel parallel test matching report to execute parallel test detection operations.

[0050] In an embodiment of the present invention, a channel parallel test signal is designed and generated according to the fault probability prediction data to stimulate the memory channel to perform parallel testing. Test signal type: random read and write operation, load pressure test signal. Signal generation logic: dynamically adjust the test intensity according to the fault probability of each channel, high fault probability channel: increase the proportion of high-load random signals, low fault probability channel: maintain the basic test signal, specific channel 1 (failure probability 0.3): generate high-load read and write signals (80% random read and write, 20% sequential read and write). Channel 2 (failure probability 0.1): generate medium-load signals (50% random read and write, 50% sequential read and write). Output channel parallel test signal: describe the strength, type and timing of each channel test signal. Execute the test signal through the parallel test pipeline, collect the operating status of each channel in real time, and generate channel parallel actual test data. Collection indicators: read and write delay, throughput, error rate, data consistency status, etc. Collection tool: log system and performance monitoring tool based on distributed memory nodes. Specifically, channel 1: read and write delay 12 milliseconds, error rate 0.05%, channel 2: read and write delay 8 milliseconds, error rate 0.01%. Match and calculate the channel parallel actual test data with the fault probability prediction data to generate channel parallel test matching data. Compare the actual test value and the predicted value at each time step to calculate the matching deviation and accuracy. Deviation: D=|P−A|; where P is the predicted value, A is the actual value, and D is the deviation. Accuracy: R=1−D÷A; channel 1: predicted delay 10 milliseconds, actual delay 12 milliseconds, deviation 2 milliseconds, accuracy 83%. Channel 2: predicted delay 8 milliseconds, actual delay 8 milliseconds, deviation 0 milliseconds, accuracy 100%. Output channel parallel test matching data: matching deviation and accuracy of each channel. Perform data visualization on the channel parallel test matching data to generate a memory multi-channel parallel test matching report. The visualization content includes the matching deviation heat map: showing the matching deviation of each channel at different time steps, the accuracy trend chart: a curve chart showing the matching accuracy of each channel changing over time, and the output memory multi-channel parallel test matching report: summarizing the test results in the form of tables and charts for performing subsequent parallel test detection operations.

[0051] In this specification, a memory-based multi-channel parallel testing system is provided, which is used to execute the above-mentioned memory-based multi-channel parallel testing method. The memory-based multi-channel parallel testing system includes: A channel resource allocation module is used to obtain the original data of the memory test channel; perform topological analysis on the original data of the memory test channel to generate storage channel node distribution data; perform dynamic weight calculation on the storage channel node distribution data to obtain channel priority data; perform resource competition arbitration on the storage channel node distribution data according to the channel priority data to generate channel resource allocation data; The concurrent scheduling module is used to perform control plane mapping on the channel resource allocation data to generate network topology virtualization data; perform routing strategy optimization processing on the network topology virtualization data to generate dynamic routing table data; perform elastic pipeline concurrent scheduling on the dynamic routing table data to generate parallel test pipeline data; perform adaptive cache synchronization on the parallel test pipeline data to generate channel parallel cache consistency state data; A fault prediction module is used to extract timing features of parallel test pipeline data based on cache consistency state data to obtain parallel test timing feature data; perform streaming calculations on the parallel test timing feature data to obtain real-time abnormal indicator data; construct a model based on the real-time abnormal indicator data to generate a memory multi-channel fault probability distribution prediction model; import the parallel test timing feature data into the memory multi-channel fault probability distribution prediction model to perform test fault prediction and generate fault probability prediction data; The parallel test module is used to collect test data for the parallel test pipeline data according to the fault probability prediction data to obtain the actual channel parallel test data; match the actual channel parallel test data with the fault probability prediction data to generate a memory multi-channel parallel test matching report to execute parallel test detection operations.

[0052] The beneficial effect of the present invention is that through topology analysis and dynamic weight calculation, resources can be accurately allocated to each storage channel, resource conflicts and unnecessary delays can be avoided, high-priority channels can be ensured to get faster responses, and overall system performance can be improved. Through network topology virtualization and route optimization, efficient data transmission and fluency are ensured, the risk of network congestion is reduced, and the reliability of data transmission is improved. By performing adaptive cache synchronization in a parallel test pipeline, data consistency between multiple test channels is ensured, test errors caused by cache inconsistency are avoided, and the stability of parallel testing is improved. Through timing feature extraction and streaming computing, potential faults in the system can be detected and predicted in real time. By constructing a multi-channel fault probability distribution prediction model for a memory, potential faults can be warned in advance, thereby improving the reliability of the system. By matching the fault probability prediction data with the actual test data, a parallel test matching report is generated, which provides an accurate execution basis for the parallel test operation of the memory, helps to reduce test time and cost, and improves the accuracy of fault detection. Therefore, the present invention improves the efficiency and accuracy of multi-channel parallel testing of the memory by optimizing channel resource allocation, topology virtualization management, elastic scheduling synchronization, fault prediction and data matching.

[0053] Therefore, the embodiments should be regarded as illustrative and non-restrictive from all points, and the scope of the present invention is limited by the appended claims rather than the above description, and it is therefore intended that all changes falling within the meaning and range of equivalent elements of the application documents are included in the present invention.

[0054] The above description is only a specific embodiment of the present invention, so that those skilled in the art can understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but should conform to the widest scope consistent with the principles and novel features invented herein.

Claims

1. A memory-based multi-channel parallel testing method, characterized in that: The following steps are involved: Step S1: Obtaining raw data of a memory test channel; Perform topological analysis on the original data of the memory test channel to generate the memory channel node distribution data; Perform dynamic weight calculation on the storage channel node distribution data to obtain channel priority data; Perform resource competition arbitration on the storage channel node distribution data according to the channel priority data, and generate channel resource allocation data; Step S2: performing control plane mapping on the channel resource allocation data to generate network topology virtualization data; Perform routing strategy optimization processing on network topology virtualization data to generate dynamic routing table data; perform elastic pipeline concurrent scheduling on dynamic routing table data to generate parallel test pipeline data; Adaptively synchronize caches of parallel test pipeline data to generate channel parallel cache consistency state data; Step S3: extracting timing characteristics of the parallel test pipeline data based on the cache consistency state data to obtain parallel test timing characteristic data; Perform streaming calculations on parallel test time series feature data to obtain real-time abnormal indicator data; Based on the real-time abnormal index data, a model is constructed to generate a memory multi-channel fault probability distribution prediction model; parallel test timing feature data is imported into the memory multi-channel fault probability distribution prediction model to perform test fault prediction and generate fault probability prediction data; Step S4: collecting test data for the parallel test pipeline data according to the fault probability prediction data to obtain channel parallel actual test data; The actual channel parallel test data and the fault probability prediction data are matched to generate a memory multi-channel parallel test matching report to perform parallel test detection operations.

2. The memory-based multi-channel parallel testing method according to claim 1, characterized in that: Step S1 includes the following steps: Step S11: obtaining original data of the memory test channel; Step S12: performing data preprocessing on the original data of the memory test channel to generate standard memory test channel data, wherein the data preprocessing includes data cleaning, data denoising, data missing value filling and data standardization; performing NUMA topology analysis on the standard memory test channel data to generate storage channel node distribution data; Step S13: performing node edge computing resource evaluation on the storage channel node distribution data to generate node computing load distribution data; performing dynamic weight calculation on the storage channel nodes through the node computing load distribution data to obtain channel priority data; Step S14: performing resource competition arbitration on the storage channel node distribution data according to the channel priority data to generate channel resource allocation data.

3. The memory-based multi-channel parallel testing method according to claim 2, characterized in that: Step S14 includes the following steps: Step S141: performing resource competition identification on the storage channel node distribution data to obtain channel node resource competition data; Step S142: defining arbitration rules for channel node resource competition data based on the first-in-first-out principle to obtain node resource competition arbitration rule data; Step S143: performing local resource allocation on the channel node resource competition data according to the node resource competition arbitration rule data to generate node resource allocation data; Step S144: using the channel priority data to perform global channel resource allocation adjustment on the node resource allocation data to generate channel resource allocation data.

4. The memory-based multi-channel parallel testing method according to claim 1, characterized in that: Step S2 includes the following steps: Step S21: performing resource data abstraction on the channel resource allocation data to obtain channel resource allocation abstract data, wherein the resource data abstraction includes device type abstraction, connection relationship abstraction and address information abstraction; performing topology modeling on the channel resource allocation abstract data to generate resource allocation physical network topology data; Step S22: performing control plane mapping on the resource allocation physical network topology data through the SDN controller to generate network topology virtualization data; performing routing demand analysis on the network topology virtualization data to generate routing demand data; performing routing strategy optimization processing on the network topology virtualization data based on the routing demand data to generate dynamic routing table data; Step S23: performing link aggregation analysis on the dynamic routing table data to generate bandwidth allocation strategy data; performing topology adaptive processing on the bandwidth allocation strategy data to generate channel interconnection topology data; performing elastic pipeline concurrent scheduling on the channel interconnection topology data to generate parallel test pipeline data; Step S24: performing adaptive cache synchronization on the parallel test pipeline data to generate channel parallel cache consistency state data.

5. The memory-based multi-channel parallel testing method according to claim 4, characterized in that: Flexible pipeline concurrent scheduling of channel interconnect topology data includes: Extract key channel features from the channel interconnection topology data to obtain channel interconnection key feature data, wherein the channel interconnection key feature data includes key node data and channel interconnection link data; perform dependency analysis on the key node data and the channel interconnection link data to generate channel interconnection dependency data; According to the channel interconnection dependency data, the channel interconnection topology data is divided into service units to generate independent service unit data; based on the independent service unit data, the channel interconnection topology data is segmented into microservices to generate service unit division data; Perform service unit containerization on the service unit division data to generate containerized service unit data; perform container network orchestration on the containerized service unit data to generate unit container network orchestration data; perform container orchestration mapping on the containerized service unit data through the unit container network orchestration data to generate container scheduling strategy data; Concurrency optimization is performed on the container scheduling strategy data to generate task parallelism data; pipeline synchronization is performed on the task parallelism data to generate parallel test pipeline data.

6. The memory-based multi-channel parallel testing method according to claim 5, characterized in that: Concurrency optimization of container scheduling policy data includes: Perform policy execution on the container scheduling policy data to generate container scheduling policy execution data; perform scheduling node screening on the storage channel node distribution data based on the container scheduling policy execution data to obtain the policy execution scheduling node; perform scheduling timestamp analysis on the policy execution scheduling node to generate the node scheduling timestamp; According to the node scheduling timestamp, the strategy execution scheduling nodes are divided into nodes with timestamp differences, and concurrent synchronous timestamp node data and concurrent asynchronous timestamp node data are generated; node task batch processing is performed on the concurrent synchronous timestamp node data to generate a concurrent synchronous node task batch processing strategy; Perform concurrent timestamp calibration on the data of concurrent non-synchronous timestamp nodes and concurrent synchronous timestamp nodes to obtain concurrent timestamp calibration data; perform transaction rollback within the difference timestamp on the concurrent non-synchronous timestamp nodes based on the concurrent timestamp calibration data to generate a non-concurrent synchronous node task rollback strategy; The concurrent synchronization node task batch processing strategy and the non-concurrent synchronization node task rollback strategy are used to concurrently optimize the container scheduling strategy data and generate task parallelism data.

7. The memory-based multi-channel parallel testing method according to claim 4, characterized in that: Adaptive cache synchronization of parallel test pipeline data includes: Perform distributed cache stratification on parallel test pipeline data to generate cache hierarchy data; perform memory queue optimization on cache hierarchy data to generate queue scheduling strategy data; The queue scheduling policy data is processed by a consistency protocol to generate synchronization state machine data; conflict detection is performed on the synchronization state machine data, and when a conflict is detected in the synchronization state machine data, the conflicting data is merged to generate cache consistency state data.

8. The memory-based multi-channel parallel testing method according to claim 1, characterized in that: Step S3 includes the following steps: Step S31: extracting timing characteristics of parallel test pipeline data based on cache consistency state data to obtain parallel test timing characteristic data; Step S32: Perform streaming calculation on the parallel test time series feature data to obtain real-time abnormal index data; divide the real-time abnormal index data into data sets to generate a model training set and a model test set; Step S33: training the model training set by using a long short-term memory neural network algorithm to generate a memory multi-channel fault probability distribution prediction pre-model; optimizing and iterating the memory multi-channel fault probability distribution prediction pre-model by using a model test set to generate a memory multi-channel fault probability distribution prediction model; Step S34: Importing the parallel test timing feature data into the memory multi-channel fault probability distribution prediction model to perform test fault prediction and generate fault probability prediction data.

9. The memory-based multi-channel parallel testing method according to claim 1, characterized in that: Step S4 includes the following steps: Step S41: Generate test signals for parallel test pipeline data according to the fault probability prediction data to obtain channel parallel test signals; collect test data for the channel parallel test signals to obtain channel parallel actual test data; Step S42: Perform data matching calculation on the channel parallel actual test data and the fault probability prediction data to obtain channel parallel test matching data; perform data visualization on the channel parallel test matching data to generate a memory multi-channel parallel test matching report to execute parallel test detection operations.

10. A memory-based multi-channel parallel test system, characterized in that: For executing the memory-based multi-channel parallel testing method as claimed in claim 1, the memory-based multi-channel parallel testing system comprises: A channel resource allocation module is used to obtain the original data of the memory test channel; perform topological analysis on the original data of the memory test channel to generate storage channel node distribution data; perform dynamic weight calculation on the storage channel node distribution data to obtain channel priority data; perform resource competition arbitration on the storage channel node distribution data according to the channel priority data to generate channel resource allocation data; The concurrent scheduling module is used to perform control plane mapping on the channel resource allocation data to generate network topology virtualization data; perform routing strategy optimization processing on the network topology virtualization data to generate dynamic routing table data; perform elastic pipeline concurrent scheduling on the dynamic routing table data to generate parallel test pipeline data; perform adaptive cache synchronization on the parallel test pipeline data to generate channel parallel cache consistency state data; A fault prediction module is used to extract timing features of parallel test pipeline data based on cache consistency state data to obtain parallel test timing feature data; perform streaming calculations on the parallel test timing feature data to obtain real-time abnormal indicator data; construct a model based on the real-time abnormal indicator data to generate a memory multi-channel fault probability distribution prediction model; import the parallel test timing feature data into the memory multi-channel fault probability distribution prediction model to perform test fault prediction and generate fault probability prediction data; The parallel test module is used to collect test data for the parallel test pipeline data according to the fault probability prediction data to obtain the actual channel parallel test data; match the actual channel parallel test data with the fault probability prediction data to generate a memory multi-channel parallel test matching report to perform parallel test detection operations.

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