Cache architecture optimization method and device of multi-core particle integration system and storage medium

Abstract

The application relates to a cache architecture optimization method, device and storage medium of a multi-core particle integrated system, wherein the cache architecture optimization method of the multi-core particle integrated system comprises the following steps: acquiring an architecture topology graph of the multi-core particle integrated system; the architecture topology graph comprises a storage hierarchy graph and a network topology graph; the storage hierarchy graph is a hierarchical connection graph of a cache subsystem of the multi-core particle integrated system; the network topology graph is a core particle connection graph of the multi-core particle integrated system; based on the architecture topology graph, a system performance model is constructed; the system performance model is solved to obtain target cache parameters, and based on the target cache parameters and the storage hierarchy graph, a target cache architecture graph is generated. Through the application, the problem that the architecture of the cache subsystem in the multi-core particle integrated system is difficult to achieve optimal optimization is solved.

Description

Technical Field

[0001] This application relates to the field of integrated circuits, and in particular to methods, apparatus and storage media for optimizing cache architectures in multi-chip integrated systems. Background Technology

[0002] Multi-chiplet integration technology is a semiconductor technology that integrates multiple chips with specific functions to create high-performance, multi-functional chips. This technology breaks the area limitations of single-chip manufacturing, achieving higher integration and computing power. A multi-chiplet system refers to a manufacturer dividing a single chip into multiple smaller chips (such as processor cores, cache, memory controllers, I / O interfaces, etc.) according to system performance requirements, and combining them using advanced packaging technologies.

[0003] In multi-core integrated systems, multi-level cache structures can be used to optimize the performance of the cache subsystem. Among related technologies, the architectural designs of multi-core-based cache subsystems mainly fall into two categories. One category is similar to chips designed by chip manufacturers such as Intel and AMD, designed to support a wide range of computing tasks and applications, from simple office software to complex scientific computing and gaming. This architecture design is not optimized for any specific application but rather provides a balanced performance to meet the needs of most users. Therefore, for specific or non-general-purpose applications, its designed architecture may not achieve optimal performance. The other category involves cache subsystem architecture parameters obtained through design space exploration. However, existing design space exploration methods have the following problems: they are not specifically designed for multi-core integrated systems or have limited cache parameters based on multi-core integrated systems, and there are restrictions on the types of cores.

[0004] Currently, no effective solution has been proposed to address the issue of the difficulty in achieving optimal architecture for the cache subsystem in multi-core integrated systems in related technologies. Summary of the Invention

[0005] This application provides a method, apparatus, and storage medium for optimizing the cache architecture of a multi-core integrated system, in order to at least solve the problem that the architecture of the cache subsystem in a multi-core integrated system is difficult to optimize in the related art.

[0006] In a first aspect, embodiments of this application provide a method for optimizing the cache architecture of a multi-core integrated system, the method comprising:

[0007] Obtain the architecture topology diagram of the multi-core integrated system; the architecture topology diagram includes a storage hierarchy diagram and a network topology diagram; the storage hierarchy diagram is the hierarchical connection diagram of the cache subsystem of the multi-core integrated system; the network topology diagram is the core connection diagram of the multi-core integrated system.

[0008] Based on the aforementioned architecture topology diagram, a system performance model is constructed;

[0009] The system performance model is solved to obtain the target cache parameters, and a target cache architecture diagram is generated based on the target cache parameters and the storage hierarchy diagram.

[0010] In some embodiments, constructing a system performance model based on the architecture topology diagram includes:

[0011] Based on the storage hierarchy diagram in the architecture topology diagram, the miss rate of the cache subsystem is modeled to generate a miss rate model, and based on the network topology diagram in the architecture topology diagram, the network latency of the multi-core integrated system is modeled to generate a latency model.

[0012] Based on the missing rate model and the latency model, the system performance model is constructed.

[0013] In some embodiments, modeling the miss rate of the cache subsystem based on the storage hierarchy diagram in the architecture topology diagram to generate a miss rate model includes:

[0014] Based on the storage hierarchy diagram, the cache hierarchy node set of the cache subsystem is determined; the cache hierarchy node set is the set of upper-level cache nodes of the current node in the cache hierarchy structure of the cache subsystem.

[0015] Based on the set of cache hierarchy nodes, the missing rate of the cache subsystem is modeled to generate the missing rate model.

[0016] In some embodiments, modeling the network latency of the multi-core integrated system based on the network topology diagram in the architecture topology diagram to generate a latency model includes:

[0017] Based on the network topology, the node positional relationship between the starting node and the destination node in the multi-core integrated system is determined;

[0018] When the node position relationship indicates that the starting node and the destination node are located in the same chip, a first delay model is generated based on the chip-on-chip delay in the multi-chip integrated system.

[0019] When the node position relationship indicates that the starting node and the destination node are located in different chips, a second delay model is generated based on the intra-chip delay and inter-chip delay in the multi-chip integrated system.

[0020] The delay model includes the first delay model and the second delay model.

[0021] In some embodiments, the different granules include a first granule and a second granule, wherein the first granule is the granule containing the starting node, and the second granule is the granule containing the destination node; generating a second delay model based on the intra-chip delay and inter-chip delay in the multi-granule integrated system includes:

[0022] Identify the first interface node in the first core and the second interface node in the second core;

[0023] Based on the network topology, a first path, a second path, and a third path are calculated; the first path is the path between the starting node and the first interface node in the first core, the second path is the path between the destination node and the second interface node in the second core, and the third path is the path between the first interface node and the second interface node.

[0024] Based on the first path and the second path, the intra-chip delay is obtained, the inter-chip delay is obtained based on the third path, and a second delay model is generated according to the intra-chip delay and the inter-chip delay.

[0025] In some embodiments, constructing the system performance model based on the missing rate model and the latency model includes:

[0026] Based on the missing rate model and the latency model, the cache missing rate and cache latency time of each level of cache in the cache subsystem are obtained, and based on the cache latency time, the average latency time between adjacent cache levels in the core is calculated.

[0027] The system performance model is constructed based on the cache miss rate and the average latency.

[0028] In some embodiments, solving the system performance model to obtain the target cache parameters includes:

[0029] Obtain the preset architecture area of ​​the cache subsystem, and determine the area constraint condition that the architecture area of ​​the cache subsystem is less than the preset architecture area;

[0030] Obtain the preset architecture power consumption of the cache subsystem, and determine the power consumption constraint condition that the architecture power consumption of the cache subsystem is less than the preset architecture power consumption;

[0031] Based on the area constraint and the power consumption constraint, the system performance model is solved to obtain the target cache parameters.

[0032] In some embodiments, solving the system performance model to obtain the target cache parameters includes:

[0033] Based on the system performance model, the root node is constructed according to the architecture topology diagram;

[0034] Starting from the root node, the branch value range of each layer of child nodes is determined layer by layer based on the architecture topology diagram, and a search tree is constructed layer by layer according to the branch value range; the search tree includes the root node and each layer of child nodes;

[0035] The target cache parameters are obtained by traversing the tree nodes in the search tree and solving for them.

[0036] Secondly, embodiments of this application provide a cache architecture optimization device for a multi-core integrated system, comprising:

[0037] The acquisition module is used to acquire the architecture topology diagram of the multi-core integrated system; the architecture topology diagram includes a storage hierarchy diagram and a network topology diagram; the storage hierarchy diagram is a hierarchical connection diagram of the cache subsystem of the multi-core integrated system; the network topology diagram is a core connection diagram of the multi-core integrated system.

[0038] The model building module is used to build a system performance model based on the architecture topology diagram.

[0039] The generation module is used to solve the system performance model to obtain the target cache parameters, and generate the target cache architecture diagram based on the target cache parameters and the storage hierarchy diagram.

[0040] Thirdly, embodiments of this application provide a storage medium storing a computer program thereon, which, when executed by a processor, implements the cache architecture optimization method for a multi-core integrated system as described in the first aspect above.

[0041] Compared to related technologies, the cache architecture optimization method, apparatus, and storage medium for multi-core integrated systems provided in this application obtain an architecture topology diagram of the multi-core integrated system. The architecture topology diagram includes a storage hierarchy diagram and a network topology diagram. The storage hierarchy diagram is a hierarchical connection diagram of the cache subsystems of the multi-core integrated system. The network topology diagram is a core connection diagram of the multi-core integrated system. Based on the architecture topology diagram, a system performance model is constructed. The system performance model is solved to obtain target cache parameters, and a target cache architecture diagram is generated based on the target cache parameters and the storage hierarchy diagram.

[0042] Based on this, by designing configurable caching hierarchies (such as resizable first-level and second-level caches), cache resource allocation can be dynamically adjusted according to application needs to improve system performance. This enables modeling of the cache subsystem based on the multi-core integrated system, and designing corresponding cache subsystem architectures for different types of applications, solving the problem that the architecture of the cache subsystem in the multi-core integrated system is difficult to optimize. At the same time, the cache subsystem based on the multi-core integrated system has a large number of related parameters, which can meet the current needs for exploring the design space of the cache subsystem.

[0043] Details of one or more embodiments of this application are set forth in the following drawings and description to make other features, objects and advantages of this application more readily apparent. Attached Figure Description

[0044] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0045] Figure 1 This is a hardware structure block diagram of a terminal for a cache architecture optimization method of a multi-core integrated system according to an embodiment of this application;

[0046] Figure 2 This is a flowchart of a cache architecture optimization method for a multi-core integrated system according to an embodiment of this application;

[0047] Figure 3 This is a schematic diagram of a storage hierarchy diagram according to an embodiment of this application;

[0048] Figure 4 This is a schematic diagram of a network topology according to an embodiment of this application;

[0049] Figure 5 This is a flowchart of another cache architecture optimization method for a multi-core integrated system according to an embodiment of this application;

[0050] Figure 6 This is a structural block diagram of a cache architecture optimization device for a multi-core integrated system according to an embodiment of this application. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of this application clearer, the application is described and illustrated below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the application. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application without inventive effort are within the scope of protection of this application. Furthermore, it is understood that although the efforts made in such a development process may be complex and lengthy, for those skilled in the art related to the content disclosed in this application, modifications to design, manufacturing, or production based on the technical content disclosed in this application are merely conventional technical means and should not be construed as insufficient disclosure of the content of this application.

[0052] In this application, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment that is mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this application may be combined with other embodiments without conflict.

[0053] Unless otherwise defined, the technical or scientific terms used in this application shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms “a,” “an,” “an,” “the,” and similar words used in this application do not indicate quantity limitation and may indicate singular or plural. The terms “comprising,” “including,” “having,” and any variations thereof used in this application are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may also include steps or units not listed, or may include other steps or units inherent to these processes, methods, products, or devices. The terms “connected,” “linked,” “coupled,” and similar words used in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. “Multiple” used in this application means two or more. “And / or” describes the relationship between related objects, indicating that three relationships may exist; for example, “A and / or B” can represent: A alone, A and B simultaneously, and B alone. The terms “first,” “second,” “third,” etc., used in this application are merely to distinguish similar objects and do not represent a specific ordering of the objects.

[0054] The method embodiments provided in this example can be executed on a terminal, computer, or similar computing device. Taking running on a terminal as an example, Figure 1 This is a hardware structure block diagram of a terminal for a cache architecture optimization method of a multi-core integrated system according to an embodiment of this application. Figure 1 As shown, a terminal may include one or more ( Figure 1 Only one is shown in the diagram. A processor 102 (which may include, but is not limited to, a microprocessor MCU or a programmable logic device FPGA, etc.) and a memory 104 for storing data are also shown. Optionally, the terminal may further include a transmission device 106 for communication functions and an input / output device 108. Those skilled in the art will understand that... Figure 1 The structure shown is for illustrative purposes only and does not limit the structure of the terminal described above. For example, the terminal may also include components that are more... Figure 1 The more or fewer components shown, or having the same Figure 1 The different configurations shown.

[0055] The memory 104 can be used to store computer programs, such as application software programs and modules, like the computer program corresponding to the cache architecture optimization method of the multi-core integrated system in this embodiment. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, thereby implementing the above-described method. The memory 104 may include high-speed random access memory and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include memory remotely located relative to the processor 102, and these remote memories can be connected to the terminal via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0056] The transmission device 106 is used to receive or send data via a network. Specific examples of the network described above may include a wireless network provided by the terminal's communication provider. In one example, the transmission device 106 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device 106 may be a Radio Frequency (RF) module used for wireless communication with the Internet.

[0057] This embodiment provides a method for optimizing the cache architecture of a multi-core integrated system. Figure 2 This is a flowchart of a cache architecture optimization method for a multi-core integrated system according to an embodiment of this application, such as... Figure 2 As shown, the process includes the following steps:

[0058] Step S210: Obtain the architecture topology diagram of the multi-core integrated system; the architecture topology diagram includes a storage hierarchy diagram and a network topology diagram; the storage hierarchy diagram is the hierarchical connection diagram of the cache subsystem of the multi-core integrated system; the network topology diagram is the core connection diagram of the multi-core integrated system.

[0059] Specifically, the aforementioned storage hierarchy graph G1(V,E) is an undirected graph, referring to the storage hierarchy graph of the cache subsystem of a multi-core integrated system. Each node v... ijk ∈V can represent a CPU core, cache unit, or memory unit. Its subscript i indicates the node number within the core, and j indicates the cache level where the node is located; when j = 0, it represents the current node as a CPU core, and when j = 0, it represents the current node as a cache level. <j<h k When j = h, it means the current node is a cache unit. k When , it indicates that the current node is a memory unit; k indicates the node's core number. e ijk,mno (v ijk ,v mno )∈E represents v ijk and v mno Interconnectivity between (e.g., between the core and cache, between two levels of cache units, or between cache and memory). If v ijk and v mno If they are reachable, then e ijk,mno (v ijk ,v mno =1, otherwise 0.

[0060] For example, please refer to Figure 3 The multi-chip integrated system shown in the diagram includes Chiplet1, Chiplet2, and Chiplet3. Chiplet1 and Chiplet2 each include a CPU, a Level 1 cache, a Level 2 cache, and a Level 3 cache, respectively, while Chiplet3 includes a Level 1 cache. Each level includes cache nodes, such as V... 101 This represents the first node within a core, located in level 0 cache (i.e., the CPU core), and belonging to core 1. Based on the connectivity between cache levels within each core, the storage hierarchy diagram of the cache subsystem in this multi-core integrated system is determined.

[0061] On the other hand, the network topology graph G2(N,C) is an undirected graph, referring to the connections between cores and within cores in a multi-core integrated system. Each node n... pq ∈N represents a node in the system, composed of the core, cache, and routing. Its subscript p indicates the node number within the core, and q indicates the core number. c p,q,r,s (np,q ,n r,s )∈C represents adjacent node n p,q and n r,s Connectivity between; n r,s In a multi-core integrated system, the relationship between node n... pq Adjacent nodes; similarly, its subscript r indicates the node number within the core, and s indicates the core number. If n p,q and n r,s If there is a connection between them, then c p,q,r,s (n p,q ,n r,s =1, otherwise 0.

[0062] For example, please see Figure 4 In the multi-core integrated system shown in the figure, core 1, core 2, and core 3 each include various system nodes, such as n 11 n 21 Let represent the first node and the second node in core 1. Based on the connections between and within each core, the network topology of the multi-core integrated system is determined.

[0063] Step S220: Based on the architecture topology diagram, construct a system performance model.

[0064] Specifically, based on the application requirements of the multi-core integrated system, the performance indicators to be evaluated, such as throughput, response time, and power consumption, are determined. Furthermore, based on the storage hierarchy diagram and network topology diagram in the aforementioned architecture topology, a data model of system performance is established. This model reflects the interactions and influences between the components of the cache subsystem in the multi-core integrated system, as well as the relationship between performance indicators and cache parameters.

[0065] It should also be noted that, in this step, necessary constraints can be introduced based on the actual situation of the multi-core integrated system, such as cache size, bandwidth limit, power consumption budget, etc.

[0066] Step S230: Solve the system performance model to obtain the target cache parameters, and generate the target cache architecture diagram based on the target cache parameters and the storage hierarchy diagram.

[0067] Based on the complexity of the system performance model and the solution requirements, an appropriate solution method is selected, such as branch and bound, dynamic programming, or simulated annealing. Using the selected method, the system performance model is solved to find the optimal combination of cache parameters that satisfies the constraints and achieves the best performance.

[0068] Optionally, the target cache parameters obtained in the above process are also verified to ensure that they can meet the system's performance and constraint requirements in practical applications.

[0069] Optionally, the above system performance model can be an average number of instructions executed per clock cycle (IPC) model. Based on the IPC model, the IPC parameters of the multi-chip integrated system can be calculated, which is the number of instructions that the multi-chip integrated system can execute in each clock cycle. The IPC parameters can be used to evaluate the performance of the multi-chip integrated system.

[0070] Next, based on the target cache parameters obtained from the solution, the cache levels and parameter settings in the storage hierarchy diagram are updated. Then, using graphical tools or specialized software, the target cache architecture diagram is drawn based on the updated storage hierarchy diagram, ultimately obtaining the optimal architecture parameters for the cache subsystem of the multi-core integrated system. Through the above steps, the target cache architecture diagram is optimized to ensure good performance and scalability in practical applications, achieving architectural optimization of the cache subsystem in the multi-core integrated system. Furthermore, the above modeling does not restrict the internal structure of the cores, allowing for arbitrary combinations of various core types, and each core has a different internal structure.

[0071] The cache architecture optimization method for multi-core integrated systems provided in this application involves modeling the storage hierarchy of the cache subsystem and the network topology of the multi-core integrated system. A performance model is then constructed based on the obtained storage hierarchy and network topology diagrams to solve for cache parameters. By designing configurable cache hierarchies (such as resizable level 1 and level 2 caches), cache resource allocation can be dynamically adjusted according to application requirements to improve system performance. This allows for modeling the cache subsystem of the multi-core integrated system and designing corresponding cache subsystem architectures for different types of applications, solving the problem of achieving optimal cache subsystem architecture in multi-core integrated systems. Furthermore, the numerous parameters related to the cache subsystem of the multi-core integrated system meet the current needs for exploring the design space of cache subsystems.

[0072] In some embodiments, a method for optimizing the cache architecture of a multi-core integrated system is also provided. Figure 5 This is a flowchart of another cache architecture optimization method for a multi-core integrated system according to an embodiment of this application, such as... Figure 5 As shown, the process includes Figure 2 The steps S210 and S230 shown herein also include the following steps:

[0073] Step S510: Based on the storage hierarchy diagram in the architecture topology diagram, model the miss rate of the cache subsystem to generate a miss rate model, and based on the network topology diagram in the architecture topology diagram, model the network latency of the multi-core integrated system to generate a latency model.

[0074] Specifically, relevant parameters of the caching subsystem, such as cache size, cache level, and caching strategy, are extracted from the storage hierarchy diagram. An appropriate miss rate model is selected based on system characteristics and requirements, such as a model based on access frequency or a working set model. The extracted parameters are input into the miss rate model, and the initial and boundary conditions of the model are set to generate the miss rate model for the caching subsystem.

[0075] Furthermore, relevant network parameters, such as network bandwidth, latency, and topology, are extracted from the network topology diagram. An appropriate latency model, such as a queue-based model or a flow-based model, is selected based on network characteristics and requirements. The extracted parameters are then input into the latency model, and initial and boundary conditions are set to generate a network latency model for the multi-core integrated system.

[0076] Step S520: Construct a system performance model based on the missing rate model and the latency model.

[0077] In this step, the missing rate model and the latency model are integrated to form a complete system performance model.

[0078] Through steps S510 to S520 above, an accurate and efficient system performance model can be constructed, providing strong support for the performance evaluation and optimization of actual systems.

[0079] In some embodiments, the above-mentioned modeling of the miss rate of the cache subsystem based on the storage hierarchy diagram in the architecture topology diagram to generate a miss rate model may further include the following steps:

[0080] Based on the storage hierarchy graph, the cache hierarchy node set of the cache subsystem is determined; the cache hierarchy node set is the set of upper-level cache nodes of the current node in the cache hierarchy structure of the cache subsystem; based on the cache hierarchy node set, the miss rate of the cache subsystem is modeled to generate a miss rate model.

[0081] In this step, the miss rate of the cache subsystem of the multi-core integrated system can be modeled using the storage hierarchy graph G1(V,E). The cache parameters involved in the modeling include those related to the miss rate of each level of the cache subsystem, such as cache size, cache line size, and cache associativity.

[0082] Specifically, based on the given storage hierarchy graph G1(V,E), node v ijk (0 <j≤h ε The missing rate of -1) is M(v ijk ).definition It is a cache hierarchy that contains v ijkThe set of upper-level cache nodes (i.e., the aforementioned cache hierarchy node set). Then, based on this cache hierarchy node set, the miss rate modeling formula is extended to a multi-parameter, polynomial form, without termination restrictions, and the cache correlation coefficient and polynomial order are specifically defined for the core, thereby establishing a miss rate model. For example, v ijk The cache miss rate is modeled as follows:

[0083]

[0084] In the above formula, M(v) ijk ) represents the cache miss rate (i.e., the missing rate), where a, b, c, and a' represent the cache miss rate. i b i and c i These are cache correlation coefficients, α, β, γ, and α, used to model the missing rate in core particle k. i β i and γ i cs(v) is the polynomial order used to model the missing rate in core particle k. ijk ) is the cache size, cl(v) ijk ) is the cache line size, as(v ijk ) represents cache relevance; n α It represents the total number of cores.

[0085] In existing technologies, missing rate modeling usually focuses directly on the attributes of a single node and its parent nodes, without emphasizing the interaction between parameters or the global impact. Parameter collection and organization rely on explicit traversal of node paths, which is a complex process. Furthermore, the limitation on the fitting order during modeling results in a relatively fixed number and complexity of parameters.

[0086] In comparison, this application, through the above embodiments, directly uses defined cache parameters for modeling, and simultaneously expresses the upper-level cache nodes to which a node belongs through a set, uniformly considering the cumulative effect of the attributes of each level of cache node and the parameters of the upper-level node. This, combined with the above-defined storage hierarchy diagram and its nodes, expresses the hierarchical relationship of the overall multi-core integrated system, making the modeling clearer and simpler. Furthermore, the embodiments of this application extend the missing rate modeling formula to a multi-parameter, polynomial form, without limiting the order, and the cache correlation coefficient and polynomial order in the modeling formula are specifically defined for cores, thereby improving the flexibility of missing rate modeling.

[0087] In some embodiments, the above-mentioned network topology diagram based on the architecture topology diagram, which models the network latency of the multi-core integrated system and generates a latency model, may further include the following steps:

[0088] Step S511: Based on the network topology diagram, determine the node position relationship between the starting node and the destination node in the multi-core integrated system.

[0089] In this embodiment, the network latency of the multi-core integrated system can be modeled using the network topology diagram described above, and D(n) can be used to model the network latency of the multi-core integrated system. p,q ,n r,s ) is defined as node n p,q to node n r,s The transmission delay. (The last part is incomplete and likely refers to a specific value or parameter.) y (n p,q ,n r,s )={n p,q ,n x,y ,…,n r,s} is defined as starting from node n p,q to n r,s The set of all nodes in the path, where n p,q It is Γ1, n r,s It is Γ n The path length is l. A set of paths provides a unified description of all nodes within the path, making the modeling more systematic.

[0090] When considering the delay between two nodes, it is necessary to discuss whether they are located on the same core. Specifically, when calculating the delay, each node on the core of the multi-core integrated system is traversed as the starting node to calculate the delay between the starting node and other nodes, and it is determined whether the starting node and other nodes that are the destination nodes are on the same core, so that different delay models can be used in subsequent steps.

[0091] Step S512: When the node position relationship indicates that the starting node and the destination node are located in the same core, the on-chip delay of the core in the multi-core integrated system is obtained according to the network topology diagram, and a first delay model is generated based on the on-chip delay of the core.

[0092] Where, if the two nodes n involved in calculating the delay p,q and n r,s (node ​​n can be used) p,q Treat node n as the starting node, and... r,s If the target node is located on the same chip, such that q = s, then the delay is only the intra-chip delay of the multi-chip integrated system. The delay model is as follows:

[0093]

[0094] In the above formula, c p,q,r,q Used to represent node n p,q and n r,s The path between; for any p, there exists a path such that p is greater than or equal to 1 and less than or equal to |R|. q| holds true; for any q, there exists a q such that q is greater than or equal to 1 and less than or equal to m; for any r, there exists a r such that r is greater than or equal to 1 and less than or equal to |R|. q |+d q Established. Among them, |R q | represents the number of cores in the q-th core, m represents the number of cores, and dq represents the number of D2D communication interfaces in the core.

[0095] Step S513: When the node position relationship indicates that the starting node and the destination node are located in different chips, obtain the intra-chip delay and inter-chip delay in the multi-chip integrated system according to the network topology diagram, and generate a second delay model based on the intra-chip delay and inter-chip delay; wherein, the delay model includes a first delay model and a second delay model.

[0096] If node n p,q and n r,s On different cores, if q≠s, then the delay is the sum of the intra-core delay and the inter-core delay of the multi-core integrated system. Therefore, by determining whether adjacent nodes are located on the same core, the corresponding delay model is determined, thus more accurately describing the communication delay characteristics of the multi-core integrated system.

[0097] Optionally, in some embodiments, the aforementioned different cores include a first core and a second core; in other words, it can be determined that the starting node and the destination node currently participating in the delay calculation are located on the first core and the second core, respectively; wherein, the first core is the core where the starting node is located, and the second core is the core where the destination node is located. The generation of the second delay model based on the intra-chip delay and inter-chip delay in the multi-core integrated system may further include the following steps:

[0098] Identify the first interface node in the first core and the second interface node in the second core; calculate the first path, the second path, and the third path based on the network topology graph; the first path is the path between the starting node and the first interface node in the first core, the second path is the path between the destination node and the second interface node in the second core, and the third path is the path between the first interface node and the second interface node; obtain the intra-chip delay based on the first path and the second path, obtain the inter-chip delay based on the third path, and generate a second delay model based on the intra-chip delay and the inter-chip delay.

[0099] Specifically, when, based on the node position relationships determined above, it is detected that the current adjacent nodes are located in different core particles, these different core particles are distinguished as a first core particle and a second core particle. p' is defined as a D2D (Die-to-Die) interface node on the first core particle (i.e., the aforementioned first interface node), and r' is defined as a D2D interface node located on the second core particle (i.e., the aforementioned second interface node). For example, please refer to... Figure 3 or Figure 4 Each core has one or more D2D interfaces for data communication between different cores. Each core should not have more than four D2D interfaces, i.e., the number of D2D interfaces is di, i = {1, ..., 4}. For the j-th core, the index of the D2D interface can be defined as: n |Rj|+1，j , ..., n |Rj|+di，j |Rj| represents the number of cores in core j. The first interface node and the second interface node are located on the first and second cores, respectively, and communicate with nodes on the other core via a D2D interface. The first interface node p` satisfies p`∈Γ. y (n p,q ,n r,s The second interface node r` satisfies r`∈Γ y (n p,q ,n r,s ).

[0100] For example, one of the delay models established above based on the first path, the second path, and the third path is shown in the following formula:

[0101]

[0102] In the above formula, |R s | represents the number of cores in the s-th core. The first term represents the path between each node in the first core and the first interface node (i.e., the first path), the second term represents the path between the first interface node and the second interface node (i.e., the third path), and the third term represents the path between each node in the second core and the second interface node (i.e., the second path). It can be seen that the sum of the first and third terms is the formula for calculating the intra-core delay, and the second term is the formula for calculating the inter-core delay. By adding the intra-core delay and the inter-core delay, a delay model can be established when adjacent nodes are located in different cores.

[0103] Through the above embodiments, intra-chip latency and inter-chip latency are distinguished, and relevant latency models are defined for each, describing in detail the latency composition of intra-chip paths and cross-chip paths. At the same time, p` and r` are innovatively introduced to represent inter-chip D2D interface nodes, and the latency accumulation of intra-chip paths and cross-chip paths is calculated respectively, thereby more accurately describing the latency characteristics of inter-chip communication.

[0104] In some embodiments, the construction of the system performance model based on the missing rate model and the latency model may further include the following steps:

[0105] Based on the missing rate model and the latency model, obtain the cache missing rate and cache latency of each level of cache in the cache subsystem, and calculate the average latency between adjacent cache levels in the kernel based on the cache latency; construct a system performance model based on the cache missing rate and average latency.

[0106] Specifically, y(j) is defined as a switching quantity used to determine the coefficient relationships in the system performance model formula, as detailed below:

[0107]

[0108] Assuming there are at most three cache levels in the caching subsystem, the above system performance model formula is defined as follows:

[0109]

[0110] In the above formula, CPI(v) i0k H(v) is the number of cycles per instruction (CPI) under the ideal condition of no cache misses. ijk ) is the hit time of the j-th level cache of particle k, M(v ijk ) is the miss rate of the j-th level cache of particle k. The average latency between adjacent level j-1 and level j caches in core k, n α It is the total number of cores, |R k | represents the number of cores in chip k, and T represents the time spent accessing memory.

[0111] More specifically, to estimate the average latency between adjacent caches, it is necessary to calculate the point-to-point latency between two nodes in the inter-chip and intra-chip interconnect systems, based on the latency model and the aforementioned flow theory. The formula for calculating the average latency is as follows:

[0112]

[0113] in, From node n p,q to node n r,s The flow rate, c = 1, ..., g.

[0114] Through the above embodiments, a system performance model was generated based on the missing rate model and the latency model. The average latency between adjacent cache levels was introduced into the performance model. By optimizing the data flow path and strategy between cache levels, the latency of data access can be reduced and the system response speed can be improved. After introducing the average latency between adjacent cache levels, the hit rate under different caching strategies can be evaluated more accurately, which is beneficial to the architecture optimization of the caching subsystem.

[0115] In some embodiments, solving the system performance model to obtain the target cache parameters may further include the following steps:

[0116] Obtain the preset architecture area of ​​the cache subsystem and determine the area constraint condition that the architecture area of ​​the cache subsystem is less than the preset architecture area; obtain the preset architecture power consumption of the cache subsystem and determine the power consumption constraint condition that the architecture power consumption of the cache subsystem is less than the preset architecture power consumption; based on the area constraint condition and the power consumption constraint condition, solve the system performance model to obtain the target cache parameters.

[0117] Specifically, the architectural area formula for the cache subsystem based on a multi-core integrated system is the cumulative area of ​​each component. The area modeling of the multi-core system is as follows:

[0118]

[0119] Among them, A1(v ijk A2(v) is the area of ​​the core. ijk ) is the area of ​​the memory, A3(v ijk () is the area of ​​the router.

[0120] On the other hand, the power consumption formula for the cache subsystem based on the multi-core integrated system is the cumulative power consumption of each component. The power consumption modeling of the multi-core system is as follows:

[0121]

[0122] Among them, P1(v ijk ) is the core power consumption, P2(v ijk ) is the power consumption of the memory, P3(v ijk () represents the router's power consumption.

[0123] Using performance, power, and area models, and under area and power constraints, the storage hierarchy graph G1(V,E) and network topology graph G2(N,C) of the cache subsystem in a multi-core integrated system are solved to achieve optimal performance of the cache subsystem, thereby maximizing IPC. The architecture area of ​​the multi-core system is smaller than the constraint area A. T The power of the multi-core system architecture is lower than the constrained power P. TThe optimization problem can then be defined as follows:

[0124] maxIPC(G1,G2)

[0125] stA(G1,G2)≤A T

[0126] P(G1,G2)≤P T

[0127] Through the above embodiments, the impact of different design schemes on circuit performance, area, and power consumption can be more accurately predicted and evaluated using area-constrained performance models. Area-constrained performance models can design more compact circuit layouts and reduce circuit area, while power-constrained performance models help reduce circuit power consumption. Therefore, defining optimization problems through area-constrained performance models can significantly improve the performance and reliability of the cache subsystem.

[0128] In some embodiments, solving the system performance model to obtain the target cache parameters may further include the following steps:

[0129] Based on the system performance model, a root node is constructed according to the architecture topology diagram. Starting from the root node, the branch value range of each child node is determined layer by layer according to the architecture topology diagram, and a search tree is constructed layer by layer according to the branch value range. The search tree includes the root node and each layer of child nodes. The tree nodes are traversed in the search tree, and the target cache parameters are obtained by solving.

[0130] Specifically, due to the large design space of the cache subsystem in a multi-core integrated system, the defined problem has high complexity. To effectively solve this problem, a branch and bound algorithm is employed. This algorithm uses a search tree, where the tree node τ i The definition is as follows:

[0131]

[0132] Where G1, G2, ..., G j It is an adjacency matrix abstracted from G1(V,E), representing the connection relationships between nodes; |R1|,|R2|,…,|R j | are the core particles R1, R2, ..., R j The number of cores within; c1, c2, ..., c j The number of cores in a multi-core integrated system; h1, h2, ..., h j It is the maximum number of cache levels within each core; w1, w2, ..., w j These are cache-related parameters, including cache size, cache line size, and correlation; t1, t2, ..., t jIt is the network topology of G2, including Mesh, Ring, Crossbar, etc.

[0133] Starting from the root node, based on the storage hierarchy and network topology in the architecture topology diagram, the value range of each child node branch is gradually determined layer by layer, and a search tree is constructed. Specifically, from layer 0 to layer 1c, the root node branches into j child nodes, corresponding to the adjacency matrix G1, G2, ..., G... j From layer 1c to layer 2c, the branching of child nodes is based on CPI(v). i0k The range of ) is {0,1}; for nodes from level 2c to level 3c, the branching of child nodes is based on cs(v ijk The range of ), namely {256kB, 512kB, 1MB, 2MB, 4MB, 8MB, 16MB}, represents powers of 2; for nodes from layer 3c to layer 4c, the branching of child nodes is based on cl(v ijk The range of ) is {16, 32}; for nodes from level 4c to level 5c, the branching of child nodes is based on as(v ijk The range of ) is {1, 2, 4}. For nodes from layer 5c to layer 6c, the branching of child nodes is based on the number of cores |R| within each core. i |, with a value range of {4, 8, 16}; for nodes from layer 6c to layer 7c, the branching of child nodes is based on the number of cores, with a value range of {32, 64, 128}; for nodes from layer 7c to layer 8c, the branching of child nodes is based on the maximum cache level h. i The value range is {2, 3, 4}; for nodes from layer 8c to layer 9c, the branches of the child nodes are based on the network topology t of the network topology graph G2 in the multi-core integrated system. i The topology consists of six specific topologies represented by the values ​​{0,1,2,3,4,5}.

[0134] It should also be noted that, in the process of constructing the search tree and traversing its nodes, a pruning algorithm for the search tree is also provided:

[0135] In the detection tree node, there are tree nodes that need to be pruned if the feasible solution is less than the preset current maximum value or does not meet the preset constraints. For the branches where the detected tree nodes need to be pruned are located, pruning is performed to obtain the updated search tree. The tree nodes are traversed in the updated search tree to obtain the target cache parameters.

[0136] Specifically, for optimality pruning, the pruning process can be: when the currently searched node τ i If a node is a leaf node and the feasible solution obtained by the current node is still less than the current maximum value, a pruning operation is performed. For infeasible pruning, this pruning process can be: when the currently searched node τi The above constraints are not met, i.e., A(G1,G2)≤A T Or P(G1,G2)≤P T At that time, a pruning operation is performed. This method prunes branches in the search tree that do not meet constraints and other conditions, thus speeding up the search process.

[0137] The above embodiments provide a solution method for optimization problems using branch and bound, and the algorithm provides a method for constructing a search tree that reflects hierarchy and progressive refinement, thereby ensuring that the search tree can comprehensively and systematically search for architecture configurations, which is conducive to quickly and accurately finding the optimal architecture configuration parameters.

[0138] It should be noted that the steps shown in the above process or in the flowchart of the accompanying figures can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases the steps shown or described may be executed in a different order than that shown here.

[0139] This embodiment also provides a cache architecture optimization device for a multi-core integrated system. This device is used to implement the above embodiments and preferred embodiments, and details already described will not be repeated. As used below, the terms "module," "unit," "subunit," etc., can refer to a combination of software and / or hardware that performs a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0140] Figure 6 This is a structural block diagram of a cache architecture optimization device for a multi-core integrated system according to an embodiment of this application, such as... Figure 6 As shown, the device includes: an acquisition module 61, a model building module 62, and a generation module 63; wherein:

[0141] The acquisition module 61 is used to acquire the architecture topology diagram of the multi-core integrated system; the architecture topology diagram includes a storage hierarchy diagram and a network topology diagram; the storage hierarchy diagram is the hierarchical connection diagram of the cache subsystem of the multi-core integrated system; the network topology diagram is the core connection diagram of the multi-core integrated system.

[0142] Model building module 62 is used to build a system performance model based on the architecture topology diagram;

[0143] The generation module 63 is used to solve the system performance model, obtain the target cache parameters, and generate the target cache architecture diagram based on the target cache parameters and the storage hierarchy diagram.

[0144] It should be noted that the above modules can be functional modules or program modules, and can be implemented in software or hardware. For modules implemented in hardware, the above modules can reside in the same processor; or the above modules can be located in different processors in any combination. Each module can be a functional module or a program module, and can be implemented in software or hardware. Specific examples in this embodiment can be found in the examples described in the above embodiments and optional implementations, and will not be repeated in this embodiment.

[0145] This embodiment also provides an electronic device, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0146] Optionally, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor and the input / output device is connected to the processor.

[0147] Optionally, in this embodiment, the processor can be configured to perform the following steps via a computer program:

[0148] S1. Obtain the architecture topology diagram of the multi-core integrated system; the architecture topology diagram includes a storage hierarchy diagram and a network topology diagram; the storage hierarchy diagram is the hierarchical connection diagram of the cache subsystem of the multi-core integrated system; the network topology diagram is the core connection diagram of the multi-core integrated system.

[0149] S2, based on the architecture topology diagram, constructs a system performance model.

[0150] S3 solves the system performance model to obtain the target cache parameters, and generates the target cache architecture diagram based on the target cache parameters and the storage hierarchy diagram.

[0151] It should be noted that the specific examples in this embodiment can refer to the examples described in the above embodiments and optional implementations, and will not be repeated here.

[0152] Furthermore, in conjunction with the cache architecture optimization method for the multi-core integrated system described in the above embodiments, this application embodiment can provide a storage medium for implementation. This storage medium stores a computer program; when executed by a processor, the computer program implements any of the cache architecture optimization methods for the multi-core integrated system described in the above embodiments.

[0153] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties.

[0154] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0155] Those skilled in the art should understand that the technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments have been described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0156] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for optimizing the cache architecture of a multi-core integrated system, characterized in that, The method includes: Obtain the architecture topology diagram of the multi-core integrated system; the architecture topology diagram includes a storage hierarchy diagram and a network topology diagram; the storage hierarchy diagram is the hierarchical connection diagram of the cache subsystem of the multi-core integrated system; the network topology diagram is the core connection diagram of the multi-core integrated system. Based on the architecture topology diagram, a system performance model is constructed, including: modeling the miss rate of the cache subsystem based on the storage hierarchy diagram in the architecture topology diagram to generate a miss rate model; and modeling the network latency of the multi-core integrated system based on the network topology diagram in the architecture topology diagram to generate a latency model; and constructing the system performance model based on the miss rate model and the latency model. The system performance model is solved to obtain the target cache parameters, and a target cache architecture diagram is generated based on the target cache parameters and the storage hierarchy diagram. The step of modeling the network latency of the multi-core integrated system based on the network topology diagram in the architecture topology diagram to generate a latency model includes: Based on the network topology, the node positional relationship between the starting node and the destination node in the multi-core integrated system is determined; When the node position relationship indicates that the starting node and the destination node are located in the same chip, a first delay model is generated based on the chip-on-chip delay in the multi-chip integrated system. When the node position relationship indicates that the starting node and the destination node are located in different chips, a second delay model is generated based on the intra-chip delay and inter-chip delay in the multi-chip integrated system. The delay model includes the first delay model and the second delay model.

2. The caching architecture optimization method according to claim 1, characterized in that, The method of modeling the miss rate of the cache subsystem based on the storage hierarchy diagram in the architecture topology diagram and generating a miss rate model includes: Based on the storage hierarchy diagram, the cache hierarchy node set of the cache subsystem is determined; the cache hierarchy node set is the set of upper-level cache nodes of the current node in the cache hierarchy structure of the cache subsystem. Based on the set of cache hierarchy nodes, the missing rate of the cache subsystem is modeled to generate the missing rate model.

3. The caching architecture optimization method according to claim 1, characterized in that, The different cores include a first core and a second core, where the first core is the core containing the starting node and the second core is the core containing the destination node; the step of generating a second delay model based on the intra-chip delay and inter-chip delay in the multi-core integrated system includes: Identify the first interface node in the first core and the second interface node in the second core; Based on the network topology, a first path, a second path, and a third path are calculated; the first path is the path between the starting node and the first interface node in the first core, the second path is the path between the destination node and the second interface node in the second core, and the third path is the path between the first interface node and the second interface node. Based on the first path and the second path, the intra-chip delay is obtained, the inter-chip delay is obtained based on the third path, and a second delay model is generated according to the intra-chip delay and the inter-chip delay.

4. The cache architecture optimization method according to claim 1, characterized in that, The step of constructing the system performance model based on the missing rate model and the latency model includes: Based on the missing rate model and the latency model, the cache missing rate and cache latency time of each level of cache in the cache subsystem are obtained, and based on the cache latency time, the average latency time between adjacent cache levels in the core is calculated. The system performance model is constructed based on the cache miss rate and the average latency.

5. The caching architecture optimization method according to claim 1, characterized in that, Solving the system performance model to obtain the target cache parameters includes: Obtain the preset architecture area of ​​the cache subsystem, and determine the area constraint condition that the architecture area of ​​the cache subsystem is less than the preset architecture area; Obtain the preset architecture power consumption of the cache subsystem, and determine the power consumption constraint condition that the architecture power consumption of the cache subsystem is less than the preset architecture power consumption; Based on the area constraint and the power consumption constraint, the system performance model is solved to obtain the target cache parameters.

6. The cache architecture optimization method according to any one of claims 1 to 5, characterized in that, Solving the system performance model to obtain the target cache parameters includes: Based on the system performance model, the root node is constructed according to the architecture topology diagram; Starting from the root node, the branch value range of each layer of child nodes is determined layer by layer based on the architecture topology diagram, and a search tree is constructed layer by layer according to the branch value range; the search tree includes the root node and each layer of child nodes; The tree nodes are traversed in the search tree, and the target cache parameters are obtained by solving the problem.

7. A cache architecture optimization device for a multi-core integrated system, characterized in that, include: The acquisition module is used to acquire the architecture topology diagram of the multi-core integrated system; The architecture topology diagram includes a storage hierarchy diagram and a network topology diagram; The storage hierarchy diagram is a hierarchy connection diagram of the cache subsystem of the multi-core integrated system; the network topology diagram is a core connection diagram of the multi-core integrated system. The model building module is used to build a system performance model based on the architecture topology diagram, including: modeling the miss rate of the cache subsystem based on the storage hierarchy diagram in the architecture topology diagram to generate a miss rate model, and modeling the network latency of the multi-core integrated system based on the network topology diagram in the architecture topology diagram to generate a latency model; and building the system performance model based on the miss rate model and the latency model. The model building module is further configured to determine the node positional relationship between the starting node and the destination node in the multi-core integrated system based on the network topology diagram; when the node positional relationship indicates that the starting node and the destination node are located in the same core, generate a first delay model based on the intra-core delay in the multi-core integrated system; when the node positional relationship indicates that the starting node and the destination node are located in different cores, generate a second delay model based on the intra-core delay and inter-core delay in the multi-core integrated system; wherein, the delay model includes the first delay model and the second delay model; The generation module is used to solve the system performance model to obtain the target cache parameters, and generate the target cache architecture diagram based on the target cache parameters and the storage hierarchy diagram.

8. A storage medium, characterized in that, The storage medium stores a computer program, wherein the computer program is configured to execute the cache architecture optimization method for the multi-core integrated system according to any one of claims 1 to 6 at runtime.

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