Design method and system of profound hypothermia transistor model and medium

Abstract

The invention provides a design method and system for a profound hypothermia transistor model and a medium, and the method comprises the steps: S1, determining the size of a transistor through device design; s2, layout realization: based on the sizes of the transistors, drawing MOS, CV, LOD, WPE and MIS test structures corresponding to the transistors; s3, testing and parameter extraction: based on the test structure, the transistor is tested at a deep hypothermia, various test data are obtained, and the deep hypothermia is below 10K; and S4, model establishment: designing a deep hypothermia transistor model based on a BSIM4 model and various test data, and visualizing the modeling process by using a matched HSPICE simulator. The invention provides a large-scale chip scanning test method. Modeling is carried out more accurately by obtaining statistical characteristics of chips. Meanwhile, the testing method covers CV testing, IV testing, mismatch testing, LOD testing, WPE testing and noise testing, and the reliability and integrity of modeling data are guaranteed.

Description

Technical Field

[0001] The present invention relates to integrated circuit technology, and in particular to a design method, system and medium for a deep cryogenic transistor model. Background Art

[0002] In the field of infrared detection, the blocking impurity band (BIB) detector is a new type of infrared detector based on photoconductive technology. It can effectively detect infrared radiation in the 8-20μm band, and has significant advantages such as high sensitivity, large array scale, and wide response frequency band. It has shown extremely broad application prospects in many key fields such as biological detection, deep space exploration, and material exploration.

[0003] The BIB detector is mainly composed of a detector photosensitive chip and a readout circuit chip interconnected by reverse soldering. Among them, the readout circuit chip is an important component of the detector. It undertakes key tasks such as reading, sampling, preprocessing and outputting the current generated by the photosensitive chip. However, since the detector photosensitive chip must work in a deep low temperature (≤6K) environment, the readout circuit chip interconnected with it also needs to operate under deep low temperature conditions accordingly. CMOS circuits designed using transistor models at room temperature will encounter a series of non-ideal effects such as carrier freezing effect and warping effect once they enter a deep low temperature environment. These effects will directly lead to the failure of the CMOS readout circuit. Therefore, in order to ensure circuit performance and improve circuit design accuracy, it is particularly urgent to perform deep low temperature modeling on devices such as transistors.

[0004] Judging from the current domestic research status, the research on deep cryogenic device modeling is still in its infancy and is very limited. Southeast University and Tianjin University have conducted some research on CMOS process devices at liquid nitrogen temperature, and Nanjing University has also conducted characterization and modeling work on 0.25μm CMOS process. But in general, domestic research on deep cryogenic device models lacks systematicity and has few research results. This situation has seriously restricted the development of my country in the field of deep cryogenic readout circuit chip research and development of BIB detectors.

[0005] Through searching patent documents, it was found that the invention patent with the announcement number CN113128155B disclosed a system and method for establishing a simulation model of a field effect transistor. The simulation model of the field effect transistor includes: a field effect transistor model, including four connection terminals of the gate, source, drain and body electrode of the field effect transistor; a first diode model, including a first diode, connected between the body electrode and the drain of the field effect transistor model; a second diode model, including a second diode, connected between the body electrode and the source of the field effect transistor model, and the first diode model and the second diode model characterize the leakage characteristics and capacitance voltage characteristics of the field effect transistor through breakdown voltage parameters and temperature parameters. The application scenario of this patent is relatively narrow, and the data processing is not comprehensive enough.

[0006] In summary, in view of the above-mentioned problems of the prior art, carrying out the design of deep-cryogenic transistor models is of indispensable importance for the successful development of deep-cryogenic readout circuit chips suitable for BIB detectors. Summary of the invention

[0007] In view of the defects in the prior art, the object of the present invention is to provide a design method, system and medium for a deep low temperature transistor model.

[0008] A method for designing a deep cryogenic transistor model according to the present invention comprises the following steps:

[0009] Step S1, determining transistor size through device design;

[0010] Step S2, layout realization: based on the transistor size, draw the MOS, CV, LOD, WPE and MIS test structures corresponding to each transistor;

[0011] Step S3, test and parameter extraction: based on the test structure, the transistor is tested at a deep low temperature to obtain various test data, and the deep low temperature is below 10K;

[0012] Step S4, model building: Based on the BSIM4 model and various test data, a deep cryogenic transistor model is designed, and the modeling process is visualized using a matching HSPICE simulator.

[0013] Preferably, step S1 includes: first determining the transistor characteristic range within the circuit design range required to be covered by the modeling based on the design goal of the deep low temperature transistor model, adapting the width and length of the gate of the transistor device in the planar Si-based transistor process within the design rules, and determining the transistor size.

[0014] Preferably, in step S1, the width of the transistor is decreased from a preset maximum value to a minimum value according to a certain gradient, and the length of the transistor is set similarly, so that the width and length cover different sizes from large to small, thereby constructing a transistor device array for extracting the intrinsic, short channel, narrow channel and other related effect parameters of the device.

[0015] Preferably, in step S2, the MOS test structure is used to extract the DC characteristics of the transistor to construct a DC model; the CV test structure is used to extract the gate capacitance Cgc and the gate capacitance Cgg of the transistor; the LOD test structure is used to obtain the influencing parameters corresponding to the shallow trench isolation stress effect; the WPE test structure is used to extract the influencing parameters of the well proximity effect; and the MIS test structure is used to extract the influencing parameters caused by the transistor processing adaptation.

[0016] Preferably, step S3 includes: placing the transistor device chip on a low-temperature probe station, connecting the electrical signal to the four terminals of the device through four probe arms, and cooling the probe station by liquid helium so that the temperature varies within the range of 4K to 300K.

[0017] Preferably, in step S3, the deep cryogenic temperature is 4K.

[0018] Preferably, in step S3, a large-scale chip scanning test method is adopted, and the test content includes CV test, IV test, mismatch test, LOD test, WPE test and noise test, and includes all low-temperature test information and normal temperature process angle data under the target process, so as to obtain various test data.

[0019] Preferably, in step S4, a dedicated model design software is used to design the deep cryogenic transistor model so that its performance conforms to the electrical parameters of the deep cryogenic transistor.

[0020] The present invention also provides a design system for a deep cryogenic transistor model, comprising:

[0021] Module M1, determines transistor size through device design;

[0022] Module M2, layout implementation: based on transistor size, draw the MOS, CV, LOD, WPE and MIS test structures corresponding to each transistor;

[0023] Module M3, test and parameter collection: Based on the test structure, the transistor is tested at a deep low temperature to obtain various test data. The deep low temperature is below 10K.

[0024] Module M4, model building: Based on the BSIM4 model and various test data, the deep cryogenic transistor model is designed, and the modeling process is visualized using the matching HSPICE simulator.

[0025] The present invention also provides a computer-readable storage medium storing a computer program, and when the computer program is executed by a processor, the steps of the above-mentioned method for designing a deep low-temperature transistor model are implemented.

[0026] Compared with the prior art, the present invention has the following beneficial effects:

[0027] 1. The present invention is different from the traditional model design method that only selects one or two chip samples for curve testing, making it difficult for the accuracy and reliability of the test to meet the design requirements. The present invention proposes a large-scale chip scanning test method, which obtains the statistical characteristics of the chip for more accurate modeling. At the same time, the large-scale chip scanning test method proposed by the present invention covers test contents such as CV test, IV test, mismatch test, LOD test, WPE test and noise test, ensuring the reliability and integrity of the modeling data of the present invention.

[0028] 2. The present invention is different from the traditional model design method that performs curve fitting based on the test content, making the constructed low-temperature model not comprehensive enough. The present invention covers all low-temperature test contents and normal temperature process corner data under the target process. On this basis, other ultra-low temperature data models of similar processes are referenced, so that the final designed low-temperature transistor model covers the most comprehensive model data.

[0029] 3. The present invention is different from the traditional model design method that uses sub-circuit modeling, which sacrifices the convergence and speed of the model in order to improve the model accuracy. On the premise of ensuring the model accuracy, the present invention uses the core parameters of BSIM4 for fitting to improve the speed and convergence of the model in circuit simulation.

[0030] 4. The present invention effectively solves the problems of insufficient accuracy, reliability and comprehensiveness of traditional model design methods by proposing a large-scale chip scanning test method and a comprehensive data processing method, which is conducive to promoting the development of BIB detector deep cryogenic readout circuit chips and related technical developments.

[0031] 5. The present invention eliminates non-ideal effects such as carrier freeze-out effect and warping effect produced by the normal temperature model at deep low temperatures, thereby improving the accuracy of the model. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Other features, objects and advantages of the present invention will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings:

[0033] Figure 1 A flow chart of a design method of a deep cryogenic transistor model in an embodiment of the present invention;

[0034] Figure 2 is a schematic diagram of the dimensions of a deep cryogenic transistor device in an embodiment of the present invention;

[0035] Figure 3 is a layout of a deep low temperature transistor device in an embodiment of the present invention;

[0036] Figure 4 The output characteristic curve (solid line) of the NMOS normal temperature model with W / L=10 / 10 provided by the process factory is compared with the 4K low temperature test data (dashed line);

[0037] Figure 5 The output characteristic curve (solid line) of the established NMOS deep cryogenic transistor model with W / L=10 / 10 is compared with the 4K low temperature test data (dashed line);

[0038] Figure 6 The transfer characteristic curve (solid line) of the NMOS room temperature model with W / L=10 / 10 provided to the process factory is compared with the 4K low temperature test data (dashed line);

[0039] Figure 7 The transfer characteristic curve (solid line) of the established NMOS deep cryogenic transistor model with W / L=10 / 10 is compared with the 4K low temperature test data (dashed line);

[0040] Figure 8 The output characteristic curve (solid line) of the PMOS normal temperature model with W / L=10 / 10 provided by the process factory is compared with the 4K low temperature test data (dashed line);

[0041] Fig. 9 The output characteristic curve (solid line) of the established PMOS deep cryogenic transistor model with W / L=10 / 10 is compared with the 4K low temperature test data (dashed line);

[0042] Fig.10 The transfer characteristic curve (solid line) of the PMOS room temperature model with W / L=10 / 10 provided to the process factory is compared with the 4K low temperature test data (dashed line);

[0043] Fig.11 The transfer characteristic curve (solid line) of the established PMOS deep low temperature transistor model with W / L=10 / 10 is compared with the 4K low temperature test data (dashed line). DETAILED DESCRIPTION

[0044] The present invention is described in detail below in conjunction with specific embodiments. The following embodiments will help those skilled in the art to further understand the present invention, but are not intended to limit the present invention in any form. It should be noted that, for those of ordinary skill in the art, several changes and improvements can also be made without departing from the concept of the present invention. These all belong to the protection scope of the present invention.

[0045] Embodiment 1:

[0046] Figure 1 This is a flow chart of a design method of a deep cryogenic transistor model in an embodiment of the present invention.

[0047] like Figure 1 As shown, this embodiment provides a design method for a deep cryogenic transistor model, comprising the following steps:

[0048] Step S1, determining transistor size through device design.

[0049] The essence of cryogenic transistor model design is to reproduce the electrical characteristics of transistors obtained by process processing working in a cryogenic environment, which is used for circuit design simulation to evaluate the electrical characteristics of the circuit at deep low temperatures. Therefore, it is necessary to obtain information from the test data of the transistor itself to construct a cryogenic transistor model. In order to be able to fully reproduce these characteristics, it is necessary to design a reasonable transistor device array to reflect the behavior of all transistor characteristics within the overall circuit design range through the characteristic values ​​of some transistors.

[0050] Step S1 includes: first, according to the design goal of the deep low-temperature transistor model, determine the transistor characteristic range within the circuit design range required for modeling, adapt the width (W) and length (L) of the gate of the transistor device in the planar Si-based transistor process within the design rules, and determine the transistor size.

[0051] Specifically, the width (W) of the transistor is reduced from a preset maximum value to a minimum value according to a certain gradient, and the length (L) is set similarly, so that the width and length cover different sizes from large to small, thereby constructing a transistor device array for extracting the intrinsic, short channel, narrow channel and other related effect parameters of the device.

[0052] In this embodiment, for the planar Si-based transistor process, the width (W) and length (L) of the gate of the transistor device are adaptively set between a maximum size of 10 μm and a minimum size of 0.5 μm.

[0053] Step S2, layout realization: based on the transistor size, draw the MOS, CV, LOD, WPE and MIS test structures corresponding to each transistor.

[0054] Since the deep low-temperature transistor model is closely linked to the manufacturing process and is used to reflect the electrical characteristics of the transistor, the transistor tape-out used for modeling must be consistent with the manufacturer and process node of the circuit tape-out.

[0055] In this embodiment, the purpose of drawing the test structure is to facilitate subsequent testing and extraction of transistor-related parameters such as mismatch, LOD, WPE, and Noise. Among them, the MOS test structure is used to extract the DC characteristics of the transistor to build a DC model; the CV test structure is used to extract the gate capacitance Cgc and gate capacitance Cgg of the transistor; the LOD test structure is used to obtain the influencing parameters corresponding to the shallow trench isolation stress effect; the WPE test structure is used to extract the influencing parameters of the well proximity effect; and the MIS test structure is used to extract the influencing parameters caused by transistor processing adaptation.

[0056] Step S3, test parameters: Based on the test structure, the transistor is tested at a deep low temperature to obtain various test data, and the deep low temperature is below 10K.

[0057] Specifically, the transistor device chip is placed on a low-temperature probe station, and the electrical signal is connected to the four ends of the device through four probe arms. The temperature of the probe station is changed within the range of 4K to 300K by cooling with liquid helium.

[0058] In this embodiment, the deep low temperature is 4K, and a large-scale chip scanning test method is adopted. The test content includes CV test, IV test, mismatch test, LOD test, WPE test and noise test, etc., and includes all low-temperature test information and normal temperature process angle data under the target process, so as to obtain various test data, provide strong support for accurate modeling, and ensure the reliability and integrity of the modeling data.

[0059] Step S4, model establishment: Based on the BSIM4 model and various test data, the deep low-temperature transistor model is designed. At the same time, the matching HSPICE simulator is used to display the test data curve and model simulation curve in real time, visualize the modeling process, and facilitate the adjustment of model parameters at any time according to actual conditions to improve model accuracy.

[0060] Specifically, the present invention uses the BSIM4 model as a theoretical basis to implement the design of a cryogenic transistor model, while ensuring the accuracy of the model, improving the speed and convergence of the model in circuit simulation. Using dedicated model design software, the cryogenic transistor model is designed so that its performance meets the electrical parameters of the cryogenic transistor.

[0061] Embodiment 2:

[0062] This embodiment is based on the design method of the deep cryogenic transistor model of the above-mentioned embodiment 1, combined with the modeling examples of 3.3V NMOS and PMOS, and is specifically introduced as follows:

[0063] Step S1, deep cryogenic transistor device design.

[0064] Figure 2 Schematic diagram of the dimensions of a deep low temperature transistor device in an embodiment of the present invention.

[0065] In order to achieve the purpose of partial transistors reflecting the overall characteristics, the width and length of the MOSFET selected in the device design cover different sizes from large to small to ensure that the intrinsic, short channel, narrow channel and other related effect parameters of the device can be effectively extracted. The size of the MOSFET device array designed in this example is as follows: Figure 2 As shown, the array includes two-dimensional information of the device W and L. The selected devices are distributed on the outermost four sides of the two-dimensional array from the maximum size of 10μm to the minimum size of 0.5μm. In this way, the changes in model parameters of MOSFET devices as W and L change can be extracted by comparing the four groups of devices Wmin-Larray, Wmax-Larray, Lmin-Warray, and Lmax-Warray.

[0066] Step S2, deep low temperature transistor layout realization.

[0067] Figure 3 This is a layout of a deep low temperature transistor device in an embodiment of the present invention.

[0068] In this example, the circuit was taped out using SMIC's 0.18μm process. Figure 3 The layout of the MOSFET array can be delivered to the process manufacturer to produce the required MOSFET device physical chip.

[0069] Step S3, deep cryogenic transistor test and parameter collection.

[0070] During the test, the MOSFET device chip is placed on a low-temperature probe station, and the electrical signal is connected to the four ends of the device through four probe arms. The probe station temperature can be changed between 4K and 300K by cooling with an external liquid helium tank. Take 3.3V NMOS as an example:

[0071] (1) Vds = 0.05 V. At different substrate bias voltages Vbs (Vbs = 0, -0.5 V, -1 V, -1.5 V, -2 V, -2.5 V, -3 V), scan Vgs with a 0.01 V step, measure the Ids-Vgs characteristics, and output a set of data and a set of curves.

[0072] (2) Vds = 3.3 V. At different substrate bias voltages Vbs (Vbs = 0, -0.5 V, -1 V, -1.5 V, -2 V, -2.5 V, -3 V), scan Vds with a step of 0.01 V, measure the Ids-Vgs characteristics, and output a set of data and a set of curves.

[0073] (3) Vbs = 0 V. At different gate voltages Vgs (Vgs = 0.8 V, 1.3 V, 1.8 V, 2.3 V, 2.8 V, 3.3 V), scan Vds with a 0.01 V step, measure the Ids-Vds characteristics, and output a set of data and a set of curves.

[0074] (4) Vbs = -3 V. At different gate voltages Vgs (Vgs = 0.8 V, 1.3 V, 1.8 V, 2.3 V, 2.8 V, 3.3 V), scan Vds with a step of 0.01 V, measure the Ids-Vds characteristics, and output a set of data and a set of curves.

[0075] For PMOS, the test method and content are the same as NMOS, and the bias voltage is reversed. This example uses a large-scale chip scanning test method to cover CV test, IV test, mismatch test, LOD test, WPE test and noise test, etc., to ensure the reliability and integrity of the modeling data.

[0076] Step S4, establishing a deep cryogenic transistor model.

[0077] This example covers all low-temperature test contents and normal-temperature process corner data under the target process when the model is established. On this basis, the data models of other similar processes with ultra-low temperatures are referenced to make the final designed low-temperature transistor model cover the most comprehensive model data. At the same time, this example uses the core parameters of BSIM4 for fitting while ensuring the accuracy of the model to improve the speed and convergence of the model in circuit simulation.

[0078] Figure 4 The output characteristic curve (solid line) of the NMOS normal temperature model with W / L=10 / 10 provided by the process factory is compared with the 4K low temperature test data (dashed line); Figure 5 The output characteristic curve (solid line) of the established NMOS deep cryogenic transistor model with W / L=10 / 10 is compared with the 4K low temperature test data (dashed line). Figure 4 and Figure 5 , the model matching degree of the NMOS output characteristic curve with W / L=10 / 10 is improved from 71.0% to 97.14%.

[0079] Figure 6 The transfer characteristic curve (solid line) of the NMOS room temperature model with W / L=10 / 10 provided by the process factory is compared with the 4K low temperature test data (dashed line). Figure 7 The transfer characteristic curve (solid line) of the established NMOS deep cryogenic transistor model with W / L=10 / 10 is compared with the 4K low temperature test data (dashed line). Figure 6 and Figure 7 , the model matching degree of the NMOS transfer characteristic curve with W / L=10 / 10 is improved from 83.1% to 98.07%.

[0080] Figure 8 The output characteristic curve (solid line) of the PMOS normal temperature model with W / L=10 / 10 provided by the process factory is compared with the 4K low temperature test data (dashed line). Fig. 9 The output characteristic curve (solid line) of the established PMOS deep low temperature transistor model with W / L=10 / 10 is compared with the 4K low temperature test data (dashed line). Figure 8 and Fig. 9 , the model matching degree of the PMOS output characteristic curve with W / L=10 / 10 is improved from 73.3% to 97.75%.

[0081] Fig.10 The transfer characteristic curve (solid line) of the PMOS room temperature model with W / L=10 / 10 provided to the process factory is compared with the 4K low temperature test data (dashed line). Fig.11 The transfer characteristic curve (solid line) of the established PMOS deep low temperature transistor model with W / L=10 / 10 is compared with the 4K low temperature test data (dashed line). Fig.10 and Fig.11 , the model matching degree of the PMOS transfer characteristic curve with W / L=10 / 10 is improved from 85.9% to 98.43%.

[0082] Embodiment 3:

[0083] This embodiment provides a design system for a deep cryogenic transistor model. The design system for a deep cryogenic transistor model can be implemented by executing the process steps of a design method for a deep cryogenic transistor model. That is, those skilled in the art can understand the design method for a deep cryogenic transistor model as a preferred implementation of the design system for a deep cryogenic transistor model.

[0084] The design system includes:

[0085] Module M1, determines transistor size through device design;

[0086] Module M2, layout implementation: based on transistor size, draw the MOS, CV, LOD, WPE and MIS test structures corresponding to each transistor;

[0087] Module M3, test and parameter collection: Based on the test structure, the transistor is tested at a deep low temperature to obtain various test data. The deep low temperature is below 10K.

[0088] Module M4, model building: Based on the BSIM4 model and various test data, the deep cryogenic transistor model is designed, and the modeling process is visualized using the matching HSPICE simulator.

[0089] Embodiment 4:

[0090] This embodiment provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, the steps of a method for designing a deep cryogenic transistor model in the above-mentioned embodiment 1 are implemented.

[0091] Those skilled in the art know that, in addition to realizing the system and its various devices, modules, and units provided by the present invention in a purely computer-readable program code, it is entirely possible to realize the same functions in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers by logically programming the method steps. Therefore, the system and its various devices, modules, and units provided by the present invention can be considered as a hardware component, and the devices, modules, and units included therein for realizing various functions can also be regarded as structures within the hardware component; the devices, modules, and units for realizing various functions can also be regarded as both software modules for realizing the method and structures within the hardware component.

[0092] The above describes the specific embodiments of the present invention. It should be understood that the present invention is not limited to the above specific embodiments, and those skilled in the art can make various changes or modifications within the scope of the claims, which does not affect the essence of the present invention. In the absence of conflict, the embodiments of the present application and the features in the embodiments can be combined with each other arbitrarily.

Claims

1. A method for designing a deep cryogenic transistor model, characterized in that: The steps include: Step S1, determining transistor size through device design; Step S2, layout realization: based on the transistor size, drawing the MOS, CV, LOD, WPE and MIS test structures corresponding to each transistor; Step S3, test and parameter collection: based on the test structure, test the transistor at a deep low temperature to obtain various test data, wherein the deep low temperature is below 10K; Step S4, model building: based on the BSIM4 model and the various test data, a deep cryogenic transistor model is designed, and the modeling process is visualized using a matching HSPICE simulator.

2. The method for designing a deep cryogenic transistor model according to claim 1, characterized in that: The step S1 includes: firstly determining the transistor characteristic range within the circuit design range required to be covered by the modeling according to the design goal of the deep low temperature transistor model, adapting the width and length of the gate of the transistor device in the planar Si-based transistor process within the design rules, and determining the transistor size.

3. The method for designing a deep cryogenic transistor model according to claim 2, characterized in that: In step S1, the width of the transistor is reduced from a preset maximum value to a minimum value according to a certain gradient, and the length of the transistor is set similarly, so that the width and length cover different sizes from large to small, thereby constructing a transistor device array for extracting the intrinsic, short channel, narrow channel and other related effect parameters of the device.

4. The method for designing a deep cryogenic transistor model according to claim 1, characterized in that: In step S2, the MOS test structure is used to extract the DC characteristics of the transistor to construct a DC model; the CV test structure is used to extract the gate capacitance Cgc and the gate capacitance Cgg of the transistor; The LOD test structure is used to obtain the influencing parameters corresponding to the shallow trench isolation stress effect; the WPE test structure is used to extract the influencing parameters of the well proximity effect; and the MIS test structure is used to extract the influencing parameters caused by transistor processing adaptation.

5. The method for designing a deep cryogenic transistor model according to claim 1, characterized in that: The step S3 includes: placing the transistor device chip on a low-temperature probe station, connecting the electrical signal to the four terminals of the device through four probe arms, and cooling the probe station by liquid helium to change the temperature within the range of 4K to 300K.

6. The method for designing a deep cryogenic transistor model according to claim 5, characterized in that: In step S3, the deep cryogenic temperature is 4K.

7. The method for designing a deep cryogenic transistor model according to claim 6, characterized in that: In the step S3, a large-scale chip scanning test method is adopted, and the test content includes CV test, IV test, mismatch test, LOD test, WPE test and noise test, and includes all low-temperature test information and normal temperature process angle data under the target process, so as to obtain various test data.

8. The method for designing a deep cryogenic transistor model according to claim 1, characterized in that: In step S4, a dedicated model design software is used to design the deep cryogenic transistor model so that its performance conforms to the electrical parameters of the deep cryogenic transistor.

9. A design system for a deep cryogenic transistor model, characterized in that: include: Module M1, determines transistor size through device design; Module M2, layout implementation: based on the transistor size, draw the MOS, CV, LOD, WPE and MIS test structures corresponding to each transistor; Module M3, test and parameter collection: Based on the test structure, the transistor is tested at a deep low temperature to obtain various test data, wherein the deep low temperature is below 10K; Module M4, model building: Based on the BSIM4 model and the various test data, a deep cryogenic transistor model is designed, and the modeling process is visualized using a matching HSPICE simulator.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of a method for designing a deep cryogenic transistor model according to any one of claims 1 to 8 are implemented.

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