Method, device and system for predicting etching contour of integrated circuit and medium

Abstract

The invention provides an integrated circuit etching contour prediction method, device and system and a medium. The method comprises the steps of collecting a current design layout of an integrated circuit; obtaining a training set of a generative adversarial network model of the initial pixel points to the pixel points, wherein the training set comprises a known design layout of the integrated circuit and an actual etching contour corresponding to the known design layout of the integrated circuit; learning a mapping relation between the known design layout of the integrated circuit and the actual etching contour corresponding to the known design layout of the integrated circuit by utilizing the training set; determining model parameters of a generative adversarial network model of the initial pixel point pair pixel points according to the mapping relation so as to obtain a trained generative adversarial network model of the pixel point pair pixel points; and inputting the current design layout of the integrated circuit into the trained generative adversarial network model of the pixel points to the pixel points to obtain a predicted etching contour corresponding to the current design layout of the integrated circuit. And the contour of the etched integrated circuit is accurately and quickly predicted by adopting a generative adversarial network of pixel points to pixel points.

Description

Technical Field

[0001] The present application relates to the field of process simulation technology, and in particular to an integrated circuit etching profile prediction method, device, system and medium. Background Art

[0002] In integrated circuit manufacturing, the design board Figure 1 It is generally transferred to the substrate through photolithography and etching processes. The quality of the pattern finally etched on the substrate determines the yield of the product.

[0003] The process of graphic transfer will produce deviations from the original design layout. If a model can be established to accurately predict the graphics of the design layout after etching, it will be of great significance for guiding process production.

[0004] However, the current mature etching pattern simulation method, which is also a common practice in commercial software, is to first obtain the imaging of the layout on the photoresist through optical simulation, and then add the etching model based on the kernel function to obtain the final etched pattern. Another research method is the prediction of etching patterns based on machine learning, which is to extract layout information by designing a feature extractor, and learn the relationship between the original layout and the corresponding post-etching contour to obtain a model.

[0005] Of the above two methods, the former has higher accuracy, but a large number of optical simulations result in slow calculation speed; the latter has fast calculation speed, but the design of the feature extractor usually misses some features of the layout, resulting in low prediction accuracy.

[0006] Therefore, how to achieve accurate and rapid prediction of the etching profile of integrated circuits is a technical problem that needs to be solved in this field. Summary of the invention

[0007] In view of this, this summary of the invention is provided to introduce the concepts in a brief form, which will be described in detail in the detailed description section below. This summary of the invention is not intended to identify the key features or essential features of the technical solution claimed for protection, nor is it intended to be used to limit the scope of the technical solution claimed for protection.

[0008] The purpose of the present application is to provide a method, device, system and medium for predicting the etching profile of an integrated circuit, which can accurately and quickly predict the etching profile of an integrated circuit.

[0009] To achieve the above purpose, this application has the following technical solutions:

[0010] In a first aspect, an embodiment of the present application provides a method for predicting an integrated circuit etching profile, comprising:

[0011] Collect the current design layout of the integrated circuit;

[0012] Obtaining a training set of an initial pixel-to-pixel generative adversarial network model, the training set comprising: a known design layout of an integrated circuit and an actual etching profile corresponding to the known design layout of the integrated circuit;

[0013] Using the training set to learn the mapping relationship between the known design layout of the integrated circuit and the actual etching profile corresponding to the known design layout of the integrated circuit;

[0014] Determining model parameters of the initial pixel-to-pixel generative adversarial network model according to the mapping relationship to obtain a trained pixel-to-pixel generative adversarial network model;

[0015] The current design layout of the integrated circuit is input into the trained pixel-to-pixel generative adversarial network model to obtain a predicted etching profile corresponding to the current design layout of the integrated circuit.

[0016] In a possible implementation, the acquisition of the current design layout of the integrated circuit includes:

[0017] Collect the original design layout of integrated circuits;

[0018] Segmenting the original design layout of the integrated circuit according to a preset size to obtain an integrated circuit segmentation design layout;

[0019] The integrated circuit segmentation design layout is binarized to obtain an integrated circuit binary design layout; and the integrated circuit binary design layout is used as the current design layout of the integrated circuit.

[0020] In a possible implementation, the loss function of the initial pixel-to-pixel generative adversarial network model includes: a binary cross entropy loss function.

[0021] In a possible implementation, the hyper parameters of the initial pixel-to-pixel generative adversarial network model include: a learning rate, a number of samples selected for one training, a training round, and an optimizer;

[0022] The learning rate is equal to 0.0005, the number of samples selected for one training is equal to 8, the number of training rounds is equal to 20, and the optimizer is an adaptive moment estimation optimizer.

[0023] In a second aspect, an embodiment of the present application provides an integrated circuit etching profile prediction device, comprising:

[0024] A collection unit, used for collecting the current design layout of the integrated circuit;

[0025] An acquisition unit is used to acquire a training set of an initial pixel-to-pixel generative adversarial network model, wherein the training set includes: a known design layout of an integrated circuit and an actual etching profile corresponding to the known design layout of the integrated circuit;

[0026] A learning unit, configured to use the training set to learn a mapping relationship between the known design layout of the integrated circuit and an actual etching profile corresponding to the known design layout of the integrated circuit;

[0027] A determination unit, configured to determine model parameters of the initial pixel-to-pixel generative adversarial network model according to the mapping relationship, so as to obtain a trained pixel-to-pixel generative adversarial network model;

[0028] An input unit is used to input the current design layout of the integrated circuit into the trained pixel-to-pixel generative adversarial network model to obtain a predicted etching profile corresponding to the current design layout of the integrated circuit.

[0029] In a possible implementation, the collection unit is specifically configured to:

[0030] Collect the original design layout of integrated circuits;

[0031] Segmenting the original design layout of the integrated circuit according to a preset size to obtain an integrated circuit segmentation design layout;

[0032] The integrated circuit segmentation design layout is binarized to obtain an integrated circuit binary design layout; and the integrated circuit binary design layout is used as the current design layout of the integrated circuit.

[0033] In a possible implementation, the loss function of the initial pixel-to-pixel generative adversarial network model includes: a binary cross entropy loss function.

[0034] In a possible implementation, the hyper parameters of the initial pixel-to-pixel generative adversarial network model include: a learning rate, a number of samples selected for one training, a training round, and an optimizer;

[0035] The learning rate is equal to 0.0005, the number of samples selected for one training is equal to 8, the number of training rounds is equal to 20, and the optimizer is an adaptive moment estimation optimizer.

[0036] In a third aspect, an embodiment of the present application provides an integrated circuit etching profile prediction system, comprising:

[0037] Memory for storing computer programs;

[0038] A processor is used to implement the steps of the integrated circuit etching profile prediction method as described above when executing the computer program.

[0039] In a fourth aspect, an embodiment of the present application provides a computer-readable medium having a computer program stored thereon, and when the computer program is processed and executed, the steps of the integrated circuit etching profile prediction method as described above are implemented.

[0040] Compared with the prior art, the embodiments of the present application have the following beneficial effects:

[0041] The embodiment of the present application provides a method, device, system and medium for predicting the etching profile of an integrated circuit, the method comprising: collecting the current design layout of the integrated circuit; obtaining a training set of an initial pixel-to-pixel generative adversarial network model, the training set comprising: a known design layout of the integrated circuit and the actual etching profile corresponding to the known design layout of the integrated circuit; using the training set to learn the mapping relationship between the known design layout of the integrated circuit and the actual etching profile corresponding to the known design layout of the integrated circuit; determining the model parameters of the initial pixel-to-pixel generative adversarial network model according to the mapping relationship to obtain a trained pixel-to-pixel generative adversarial network model; inputting the current design layout of the integrated circuit into the trained pixel-to-pixel generative adversarial network model to obtain the predicted etching profile corresponding to the current design layout of the integrated circuit. The present application realizes the prediction of the graphics after the design layout is etched on the substrate by adopting a pixel-to-pixel generative adversarial network based on pixel-to-pixel. Compared with the traditional machine learning method, its prediction accuracy is very high and its prediction speed is also faster. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0043] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. Throughout the accompanying drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic and the originals and elements are not necessarily drawn to scale.

[0044] Figure 1 A flow chart of an integrated circuit etching profile prediction method provided by an embodiment of the present application is shown;

[0045] Figure 2 A schematic diagram of a side view of a photolithography and etching profile provided in an embodiment of the present application is shown;

[0046] Figure 3 A schematic diagram showing a top view of a contour pattern after photolithography and a contour pattern after etching provided in an embodiment of the present application;

[0047] Figure 4 A schematic diagram of a generative adversarial network provided in an embodiment of the present application is shown;

[0048] Figure 5 A schematic diagram of an initial pixel-to-pixel generative adversarial network model provided in an embodiment of the present application is shown;

[0049] Figure 6 A schematic diagram showing a generator structure of an initial pixel-to-pixel generative adversarial network model provided in an embodiment of the present application is shown;

[0050] Figure 7 A schematic diagram of a Markov discriminator provided in an embodiment of the present application is shown;

[0051] Figure 8 A schematic diagram showing a set of test results of a model provided in an embodiment of the present application;

[0052] Fig. 9 A schematic diagram showing a set of test results of another model provided in an embodiment of the present application;

[0053] Fig.10 A schematic diagram showing a set of test results of another model provided in an embodiment of the present application;

[0054] Fig.11 A schematic diagram showing a known integrated circuit design layout provided by an embodiment of the present application and an actual etching profile corresponding to the known integrated circuit design layout, as well as images of the two after being imaged;

[0055] Fig.12 A schematic diagram of an integrated circuit etching profile prediction device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0056] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below with reference to the accompanying drawings.

[0057] In the following description, many specific details are set forth to facilitate a full understanding of the present application, but the present application may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0058] As described in the background technology, the applicant has found that in the manufacture of integrated circuits, the design board Figure 1It is generally transferred to the substrate through photolithography and etching processes. The quality of the pattern finally etched on the substrate determines the yield of the product.

[0059] The process of graphic transfer will produce deviations from the original design layout. If a model can be established to accurately predict the graphics of the design layout after etching, it will be of great significance for guiding process production.

[0060] However, the current mature etching pattern simulation method, which is also a common practice in commercial software, is to first obtain the imaging of the layout on the photoresist through optical simulation, and then add the etching model based on the kernel function to obtain the final etched pattern. Another research method is the prediction of etching patterns based on machine learning, which is to extract layout information by designing a feature extractor, and learn the relationship between the original layout and the corresponding post-etching contour to obtain a model.

[0061] Of the above two methods, the former has higher accuracy, but a large number of optical simulations result in slow calculation speed; the latter has fast calculation speed, but the design of the feature extractor usually misses some features of the layout, resulting in low prediction accuracy.

[0062] Therefore, how to achieve accurate and rapid prediction of the etching profile of integrated circuits is a technical problem that needs to be solved in this field.

[0063] In order to solve the above technical problems, the embodiment of the present application provides an integrated circuit etching profile prediction method, device, system and medium, the method comprising: collecting the current design layout of the integrated circuit; obtaining the training set of the initial pixel-to-pixel generative adversarial network model, the training set comprising: the known design layout of the integrated circuit and the actual etching profile corresponding to the known design layout of the integrated circuit; using the training set to learn the mapping relationship between the known design layout of the integrated circuit and the actual etching profile corresponding to the known design layout of the integrated circuit; determining the model parameters of the initial pixel-to-pixel generative adversarial network model according to the mapping relationship to obtain the trained pixel-to-pixel generative adversarial network model; inputting the current design layout of the integrated circuit into the trained pixel-to-pixel generative adversarial network model to obtain the predicted etching profile corresponding to the current design layout of the integrated circuit. The present application realizes the prediction of the graphics after the design layout is etched on the substrate by adopting a pixel-to-pixel generative adversarial network based on pixel-to-pixel. Compared with the traditional machine learning method, its prediction accuracy is very high and its prediction speed is also faster.

[0064] Exemplary Methods

[0065] See also Figure 1 As shown, it is a flow chart of an integrated circuit etching profile prediction method provided by an embodiment of the present application, including:

[0066] S101: Collect the current design layout of the integrated circuit.

[0067] In the embodiment of the present application, in the integrated circuit manufacturing, the design board Figure 1 Generally, it is transferred to the substrate through the photolithography process. Light is irradiated on the photoresist on the surface of the substrate through the mask, and a photochemical reaction occurs on the photoresist. After development, the required pattern is left on the photoresist. However, photolithography is not the last step to transfer the target layout to the wafer. After photolithography, the etching process is required to transfer the pattern to the substrate. The pattern formed on the substrate after etching after photolithography is called the etched profile.

[0068] See also Figure 2 As shown, it is a schematic diagram of a side view of a photolithography and etching profile provided by an embodiment of the present application. A photoresist is formed on the substrate silicon (Bulk Si). Usually, the size of the pattern on the photoresist after photolithography (Litho) is different from the size of the design layout, and the size of the pattern on the photoresist is different from the size of the pattern on the substrate after the final etching (Final Etch). It can be said that the quality of the final pattern on the substrate is determined by the photolithography and etching.

[0069] See also Figure 3 As shown, it is a schematic diagram of a top view of a contour figure after lithography (litho contour) and a contour figure after etching (etch contour) provided in an embodiment of the present application. The left side is the original design layout (Origindesign), and the right side is the sampling after etching (sampling). It is found that there is an etching bias (Etch bias) between the contour figure after lithography and the contour figure after etching. If a model can be established to predict the contour of the final etched design layout, it can guide the process design well and improve the efficiency of production.

[0070] Therefore, the embodiment of the present application first needs to collect the current design layout of the integrated circuit for use in the prediction of the subsequent model. The current design layout of the integrated circuit can be a layout file that meets the GDSII (Graphic Data System II) format.

[0071] S102: Obtain a training set of an initial pixel-to-pixel generative adversarial network model, wherein the training set includes: a known design layout of an integrated circuit and an actual etching profile corresponding to the known design layout of the integrated circuit.

[0072] S103: using the training set to learn a mapping relationship between the known design layout of the integrated circuit and an actual etching profile corresponding to the known design layout of the integrated circuit;

[0073] S104: Determine the model parameters of the initial pixel-to-pixel generative adversarial network model according to the mapping relationship to obtain a trained pixel-to-pixel generative adversarial network model;

[0074] S105: Inputting the current design layout of the integrated circuit into the trained pixel-to-pixel generative adversarial network model to obtain a predicted etching profile corresponding to the current design layout of the integrated circuit.

[0075] In an embodiment of the present application, in order to train the initial pixel-to-pixel generative adversarial network model, a training set of the initial pixel-to-pixel generative adversarial network model can be first obtained, and the training set includes: a known design layout of the integrated circuit and an actual etching contour corresponding to the known design layout of the integrated circuit.

[0076] Specifically, the training set can be simulated on the commercial simulation software Calibre, for example, which can simulate the post-etching contour according to the design layout.

[0077] In addition, the Generative Adversarial Network (GAN) is a special generative network that consists of two sub-networks: a generator and a discriminator. The task of the generator is to generate realistic data as much as possible, while the task of the discriminator is to distinguish between real data and generated data as much as possible. The two networks compete with each other, constantly improving their capabilities, and eventually reach a state of equilibrium, that is, the generator can generate data that is consistent with the distribution of real data, while the discriminator cannot distinguish between real and fake data.

[0078] The GAN network structure is as follows Figure 4 As shown, Figure 4 A schematic diagram of a generative adversarial network provided for an embodiment of the present application, wherein G represents a generative network and D represents a discriminative network. The input of the generative network is random noise z, which is randomly distributed sample data and can conform to a Gaussian distribution, etc. The generative network generates false data G(z) that conforms to the distribution of the real sample according to the discrimination result of the discriminative network. The discriminative network distinguishes G(z) from the real sample x and outputs a probability value, where a value less than 0.5 is false and a value greater than 0.5 is true. The two perform adversarial training against each other. When the discriminative network cannot accurately judge the false data G(z) and the real data x, and the ideal output value is 0.5, the two can reach a Nash equilibrium and the model training is completed.

[0079] See also Figure 5 As shown, it is a schematic diagram of an initial pixel-to-pixel generative adversarial network model provided in an embodiment of the present application.

[0080] In traditional generative models, the input of the generator of GAN is all randomly generated noise z, so the only information the generator can use is the judgment result returned by the discriminator. Ideally, this judgment result can guide the generator to iterate continuously, but most of the time it does not tell the generator "why the current data is not true enough" or "in which direction it should be improved", and the generated result is uncontrollable. In order to alleviate this problem and further improve the model performance of the generative adversarial network, we can provide "effective information" to the generator or discriminator to assist the adversarial performance of the model. This effective information can be any information related to the original data but different, such as the true label of the sample, sample data under different modes, etc. In related research, conditional generative adversarial networks (cGAN) use true labels as auxiliary information. The core idea of ​​cGAN is to input the true samples and true labels as information into the generator and discriminator to provide better guidance for the generation and discrimination behavior. More specifically, cGAN uses the true label as part of the feature and inputs it into the generator and discriminator for training.

[0081] One of the theoretical foundations of the initial pixel-to-pixel generative adversarial network model is the conditional generative adversarial network, which is mainly used in the field of generalized image translation to convert input images into output images.

[0082] See also Figure 5 As shown in the figure, it takes the input data X as the unity of the limiting condition c and the random noise z. Its characteristic is that the data to be processed and the target data are in a one-to-one matching relationship. The generative network encodes the input data X, and the discriminative network generates samples G(X) under the condition of X and discriminates the real samples Y.

[0083] For the generator G, the Unet structure is used, that is, the encoder-decoder architecture with short-circuit connections. The surface appearance of the input and output images should be different, but the underlying structure should be similar. For the image translation task, the input and output should share some underlying information, so the skip connection method of Unet is used. Figure 6 As shown, it is a schematic diagram of the generator structure of an initial pixel-to-pixel generative adversarial network model provided in an embodiment of the present application.

[0084] For the discriminator D, the PatchGAN Markov discriminator is used, which replaces the discriminator of ordinary GAN with a fully convolutional network. The ordinary GAN discriminator maps the input into a real number, which is the probability that the input sample is a real sample. PatchGAN maps the input into an N*N patch (matrix) X. The values ​​in the matrix represent the probability that each patch is a real sample. X is actually the feature map output by the convolution layer. From this feature map, we can trace back to a certain position in the original image, and we can see the impact of this position on the final output result. See Figure 7 As shown, a schematic diagram of a Markov discriminator provided in an embodiment of the present application shows the basic structure of a patchGAN, which can be simply regarded as consisting of several layers of convolution.

[0085] The initial pixel-to-pixel generative adversarial network model provided in the embodiment of the present application is a u-net structure. Since the network input is a 1024*1024 binary image, the number of input channels for the first layer of the network should be set to 1. The encoder and decoder parts of the network are 7 layers each, and their structure is simplified as follows: c521-c512-c512-c512-c256c-c128-c64-c64-c128-c256-c512-c512-c512-c512.

[0086] Its specific parameters are shown in Table 1, padding is the filling method, and stride is the convolution step size.

[0087]

[0088]

[0089]

[0090] Table 1

[0091] The discriminator provided in the embodiment of the present application is a PatchGAN structure, which is mainly composed of five convolutional layers. Since the discriminator needs to accept inputs from the generator and real pictures, the input channel of the first layer should be set to 2. The specific parameters of the network are set as shown in Table 2 below:

[0092]

[0093]

[0094] Table 2

[0095] Then, the embodiment of the present application uses the training set to learn the mapping relationship between the known design layout of the integrated circuit and the actual etching contour corresponding to the known design layout of the integrated circuit; the model parameters of the initial pixel-to-pixel generative adversarial network model are determined according to the mapping relationship to obtain the trained pixel-to-pixel generative adversarial network model; the current design layout of the integrated circuit is input into the trained pixel-to-pixel generative adversarial network model to obtain the predicted etching contour corresponding to the current design layout of the integrated circuit.

[0096] For details, see Figure 8 As shown, it is a schematic diagram of a set of test results of a model provided by an embodiment of the present application. The embodiment of the present application can train the model on the training set data. Each set of known design layouts and their corresponding actual post-etching contour layouts are input into the model for training, and this process is repeated until the set maximum training rounds (epochs) are reached.

[0097] The embodiment of the present application can test the trained pixel-to-pixel generative adversarial network model on the test set. Select the layout data on the test set, input the known design layout into the model to obtain the predicted contour, and compare it with the actual etching contour (i.e., the contour obtained by commercial simulation software). Figure 8 This is a set of test results. The left one is the known design layout design, the middle one is the actual etching contour real_contour, and the right one is the predicted etching contour predict_contour.

[0098] After multiple tests on the validation set, the prediction results of the trained pixel-to-pixel generative adversarial network model have a high accuracy rate, and the average pixel accuracy of the predicted image compared with the actual contour image is 95.42%. Fig. 9 and Fig.10 As shown, the results predicted by more groups of models are displayed.

[0099] At the same time, the prediction time of the trained pixel-to-pixel generative adversarial network model is very short. For each design layout on the test set, the average prediction time is 1 to 3 seconds, which is faster than the speed of using commercial simulation software. In summary, the model can achieve high-precision and high-speed prediction of the image after etching of the two-dimensional layout.

[0100] Optionally, the embodiment of the present application can delete duplicate layouts and use the remaining images as training sets and test sets, where the training set accounts for 80% and the test set accounts for 20%.

[0101] Therefore, the embodiment of the present application inputs the current design layout of the integrated circuit into the trained pixel-to-pixel generative adversarial network model, and can quickly and accurately obtain the predicted etching profile corresponding to the current design layout of the integrated circuit.

[0102] In a possible implementation, the current design layout of the acquisition integrated circuit provided in the embodiment of the present application may specifically include:

[0103] Collecting the original design layout of the integrated circuit; dividing the original design layout of the integrated circuit according to a preset size to obtain a divided design layout of the integrated circuit; binarizing the divided design layout of the integrated circuit to obtain a binary design layout of the integrated circuit; and using the binary design layout of the integrated circuit as the current design layout of the integrated circuit.

[0104] For details, see Fig.11 As shown, the known design layout of the integrated circuit provided in the embodiment of the present application and the actual etching outline corresponding to the known design layout of the integrated circuit, as well as the schematic diagram of the image of the two after being imaged, the upper left is the known design layout of the integrated circuit, the lower left is the actual etching outline corresponding to the known design layout of the integrated circuit, and the right part is the image of the two after being imaged. Because the input and output of the data processed by the pixel-to-pixel generative adversarial network model are in the form of images, it is necessary to image the layout file, convert the layout file into a binary image, and obtain the original data set for further operation.

[0105] The known design layout of the integrated circuit should include a variety of two-dimensional graphic designs, including two-dimensional graphics of various shapes (such as cross, L and H shapes, etc.) and the distribution of various graphics (sparse and dense).

[0106] For the current design layout of the integrated circuit, image processing is also required to input the trained pixels into the generative adversarial network model to make predictions on the pixels.

[0107] First, the original design layout of the integrated circuit must be collected. The size of the original design layout of the integrated circuit is generally large. In order to ensure the accuracy requirements of the subsequent processing into an image, the original layout is segmented and the large layout is evenly divided into small layouts of 1um*1um size. That is, the original design layout of the integrated circuit is segmented according to the preset size to obtain the segmented design layout of the integrated circuit.

[0108] Then, the integrated circuit segmentation design layout is binarized to obtain an integrated circuit binary design layout; and the integrated circuit binary design layout is used as the integrated circuit current design layout.

[0109] Specifically, the embodiment of the present application can convert each segmented small map into a black and white binary image with a size of 1024*1024. This ensures that the size of each pixel of the image corresponds approximately to 1nm, and high-resolution image information can improve the accuracy of prediction.

[0110] In one possible implementation, the loss function of the initial pixel-to-pixel generative adversarial network model provided in the embodiment of the present application may include: a binary cross entropy loss function.

[0111] Specifically, for the design of a common pixel-to-pixel generative adversarial network model, the loss function will use the L1 norm loss, which is also the absolute loss function. However, the layout prediction task can be regarded as a binary classification problem, which aims to predict whether each pixel belongs to the target area or the background area. Therefore, the binary cross entropy loss function is more conducive to obtaining accurate results.

[0112] In one possible implementation, the hyperparameters of the initial pixel-to-pixel generative adversarial network model provided in the embodiment of the present application may include: learning rate, the number of samples selected for one training (BatchSize), training rounds (epochs) and optimizer, etc.

[0113] The learning rate provided in the embodiment of the present application may be equal to 0.0005, the number of samples selected for one training may be equal to 8, the number of training rounds may be equal to 20, and the optimizer may be an adaptive moment estimation optimizer, so as to improve the accuracy of model training while taking into account the speed of training.

[0114] The embodiment of the present application provides a method for predicting the etching profile of an integrated circuit, the method comprising: collecting the current design layout of the integrated circuit; obtaining a training set of an initial pixel-to-pixel generative adversarial network model, the training set comprising: a known design layout of the integrated circuit and the actual etching profile corresponding to the known design layout of the integrated circuit; using the training set to learn the mapping relationship between the known design layout of the integrated circuit and the actual etching profile corresponding to the known design layout of the integrated circuit; determining the model parameters of the initial pixel-to-pixel generative adversarial network model according to the mapping relationship to obtain a trained pixel-to-pixel generative adversarial network model; inputting the current design layout of the integrated circuit into the trained pixel-to-pixel generative adversarial network model to obtain the predicted etching profile corresponding to the current design layout of the integrated circuit. The present application realizes the prediction of the graphics after the design layout is etched on the substrate by adopting a pixel-to-pixel generative adversarial network based on pixel-to-pixel. Compared with the traditional machine learning method, its prediction accuracy is very high and its prediction speed is also faster.

[0115] Exemplary Devices

[0116] See also Fig.12 FIG. 1 is a schematic diagram of an integrated circuit etching profile prediction device provided in an embodiment of the present application, comprising:

[0117] A collection unit 201 is used to collect the current design layout of the integrated circuit;

[0118] An acquisition unit 202 is used to acquire a training set of an initial pixel-to-pixel generative adversarial network model, wherein the training set includes: a known design layout of an integrated circuit and an actual etching profile corresponding to the known design layout of the integrated circuit;

[0119] A learning unit 203 is used to learn the mapping relationship between the known design layout of the integrated circuit and the actual etching profile corresponding to the known design layout of the integrated circuit by using the training set;

[0120] A determination unit 204 is used to determine the model parameters of the initial pixel-to-pixel generative adversarial network model according to the mapping relationship to obtain a trained pixel-to-pixel generative adversarial network model;

[0121] The input unit 205 is used to input the current design layout of the integrated circuit into the trained pixel-to-pixel generative adversarial network model to obtain a predicted etching profile corresponding to the current design layout of the integrated circuit.

[0122] In a possible implementation, the collection unit is specifically configured to:

[0123] Collect the original design layout of integrated circuits;

[0124] Segmenting the original design layout of the integrated circuit according to a preset size to obtain an integrated circuit segmentation design layout;

[0125] The integrated circuit segmentation design layout is binarized to obtain an integrated circuit binary design layout; and the integrated circuit binary design layout is used as the current design layout of the integrated circuit.

[0126] In a possible implementation, the loss function of the initial pixel-to-pixel generative adversarial network model includes: a binary cross entropy loss function.

[0127] In a possible implementation, the hyper parameters of the initial pixel-to-pixel generative adversarial network model include: a learning rate, a number of samples selected for one training, a training round, and an optimizer;

[0128] The learning rate is equal to 0.0005, the number of samples selected for one training is equal to 8, the number of training rounds is equal to 20, and the optimizer is an adaptive moment estimation optimizer.

[0129] The embodiment of the present application provides an integrated circuit etching profile prediction device, and the method applied to the device includes: collecting the current design layout of the integrated circuit; obtaining the training set of the initial pixel-to-pixel generative adversarial network model, the training set including: the known design layout of the integrated circuit and the actual etching profile corresponding to the known design layout of the integrated circuit; using the training set to learn the mapping relationship between the known design layout of the integrated circuit and the actual etching profile corresponding to the known design layout of the integrated circuit; determining the model parameters of the initial pixel-to-pixel generative adversarial network model according to the mapping relationship to obtain the trained pixel-to-pixel generative adversarial network model; inputting the current design layout of the integrated circuit into the trained pixel-to-pixel generative adversarial network model to obtain the predicted etching profile corresponding to the current design layout of the integrated circuit. The present application realizes the prediction of the graphics after the design layout is etched on the substrate by adopting a pixel-to-pixel generative adversarial network based on pixel-to-pixel. Compared with the traditional machine learning method, its prediction accuracy is very high and its prediction speed is also faster.

[0130] Based on the above embodiments, the present application embodiment provides an integrated circuit etching profile prediction system, including:

[0131] Memory for storing computer programs;

[0132] A processor is used to implement the steps of the above-mentioned integrated circuit etching profile prediction method when executing the computer program.

[0133] Based on the above embodiments, the embodiments of the present application further provide a computer-readable medium, on which a computer program is stored, and when the computer program is processed and executed, the steps of the above-mentioned integrated circuit etching profile prediction method are implemented.

[0134] It should be noted that the computer-readable medium disclosed above may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that may be used by or in combination with an instruction execution system, device or device. In the present disclosure, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, in which a computer-readable program code is carried. This propagated data signal may take a variety of forms, including but not limited to an electromagnetic signal, an optical signal, or any suitable combination of the above. The computer readable signal medium may also be any computer readable medium other than a computer readable storage medium, which may send, propagate or transmit a program for use by or in conjunction with an instruction execution system, apparatus or device. The program code contained on the computer readable medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.

[0135] The computer-readable medium may be included in the system; or may exist independently without being assembled into the system.

[0136] In particular, according to an embodiment of the present disclosure, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a non-transitory computer-readable medium, and the computer program includes a program code for executing the method shown in the flowchart.

[0137] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0138] The above is only a preferred implementation of the present application. Although the present application has been disclosed as a preferred embodiment, it is not intended to limit the present application. Any technician familiar with the art can use the above disclosed methods and technical contents to make many possible changes and modifications to the technical solution of the present application without departing from the scope of the technical solution of the present application, or modify it into an equivalent embodiment of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application still falls within the scope of protection of the technical solution of the present application.

Claims

1. A method for predicting an integrated circuit etching profile, characterized in that: include: Collect the current design layout of the integrated circuit; Obtaining a training set of an initial pixel-to-pixel generative adversarial network model, the training set comprising: a known design layout of an integrated circuit and an actual etching profile corresponding to the known design layout of the integrated circuit; Using the training set to learn the mapping relationship between the known design layout of the integrated circuit and the actual etching profile corresponding to the known design layout of the integrated circuit; Determining model parameters of the initial pixel-to-pixel generative adversarial network model according to the mapping relationship to obtain a trained pixel-to-pixel generative adversarial network model; The current design layout of the integrated circuit is input into the trained pixel-to-pixel generative adversarial network model to obtain a predicted etching profile corresponding to the current design layout of the integrated circuit.

2. The method according to claim 1, characterized in that The current design layout of the acquisition integrated circuit includes: Collect the original design layout of integrated circuits; Segmenting the original design layout of the integrated circuit according to a preset size to obtain an integrated circuit segmentation design layout; The integrated circuit segmentation design layout is binarized to obtain an integrated circuit binary design layout; and the integrated circuit binary design layout is used as the current design layout of the integrated circuit.

3. The method according to claim 1, characterized in that The loss function of the initial pixel-to-pixel generative adversarial network model includes: a binary cross entropy loss function.

4. The method according to claim 1, characterized in that The hyper parameters of the initial pixel-to-pixel generative adversarial network model include: learning rate, number of samples selected for one training, training rounds and optimizer; The learning rate is equal to 0.0005, the number of samples selected for one training is equal to 8, the number of training rounds is equal to 20, and the optimizer is an adaptive moment estimation optimizer.

5. An integrated circuit etching profile prediction device, characterized in that: include: A collection unit, used for collecting the current design layout of the integrated circuit; An acquisition unit is used to acquire a training set of an initial pixel-to-pixel generative adversarial network model, wherein the training set includes: a known design layout of an integrated circuit and an actual etching profile corresponding to the known design layout of the integrated circuit; A learning unit, configured to use the training set to learn a mapping relationship between the known design layout of the integrated circuit and an actual etching profile corresponding to the known design layout of the integrated circuit; A determination unit, configured to determine model parameters of the initial pixel-to-pixel generative adversarial network model according to the mapping relationship, so as to obtain a trained pixel-to-pixel generative adversarial network model; An input unit is used to input the current design layout of the integrated circuit into the trained pixel-to-pixel generative adversarial network model to obtain a predicted etching profile corresponding to the current design layout of the integrated circuit.

6. The device according to claim 5, characterized in that The acquisition unit is specifically used for: Collect the original design layout of integrated circuits; Segmenting the original design layout of the integrated circuit according to a preset size to obtain an integrated circuit segmentation design layout; The integrated circuit segmentation design layout is binarized to obtain an integrated circuit binary design layout; and the integrated circuit binary design layout is used as the current design layout of the integrated circuit.

7. The device according to claim 5, characterized in that The loss function of the initial pixel-to-pixel generative adversarial network model includes: a binary cross entropy loss function.

8. The device according to claim 5, characterized in that The hyper parameters of the initial pixel-to-pixel generative adversarial network model include: learning rate, number of samples selected for one training, training rounds and optimizer; The learning rate is equal to 0.0005, the number of samples selected for one training is equal to 8, the number of training rounds is equal to 20, and the optimizer is an adaptive moment estimation optimizer.

9. An integrated circuit etching profile prediction system, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the integrated circuit etching profile prediction method as claimed in any one of claims 1 to 4 when executing the computer program.

10. A computer-readable medium, characterized in that The computer readable medium stores a computer program, and when the computer program is processed and executed, the steps of the integrated circuit etching profile prediction method according to any one of claims 1 to 4 are implemented.

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