Sensitive amplifier circuit, sensitive amplifier module, working method and low-voltage storage unit memory

Abstract

The invention discloses a sensitive amplifier circuit, a module, a working method and a low-voltage type storage unit storer, the sensitive amplifier circuit comprises an induction amplification circuit, the induction amplification circuit comprises an enable circuit part, a pull-up circuit part, a lower cross coupling part and an automatic turn-off circuit part, an input circuit part comprises two PMOS tubes, the upper cross coupling part is connected with the pull-up circuit part in series and adopts bit line voltage as grid control voltage of the two PMOS tubes, the lower cross coupling part is connected with the pull-up circuit part in series and is used for being matched with the pull-up circuit part to rapidly amplify voltage difference between a node Q and a node QB, and the automatic turn-off circuit part automatically turns off bit line voltage input with relatively high voltage according to the voltage difference between the node Q and the node QB. According to the sensitive amplifier circuit provided by the embodiment of the invention, the bit line voltage is used as the grid control voltage of the pull-up tube, and the automatic turn-off circuit part is arranged, so that the node voltage corresponding to the bit line with relatively high voltage is quickly pulled up, the input of the bit line with relatively high voltage is automatically turned off, the speed of read operation can be increased, and the power consumption is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a sense amplifier circuit, a module, a working method and a low-voltage storage unit memory. Background Art

[0002] The sense amplifier is an important component of semiconductor memory, which directly affects the reading and writing speed of semiconductor memory. Since the time consumed by semiconductor memory to read data is generally greater than the time consumed to write data, the speed of semiconductor memory is mainly determined by the time to read data. With the increase in density and capacity of semiconductor memory, the number of storage cells connected to each bit line in the storage array is also increasing, which leads to the increasing parasitic capacitance on a single bit line. In this way, the speed of the bit line will slow down during the charging and discharging process, affecting the speed of data reading. In order to read data sensitively and quickly, a sense amplifier circuit is usually used as a reading circuit. The task of the sense amplifier is to read the information in the storage cell of the memory as quickly as possible. At present, common sense amplifiers mainly include voltage-type sense amplifiers and current-type sense amplifiers. Voltage-type sense amplifiers have been widely used due to their simple structure, high stability and low power consumption.

[0003] Among mainstream semiconductor memories, electrically programmable fuse (eFuse) technology is widely used as a one-time programmable memory in many circuits, such as fine-tuning circuit structures and OTP structures, due to its compatibility with complementary metal oxide semiconductor (CMOS) logic devices, simple fuse manufacturing process, low production cost, and ease of use. Based on the electromigration theory, eFuse technology stores information by whether the electric fuse is blown by the current. Specifically, the initial resistance of the eFuse is very small. When a large current continues to pass through, the fuse begins to burn until it blows, achieving a significant increase in resistance, thereby achieving the distinction between "0" and "1" storage units and realizing information storage. However, in order to ensure that the eFuse is not burned by mistake when reading data, the current range that can be distinguished before and after programming of the memory device based on the electrical characteristics of the fuse is very small, so the reading current is usually not very large, that is, the voltage read from the bit line of the "0" and "1" storage cells is low, and with the reduction of process nodes and the application demand for low-power memory design, the operating voltage of the memory chip will be further reduced, which leads to a smaller and smaller voltage window of the sensitive amplifier, and then leads to a decrease in the data reading speed, making it difficult to read data. In addition, since the eFuse IP (memory device based on the electrical characteristics of the fuse) circuit usually requires a more complex control circuit to realize the timing control of the read operation, it not only consumes a part of the chip area, but also further leads to a longer reading time, slow reading speed, and high power consumption. Summary of the invention

[0004] The embodiments of the present invention provide a sensitive amplifier circuit, a module, a working method and a low-voltage storage unit memory. The sensitive amplifier circuit can quickly amplify and identify a slight voltage difference between a storage bit line and a reference bit line when the memory is at a relatively low operating voltage, thereby realizing rapid reading of data in a storage unit of the memory at a relatively low operating voltage. The sensitive amplifier circuit can be effectively applied to low-voltage Bitcell memories, such as eFuse IP.

[0005] In a first aspect, an embodiment of the present invention provides a sense amplifier circuit, including a sense amplifier circuit and an output amplifier circuit, wherein the sense amplifier circuit includes: An enabling circuit part, used to control whether the sensing amplifier circuit works or not; A pull-up circuit portion, comprising a first PMOS tube and a second PMOS tube, wherein the first PMOS tube uses a first bit line voltage as its gate control voltage, the second PMOS tube uses a second bit line voltage as its gate control voltage, the drain of the first PMOS tube is connected to a first node Q, the drain of the second PMOS tube is connected to a second node QB, and the sources of the first PMOS tube and the second PMOS tube are both connected to the enabling circuit portion; A lower cross-coupling portion is connected in series with the pull-up circuit portion and is used to cooperate with the pull-up circuit portion to quickly amplify the voltage difference between the first node Q and the second node QB; The automatic shut-off circuit unit is used to automatically shut down the relatively high-voltage bit line voltage input of the first bit line and the second bit line according to the amplification result of the voltage difference between the first node Q and the second node QB by the lower cross-coupling unit, and pull up the voltage of the relatively high-voltage node of the first node Q and the second node QB to VDD.

[0006] In some embodiments, an output amplifier circuit is further included, wherein the output amplifier circuit is configured to output a reading according to a voltage of the first node Q or the second node QB when the sensing amplifier circuit is operating.

[0007] In some embodiments, a precharge reset circuit is further included, wherein the precharge reset circuit is used to pull down the voltage of the first node Q and the second node QB to VSS when the sensing amplifier circuit is not working.

[0008] In some embodiments, a logic control circuit is further included, wherein the logic control circuit is used to generate an enable control signal to control the operation of the sense amplifier circuit, the output amplifier circuit, and the pre-charge reset circuit in the sense amplifier circuit.

[0009] In a second aspect, an embodiment of the present invention provides a sense amplifier module, which adopts the circuit layout of the sense amplifier circuit of the first aspect.

[0010] In some implementations, the pins of the sense amplifier module include: A first pin, which is used to connect the source electrodes of the third PMOS tube, the fourth PMOS tube, the fifth PMOS tube, the sixth PMOS tube, the seventh PMOS tube, and the eighth PMOS tube to VDD; A second pin is used to connect the source electrodes of the eighth NMOS tube, the ninth NMOS tube, and the tenth NMOS tube to VSS; A third pin, which is used to connect the gate of the tenth PMOS tube and the input of the logic control circuit to a fourth enable signal EN; A fourth pin, used to connect the source electrodes of the first NMOS tube, the third NMOS tube, and the fifth NMOS tube to the first bit line; A fifth pin, used to connect the source electrodes of the second NMOS tube, the fourth NMOS tube, and the sixth NMOS tube to the second bit line; The sixth pin is used to connect the output node QOUT.

[0011] In a third aspect, an embodiment of the present invention provides a low-voltage storage unit memory, which includes the sense amplifier circuit of the first aspect or the sense amplifier module of the second aspect.

[0012] In a fourth aspect, an embodiment of the present invention provides a working method of a sense amplifier circuit, wherein the sense amplifier circuit is the sense amplifier circuit of the first aspect, and the method comprises: Generate a first control signal through a logic control circuit to control the precharge reset circuit in the sense amplifier circuit to be in an operating state, and simultaneously control the sense amplifier circuit and the output amplifier circuit to be in an off state, so as to pull down the first node Q and the second node QB in the sense amplifier circuit to VSS, and transmit the first bit line voltage to the second input node IN2, and transmit the second bit line voltage to the first input node IN1; Generate a second control signal through the logic control circuit to control the sense amplifier circuit in the sense amplifier circuit to be in a working state, and simultaneously control the precharge reset circuit and the output amplifier circuit to be in a closed state, so as to quickly amplify the voltage difference between the first node Q and the second node QB, and automatically shut off the relatively high-voltage bit line voltage input of the first bit line and the second bit line according to the amplification result of the voltage difference between the first node Q and the second node QB, and pull up the voltage of the relatively high-voltage node of the first node Q and the second node QB to VDD; A third control signal is generated by a logic control circuit to control the sensing amplifier circuit and the output amplifier circuit in the sensitive amplifier circuit to be in a working state, and at the same time control the pre-charge reset circuit to be in a closed state, so as to output a reading according to the voltage of the first node Q or the second node QB.

[0013] The sense amplifier circuit provided by the embodiment of the present invention uses the bit line voltage as the gate control voltage of the pull-up tube, and an automatic shut-down circuit part is provided in the sense amplifier circuit of the sense amplifier circuit, wherein the automatic shut-down circuit part can automatically shut down the relatively high-voltage bit line voltage input of the first bit line and the second bit line according to the amplification result of the voltage difference between the first node Q and the second node QB by the sense amplifier circuit, thereby controlling the input of the gate voltage of the corresponding pull-up tube, thereby controlling the on-off of the corresponding pull-up tube, and at the same time quickly pull up the voltage of the relatively high-voltage node of the first node Q and the second node QB to VDD, so as to achieve rapid amplification and output of the corresponding node voltage, so as to improve the speed of the read operation and reduce power consumption; in addition, since the solution of the embodiment of the present invention can automatically shut down the input of the relatively high-voltage bit line in time, it can also quickly identify and amplify the small voltage difference between the bit lines in the lower operating voltage range, so as to achieve fast and accurate data reading in this scenario, so it can be applicable to low-voltage Bitcell memory (storage unit memory), such as eFuse IP, and when it is applied in eFuse IP, it can also effectively avoid mis-burning of eFuse. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying any creative work.

[0015] Figure 1 is a circuit structure diagram of a sense amplifier circuit according to an embodiment of the present invention; Figure 2 A circuit structure diagram of a sense amplifier circuit and a precharge reset circuit of a sense amplifier circuit according to an embodiment of the present invention; Figure 3 is a circuit structure diagram of an output amplifier circuit of a sense amplifier circuit according to an embodiment of the present invention; Figure 4 A circuit structure diagram of a logic control circuit of a sense amplifier circuit according to an embodiment of the present invention; Figure 5 A circuit structure diagram of a delay module in a logic control circuit of a sense amplifier circuit according to an embodiment of the present invention; Figure 6 A pin distribution diagram of a sense amplifier module according to an embodiment of the present invention; Figure 7 is an output waveform diagram of a logic control circuit in a sense amplifier circuit according to an embodiment of the present invention; Figure 8 is an output waveform diagram of a sense amplifier circuit according to an embodiment of the present invention; Fig. 9 This is a waveform diagram of the sense amplifier circuit according to one embodiment of the present invention when operating in a scenario where the voltage of the first bit line FUSE_BL is greater than the voltage of the second bit line REF_BLB; Fig.10 Flow chart of a working method of a sense amplifier circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0016] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0017] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application may be combined with each other.

[0018] The term "connection" mentioned in the present invention may include direct connection and indirect connection. In a direct connection, there are no components between the ends. For example, the first end of switch A is connected to the first end of switch B. It can be that there is only a connection line (such as a metal line) on the connection line between the first end of switch A and the first end of switch B, and there are no other components. In an indirect connection, there may be other components between the ends. For example, the first end of switch C is connected to the first end of switch D. It can be that there is at least one other component (such as switch E, etc.) on the connection line between the first end of switch C and the first end of switch D in addition to the connection line.

[0019] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include" and "comprise" include not only those elements, but also other elements that are not explicitly listed, or also include elements inherent to such processes, methods, articles or equipment. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the existence of other identical elements in the process, method, article or equipment that includes the elements.

[0020] The present invention will be further described in detail below in conjunction with the accompanying drawings.

[0021] Figure 1 The circuit structure of the sense amplifier circuit according to one embodiment of the present invention is schematically shown. Figure 1 As shown, the sense amplifier circuit includes an inductive amplifier circuit.

[0022] The sensing amplifier circuit is used to sense and amplify the voltage difference between the input first bit line and the second bit line.

[0023] The inductive amplifier circuit includes an enabling circuit part, a pull-up circuit part, a lower cross-coupling part and an automatic shut-off circuit part. The enabling circuit part is used to control whether the inductive amplifier circuit works or not. The pull-up circuit part is connected in series with the lower cross-coupling part. The two cooperate with each other to quickly amplify the voltage difference between the first node Q and the second node QB. The automatic shut-off circuit part is used to automatically shut off the relatively high voltage voltage input in the first bit line and the second bit line according to the amplification result of the voltage difference between the first node Q and the second node QB by the lower cross-coupling part, and pull up the voltage of the relatively high voltage node in the first node Q and the second node QB to VDD. Preferably, in the embodiment of the present invention, the first bit line voltage and the second bit line voltage are used as the gate control voltage of the pull-up tube in the pull-up circuit part, so as to realize the automatic shut-off of the relatively high voltage voltage input in the first bit line and the second bit line based on the amplification result of the voltage difference between the first node Q and the second node QB. Among them, the first bit line and the second bit line are a storage fuse bit line (FUSE_BL) and a reference fuse bit line (REF_BLB). Which bit line the first bit line and the second bit line specifically refer to can be set according to needs and expectations, and the two can be interchanged with each other, which has no impact on the present invention. For the sake of convenience of explanation, in subsequent implementation methods, the first bit line is taken as a storage fuse bit line (FUSE_BL) and the second bit line is taken as a reference fuse bit line (REF_BLB) as an example for further explanation.

[0024] In some embodiments, the sense amplifier circuit may further include an output amplifier circuit and a pre-charge reset circuit, wherein the output amplifier circuit is used to output a reading based on the voltage of the first node Q or the second node QB when the sense amplifier circuit is working, and the pre-charge reset circuit is used to pull down the voltage of the first node Q and the second node QB to VSS for charging and resetting when the sense amplifier circuit is not working.

[0025] Specifically, refer to Figure 2 As shown, in the inductive amplifier circuit, the pull-up circuit section includes two PMOS tubes, namely, a first PMOS tube P1 and a second PMOS tube P2. The first PMOS tube uses the first bit line voltage as its gate control voltage, the second PMOS tube uses the second bit line voltage as its gate control voltage, the drain of the first PMOS tube is connected to the first node Q, the drain of the second PMOS tube is connected to the second node QB, and the sources of the first PMOS tube and the second PMOS tube are both connected to the enabling circuit section.

[0026] Continue to refer to Figure 2As shown, in the sensing amplifier circuit, the enabling circuit part may include a PMOS tube, which is a third PMOS tube P3. The source of the third PMOS tube is connected to VDD, the drain is connected to the source of the first PMOS tube and the source of the second PMOS tube, and the gate is connected to the first enabling signal ENB. When the first enabling signal ENB is connected to a low level, the third PMOS tube is turned on, so that the overall sensing amplifier circuit is in a working state; when the first enabling signal ENB is connected to a high level, the third PMOS tube is turned off, so that the overall sensing amplifier circuit does not work and is in a closed state.

[0027] Continue to refer to Figure 2 As shown, in the inductive amplifier circuit, the lower cross-coupling part may include two NMOS transistors, namely, a first NMOS transistor N1 and a second NMOS transistor N2. The drain of the first NMOS transistor is connected to the first node Q, the source is connected to the first bit line, and the gate is connected to the second node QB; the drain of the second NMOS transistor is connected to the second node QB, the source is connected to the second bit line, and the gate is connected to the first node Q.

[0028] Continue to refer to Figure 2 As shown, in the inductive amplifier circuit, the automatic shutdown circuit part may include four PMOS tubes and four NMOS tubes, namely, the fourth PMOS tube P4, the fifth PMOS tube P5, the sixth PMOS tube P6, the seventh PMOS tube P7 and the third NMOS tube N3, the fourth NMOS tube N4, the fifth NMOS tube N5, and the sixth NMOS tube N6. Among them, the source of the fourth PMOS tube is connected to VDD, the gate of the fourth PMOS tube and the gate of the third NMOS tube are both connected to the first node Q, the drain of the fourth PMOS tube is connected to the drain of the third NMOS tube, and a first intermediate node X1 is provided, and the source of the third NMOS tube is connected to the first bit line; the source of the sixth PMOS tube is connected to VDD, the gate of the sixth PMOS tube and the gate of the fifth NMOS tube are both connected to the first intermediate node X1, the drain of the sixth PMOS tube is connected to the drain of the fifth NMOS tube, and a second input node IN2 is provided, the second input node IN2 is connected to the gate of the second PMOS tube, and the source of the fifth NMOS tube is connected to the first bit line The source of the fifth PMOS tube is connected to VDD, the gate of the fifth PMOS tube and the gate of the fourth NMOS tube are both connected to the second node QB, the drain of the fifth PMOS tube is connected to the drain of the fourth NMOS tube, and a second intermediate node X2 is provided, and the source of the fourth NMOS tube is connected to the second bit line; the source of the seventh PMOS tube is connected to VDD, the gate of the seventh PMOS tube and the gate of the sixth NMOS tube are both connected to the second intermediate node X2, the drain of the seventh PMOS tube is connected to the drain of the sixth NMOS tube, and a first input node IN1 is provided, the first input node IN1 is connected to the gate of the first PMOS tube, and the source of the sixth NMOS tube is connected to the second bit line.

[0029] For the output amplifier circuit, it can be set to output a reading according to the voltage of the first node Q, or it can be set to output a reading according to the voltage of the second node QB. It can be understood that the purpose of the sense amplifier circuit of the present invention is to output a reading according to the voltage of the first bit line relative to the second bit line, such as when the voltage of the first bit line is higher than the voltage of the second bit line, read "1", and when the voltage of the first bit line is lower than the voltage of the second bit line, read "0", so the output amplifier circuit outputs a reading according to the voltage of the first node Q and when it outputs a reading according to the voltage of the second node QB, the mode is different. Specifically, when the output amplifier circuit is set to output a reading according to the voltage of the first node Q, it can be set to directly output a reading according to the voltage of the first node Q relative to the voltage of the second node QB, that is, when the voltage of the first node Q is pulled up to VDD and higher than the voltage of the second node QB, the reading "1" is output, and when the voltage of the first node Q is not pulled up to VDD and lower than the voltage of the second node QB, the reading "0" is output. When the output amplifier circuit is configured to output a reading according to the voltage of the second node QB, it can be configured to output an opposite reading according to the voltage of the second node QB relative to the voltage of the first node Q, that is, when the voltage of the second node QB is pulled up to VDD and is higher than the voltage of the first node Q, the output reading is "0", and when the voltage of the second node QB is not pulled up to VDD and is lower than the voltage of the first node Q, the output reading is "1". Thus, it is possible to output a reading according to the voltage of the first node Q, and it can also be configured to output a reading according to the voltage of the second node QB.

[0030] Reference Figure 3As shown, in this embodiment, the output amplifier circuit is set to output a reading according to the voltage of the second node QB, and the output amplifier circuit may include two PMOS tubes and two NMOS tubes, namely, the eighth PMOS tube P8, the ninth PMOS tube P9, the seventh NMOS tube N7, and the eighth NMOS tube N8. Among them, the gate of the ninth PMOS tube and the gate of the seventh NMOS tube are both connected to the first node Q or the second node QB, the drain of the ninth PMOS tube and the drain of the seventh NMOS tube are both connected to the output node QOUT, the source of the ninth PMOS tube is connected to the drain of the eighth PMOS tube, the source of the eighth PMOS tube is connected to VDD, the gate of the eighth PMOS tube is connected to the second enable signal ENB1, the source of the seventh NMOS tube is connected to the drain of the eighth NMOS tube, the source of the eighth NMOS tube is connected to VSS, and the gate of the eighth NMOS tube is connected to the third enable signal EN1, and the second enable signal ENB1 and the third enable signal EN1 are enable signals with opposite levels. When the second enable signal ENB1 is connected to a high level and the third enable signal EN1 is connected to a low level, the output amplifier circuit does not work and is in a closed state; when the second enable signal ENB1 is connected to a low level and the third enable signal EN1 is connected to a high level, the output amplifier circuit is in a working state. It should be noted that the node connected to the gate of the ninth PMOS tube and the gate of the seventh NMOS tube can be the first node Q or the second node QB. Figure 3 In the illustrated embodiment, the gate of the ninth PMOS tube and the gate of the seventh NMOS tube are both connected to the second node QB to output a reading according to the voltage of the second node QB. As a possible embodiment, the output amplifier circuit of the present invention may also include two inverters, namely, a fourth inverter INV4 and a fifth inverter INV5. The gate of the ninth PMOS tube and the drain of the seventh NMOS tube are connected to the input end of the fourth inverter, and the output end of the fourth inverter is the node QOUTB. The node QOUTB is connected to the input end of the fifth inverter, and the output end of the fifth inverter is the output node QOUT. In this way, the first inverter and the second inverter can be used to form an output buffer. The ability to drive the load can be adjusted by adjusting the size of the MOS tube of the first inverter and / or the second inverter, so that the output level can be smoother without changing the output logic.

[0031] Reference Figure 2As shown, the pre-charge reset circuit may include two NMOS tubes, namely, the ninth NMOS tube N9 and the tenth NMOS tube N10. The drain of the ninth NMOS tube is connected to the first node Q, the source is connected to VSS, and the gate is connected to the first enable signal ENB; the drain of the tenth NMOS tube is connected to the second node QB, the source is connected to VSS, and the gate is connected to the first enable signal ENB. When the first enable signal ENB is connected to a low level, the third PMOS tube of the enable circuit part will be turned on, the sense amplifier circuit is in a working state, the ninth NMOS tube and the tenth NMOS tube will be turned off, the pre-charge reset circuit does not work, and is in a closed state; when the first enable signal ENB is connected to a high level, the third PMOS tube of the enable circuit part will be turned off, the sense amplifier circuit does not work, and is in a closed state, the ninth NMOS tube and the tenth NMOS tube will be turned on, and the pre-charge reset circuit is in a working state, so as to pull down the voltage of the first node Q and the voltage of the second node QB to VSS for reset. This arrangement can reset the voltages of the first node Q and the second node QB, and can also be linked with the automatic shutdown circuit unit to use the first bit line voltage as the gate control voltage of the first PMOS tube and the second bit line voltage as the gate control voltage of the second PMOS tube.

[0032] As a more preferred embodiment, the precharge reset circuit may further include a transmission gate, one end of which is connected to the first node Q, and the other end is connected to the second node QB. When the transmission gate is turned on, the first node Q and the second node QB are turned on, thereby ensuring that when the precharge reset circuit is in a working state, the levels of the first node Q and the second node QB in the sense amplifier circuit are completely consistent, reducing the offset voltage and improving the accuracy of sensing. The transmission gate may be composed of an eleventh NMOS transistor N11 whose gate is connected to the first enable signal ENB and a tenth PMOS transistor P10 whose gate is connected to the fourth enable signal EN, wherein the fourth enable signal EN and the first enable signal ENB are enable signals with opposite levels. Specifically, referring to Figure 2As shown, the PMOS tube of the transmission gate is recorded as the tenth PMOS tube, the NMOS tube of the transmission gate is recorded as the eleventh NMOS tube, the gate of the tenth PMOS tube is connected to the fourth enable signal EN, the gate of the eleventh NMOS tube is connected to the first enable signal ENB, the source of the tenth PMOS tube is connected to the source of the eleventh NMOS tube, and the drain of the tenth PMOS tube is connected to the drain of the eleventh NMOS tube to form a transmission gate. In this way, the transmission gate is controlled by the first enable signal ENB and the fourth enable signal EN: when the first enable signal ENB is connected to a low level and the fourth enable signal EN is connected to a high level, the third PMOS tube of the enable circuit part will be turned on, the sense amplifier circuit will work, the tenth PMOS tube, the ninth NMOS tube, the tenth NMOS tube and the eleventh NMOS tube will all be turned off, the transmission gate will be turned off, the pre-charge reset circuit will not work, and it will be in a closed state; when the first enable signal ENB is connected to a high level and the fourth enable signal EN is connected to a low level, the third PMOS tube of the enable circuit part will be turned off, the sense amplifier circuit will not work, and it will be in a closed state, the tenth PMOS tube, the ninth NMOS tube, the tenth NMOS tube and the eleventh NMOS tube will all be turned on, the transmission gate will be turned on, and the pre-charge reset circuit will be in a working state, so that the first node Q and the second node QB are connected, so that the levels of the first node Q and the second node QB in the sense amplifier circuit are completely consistent, and the first node Q and the second node QB are quickly pulled down to VSS, and the first node Q and the second node QB are reset. By setting in this way, the voltage levels at both ends of SA can be controlled to be consistent during pre-charging, thereby reducing the offset voltage.

[0033] Specifically, when the sense amplifier circuit of the present invention is in operation, it includes three different operation modes, namely, a pre-charging mode, a sensing amplification mode and an output amplification mode.

[0034] In the pre-charge mode, the pre-charge reset circuit is in the working state, and the sensing amplifier circuit and the output amplifier circuit are both in the off state. At this time, the input fourth enable signal EN is low level, the first enable signal ENB is high level, the third enable signal EN1 is low level, and the second enable signal ENB1 is high level. At this time, the third PMOS tube will be turned off, and the transmission gate composed of the tenth PMOS tube and the eleventh NMOS tube will be turned on, so that the levels of the first node Q and the second node QB are consistent, and the ninth NMOS tube and the tenth NMOS tube will also be turned on, so that the levels of the first node Q and the second node QB are pulled down to VSS, and the voltages of the first node Q and the second node QB are reset. Afterwards, since the first node Q is pulled down to VSS, the fourth PMOS tube will be turned on, so that the voltage of the first intermediate node X1 is pulled up to VDD, and since the second node QB is pulled down to VSS, the fifth PMOS tube will be turned on, so that the voltage of the second intermediate node X2 is pulled up to VDD. Then, since the first intermediate node X1 is pulled up to VDD, the fifth NMOS tube is turned on, so that the second input node IN2 is connected to the first bit line FUSE_BL, and since the second intermediate node X2 is pulled up to VDD, the sixth NMOS tube is turned on, so that the first input node IN1 is connected to the second bit line REF_BLB.

[0035] In the inductive amplification mode, the inductive amplification circuit is in working state, and the pre-charge reset circuit and the output amplification circuit are both in closed state. At this time, the input fourth enable signal EN is high level, the first enable signal ENB is low level, the third enable signal EN1 is low level, and the second enable signal ENB1 is high level. At this time, the transmission gate composed of the tenth PMOS tube and the eleventh NMOS tube will be turned off, and the ninth NMOS tube and the tenth NMOS tube will also be turned off, and the third PMOS tube will be turned on, so that the source of the first PMOS tube and the source of the second PMOS tube are connected to VDD. For the inductive amplification mode, there will be two different working states based on the voltage relationship between the first bit line FUSE_BL and the second bit line REF_BLB.

[0036] When the voltage of the first bit line FUSE_BL is greater than the voltage of the second bit line REF_BLB, since in the precharge mode, the voltage value of the first bit line FUSE_BL has been transmitted to the second input node IN2, and the voltage value of the second bit line REF_BLB has been transmitted to the first input node IN1, V _IN2 >V _IN1 . Since V _IN2 >V _IN1 , so that the conduction conditions of the first PMOS tube and the second PMOS tube will be different. The |V _GS1 | will be higher than the |V of the second PMOS tube_GS2| , resulting in the pull-up capability of the first PMOS tube being higher than that of the second PMOS tube, and thus the rising speed of the voltage of the first node Q will be higher than the rising speed of the voltage of the second node QB. Therefore, the first node Q will be pulled up to VDD before the second node QB, and then the second NMOS tube will be turned on before the first NMOS tube. When the first node Q is pulled up to VDD, the second NMOS tube is turned on. At this time, the second node QB will be connected to the second bit line REF_BLB, so that the voltage of the second node QB is further pulled down, and the second node QB is gradually charged to a voltage level consistent with the second bit line REF_BLB. Afterwards, the fifth PMOS tube and the third NMOS tube will be turned on, the first intermediate node X1 will be pulled down to a voltage level consistent with the first bit line FUSE_BL, and the second intermediate node X2 will be pulled up to VDD. At this time, the V _GS6 >V _THN , the sixth NMOS tube will continue to conduct, and the V _GS5 <V _THN , the fifth NMOS tube will be turned off to automatically turn off the relatively high voltage bit line. Then, the voltage of the second input node IN2 will be pulled up to VDD and fed back to the gate of the second PMOS tube, so that the second PMOS tube is turned off, and the voltage level of the second node QB is quickly reduced to the voltage level consistent with the second bit line REF_BLB, while the first node Q will rise to VDD to pull the voltage of the relatively high voltage node up to VDD. At this time, the voltage difference between the voltage of the first node Q and the voltage of the second node QB is VDD-V _REF_BLB .

[0037] When the voltage of the first bit line FUSE_BL is lower than the voltage of the second bit line REF_BLB, since the voltage of the first bit line FUSE_BL has been transmitted to the second input node IN2 and the voltage of the second bit line REF_BLB has been transmitted to the first input node IN1 in the precharge mode, V _IN1 >V _IN2 . Since V _IN1 >V _IN2 , so that the conduction conditions of the first PMOS tube and the second PMOS tube will be different. The |V _GS1 | will be lower than the |V of the second PMOS tube _GS2|, resulting in the pull-up capability of the first PMOS tube being lower than that of the second PMOS tube, and thus the rising speed of the voltage of the first node Q will be lower than the rising speed of the voltage of the second node QB, so the second node QB will be pulled up to VDD before the first node Q, and then the first NMOS tube will be turned on before the second NMOS tube. When the second node QB is pulled up to VDD, the first NMOS tube is turned on, and at this time the first node Q will be connected to the first bit line FUSE_BL, so that the voltage of the first node Q is further pulled down, and the first node Q is gradually charged to a voltage level consistent with the first bit line FUSE_BL. Afterwards, at this time, the fourth PMOS tube and the fourth NMOS tube will be turned on, the second intermediate X2 will be pulled down to a voltage level consistent with the second bit line REF_BLB, and the first intermediate node X1 will be pulled up to VDD. At this time, the V _GS5 >V _THN , the fifth NMOS tube will continue to conduct, and the V _GS6 <V _THN , the sixth NMOS tube will be turned off to automatically turn off the relatively high voltage bit line. Then, the voltage of the first input node IN1 will be pulled up to VDD and fed back to the gate of the first PMOS tube, so that the first PMOS tube is turned off, and the voltage level of the first node Q quickly drops to the voltage level consistent with the first bit line FUSE_BL, while the second node QB will rise to VDD to pull the voltage of the relatively high voltage node up to VDD. At this time, the voltage difference between the voltage of the first node Q and the voltage of the second node QB is V _REF_BLB -VDD.

[0038] In the output amplification mode, the output amplification circuit and the sense amplification circuit are both in working state, and the precharge reset circuit is in off state. At this time, the input fourth enable signal EN is high level, the first enable signal ENB is low level, the third enable signal EN1 is high level, and the second enable signal ENB1 is low level.

[0039] When the voltage of the first bit line FUSE_BL is greater than the voltage of the second bit line REF_BLB, the voltage of the second node QB is at a voltage level consistent with the voltage of the second bit line REF_BLB. At this time, the voltage of the second node QB is input to the gates of the ninth PMOS tube and the seventh NMOS tube, so that the ninth PMOS tube is turned on. Since the second enable signal ENB1 is at a low level, the eighth PMOS tube is also turned on, and the output is pulled up to VDD. Finally, the voltage of the output node QOUT is pulled up to the VDD output through the two-stage inverter, completing the operation of reading "1".

[0040] When the voltage of the first bit line FUSE_BL is less than the voltage of the second bit line REF_BLB, the voltage of the second node QB is VDD. At this time, the voltage of the second node QB is input to the gates of the ninth PMOS tube and the seventh NMOS tube, so that the seventh NMOS tube is turned on. Since the third enable signal EN1 is at a high level, the eighth NMOS tube is also turned on, and the output is pulled down to VSS. Finally, the voltage of the output node QOUT is pulled down to VSS output through the two-stage inverter, completing the operation of reading "0".

[0041] So far, the main part of the sense amplifier circuit of the present invention has been described.

[0042] As a possible implementation, the sense amplifier circuit of the present invention may further include a logic control circuit, which is used to generate an enable control signal to control the operation of the sense amplifier circuit, the output amplifier circuit and the precharge reset circuit in the sense amplifier circuit, that is, to control the sense amplifier circuit of the present invention to switch between three different operating modes. Specifically, the logic control circuit may be configured to control and adjust other enable signals used to input the sense amplifier circuit or to input the output amplifier circuit according to the input fourth enable signal EN, such as the first enable signal ENB, the second enable signal ENB1 and the third enable signal EN1. By setting the logic control circuit, the overall sense amplifier circuit only needs to input one enable signal to adjust the input of other enable signals used to control the overall sense amplifier circuit, and then the operating mode of the overall sense amplifier circuit can be controlled by adjusting the level of one enable signal.

[0043] Figure 4 The circuit structure diagram of the logic control circuit of the sense amplifier circuit according to one embodiment of the present invention is schematically shown. Figure 4As shown, two control circuits are included, which include at least three inverters, namely, the first inverter INV1, the second inverter INV2 and the third inverter INV3. In the first control circuit, the fourth enable signal EN is connected to the input end of the first inverter, and the first inverter outputs the first enable signal ENB, so that the first enable signal ENB can be controlled to remain opposite to the fourth enable signal EN. In another control circuit, the fourth enable signal EN is connected to the input end of the second inverter, and a delay module is provided between the fourth enable signal EN and the second inverter, the second inverter outputs the second enable signal ENB1, the second enable signal ENB1 is connected to the input end of the second inverter, and the second inverter outputs the third enable signal EN1. In this way, when the fourth enable signal EN is at a low level, the first enable signal ENB is at a high level through the logic control circuit, and the third enable signal EN1 is at a low level, so that the second enable signal ENB1 is at a high level, that is, the overall sense amplifier circuit enters the pre-charge mode. When the fourth enable signal EN is at a high level, the first enable signal ENB is at a low level through the logic control circuit, and at this time, under the action of the delay module, the third enable signal EN1 and the second enable signal ENB1 will not change for the time being, so the overall sensitive amplifier circuit enters the sensing amplification mode. After a certain period of time, the logic control circuit will adjust the third enable signal EN1 and the second enable signal ENB1, so that the third enable signal EN1 is at a high level and the second enable signal ENB1 is at a low level, thereby making the overall sensitive amplifier circuit enter the output amplification mode. As a possible implementation, for the delay module, it can be used as follows Figure 5 The circuit structure shown is implemented. In this embodiment, the delay module includes 6 inverters and 5 capacitors, the 6 inverters are connected in sequence, and there is a capacitor between adjacent inverters, and the other end of the capacitor is grounded, thereby realizing the delay function. The logic control circuit in the sense amplifier circuit of this embodiment of the present invention can use the delay module to generate control signals corresponding to each circuit part of the sense amplifier, and can control the sense amplifier to work in the corresponding working mode without using an external additional input signal.

[0044] Figure 7 The output waveform diagram of the logic control circuit in the sense amplifier circuit according to one embodiment of the present invention is schematically shown. Figure 7 As shown, through the logic control circuit, the level of the fourth enable signal EN is always opposite to the level of the first enable signal ENB, and the level of the second enable signal ENB1 is always opposite to the level of the third enable signal EN1. Figure 7It can be seen from the figure that after the level of the fourth enable signal EN and the level of the first enable signal ENB change, after a period of time, the level of the second enable signal ENB1 and the level of the third enable signal EN1 change, that is, the delay module takes corresponding action. Furthermore, through the logic control circuit, it is possible to control the change of the working mode of the overall sense amplifier circuit by inputting only one enable signal. Figure 7 It can be seen that the delay generated by the logic control circuit under tt coner is 2.04ns.

[0045] Figure 8 The output waveform diagram of the sense amplifier circuit according to one embodiment of the present invention is schematically shown. Figure 8As shown, it shows the simulation effect of the function of the sensitive amplifier obtained by inputting alternating high and low levels from the first bit line FUSE_BL and the second bit line REF_BLB. When the voltage of the first bit line FUSE_BL is higher than the voltage of the second bit line REF_BLB, the fourth enable signal EN is first input at a low level. At this time, the sensitive amplifier will first enter the pre-charge mode to reset the first node Q and the second node QB. Then, after a period of time, the fourth enable signal EN is adjusted to input a high level. At this time, the sensitive amplifier will enter the sensitive amplification mode to amplify the voltage difference between the first node Q and the second node QB according to the voltage of the first bit line FUSE_BL and the voltage of the second bit line REF_BLB. Finally, after a certain delay, the input of the second enable signal ENB1 and the third enable signal EN1 are adjusted so that the monitored third enable signal EN1 is input at a high level for output amplification. Finally, the output node QOUT is output at a high level to complete the read "1" operation. When the voltage of the first bit line FUSE_BL is lower than the voltage of the second bit line REF_BLB, similarly, the fourth enable signal EN is first input at a low level. At this time, the sensitive amplifier will first enter the pre-charge mode to reset the first node Q and the second node QB. Then after a period of time, the fourth enable signal EN is adjusted to input a high level. At this time, the sensitive amplifier will enter the sensitive amplification mode to amplify the voltage difference between the first node Q and the second node QB according to the voltage of the first bit line FUSE_BL and the voltage of the second bit line REF_BLB. Finally, after a certain delay, the input of the second enable signal ENB1 and the third enable signal EN1 are adjusted so that the monitored third enable signal EN1 is input at a high level for output amplification. Finally, the output node QOUT is output at a low level, completing the read "0" operation. From this, it can be seen that the waveforms of the first bit line signal FUSE_BL, the second bit line signal REF_BLB, the fourth enable control signal EN, the third enable control signal EN1 and the output signal QOUT correspond to each other. From this, it can be seen that the sensitive amplifier circuit of the embodiment of the present invention can accurately read the data of the storage unit according to the bit line input signal under the control of the logic control circuit.

[0046] Fig. 9 The waveform diagram of the sense amplifier circuit according to one embodiment of the present invention is schematically shown when the voltage of the first bit line FUSE_BL is greater than the voltage of the second bit line REF_BLB. Fig. 9As shown, when the voltage of the first bit line FUSE_BL is greater than the voltage of the second bit line REF_BLB, the fourth enable signal EN is first input at a low level, so that the sensitive amplifier circuit enters the pre-charge mode. At this time, the first bit line FUSE_BL is connected to the second input node IN2, and the second bit line REF_BLB is connected to the first input node IN1. Since the voltage of the first bit line FUSE_BL is higher than the voltage of the second bit line REF_BLB, the voltage of the first input node IN1 will be lower than the voltage of the second input node IN2. Afterwards, the fourth enable signal EN is input at a high level, so that the sensitive amplifier circuit enters the inductive amplification mode. Since the voltage of the first bit line FUSE_BL is greater than the voltage of the second bit line REF_BLB, the input of the first bit line FUSE_BL is automatically turned off, and the second input node IN2 is pulled up to VDD, while the first input node IN1 continues to be connected to the second bit line REF_BLB, maintaining a voltage consistent with the voltage level of the second bit line REF_BLB. From Fig. 9 It can be seen that the delay from the fourth enable signal EN being enabled to automatically shutting down the high-voltage bit line under the tt corner is 405.43ps, that is, the input of the high-voltage bit line can be quickly shut down according to the input of the bit line voltage, and then the voltage of the corresponding node can be quickly adjusted to the expected position, thereby realizing fast data reading and effectively reducing power consumption.

[0047] Furthermore, by testing the sense amplifier circuit of the present invention, the delay DELAY generated by the logic control module, the delay delay_off for automatically shutting down the relatively high voltage bit line, and the systematic offset of the sense amplifier at all corners are shown in Table 1 below: Table 1: Measurement data of all corners Corner tt ff ff fs fs sf sf ss ss VDD / V 5 5.75 5.75 4.25 4.25 4.25 4.25 4.25 4.25 T / ℃ 27 -40 125 -40 125 -40 125 -40 125 DELAY / ns 2.083 1.438 1.884 2.017 2.711 2.045 2.828 2.584 3.659 delay_off / ps 403.972 263.461 370.215 411.755 599.85 398.964 595.308 535.902 791.996 Systematic_offset / mV 2.523 2.487 2.532 2.509 2.562 2.532 2.583 2.563 2.634 I_VDD / nA 4.119 4.276 20.110 4.270 2.807 3.923 5.576 4.031 0.354 It can be seen from the measurement data in Table 1 that the power consumption of the sense amplifier circuit of the present invention is relatively small, and the maximum power consumption can be controlled within 21nA. In addition, under different corner conditions, the relatively high-voltage bit line input can be automatically shut down through the logic of its own circuit within 1ns, without the need for an additional logic control circuit. At the same time, the Systematic_offset of SA is small and can be controlled within 3mV, which fully meets the application scenarios of eFuse IP.

[0048] Figure 6 The pin distribution diagram of the sense amplifier module of one embodiment of the present invention is schematically shown. Specifically, the sense amplifier module adopts the circuit layout of the sense amplifier circuit of the above embodiment. Figure 6As shown, the sensitive amplifier circuit includes 6 pins, wherein the first pin is used to connect the source of the third PMOS tube, the fourth PMOS tube, the fifth PMOS tube, the sixth PMOS tube, the seventh PMOS tube, and the eighth PMOS tube to VDD, the second pin is used to connect the source of the eighth NMOS tube, the ninth NMOS tube, and the tenth NMOS tube to VSS, the third pin is used to connect the gate of the tenth PMOS tube and the input of the logic control circuit to the fourth enable signal EN, the fourth pin is used to connect the source of the first NMOS tube, the third NMOS tube, and the fifth NMOS tube to the first bit line, the fifth pin is used to connect the source of the second NMOS tube, the fourth NMOS tube, and the sixth NMOS tube to the second bit line, and the sixth pin is used to connect the output node QOUT.

[0049] The sense amplifier circuit or sense amplifier module of the present invention can also be applied to a low-voltage storage unit memory, such as an eFuse IP, so that the low-voltage storage unit memory can also achieve fast and safe data reading.

[0050] Fig.10 The process of the working method of the sense amplifier circuit according to one embodiment of the present invention is schematically shown. Fig.10 As shown, the method comprises the following steps: Step S1: Generate a first control signal through a logic control circuit to control the precharge reset circuit in the sense amplifier circuit to be in an operating state, and simultaneously control the sense amplifier circuit and the output amplifier circuit to be in an off state, so as to pull down the first node Q and the second node QB in the sense amplifier circuit to VSS, and transmit the first bit line voltage to the second input node IN2, and transmit the second bit line voltage to the first input node IN1; Step S2: Generate a second control signal through the logic control circuit to control the sense amplifier circuit in the sense amplifier circuit to be in a working state, and simultaneously control the precharge reset circuit and the output amplifier circuit to be in a closed state, so as to quickly amplify the voltage difference between the first node Q and the second node QB, and automatically shut off the relatively high-voltage bit line voltage input of the first bit line and the second bit line according to the amplification result of the voltage difference between the first node Q and the second node QB, and pull up the voltage of the relatively high-voltage node of the first node Q and the second node QB to VDD; Step S3: Generate a third control signal through a logic control circuit to control the sensing amplifier circuit and the output amplifier circuit in the sensitive amplifier circuit to be in a working state, and simultaneously control the pre-charge reset circuit to be in a closed state to output a reading according to the voltage of the first node Q or the second node QB.

[0051] Among them, in step S1, the first control signal generated by the logic control circuit includes the first enable signal ENB being high, the second enable signal ENB1 being high, the third enable signal EN1 being low, and the fourth enable signal EN being low. At this time, the pre-charge reset circuit is in the working state, and the sense amplifier circuit and the output amplifier circuit are both in the off state, thereby entering the pre-charge mode. Specifically, when the sense amplifier circuit is in the pre-charge mode, the specific working mode of each part in the circuit can refer to the relevant description in the previous text, and will not be repeated here.

[0052] In step S2, the second control signal generated by the logic control circuit includes the first enable signal EN being low, the second enable signal ENB1 being high, the third enable signal EN1 being low, and the fourth enable signal EN being high. At this time, the sense amplifier circuit is in working state, the pre-charge reset circuit and the output amplifier circuit are both in the off state, and then enters the sense amplifier mode. Specifically, when the sense amplifier circuit is in the sense amplifier mode, the specific working mode of each part in the circuit can refer to the relevant description in the previous text, and will not be repeated here.

[0053] In step S3, the third control signal generated by the logic control circuit includes the first enable signal EN being low, the second enable signal ENB1 being low, the third enable signal EN1 being high, and the fourth enable signal EN being high. At this time, the sense amplifier circuit and the output amplifier circuit are both in working state, the pre-charge reset circuit is in the off state, and then enters the output amplifier mode. Specifically, when the sense amplifier circuit is in the output amplifier mode, the specific working mode of each part in the circuit can refer to the relevant description in the previous text, and will not be repeated here.

[0054] The sense amplifier circuit provided by the embodiment of the present invention uses the bit line voltage as the gate control voltage of the pull-up tube, and an automatic shut-down circuit portion is provided in the sense amplifier circuit of the sense amplifier circuit, wherein the automatic shut-down circuit portion can automatically shut down the relatively high-voltage bit line voltage input of the first bit line and the second bit line according to the amplification result of the voltage difference between the first node Q and the second node QB by the sense amplifier circuit, thereby controlling the input of the gate voltage of the corresponding pull-up tube, thereby controlling the on-off of the corresponding pull-up tube, and then quickly pulling up the voltage of the relatively high-voltage node of the first node Q and the second node QB to VDD, realizing the rapid amplification and output of the corresponding node voltage, so as to improve the speed of the read operation and reduce the power consumption; in addition, since the solution of the embodiment of the present invention can automatically shut down the input of the relatively high-voltage bit line in time, it can also quickly identify and amplify the small voltage difference between the bit lines in the lower operating voltage range, so as to realize the fast and accurate data reading in this scenario, so it can be applicable to low-voltage Bitcell memory (storage unit memory), such as eFuse IP, and when it is applied in eFuse IP, it can also effectively avoid the mis-burning of eFuse. At the same time, the logic control circuit in the sense amplifier circuit provided by the embodiment of the present invention uses the delay module to control whether the output amplifier circuit works or not, and forms control signals corresponding to various parts of the sense amplifier circuit, so that the overall sense amplifier circuit only needs to input an enable signal, and no additional signals need to be input to control the current working mode of the sense amplifier. In addition, the pre-charge reset circuit in the sense amplifier circuit provided by the embodiment of the present invention is provided with a transmission gate control switch, which can ensure that the levels of the first node Q and the second node QB of the sense amplifier circuit are completely consistent in the pre-charge mode, reduce the offset voltage, and improve the accuracy of sensing.

[0055] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A sensitive amplifier circuit, characterized in that The invention comprises an inductive amplifier circuit, wherein the inductive amplifier circuit comprises: An enabling circuit part, used to control whether the sensing amplifier circuit works or not; A pull-up circuit portion, comprising a first PMOS tube and a second PMOS tube, wherein the first PMOS tube uses a first bit line voltage as its gate control voltage, the second PMOS tube uses a second bit line voltage as its gate control voltage, the drain of the first PMOS tube is connected to a first node Q, the drain of the second PMOS tube is connected to a second node QB, and the sources of the first PMOS tube and the second PMOS tube are both connected to the enabling circuit portion; A lower cross-coupling portion is connected in series with the pull-up circuit portion and is used to cooperate with the pull-up circuit portion to quickly amplify the voltage difference between the first node Q and the second node QB; The automatic shut-off circuit unit is used to automatically shut down the relatively high-voltage bit line voltage input of the first bit line and the second bit line according to the amplification result of the voltage difference between the first node Q and the second node QB by the lower cross-coupling unit, and pull up the voltage of the relatively high-voltage node of the first node Q and the second node QB to VDD.

2. The sense amplifier circuit according to claim 1, characterized in that: The lower cross-coupling part includes a first NMOS transistor and a second NMOS transistor, The drain of the first NMOS tube is connected to the first node Q, the source is connected to the first bit line, and the gate is connected to the second node QB; The drain of the second NMOS tube is connected to the second node QB, the source is connected to the second bit line, and the gate is connected to the first node Q.

3. The sense amplifier circuit according to claim 1, characterized in that: The automatic shutdown circuit unit includes 4 PMOS tubes and 4 NMOS tubes, which are respectively recorded as the fourth PMOS tube, the fifth PMOS tube, the sixth PMOS tube, the seventh PMOS tube and the third NMOS tube, the fourth NMOS tube, the fifth NMOS tube, and the sixth NMOS tube; The source of the fourth PMOS tube is connected to VDD, the gate of the fourth PMOS tube and the gate of the third NMOS tube are both connected to the first node Q, the drain of the fourth PMOS tube is connected to the drain of the third NMOS tube, and a first intermediate node X1 is provided, and the source of the third NMOS tube is connected to the first bit line; The source of the sixth PMOS tube is connected to VDD, the gate of the sixth PMOS tube and the gate of the fifth NMOS tube are both connected to the first intermediate node X1, the drain of the sixth PMOS tube is connected to the drain of the fifth NMOS tube, and a second input node IN2 is provided, the second input node IN2 is connected to the gate of the second PMOS tube, and the source of the fifth NMOS tube is connected to the first bit line; The source of the fifth PMOS tube is connected to VDD, the gate of the fifth PMOS tube and the gate of the fourth NMOS tube are both connected to the second node QB, the drain of the fifth PMOS tube is connected to the drain of the fourth NMOS tube, and a second intermediate node X2 is provided, and the source of the fourth NMOS tube is connected to the second bit line; The source of the seventh PMOS tube is connected to VDD, the gate of the seventh PMOS tube and the gate of the sixth NMOS tube are both connected to the second intermediate node X2, the drain of the seventh PMOS tube is connected to the drain of the sixth NMOS tube, and a first input node IN1 is provided, the first input node IN1 is connected to the gate of the first PMOS tube, and the source of the sixth NMOS tube is connected to the second bit line.

4. The sensitive amplifier circuit according to claim 1, characterized in that: An output amplifier circuit is also included, and the output amplifier circuit is used to output a reading according to the voltage of the first node Q or the second node QB when the sensing amplifier circuit is working.

5. The sensitive amplifier circuit according to claim 4, characterized in that: When the output amplifier circuit is configured to output a reading according to the voltage of the first node Q, it directly outputs a reading according to the voltage of the first node Q relative to the voltage of the second node QB; When the output amplifier circuit is configured to output a reading according to the voltage of the second node QB, it outputs an opposite reading according to the voltage of the second node QB relative to the voltage of the first node Q.

6. The sensitive amplifier circuit according to claim 5, characterized in that: The output amplifier circuit includes two PMOS tubes and two NMOS tubes, which are respectively denoted as the eighth PMOS tube and the ninth PMOS tube and the seventh NMOS tube and the eighth NMOS tube. The gate of the ninth PMOS tube and the gate of the seventh NMOS tube are both connected to the second node QB, the drain of the ninth PMOS tube and the drain of the seventh NMOS tube are both connected to the output node QOUT, the source of the ninth PMOS tube is connected to the drain of the eighth PMOS tube, the source of the eighth PMOS tube is connected to VDD, the gate of the eighth PMOS tube is connected to the second enable signal ENB1, the source of the seventh NMOS tube is connected to the drain of the eighth NMOS tube, the source of the eighth NMOS tube is connected to VSS, and the gate of the eighth NMOS tube is connected to the third enable signal EN1, and the second enable signal ENB1 is opposite to the third enable signal EN1.

7. The sense amplifier circuit according to any one of claims 1 to 6, characterized in that: A precharge reset circuit is also included, and the precharge reset circuit is used to pull down the voltage of the first node Q and the second node QB to VSS when the sensing amplifier circuit is not working.

8. The sense amplifier circuit according to claim 7, characterized in that: The pre-charge reset circuit includes a ninth NMOS tube, a tenth NMOS tube and a transmission gate. The drain of the ninth NMOS tube is connected to the first node Q, the source is connected to VSS, and the gate is connected to the first enable signal ENB; The drain of the tenth NMOS tube is connected to the second node QB, the source is connected to VSS, and the gate is connected to the first enable signal ENB; One end of the transmission gate is connected to the first node Q, and the other end is connected to the second node QB. The transmission gate includes an eleventh NMOS tube whose gate is connected to the first enable signal ENB and a tenth PMOS tube whose gate is connected to the fourth enable signal EN. The fourth enable signal EN is opposite to the first enable signal ENB.

9. The sense amplifier circuit according to claim 8, characterized in that: The invention also includes a logic control circuit, which is used to generate an enable control signal to control the operation of the sense amplifier circuit, the output amplifier circuit and the pre-charge reset circuit in the sense amplifier circuit.

10. The sense amplifier circuit according to claim 9, characterized in that: The logic control circuit includes a first inverter, a second inverter, a third inverter and a delay module. The fourth enable signal EN is connected to the input end of the first inverter, and the output end of the first inverter outputs the first enable signal ENB. The fourth enable signal EN is connected to the delay module and then connected to the input end of the second inverter. The output end of the second inverter outputs the second enable signal ENB1. The second enable signal ENB1 is connected to the input end of the third inverter, and the output end of the third inverter outputs the third enable signal EN1.

11. A sensitive amplifier module, characterized in that: A circuit layout of the sense amplifier circuit as claimed in any one of claims 1 to 10 is adopted.

12. The sense amplifier module according to claim 11, characterized in that: The pins of the sense amplifier module include: A first pin, which is used to connect the source electrodes of the third PMOS tube, the fourth PMOS tube, the fifth PMOS tube, the sixth PMOS tube, the seventh PMOS tube, and the eighth PMOS tube to VDD; A second pin is used to connect the source electrodes of the eighth NMOS tube, the ninth NMOS tube, and the tenth NMOS tube to VSS; A third pin, which is used to connect the gate of the tenth PMOS tube and the input of the logic control circuit to a fourth enable signal EN; A fourth pin, used to connect the source electrodes of the first NMOS tube, the third NMOS tube, and the fifth NMOS tube to the first bit line; A fifth pin, used to connect the source electrodes of the second NMOS tube, the fourth NMOS tube, and the sixth NMOS tube to the second bit line; The sixth pin is used to connect the output node QOUT.

13. A low voltage storage unit memory, characterized in that: It includes the sense amplifier circuit described in any one of claims 1 to 10 or the sense amplifier module described in claim 11 or 12.

14. A method of operating a sense amplifier circuit, wherein: The sense amplifier circuit is the sense amplifier circuit according to claim 9 or 10, and the method comprises: Generate a first control signal through a logic control circuit to control the precharge reset circuit in the sense amplifier circuit to be in an operating state, and simultaneously control the sense amplifier circuit and the output amplifier circuit to be in an off state, so as to pull down the first node Q and the second node QB in the sense amplifier circuit to VSS, and transmit the first bit line voltage to the second input node IN2, and transmit the second bit line voltage to the first input node IN1; Generate a second control signal through the logic control circuit to control the sense amplifier circuit in the sense amplifier circuit to be in a working state, and simultaneously control the precharge reset circuit and the output amplifier circuit to be in a closed state, so as to quickly amplify the voltage difference between the first node Q and the second node QB, and automatically shut off the relatively high-voltage bit line voltage input of the first bit line and the second bit line according to the amplification result of the voltage difference between the first node Q and the second node QB, and pull up the voltage of the relatively high-voltage node of the first node Q and the second node QB to VDD; A third control signal is generated by a logic control circuit to control the sensing amplifier circuit and the output amplifier circuit in the sensitive amplifier circuit to be in a working state, and at the same time control the pre-charge reset circuit to be in a closed state, so as to output a reading according to the voltage of the first node Q or the second node QB.

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