Semiconductor chip and method of manufacturing semiconductor chip

Abstract

A semiconductor chip and a method of manufacturing a semiconductor chip are provided. The semiconductor chip may include: a chip substrate; a pattern on an upper surface of the chip substrate; a scribe line on an upper surface of the chip substrate and surrounding the pattern; and a chip redistribution layer in the pattern, the chip redistribution layer extending from the pattern into the scribe line, through the scribe line, and exposed to the outside of the scribe line. According to an example embodiment of the present disclosure, since the chip redistribution layer is exposed to the outside of the scribe line and the outside surface of the scribe line is coplanar with the side surface of the chip substrate, an electrical connection between the semiconductor chip and an external device may be achieved at the side surface of the semiconductor chip.

Description

Technical Field

[0001] Some example embodiments of the inventive concepts relate to the field of semiconductor packaging, and more particularly, to a semiconductor chip and / or a method of manufacturing a semiconductor chip. Background Art

[0002] In semiconductor packages, the semiconductor chip is electrically connected to one surface of the substrate by wire bonding, and the semiconductor package is formed by molding with a molding compound to protect the semiconductor chip and circuit. Balls are planted on the other surface of the substrate and finally the semiconductor package is soldered to the circuit board of the terminal product through the surface mount technology (SMT) process, thereby achieving electrical connection between the semiconductor chip and the external device.

[0003] However, as the demand for miniaturized and higher-performance semiconductor chips continues to increase, miniaturized and higher-performance semiconductor chips having a thinner thickness, a larger bandwidth, and a larger number of input and output (IO) are being studied. Summary of the invention

[0004] Some example embodiments of the inventive concepts provide a miniaturized and higher-performance semiconductor chip having a thinner thickness, a greater bandwidth, and a greater number of input-output (IO) and / or a method of manufacturing the semiconductor chip.

[0005] According to an example embodiment conceived in the present invention, a semiconductor chip may include: a chip substrate; a pattern on an upper surface of the chip substrate; a cutting path on the upper surface of the chip substrate and surrounding the pattern; and a chip redistribution layer, in which the chip redistribution layer extends from the pattern into the cutting path, passes through the cutting path, and is exposed to the outside of the cutting path.

[0006] In some example embodiments, the pattern may cover a portion of an upper surface of the chip substrate, and the dicing street may cover a remaining portion of the upper surface of the chip substrate.

[0007] In some example embodiments, inner side surfaces of the scribe lines may contact the patterns, and outer side surfaces of the scribe lines may be coplanar with side surfaces of the chip substrate.

[0008] In some example embodiments, the chip redistribution layer may extend from the pattern into the dicing street in a direction parallel to the upper surface of the chip substrate.

[0009] In some example embodiments, an exposed surface of the chip redistribution layer exposed to the outside of the scribe line may be coplanar with an outer side surface of the scribe line.

[0010] In some example embodiments, the semiconductor chip may be included in a semiconductor package.

[0011] In some example embodiments, the semiconductor chip may further include a through-mold via extending along an outer side surface of the scribe line and a side surface of the chip substrate and electrically connected to an exposed surface of the chip redistribution layer.

[0012] In some example embodiments, the semiconductor chip may further include: a chip molding layer covering an upper surface of the pattern, an upper surface of the cutting path, and an outer side surface of a through-molded via, wherein the through-molded via may pass through the chip molding layer to expose to the outside of both a first surface of the semiconductor chip serving as an active surface and a second surface of the semiconductor chip, the second surface of the semiconductor chip being opposite to the first surface of the semiconductor chip.

[0013] In some example embodiments, a semiconductor package may include: a packaging substrate including a first surface and a second surface opposite to the first surface, wherein an active surface of the semiconductor chip faces upward on the first surface of the packaging substrate, and a chip redistribution layer of the semiconductor chip is electrically connected to the packaging substrate through a through-molded via; a packaging molding layer on the first surface of the packaging substrate and covering the semiconductor chip; and external connection terminals on the second surface of the packaging substrate.

[0014] In some example embodiments, a semiconductor package may include: a packaging redistribution layer including a first surface and a second surface opposite to the first surface, wherein an active surface of the semiconductor chip faces upward on the first surface of the packaging redistribution layer, and the chip redistribution layer of the semiconductor chip is electrically connected to the packaging redistribution layer through a through-molded via; a packaging molding layer on the first surface of the packaging redistribution layer and covering the semiconductor chip; and external connection terminals on the second surface of the packaging redistribution layer.

[0015] In some example embodiments, a semiconductor package may include: a packaging redistribution layer including a first surface and a second surface opposite to the first surface, wherein an active surface of the semiconductor chip faces downward on the first surface of the packaging redistribution layer, and the chip redistribution layer of the semiconductor chip is electrically connected to the packaging redistribution layer through a through-molded via; and an external connection terminal disposed on the second surface of the packaging redistribution layer.

[0016] In some example embodiments, the semiconductor chip may be a first semiconductor chip, the semiconductor package may further include: a second semiconductor chip vertically stacked on the first semiconductor chip, and the first and second semiconductor chips may be electrically connected to each other through through-mold vias.

[0017] According to an example embodiment of the present invention, a method for manufacturing a semiconductor chip may include: forming a plurality of patterns, a plurality of cutting lanes, and a plurality of chip redistribution layers on a semiconductor mother substrate, so that the plurality of patterns are spaced apart by the plurality of cutting lanes, and the plurality of chip redistribution layers extend from corresponding patterns in the plurality of patterns to corresponding cutting lanes in the plurality of cutting lanes, respectively; performing a first cutting operation on the semiconductor mother substrate along the plurality of cutting lanes to form a first groove in each of the plurality of cutting lanes, the first groove extending into the semiconductor mother substrate and having a first depth and a first width, so that each of the plurality of chip redistribution layers is exposed through the first groove; performing a first molding operation to form a chip molding layer filling the first groove; forming a hole penetrating the chip molding layer along an inner surface of the filled first groove to expose each of the plurality of chip redistribution layers through the hole; filling the hole with a conductive material to form a plurality of through-molding vias electrically connected to the plurality of chip redistribution layers, respectively; performing a second cutting operation on the semiconductor mother substrate along the filled first groove to form a plurality of semiconductor chips respectively including the plurality of patterns.

[0018] In some example embodiments, the plurality of scribe lines may include a plurality of first scribe lines extending in a first direction and a plurality of second scribe lines extending in a second direction intersecting the first direction.

[0019] In some example embodiments, each of the plurality of patterns may be spaced apart from an adjacent pattern of the plurality of patterns by two of the plurality of first scribe lines and two of the plurality of second scribe lines.

[0020] In some example embodiments, the plurality of chip redistribution layers may include: a plurality of first chip redistribution layers, each extending from a corresponding pattern among the plurality of patterns to a corresponding first cutting street among the plurality of first cutting streets; and a plurality of second chip redistribution layers, each extending from a corresponding pattern among the plurality of patterns to a corresponding second cutting street among the plurality of second cutting streets.

[0021] In some example embodiments, the first depth may be greater than a depth of each of the plurality of scribe lines, and the first width may be smaller than a width of each of the plurality of scribe lines.

[0022] In some example embodiments, each of the plurality of patterns may be spaced apart from the first groove by an uncut portion of each of the plurality of scribe lines.

[0023] In some example embodiments, performing the first molding operation may further include forming a chip molding layer to cover upper surfaces of the plurality of patterns and upper surfaces of uncut portions of the plurality of scribe lines.

[0024] In some example embodiments, forming the hole may include forming the hole on opposite inner side surfaces of the first groove in a cross-sectional view and respectively exposing chip redistribution layers facing each other across the first groove.

[0025] In some example embodiments, the step of performing a second cutting operation includes: performing a thinning operation on the semiconductor mother substrate to expose the multiple through-molded vias; disposing the thinned semiconductor mother substrate on a first carrier; and performing a second cutting operation to form a second groove having a second width in the filled first groove, so that the multiple semiconductor chips are separated from each other by the second groove.

[0026] In some example embodiments, the second width may be smaller than the first width, and the second groove may not extend into the first carrier plate.

[0027] In some example embodiments, the first carrier may include a transparent carrier and a photosensitive adhesive film on the transparent carrier, and the semiconductor mother substrate may be attached to the photosensitive adhesive film.

[0028] In some example embodiments, after the step of performing the second cutting operation, the method may further include: picking up the plurality of semiconductor chips from the first carrier and mounting them onto the first surface of the packaging substrate; performing a second molding operation to form a packaging molding layer covering the plurality of semiconductor chips on the first surface of the packaging substrate; forming external connection terminals on a second surface of the packaging substrate opposite to the first surface; and performing a third cutting operation to form a plurality of semiconductor packages respectively including the plurality of semiconductor chips.

[0029] In some example embodiments, the picking up and mounting may include forming a plurality of semiconductor chip stacks spaced apart from each other on the first surface of the package substrate, and performing the third cutting operation may form a plurality of semiconductor packages respectively including the plurality of semiconductor chip stacks.

[0030] In some example embodiments, after the step of filling the holes with a conductive material, the method further includes: performing a thinning operation on the semiconductor mother substrate to expose the plurality of through-molded vias and obtaining a first semiconductor mother substrate; vertically stacking a second semiconductor mother substrate identical to the first semiconductor mother substrate on the first semiconductor mother substrate, so that the first semiconductor mother substrate and the second semiconductor mother substrate are electrically connected to each other through corresponding through-molded vias among the plurality of through-molded vias to form a semiconductor mother substrate combination; and disposing the semiconductor mother substrate combination on a first carrier.

[0031] In some example embodiments, the method may further include: performing a second cutting operation on the semiconductor mother substrate combination along the filled first groove of each of the first semiconductor mother substrate and the second semiconductor mother substrate to form a plurality of semiconductor chip stacks separated from each other; picking up the plurality of semiconductor chip stacks from the first carrier and mounting them on the first surface of the packaging substrate; performing a second molding operation to form a packaging molding layer covering the plurality of semiconductor chip stacks on the first surface of the packaging substrate; forming external connection terminals on a second surface of the packaging substrate opposite to the first surface; and performing a third cutting operation to form a plurality of semiconductor packages respectively including the plurality of semiconductor chip stacks.

[0032] In some example embodiments, the method may further include: performing a second cutting operation on the semiconductor mother substrate combination along the filled first groove of each of the first semiconductor mother substrate and the second semiconductor mother substrate to form a plurality of semiconductor chip stacks separated from each other; picking up the plurality of semiconductor chip stacks from the first carrier and mounting them on the first surface of the second carrier; performing a second molding operation to form a packaging molding layer covering the plurality of semiconductor chip stacks on the first surface of the second carrier; removing the second carrier to expose the plurality of semiconductor chip stacks; forming a packaging redistribution layer on the exposed surfaces of the plurality of semiconductor chip stacks; forming external connection terminals on the packaging redistribution layer; performing a third cutting operation to form a plurality of semiconductor packages respectively including the plurality of semiconductor chip stacks.

[0033] In some example embodiments, the method may further include: forming a packaging redistribution layer on a second surface of the semiconductor mother substrate combination opposite to the first surface of the semiconductor mother substrate combination mounted on the first carrier; forming external connection terminals on the packaging redistribution layer; removing the first carrier to expose the first surface of the semiconductor mother substrate combination; forming a protective layer on the first surface of the semiconductor mother substrate combination; performing a second cutting operation on the semiconductor mother substrate combination along the filled first groove of each of the first semiconductor mother substrate and the second semiconductor mother substrate to form a plurality of semiconductor packages respectively including a plurality of semiconductor chip stacks.

[0034] According to some example embodiments of the present disclosure, because the chip redistribution layer is exposed to the outside of the cutting street and the outer side surface of the cutting street is coplanar with the side surface of the chip substrate, an electrical connection between the semiconductor chip and an external device can be achieved at the side surface of the semiconductor chip, thereby reducing the thickness of the package including the semiconductor chip, and also increasing the number of input and output (IO) of the semiconductor chip to improve performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The above and / or other aspects of the inventive concept will become clearer and more easily understood through the following detailed description in conjunction with the accompanying drawings.

[0036] Figure 1 is a diagram illustrating a semiconductor chip according to an example embodiment of the present disclosure.

[0037] Figure 2A and Figure 2B is a diagram illustrating a semiconductor chip according to an example embodiment of the present disclosure.

[0038] Figure 3 is a diagram illustrating a semiconductor package according to an example embodiment of the present disclosure.

[0039] Figure 4 is a diagram illustrating a semiconductor package according to an example embodiment of the present disclosure.

[0040] Figure 5 is a diagram illustrating a semiconductor package according to an example embodiment of the present disclosure.

[0041] Figure 6 is a flowchart illustrating a method of manufacturing a semiconductor chip according to an example embodiment of the present disclosure.

[0042] 7A to 7C is a diagram showing an exemplary embodiment according to the present disclosure Figure 6 Process diagram of the method.

[0043] Figure 8 is a flow chart illustrating intermediate steps of a method of manufacturing a semiconductor chip according to an example embodiment of the present disclosure.

[0044] Fig. 9 is a flowchart illustrating a method of manufacturing a package of a semiconductor chip according to an example embodiment of the present disclosure.

[0045] Fig.10 is a flowchart illustrating a method of manufacturing a semiconductor chip according to an example embodiment of the present disclosure.

[0046] Fig.11 is a diagram showing an exemplary embodiment according to the present disclosure Fig.10 and Fig.12 Process diagram of the method.

[0047] Fig.12 is a flowchart illustrating a method of manufacturing a package of a semiconductor chip according to an example embodiment of the present disclosure.

[0048] Fig.13 is a flowchart illustrating a method of manufacturing a package of a semiconductor chip according to an example embodiment of the present disclosure.

[0049] Fig.14 is a diagram showing an exemplary embodiment according to the present disclosure Fig.13 Process diagram of the method.

[0050] Fig.15 is a flowchart illustrating a method of manufacturing a semiconductor chip and a package thereof according to an example embodiment of the present disclosure.

[0051] Fig.16 is a diagram showing an exemplary embodiment according to the present disclosure Fig.15 Process diagram of the method.

[0052] Throughout the drawings and specific example embodiments, unless otherwise described or provided, the same reference numerals will be understood to refer to the same elements, features, and structures. The drawings may not be to scale, and the relative sizes, proportions, and depictions of the elements in the drawings may be exaggerated for clarity, illustration, and convenience. DETAILED DESCRIPTION

[0053] Hereinafter, some exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily practice the inventive concept. However, the inventive concept can be implemented in various different forms and is not limited to the exemplary embodiments described herein.

[0054] In the drawings, the same reference numerals always refer to the same components. Although different drawings illustrate various example embodiments, these drawings are not necessarily intended to be mutually exclusive. On the contrary, as will be seen in the context of the detailed description below, when the drawings and their descriptions are considered as a whole, certain features depicted and described in different drawings may be combined with other features from other drawings to produce various example embodiments. In the description of the drawings, when the same or similar components are described with reference to previous drawings, the same or similar components may not be described or may only be briefly mentioned in multiple drawings.

[0055] In addition, the size and thickness of each component shown in the drawings are arbitrarily shown for the convenience of description, and therefore the inventive concept is not necessarily limited to the contents shown in the drawings. The thickness is exaggerated in the drawings to clearly show several layers and regions. In addition, for the convenience of description, the thickness of some layers or regions is exaggerated in the drawings.

[0056] In addition, when an element (such as a layer, film, region, or substrate) is referred to as being "on" or "over" another element, the element may be "directly on" the other element or may have other elements disposed therebetween. On the other hand, when an element is referred to as being "directly on" another element, there is no third element or other elements disposed therebetween. In addition, when an element is referred to as being "on" or "over" a reference element, the element may be disposed below the reference element when the example embodiments are rotated to a different orientation than that shown in the figures. As such, the use of the above terms may not be with reference to the direction of gravity, but instead may be specific to the figures being described, and may not necessarily be "on" or "over" the reference element in the opposite direction of gravity.

[0057] In addition, throughout the specification, when an element "includes" another component, unless explicitly described to the contrary, it will be understood that the element may also include a third component rather than excluding the third component. As used herein, unless the context clearly indicates otherwise, the singular form is intended to also include the plural form. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items and may be abbreviated as " / ".

[0058] Figure 1 is a diagram illustrating a semiconductor chip 10 according to an example embodiment of the present disclosure.

[0059] Reference Figure 1 The semiconductor chip 10 may include: a chip substrate 11 , a pattern 12 , a dicing street 13 and a chip redistribution layer (RDL) 14 .

[0060] The chip substrate 11 may include a semiconductor material (such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor). For example, the group IV semiconductor may include silicon, germanium, or silicon germanium. The chip substrate 11 may be configured as a silicon substrate, a silicon on insulator (SOI) substrate, a germanium substrate, a germanium on insulator (GOI) substrate, a silicon germanium substrate, or a substrate including an epitaxial layer. The chip substrate 11 may include an upper surface and a lower surface that are opposite to each other in a vertical direction.

[0061] The pattern 12 may be disposed on the upper surface of the chip substrate 11. For example, the pattern 12 may be configured to extend in parallel on the upper surface of the chip substrate 11. In an exemplary embodiment, the pattern 12 may cover a portion of the upper surface of the chip substrate 11. For example, the pattern 12 may be configured to extend in parallel on the central portion of the upper surface of the chip substrate 11 and cover the central portion of the upper surface of the chip substrate 11. The pattern 12 may be configured to implement the function of the semiconductor chip 10 and may be formed by performing a patterning process on the upper surface of the chip substrate 11. It should be understood that the function of the semiconductor chip 10 implemented by the pattern 12 may include any function, and the exemplary embodiments of the present disclosure are not limited thereto.

[0062] The dicing road 13 may be disposed on the upper surface of the chip substrate 11, may be located at the edge of the upper surface of the chip substrate 11, and may surround the pattern 12. For example, the dicing road 13 may be configured to be spaced apart from the upper surface of the chip substrate 11, extend in parallel above the upper surface of the chip substrate 11, and surround at least a portion of the side surface of the pattern 12. In one embodiment, the dicing road 13 may cover the remaining portion of the upper surface of the chip substrate 11. For example, the dicing road 13 may be configured to extend in parallel on a portion of the upper surface of the chip substrate 11 that is not covered by the pattern 12 (hereinafter, referred to as a peripheral portion), and may cover the peripheral portion of the upper surface of the chip substrate 11. In one embodiment, the inner side surface of the dicing road 13 may contact the pattern 12, and the outer side surface of the dicing road 13 may be coplanar with the side surface of the chip substrate 11. The chip redistribution layer 14 may be disposed in the pattern 12, extending from the pattern 12 into the scribe line 13 and passing through the scribe line 13 to be exposed to the outside of the scribe line 13. The chip redistribution layer 14 may be a metal layer for redistributing electrical connections and may include a plurality of wiring layers and a plurality of vias. In an example embodiment, the chip redistribution layer 14 may extend from the pattern 12 into the scribe line 13 in a direction parallel to the upper surface of the chip substrate 11. For example, the chip redistribution layer 14 may extend in parallel above the upper surface of the chip substrate 11 and be spaced apart from the upper surface of the chip substrate 11 by a desired (or optionally, predetermined) distance and the pattern 12 is placed between the lower surface of the chip redistribution layer 14 and the upper surface of the chip substrate 11. In an example embodiment, the exposed surface of the chip redistribution layer 14 exposed to the outside of the scribe line 13 may be coplanar with the outer side surface of the scribe line 13.

[0063] According to an example embodiment of the present disclosure, because the chip redistribution layer 14 is exposed to the outside of the dicing street 13 and the outer side surface of the dicing street 13 is coplanar with the side surface of the chip substrate 11, an electrical connection between the semiconductor chip 10 and an external device can be achieved at the side surface of the semiconductor chip 10, so that the thickness of the package including the semiconductor chip 10 can be reduced, and the bandwidth and input-output (IO) number of the semiconductor chip 10 can also be increased to improve performance.

[0064] Figure 2A and Figure 2B is a diagram illustrating a semiconductor chip 20 according to an example embodiment of the present disclosure.

[0065] Reference Figure 2A and Figure 2B , the semiconductor chip 20 may include: a chip substrate 21, a pattern 22, a dicing road 23, a chip redistribution layer 24, a through mold via (TMV) 25 and a chip molding layer 26. In addition to the TMV 25 and the chip molding layer 26, refer to Figure 2A and Figure 2B The chip substrate 21, pattern 22, cutting road 23 and chip redistribution layer 24 of the semiconductor chip 20 can be respectively Figure 1 The chip substrate 11 , the pattern 12 , the dicing street 13 and the chip redistribution layer 14 of the semiconductor chip 10 are the same or substantially similar, so their repeated description will be omitted.

[0066] Reference Figure 2A , the through-molded via 25 may extend along the outer side surface of the scribe line 23 and the side surface of the chip substrate 21, and may be electrically connected to the exposed surface of the chip redistribution layer 24. The chip molding layer 26 may cover the upper surface of the pattern 22, the upper surface of the scribe line 23, and the outer side surface of the through-molded via 25. In one example, the chip molding layer 26 may include, but is not limited to, for example, epoxy molding compound (EMC). In an example embodiment, the through-molded via 25 may pass through the chip molding layer 26 to be exposed to the outside of both the first surface of the semiconductor chip 20 as an active surface and the second surface of the semiconductor chip 20. The second surface of the semiconductor chip 20 is opposite to the first surface of the semiconductor chip 20.

[0067] Reference Figure 2B , the through-molded vias 25 may be arranged in plural along the periphery of the dicing lane 23. When viewed in a plan view, the dicing lane 23 may have the same shape as the chip substrate 21. For example, the dicing lane 23 may have a rectangular shape extending along the peripheral portion of the chip substrate 21. The through-molded vias 25 may be arranged along each side of the rectangular shape at uniform intervals. For example, three through-molded vias 25 may be arranged on each side of the rectangular shape. However, the exemplary embodiments of the present disclosure are not limited thereto.

[0068] According to an example embodiment of the present disclosure, because the chip redistribution layer 24 is electrically connected to the through-molded vias 25 extending along the outer surface of the cutting street 23 and the side surface of the chip substrate 21, electrical connection between the semiconductor chip 20 and an external device can be achieved at the side surface of the semiconductor chip 20, thereby reducing the thickness of the package including the semiconductor chip 20, and also increasing the bandwidth and IO number of the semiconductor chip 20 to improve performance.

[0069] Figure 3 is a diagram illustrating a semiconductor package 100 according to an example embodiment of the present disclosure.

[0070] Reference Figure 3 , the semiconductor package 100 may include: a package substrate 110 , a semiconductor chip 120 , a package mold layer 130 , and external connection terminals 140 .

[0071] The package substrate 110 may include a first surface and a second surface opposite to the first surface. In one example, the package substrate 110 may be a multilayer printed circuit board. The first surface and the second surface of the package substrate 110 may be provided with conductive contacts, and the conductive contacts on the first surface of the package substrate 110 may be electrically connected to the conductive contacts on the second surface of the package substrate 110.

[0072] The semiconductor chip 120 may be included in the semiconductor package 100. The semiconductor chip 120 may have an active surface disposed on or facing upward on the first surface of the package substrate 110. The semiconductor chip 120 may be, for example, Figure 1 The semiconductor chip 10 or the reference Figure 2A and Figure 2B The semiconductor chip 20. The chip redistribution layer of the semiconductor chip 120 may be electrically connected to the package substrate 110 through the through-mold via. For example, the chip redistribution layer of the semiconductor chip 120 may be electrically connected to the conductive contact on the first surface of the package substrate 110 through the through-mold via.

[0073] In one example embodiment, the semiconductor package 100 may include one semiconductor chip (e.g., semiconductor chip 120). In another example, the semiconductor chip 120 may include a first semiconductor chip and a second semiconductor chip. The second semiconductor chip may be vertically stacked on the first semiconductor chip, and the first semiconductor chip and the second semiconductor chip may be electrically connected to each other through corresponding through-molding vias. However, the example embodiments of the present disclosure are not limited thereto. For example, the semiconductor package 100 may include three or more semiconductor chips.

[0074] The encapsulation molding layer 130 may be on the first surface of the encapsulation substrate 110 and cover the semiconductor chip 120. In one example, the encapsulation molding layer 130 and the chip molding layer of the semiconductor chip 120 may include the same or different materials.

[0075] The external connection terminals 140 may be disposed on the second surface of the package substrate 110. For example, the external connection terminals 140 may be disposed on the conductive contacts of the second surface of the package substrate 110, and may be electrically connected to the through-molded vias of the semiconductor chip 120 disposed on the conductive contacts of the first surface of the package substrate 110 through the conductive contacts of the second surface of the package substrate 110. In one example, the external connection terminals 140 may include pins in the form of solder balls.

[0076] According to an example embodiment of the present disclosure, because the chip redistribution layer of the semiconductor chip is electrically connected to the through-molded vias extending along the outer surface of the cutting road and the side surface of the chip base, and is electrically connected to the external device through the packaging substrate 110, the electrical connection between the semiconductor chip and the external device can be achieved at the side surface of the semiconductor chip, so that the thickness of the semiconductor package 100 can be reduced, and the bandwidth and IO number of the semiconductor package 100 can also be increased to improve performance.

[0077] Figure 4 is a diagram illustrating a semiconductor package 200 according to an example embodiment of the present disclosure.

[0078] Reference Figure 4 , the semiconductor package 200 may include: a package redistribution layer 210, a semiconductor chip 220, a package molding layer 230 and an external connection terminal 240. In addition to the package redistribution layer 210, refer to Figure 4 The semiconductor chip 220, the encapsulation molding layer 230 and the external connection terminal 240 can be respectively Figure 3 The semiconductor chip 120 , the encapsulation mold layer 130 , and the external connection terminals 140 are substantially the same or similar, and thus their repeated description will be omitted.

[0079] The package redistribution layer 210 may include a first surface and a second surface opposite to the first surface. In one example, the package redistribution layer 210 may include a plurality of wiring layers located at different heights and a plurality of vias electrically connecting the plurality of wiring layers to each other. The first surface and the second surface of the package redistribution layer 210 may be respectively provided with corresponding wiring layers of the plurality of wiring layers, and the wiring layer on the first surface of the package redistribution layer 210 may be electrically connected to the wiring layer on the second surface of the package redistribution layer 210.

[0080] The semiconductor chip 220 may be included in the semiconductor package 200. The semiconductor chip 220 may have an active surface disposed on or facing upward on the first surface of the package redistribution layer 210. The semiconductor chip 220 may be, for example, Figure 1 The semiconductor chip 10 or the reference Figure 2A and Figure 2B The semiconductor chip 20. The chip redistribution layer of the semiconductor chip 220 may be electrically connected to the package redistribution layer 210 through a through-mold via. For example, the chip redistribution layer of the semiconductor chip 220 may be electrically connected to the wiring layer on the first surface of the package redistribution layer 210 through a through-mold via.

[0081] In one example embodiment, the semiconductor package 200 may include one semiconductor chip (e.g., semiconductor chip 220). In another example, the semiconductor chip 220 may include a first semiconductor chip and a second semiconductor chip. The second semiconductor chip may be vertically stacked on the first semiconductor chip, and the first semiconductor chip and the second semiconductor chip may be electrically connected to each other through corresponding through-molding vias. However, the example embodiments of the present disclosure are not limited thereto. For example, the semiconductor package 100 may include three or more semiconductor chips.

[0082] The encapsulation molding layer 230 may be on the first surface of the encapsulation redistribution layer 210 and cover the semiconductor chip 220. In one example, the encapsulation molding layer 230 and the chip molding layer of the semiconductor chip 220 may include the same or different materials.

[0083] The external connection terminals 240 may be disposed on the second surface of the package redistribution layer 210. For example, the external connection terminals 240 may be disposed on the wiring layer of the second surface of the package redistribution layer 210, and may be electrically connected to the through-mold vias of the semiconductor chip 220 disposed on the wiring layer of the first surface of the package redistribution layer 210 through the wiring layer of the second surface of the package redistribution layer 210. In one example, the external connection terminals 240 may include pins in the form of solder balls.

[0084] According to an example embodiment of the present disclosure, because the chip redistribution layer of the semiconductor chip is electrically connected to the through-molded vias extending along the outer surface of the cutting road and the side surface of the chip substrate, and is electrically connected to the external device through the package redistribution layer 210, the electrical connection between the semiconductor chip and the external device can be achieved at the side surface of the semiconductor chip, so that the thickness of the semiconductor package 200 can be reduced, and the bandwidth and IO number of the semiconductor package 200 can also be increased to improve performance.

[0085] Figure 5 is a diagram illustrating a semiconductor package 300 according to an example embodiment of the present disclosure.

[0086] Reference Figure 5 , the semiconductor package 300 may include: a package redistribution layer 310, a semiconductor chip 320, a package molding layer and an external connection terminal 330. In addition to the semiconductor chip 320, Figure 5 The package redistribution layer 310, the package molding layer and the external connection terminal 330 can be respectively Figure 4 The encapsulation redistribution layer 210 , the encapsulation molding layer 230 , and the external connection terminals 240 are identical or substantially similar, and thus their repeated description will be omitted.

[0087] The semiconductor chip 320 may be included in the semiconductor package 300. Figure 4 Unlike the semiconductor chip 220, the semiconductor chip 320 may be disposed on the first surface of the package redistribution layer with the active surface facing downward. The semiconductor chip 320 may be, for example, Figure 1 The semiconductor chip 10 or the reference Figure 2A and Figure 2B The semiconductor chip 20. The chip redistribution layer of the semiconductor chip 320 may be electrically connected to the package redistribution layer 310 through a through-mold via. For example, the chip redistribution layer of the semiconductor chip 320 may be electrically connected to the wiring layer on the first surface of the package redistribution layer 310 through a through-mold via.

[0088] In one example embodiment, the semiconductor package 300 may include one semiconductor chip (e.g., semiconductor chip 320). In another example, the semiconductor chip 320 may include a first semiconductor chip and a second semiconductor chip. The second semiconductor chip may be vertically stacked on the first semiconductor chip, and the first semiconductor chip and the second semiconductor chip may be electrically connected to each other through corresponding through-molding vias. However, the example embodiments of the present disclosure are not limited thereto. For example, the semiconductor package 100 may include three or more semiconductor chips.

[0089] In an example embodiment, the semiconductor package 300 may further include a protection layer 340. The protection layer 340 may be disposed on a second surface (eg, an upper surface) of the semiconductor chip 320, which is an uppermost surface.

[0090] According to an example embodiment of the present disclosure, because the chip redistribution layer of the semiconductor chip is electrically connected to the through-molded vias extending along the outer surface of the cutting road and the side surface of the chip substrate, and is electrically connected to the external device through the package redistribution layer 310, the electrical connection between the semiconductor chip and the external device can be achieved at the side surface of the semiconductor chip, so that the thickness of the semiconductor package 300 can be reduced, and the bandwidth and IO number of the semiconductor package 300 can also be increased to improve performance.

[0091] Figure 6 is a flowchart illustrating a method of manufacturing a semiconductor chip according to an example embodiment of the present disclosure. 7A to 7C is a diagram showing an exemplary embodiment according to the present disclosure Figure 6 Process diagram of the method.

[0092] Reference Figure 6 and 7A to 7C ,by Figure 3 Taking the semiconductor package 100 as an example, the method for manufacturing a semiconductor chip may include steps S100 to S600 .

[0093] In step S100 and process I-1, a plurality of patterns, a plurality of scribe lines, and a plurality of chip redistribution layers respectively corresponding to a plurality of semiconductor chips may be formed on a semiconductor mother substrate, so that the plurality of patterns may be separated by the plurality of scribe lines, and the plurality of chip redistribution layers may extend from corresponding patterns in the plurality of patterns to corresponding scribe lines in the plurality of scribe lines, respectively. Figure 6 and 7A to 7C The semiconductor mother substrate may be cut or diced into separate semiconductor substrates each corresponding to a semiconductor chip after performing a dicing process (eg, a sawing process). The semiconductor substrate may be, for example, Figure 1 The chip substrate 11 or reference Figure 2A and Figure 2B The chip substrate 21. In one example, referring to Figure 6 and 7A to 7C The plurality of patterns may include, for example, reference Figure 1 The pattern 12 or reference Figure 2A and Figure 2B The pattern 22. In one example, referring to Figure 6 and 7A to 7C The plurality of cutting paths may include, for example, Figure 1 The cutting path 13 or reference Figure 2A and Figure 2B The cutting path 23. In one example, referring to Figure 6 and 7A to 7C The plurality of chip redistribution layers may include, for example, Figure 1 The chip redistribution layer 14 or the reference Figure 2A and Figure 2B The chip redistribution layer 24.

[0094] In an exemplary embodiment, the plurality of cutting lanes may include a plurality of first cutting lanes extending along a first direction and a plurality of second cutting lanes extending along a second direction intersecting the first direction. The semiconductor mother substrate may be a wafer, for example, a 4-inch, 6-inch, 8-inch or 12-inch silicon wafer. The first direction and the second direction may intersect in a plane parallel to the upper surface of the semiconductor mother substrate. In this case, in an exemplary embodiment, each of the plurality of patterns may be separated from adjacent patterns in the plurality of patterns by two of the plurality of first cutting lanes and two of the plurality of second cutting lanes. In an exemplary embodiment, the plurality of chip redistribution layers may include a plurality of first chip redistribution layers extending from each of the plurality of patterns to a corresponding first cutting lane in the plurality of first cutting lanes and a plurality of second chip redistribution layers extending from each of the plurality of patterns to a corresponding second cutting lane in the plurality of second cutting lanes.

[0095] In step S200 and processes I-2 and I-3, a first cutting operation may be performed on the semiconductor mother substrate along the plurality of cutting lanes to form a first groove T1 in each of the plurality of cutting lanes. The first groove T1 may extend into the semiconductor mother substrate and may have a first depth and a first width, so that each of the plurality of chip redistribution layers may be exposed through the first groove T1. In an example embodiment, the first depth may be greater than the depth of each of the plurality of cutting lanes, and the first width may be less than the width of each of the plurality of cutting lanes. In an example embodiment, each of the plurality of patterns may be spaced apart from the first groove T1 by an uncut portion in each of the plurality of cutting lanes.

[0096] In step S300 and process I-4, a first molding operation may be performed to form a chip molding layer filling the first groove T1. Figure 6 and 7A to 7C The chip molding layer may be, for example, Figure 2A and Figure 2B The chip molding layer 26. In an example embodiment, step S300 may include forming a chip molding layer to cover upper surfaces of the plurality of patterns and upper surfaces of uncut portions of the plurality of scribe lines.

[0097] In step S400 and process I-5, a hole H penetrating the chip molding layer may be formed along the inner side surface of the filled first groove T1 to expose each of the plurality of chip redistribution layers through the hole H. In an example embodiment, the hole H may be formed on opposite inner side surfaces of the first groove T1 in a cross-sectional view and respectively expose the chip redistribution layers facing each other across the first groove T1.

[0098] In step S500 and process I-6, the hole H may be filled with a conductive material to form a plurality of through-mold vias electrically connected to the plurality of chip redistribution layers, respectively. Figure 6 and 7A to 7C The plurality of through-mold vias may include, for example, Figure 2A and Figure 2B The through-molding via 25. In one example, the conductive material may include metal. In one example, the hole H may be filled by a deposition process.

[0099] In step S600 and processes I-7 to I-8, a second cutting operation may be performed on the semiconductor mother substrate along the filled first groove T1 to form a plurality of semiconductor chips including a plurality of patterns. In one example, the formed plurality of semiconductor chips may include, for example, Figure 1 The semiconductor chip 10 or the reference Figure 2A and Figure 2B The semiconductor chip 20.

[0100] According to example embodiments of the present disclosure, since the chip redistribution layer is exposed to the outside of the cutting street and the outer side surface of the cutting street is coplanar with the side surface of the chip substrate, electrical connection between the semiconductor chip and an external device can be achieved at the side surface of the semiconductor chip, thereby reducing the thickness of the package including the semiconductor chip, and also increasing the bandwidth and input-output (IO) number of the semiconductor chip to improve performance.

[0101] Figure 8 is a flow chart illustrating intermediate steps of a method of manufacturing a semiconductor chip according to an example embodiment of the present disclosure.

[0102] and Figure 6 Refer to 7A to 7C and Figure 8 In an example embodiment, step S600 may include steps S611 to S613.

[0103] In step S611 and process I-7, a thinning operation may be performed on the semiconductor mother substrate to expose a plurality of through-molding vias. In step S612, the thinned semiconductor mother substrate may be disposed on the first carrier P1. In an exemplary embodiment, the first carrier P1 may include a transparent carrier A and a photosensitive adhesive film B located on the transparent carrier A, and the semiconductor mother substrate may be pasted onto the photosensitive adhesive film B. In step S613 and process I-8, a second cutting operation may be performed to form a second groove T2 having a second width in the filled first groove T1, so that a plurality of semiconductor chips may be spaced apart from each other by the second groove T2. In an exemplary embodiment, the second width may be less than the first width, and the second groove T2 may not extend into the first carrier P1. The second cutting operation may cut or cut the semiconductor mother substrate into a plurality of semiconductor substrates to form a plurality of semiconductor chips.

[0104] Fig. 9is a flowchart illustrating a method of manufacturing a package of a semiconductor chip according to an example embodiment of the present disclosure.

[0105] and Figure 6 Refer to 7A to 7C and Fig. 9 In one example embodiment, Figure 8 After step S613 shown in FIG. 1 , steps S710 to S740 may be performed.

[0106] In step S710 and process I-9, a plurality of semiconductor chips may be picked up from the first carrier P1 and mounted on the first surface of the package substrate. In an example embodiment, step S710 may include forming a plurality of semiconductor chip stacks STK separated from each other on the first surface of the package substrate. In an example, each of the plurality of semiconductor chip stacks STK may include a plurality of semiconductor chips stacked on each other. Figures 9 to 16 Example embodiments of forming the semiconductor chip stack body STK are described in detail.

[0107] In step S720 and process I-10, a second molding operation may be performed to form a packaging molding layer covering the plurality of semiconductor chips on the first surface of the packaging substrate. 7A to 7C and Fig. 9 The encapsulation molding layer may include, for example, Figure 3 The encapsulation molding layer 130. In step S730 and process I-10, an external connection terminal may be formed on a second surface of the encapsulation substrate opposite to the first surface. 7A to 7C and Fig. 9 The external connection terminals may include, for example, Figure 3 The external connection terminals 140. In step S740 and process I-10, a third cutting operation may be performed to form a plurality of semiconductor packages each including a plurality of semiconductor chips.

[0108] In one example, according to Fig. 9 The flowchart of manufacturing multiple semiconductor packages may include, for example Figure 3 . According to the exemplary embodiment of the present disclosure, since the chip redistribution layer is electrically connected to the through-mold via extending along the outer side surface of the dicing street and the side surface of the chip substrate, and is electrically connected to the external device through the package substrate 110, the electrical connection between the semiconductor chip and the external device can be achieved at the side surface of the semiconductor chip, so that the thickness of the semiconductor package can be reduced, and the bandwidth and IO number of the semiconductor package can also be increased to improve the performance.

[0109] In one example embodiment, after performing the third cutting operation, a plurality of semiconductor packages each including a plurality of semiconductor chip stack bodies STK may be formed. Figures 10 to 16 Example embodiments of forming a semiconductor chip package including a plurality of semiconductor chip stacks STK are described in detail.

[0110] Fig.10 is a flowchart illustrating a method of manufacturing a semiconductor chip according to an example embodiment of the present disclosure. Fig.11 is a diagram showing an exemplary embodiment according to the present disclosure Fig.10 and Fig.12 Process diagram of the method.

[0111] and Figure 6 and 7A to 7C Refer to Fig.10 and Fig.11 In one example embodiment, Figure 6 After step S500 shown in FIG. 1 , steps S810 to S830 may be performed.

[0112] In step S810 and process I-7, a semiconductor mother substrate may be thinned to expose a plurality of through-molding vias, thereby obtaining a first semiconductor mother substrate. In step S820 and process II-8, a second semiconductor mother substrate identical to the first semiconductor mother substrate may be vertically stacked on the first semiconductor mother substrate, so that the first semiconductor mother substrate and the second semiconductor mother substrate may be electrically connected to each other through corresponding through-molding vias to form a semiconductor mother substrate combination. In step S830 and process II-9, the semiconductor mother substrate combination may be disposed on a first carrier P1.

[0113] Fig.12 is a flowchart illustrating a method of manufacturing a package of a semiconductor chip according to an example embodiment of the present disclosure.

[0114] and Fig.11 Refer to Fig.10 and Fig.12 In one example embodiment, Fig.10 After step S830 shown in FIG. 8 , step S600 may be performed. In this case, step S600 may include steps S621 to S625.

[0115] In step S621 and process II-9, a second cutting operation may be performed on the semiconductor mother substrate combination along the filled first groove T1 of each of the first semiconductor mother substrate and the second semiconductor mother substrate to form a plurality of semiconductor chip stacks STK separated from each other. In step S622 and process II-10, the plurality of semiconductor chip stacks STK may be picked up from the first carrier P1 and mounted on the first surface of the packaging substrate. In step S623 and process II-10, a second molding operation may be performed to form a packaging molding layer covering the plurality of semiconductor chip stacks STK on the first surface of the packaging substrate. In step S624 and process II-10, external connection terminals may be formed on a second surface of the packaging substrate opposite to the first surface. In step S625 and process II-10, a third cutting operation may be performed to form a plurality of semiconductor packages each including a plurality of semiconductor chip stacks STK.

[0116] In one example, according to Fig.12 Each of the plurality of semiconductor packages including the plurality of semiconductor chip stacks STK manufactured by the flowchart may include, for example Figure 3 . According to the exemplary embodiment of the present disclosure, since the chip redistribution layer of the semiconductor chip is electrically connected to the through-mold via extending along the outer side surface of the dicing street and the side surface of the chip substrate, and is electrically connected to the external device through the package substrate 110, the electrical connection between the semiconductor chip and the external device can be achieved at the side surface of the semiconductor chip, so that the thickness of the semiconductor package can be reduced, and the bandwidth and IO number of the semiconductor package can also be increased to improve the performance.

[0117] Fig.13 is a flowchart illustrating a method of manufacturing a package of a semiconductor chip according to an example embodiment of the present disclosure. Fig.14 It is shown that according to the present disclosure Fig.13 Process diagram of the method.

[0118] and Fig.10 and Fig.11 Refer to Fig.13 and Fig.14 In one example embodiment, Fig.10 After step S830 shown in FIG. 1 , step S600 may be performed. In this case, step S600 may include steps S631 to S637.

[0119] In step S631 and process II-9, a second cutting operation may be performed on the semiconductor mother substrate combination along the filled first groove T1 of each of the first semiconductor mother substrate and the second semiconductor mother substrate to form a plurality of semiconductor chip stacks STK separated from each other. In step S632 and process III-10, the plurality of semiconductor chip stacks STK may be picked up from the first carrier P1 and mounted on the first surface of the second carrier P2. In step S633 and process III-10, a second molding operation may be performed to form a packaging molding layer covering the plurality of semiconductor chip stacks STK on the first surface of the second carrier P2. In step S634 and process III-11, the second carrier P2 may be removed to expose the plurality of semiconductor chip stacks STK. In step S635 and process III-11, a packaging redistribution layer may be formed on the exposed surface of the plurality of semiconductor chip stacks STK. In step S636, external connection terminals may be formed on the packaging redistribution layer. In step S637 and process III-11, a third cutting operation may be performed to form a plurality of semiconductor packages respectively including a plurality of semiconductor chip stack bodies STK.

[0120] In one example, according to Fig.13 Each of the plurality of semiconductor packages including the plurality of semiconductor chip stacks STK manufactured by the flowchart may include, for example Figure 4 . According to the exemplary embodiment of the present disclosure, since the chip redistribution layer of the semiconductor chip is electrically connected to the through-mold via extending along the outer side surface of the dicing street and the side surface of the chip substrate, and is electrically connected to the external device through the package redistribution layer, the electrical connection between the semiconductor chip and the external device can be achieved at the side surface of the semiconductor chip, so that the thickness of the semiconductor package can be reduced, and the bandwidth and IO number of the semiconductor package can also be increased to improve the performance.

[0121] Fig.15 is a flowchart illustrating a method of manufacturing a semiconductor chip and a package thereof according to an example embodiment of the present disclosure. Fig.16 are process diagrams illustrating a method of manufacturing a semiconductor chip according to an example embodiment of the present disclosure.

[0122] and 7A to 7C and Fig. 9 Refer to Fig.15 and Fig.16 In one example embodiment, Fig. 9 After step S830 shown in FIG. 1 , step S600 may be performed. In this case, step S600 may include steps S641 to S635.

[0123] In step S641 and process IV-9, a package redistribution layer may be formed on a second surface of the semiconductor mother substrate combination opposite to the first surface mounted on the first carrier P1. In step S642 and process IV-9, external connection terminals may be formed on the package redistribution layer. In step S643 and process IV-10, the first carrier P1 may be removed to expose the first surface of the semiconductor mother substrate combination. In step S644 and process IV-10, a protective layer may be formed on the first surface of the semiconductor mother substrate combination. In step S645 and process IV-10, a second cutting operation may be performed on the semiconductor mother substrate combination along the filled first groove T1 of each of the first semiconductor mother substrate and the second semiconductor mother substrate to form a plurality of semiconductor packages each including a plurality of semiconductor chip stacks STK.

[0124] In one example, according to Fig.15 Each of the plurality of semiconductor packages including the plurality of semiconductor chip stacks STK manufactured by the flowchart may include, for example Figure 5 . According to the example embodiments of the present disclosure, since the chip redistribution layer of the semiconductor chip is electrically connected to the through-mold via extending along the outer side surface of the dicing street and the side surface of the chip substrate, and is electrically connected to the external device through the package redistribution layer, the electrical connection between the semiconductor chip and the external device can be achieved at the side surface of the semiconductor chip, so that the thickness of the semiconductor package can be reduced, and the bandwidth and IO number of the semiconductor package can also be increased to improve the performance.

[0125] In the semiconductor chip according to the example embodiment of the present disclosure, because the chip redistribution layer is exposed to the outside of the cutting road and the outer side surface of the cutting road is coplanar with the side surface of the chip substrate, electrical connection between the semiconductor chip and an external device can be achieved at the side surface of the semiconductor chip, thereby reducing the thickness of the package including the semiconductor chip and increasing the IO number of the semiconductor chip to improve performance.

[0126] The present disclosure has been particularly shown and described with reference to example embodiments thereof, but it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the claims.

Claims

1. A semiconductor chip, comprising: Chip substrate; a pattern on an upper surface of a chip substrate; a dicing street on the upper surface of the chip substrate and surrounding the pattern; A chip redistribution layer extends from the pattern into the scribe line, passes through the scribe line, and is exposed to the outside of the scribe line in the pattern.

2. The semiconductor chip according to claim 1, wherein: The semiconductor chip is included in a semiconductor package. Wherein, the semiconductor chip further includes: A through-mold via extends along the outer side surface of the scribe line and the side surface of the chip substrate and is electrically connected to the exposed surface of the chip redistribution layer, A chip molding layer covers the upper surface of the pattern, the upper surface of the cutting path and the outer surface of the through-molding via, The through-molding via passes through the chip molding layer to expose the outside of both a first surface of the semiconductor chip as an active surface and a second surface of the semiconductor chip, the second surface of the semiconductor chip being opposite to the first surface of the semiconductor chip.

3. The semiconductor chip according to claim 2, wherein: Semiconductor packages include: a package substrate comprising a first surface and a second surface opposite to the first surface, wherein an active surface of the semiconductor chip faces upward on the first surface of the package substrate, and a chip redistribution layer of the semiconductor chip is electrically connected to the package substrate through a through-mold via; A packaging molding layer, on the first surface of the packaging substrate and covering the semiconductor chip; external connection terminals on the second surface of the package substrate, Alternatively, the semiconductor package comprises: a package redistribution layer comprising a first surface and a second surface opposite to the first surface, wherein an active surface of the semiconductor chip faces upward on the first surface of the package redistribution layer, and the chip redistribution layer of the semiconductor chip is electrically connected to the package redistribution layer through a through-mold via; a packaging molding layer, on the first surface of the packaging redistribution layer and covering the semiconductor chip; External connection terminals, on the second surface of the package redistribution layer, Alternatively, the semiconductor package comprises: a package redistribution layer comprising a first surface and a second surface opposite to the first surface, wherein an active surface of the semiconductor chip faces downward on the first surface of the package redistribution layer, and the chip redistribution layer of the semiconductor chip is electrically connected to the package redistribution layer through a through-mold via; The external connection terminal is on the second surface of the package redistribution layer.

4. The semiconductor chip according to claim 2, wherein: The semiconductor chip is a first semiconductor chip, Semiconductor packages also include: A second semiconductor chip is vertically stacked on the first semiconductor chip, and the first semiconductor chip and the second semiconductor chip are electrically connected to each other through a through-mold via.

5. A method for manufacturing a semiconductor chip, comprising: forming a plurality of patterns, a plurality of scribe lines, and a plurality of chip redistribution layers on a semiconductor mother substrate, such that the plurality of patterns are separated by the plurality of scribe lines, and the plurality of chip redistribution layers extend from corresponding patterns in the plurality of patterns to corresponding scribe lines in the plurality of scribe lines, respectively; performing a first cutting operation on the semiconductor mother substrate along the plurality of cutting streets to form a first groove in each of the plurality of cutting streets, the first groove extending into the semiconductor mother substrate and having a first depth and a first width, so that each of the plurality of chip redistribution layers is exposed through the first groove; performing a first molding operation to form a chip molding layer filling the first groove; forming a hole penetrating the chip molding layer along an inner side surface of the filled first groove to expose each of the plurality of chip redistribution layers through the hole; filling the holes with a conductive material to form a plurality of through-mold vias electrically connected to the plurality of chip redistribution layers, respectively; A second cutting operation is performed on the semiconductor mother substrate along the filled first grooves to form a plurality of semiconductor chips respectively including the plurality of patterns.

6. The method according to claim 5, wherein: The steps of performing the second cutting operation include: performing a thinning operation on the semiconductor mother substrate to expose the plurality of through-mold vias; Placing the thinned semiconductor mother substrate on a first carrier; A second cutting operation is performed to form second grooves having a second width in the filled first grooves so that the plurality of semiconductor chips are spaced apart from each other by the second grooves.

7. The method according to claim 6, further comprising: After the step of performing the second cutting operation, Picking up the plurality of semiconductor chips from the first carrier and mounting them on the first surface of the packaging substrate; performing a second molding operation to form a packaging molding layer covering the plurality of semiconductor chips on the first surface of the packaging substrate; forming external connection terminals on a second surface of the package substrate opposite to the first surface; A third cutting operation is performed to form a plurality of semiconductor packages respectively including the plurality of semiconductor chips.

8. The method according to claim 7, wherein: The steps for picking up and installing include: forming a plurality of semiconductor chip stacks separated from each other on a first surface of the packaging substrate, The step of performing a third cutting operation forms a plurality of semiconductor packages each including the plurality of semiconductor chip stacks.

9. The method according to claim 5, further comprising: After the step of filling the holes with a conductive material, performing a thinning operation on the semiconductor mother substrate to expose the plurality of through-mold vias and obtain a first semiconductor mother substrate; vertically stacking a second semiconductor mother substrate identical to the first semiconductor mother substrate on the first semiconductor mother substrate so that the first semiconductor mother substrate and the second semiconductor mother substrate are electrically connected to each other through corresponding through-mold vias among the plurality of through-mold vias to form a semiconductor mother substrate combination; The semiconductor mother substrate combination is arranged on the first carrier.

10. The method according to claim 9, further comprising: performing a second cutting operation on the semiconductor mother substrate combination along the filled first grooves of each of the first semiconductor mother substrate and the second semiconductor mother substrate to form a plurality of semiconductor chip stacks separated from each other; picking up the plurality of semiconductor chip stacks from the first carrier and mounting them on the first surface of the packaging substrate; performing a second molding operation to form an encapsulation molding layer covering the plurality of semiconductor chip stacks on the first surface of the encapsulation substrate; forming external connection terminals on a second surface of the package substrate opposite to the first surface; performing a third cutting operation to form a plurality of semiconductor packages respectively including the plurality of semiconductor chip stacks, Alternatively, the method further comprises: performing a second cutting operation on the semiconductor mother substrate combination along the filled first grooves of each of the first semiconductor mother substrate and the second semiconductor mother substrate to form a plurality of semiconductor chip stacks separated from each other; picking up the plurality of semiconductor chip stacks from the first carrier and mounting them on the first surface of the second carrier; performing a second molding operation to form a packaging molding layer covering the plurality of semiconductor chip stacks on the first surface of the second carrier; removing the second carrier to expose the plurality of semiconductor chip stacks; forming a package redistribution layer on the exposed surfaces of the plurality of semiconductor chip stacks; forming external connection terminals on the package redistribution layer; performing a third cutting operation to form a plurality of semiconductor packages respectively including the plurality of semiconductor chip stacks, Alternatively, the method further comprises: forming a package redistribution layer on a second surface of the semiconductor mother substrate assembly opposite to a first surface of the semiconductor mother substrate assembly mounted on the first carrier; forming external connection terminals on the package redistribution layer; Removing the first carrier to expose the first surface of the semiconductor mother substrate combination; forming a protective layer on the first surface of the semiconductor mother substrate combination; A second cutting operation is performed on the semiconductor mother substrate combination along the filled first grooves of each of the first semiconductor mother substrate and the second semiconductor mother substrate to form a plurality of semiconductor packages respectively including a plurality of semiconductor chip stacks.

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