Dielectric filled bond pad in clip package

Abstract

The invention relates to a dielectric filled bond pad in a clip package. A package (104) includes: a semiconductor die (110) including a device side (111) having circuitry formed therein; and a first metal member (118) on the device side of the die and having a top surface (123) facing away from the die. The first metal member includes a set of dielectric members (120), each dielectric member of the set extending at least partially through a thickness of the first metal member. The package also includes a solder material (122) contacting the top surface of the first metal member and a top surface (125) of the dielectric member of the set of dielectric members. The package also includes a second metal member (124) coupled to the solder material and a conductive terminal (109) of the package, the conductive terminal being exposed to an exterior of the package.

Description

Technical Field

[0001] The present application relates to dielectric filled bond pads in clip packages. Background Art

[0002] A semiconductor wafer is a circular piece of semiconductor material, such as silicon, used to make semiconductor chips. Typically, many integrated circuits are formed on a single wafer using complex manufacturing processes. Forming such circuits on a wafer is called fabrication. After wafer fabrication, the wafer is cut into multiple pieces, called semiconductor dies, where each die contains a circuit. Cutting or sawing the wafer into individual dies is called singulation. The dies are then coupled to a lead frame and covered with a molding compound, which is then sawn to produce a package. Summary of the invention

[0003] A package includes: a semiconductor die including a device side in which a circuit system is formed; and a first metal member on the device side of the die and having a top surface facing away from the die. The first metal member includes a set of dielectric members, each dielectric member in the set of dielectric members extending at least partially through the thickness of the first metal member. The package also includes a solder material contacting the top surface of the first metal member and the top surfaces of the dielectric members in the set of dielectric members. The package also includes a second metal member coupled to the solder material and to a conductive terminal of the package, the conductive terminal being exposed to the exterior of the package.

[0004] A method for manufacturing a package includes: sputtering a seed layer on a device side of a semiconductor wafer, in which a circuit system is formed; covering the seed layer with a photoresist; performing photolithography on the photoresist to form a cavity in the photoresist; and electroplating a metal component in the cavity of the photoresist and on the device side of the wafer. The method also includes removing the photoresist and a portion of the seed layer to create a cavity in the metal component, and coating a dielectric component on the metal component and in the cavity in the metal component. The method also includes exposing the dielectric component using a mask, the mask including a first portion having a first opacity and a second portion having a second opacity, wherein the first portion of the mask is vertically aligned with the cavity in the metal component. The method includes developing the dielectric component to remove a portion of the dielectric component. The exposure and development cause the portion of the dielectric component outside the cavity in the metal component to be removed, and cause the portion of the dielectric component within the cavity of the metal component to have a top surface that is substantially flush with the top surface of the metal component. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1A is a cutaway cross-sectional view of a clip package including a dielectric-filled bond pad according to various examples.

[0006] Figure 1B is a top view of a clip package including dielectric-filled bond pads according to various examples.

[0007] Figure 1C is a perspective view of a clip package including a dielectric-filled bond pad according to various examples.

[0008] Figure 2 is a flow chart of a method for fabricating a clip package including dielectric-filled bond pads according to various examples.

[0009] Figures 3A1 to 3K3 is a process flow depicting the fabrication of a clip package including dielectric-filled bond pads according to various examples.

[0010] Figure 4 An electronic device including a clip package with a dielectric-filled bond pad according to various examples. DETAILED DESCRIPTION

[0011] During the manufacturing stage, circuits and various types of metal features (e.g., copper bond pads) are added to the device side of the semiconductor wafer. The metal features may have a high density, and during the manufacturing stage, the high density of the metal features may cause the wafer to physically warp, rendering the wafer no longer usable. The density of the metal features may be reduced by forming multiple cavities in the metal features, and this reduced density reduces or eliminates wafer warping.

[0012] However, forming cavities in metal components presents additional technical challenges. For example, a clip can be used to couple a metal component to a package conductive terminal (e.g., a package lead or other metal component exposed to the exterior of the package). A solder paste can be used to couple the clip to the metal component, and this solder paste can at least partially fill the cavity in the metal component. In such cases, voids often occur in the solder paste present in the cavity, and such voids can lead to mechanical instabilities (e.g., cracks formed in the solder paste), which can compromise the functionality and structural integrity of the package. Voids can also make it difficult to distinguish voids from significant manufacturing defects during quality control inspections, which can lead to false positives during inspections and can reduce production yields.

[0013] The present disclosure describes various packaging examples that mitigate the technical challenges described above by filling the metal component cavity with a dielectric material during the wafer manufacturing stage of manufacturing. Solder paste is then applied to the top surface of the dielectric material and the metal component, and a clip is attached using the solder paste. The clip is also attached to a conductive terminal. By filling the metal component cavity with a dielectric material before applying the solder paste, the solder paste is prevented from entering the cavity, and the problematic voids described above are thus eliminated. Therefore, solder paste cracks are not formed, and false positives during quality control inspections are reduced. In addition, the solder paste forms a smooth, flat and uniform surface, which helps to securely connect with the clip. In an example, a package includes a semiconductor die, the semiconductor die includes a device side, and a circuit system is formed in the device side. The package includes a first conductive (e.g., metal) member, the first conductive member is on the device side of the die and has a top surface facing away from the die, wherein the first metal member includes a set of dielectric members, and each dielectric member in the set of dielectric members extends at least partially through the thickness of the first metal member. The package further comprises a solder material contacting a top surface of the first metal component and a top surface of a dielectric component in the set of dielectric components. The package further comprises a second metal component coupled to the solder material and a conductive terminal of the package, wherein the conductive terminal is exposed to the outside of the package.

[0014] Figure 1A 1 is a cutaway cross-sectional view of a clip package 104 including dielectric-filled bond pads according to various examples. Package 104 may include a die pad 106 and conductive terminals 108, 109. Package 104 is depicted as a quad flat no-lead (QFN) package, but package 104 may be any suitable type of package in which a clip is coupled to a metal member inside the package. A clip may be defined herein as a rigid, non-linear metal member that couples a semiconductor die (or a metal member coupled to a semiconductor die, such as a bond pad) to one or more conductive terminals of the package (e.g., a metal member, such as a package lead, that is exposed to the exterior of the package to couple to a substrate such as a printed circuit board). The structures described herein may also be used for packages having other types of metal members (e.g., heat sinks) coupled to the semiconductor die in a manner similar to the clip. All such metal members are contemplated and included within the scope of the present disclosure.

[0015] Package 104 may include a semiconductor die 110 coupled to a die pad 106 by means of a die attach material. Die 110 includes a device side 111 in which circuitry is formed. Bond pads 112 are coupled to device side 111. A dielectric layer 114, which may include polyimide, a passivation overcoat, a polyimide stacked on top of a passivation overcoat, or some other dielectric material, contacts device side 111 and surrounds bond pads 112. Bond wires 116 couple bond pads 112 to conductive terminals 108. Suitable types of wire bonds, such as ball bonds, stitch bonds, etc., may be useful.

[0016] The package 104 also includes a metal component 118 (e.g., a bonding pad). In an example, the metal component 118 is a metal stack in which the base layer or first layer is copper, the second layer or middle layer is nickel, and the third layer or top layer is palladium. Other combinations of metals and / or alloys are contemplated and are included within the scope of the present disclosure. By including multiple dielectric components 120 in the metal component 118, the density of the metal component 118 is reduced relative to the density that the metal component 118 would otherwise have. The dielectric components 120 are vertically oriented, extending through the thickness of the metal component 118 so that the dielectric components 120 are in contact with the device side 111. In some examples, a thin layer of the metal component 118 is positioned between each of the dielectric components 120 and the device side 111 to prevent contact between the dielectric components 120 and the device side 111.

[0017] Package 104 includes solder paste 122 on top surface 123 of metal member 118. Solder paste 122 contacts top surface 123 and top surface 125 of dielectric member 120. Package 104 includes clip 124 coupled to top surfaces 123, 125 via solder paste 122. Clip 124 is also coupled to conductive terminal 109 as shown. Figure 1B is a top view of package 104 according to various examples. Figure 1C is a perspective view of a package 104 according to various examples.

[0018] As described in more detail below, the dielectric member 120 is formed by filling the cavity of the metal member 118 with a dielectric material. To avoid voids in the dielectric member 120 and challenges associated with voids, such as those described herein, the dielectric material is a polyimide or other material with a suitably low viscosity. The viscosity of the dielectric material forming the dielectric member 120 is in the range of 3550 millipascal-seconds (mPa-s) to 3650 mPa-s, wherein viscosities below this range are disadvantageous because they result in runoff and dripping, unacceptably poor adhesion, and unacceptably long cure times, and wherein viscosities above this range are disadvantageous because they are unacceptably poor at filling the cavity in which the dielectric member 120 is formed, have limited flow, and entrap air during application. The top surface 125 of the dielectric member 120 is substantially flush with the top surface 123 of the metal member 118, meaning that the top surface 125 is within 1 micron above or below the top surface 123. A difference between the top surfaces 123 , 125 greater than this threshold is unfavorable because it may result in the formation of voids within the solder paste 122 and an uneven and therefore weaker mechanical connection to the clip 124 . In an example, no dielectric material is present on the top surface 123 .

[0019] The top surface 125 does not have to be completely flat. Figure 3J1 , described below, top surface 125 may have a flat central region that is flush with top surface 123, but may also have downwardly sloping regions where top surface 125 intersects top surface 123. These downwardly sloping regions of top surface 125 near top surface 123 do not significantly contribute to the void and / or uneven clip 124 coupling issues described above, as long as they do not exceed a depth of 2.88 microns below surface 123.

[0020] The density of the dielectric member 120 within the metal member 118 is in the range of 20% to 40%, wherein a density below this range is disadvantageous because the material becomes susceptible to warping due to the increased density of the metal member 118, and wherein a density above this range is disadvantageous because resistance increases, integration is limited, and conductivity decreases. The horizontal cross-sectional dimension of each of the dielectric members 120 is in the range of 10.42 microns to 16.18 microns, wherein a dimension below this range is disadvantageous because voids may occur near the metal member 118 and dielectric member 120 area, and wherein a dimension above this range is disadvantageous because voids may occur at the interface of the metal member 118 and the clip 124. The molding compound 126 covers the remaining structure of the package 104.

[0021] Figure 2 is a flow chart of a method 200 for fabricating a clip package including dielectric-filled bond pads according to various examples. Figures 3A1 to 3K3The present invention is a process flow for fabricating a clip package including a dielectric-filled bond pad according to various embodiments. Figure 2 and Figures 3A1 to 3K3 .

[0022] The method 200 includes sputtering a seed layer on a device side of a semiconductor die (202). Figure 3A1 2 is a cross-sectional view of a semiconductor wafer 110 (which may also be referred to herein as semiconductor die 110, as the steps of method 200 may be performed during a wafer fabrication stage and / or during a post-singulation stage). A copper seed layer 300 is sputtered on a device side 111 of wafer 110 in which circuitry is formed. Figure 3A2 Based on various examples Figure 3A1 Top view of the structure. Figure 3A3 Based on various examples Figure 3A1 perspective view of the structure.

[0023] The method 200 includes applying a photoresist layer to the seed layer (204). Figure 3B1 Based on various examples Figure 3A1 The structure of FIG. 1 is a cross-sectional view of FIG. 1 , except that a photoresist layer 302 is coated on top of the seed layer 300. The thickness of the photoresist layer 302 is the same as the target thickness of the metal member 118 ( Figure 1A ). Figure 3B2 Based on various examples Figure 3B1 Top view of the structure. Figure 3B3 Based on various examples Figure 3B1 perspective view of the structure.

[0024] The method 200 includes exposing and developing the photoresist layer to form a cavity in the photoresist layer (206). Fig.3C1 Based on various examples Figure 3B1 , except that photolithography techniques have been used to expose regions 304 of the photoresist layer 302. Figure 3C2 Based on various examples Fig.3C1 Top view of the structure. Figure 3C3 Based on various examples Fig.3C1 perspective view of the structure. Figure 3D1 yes Fig.3C1 , except that the exposed areas 304 of the photoresist layer 302 have been developed and removed, thereby leaving a cavity 306 in the photoresist layer 302, as shown. Figure 3D2 Based on various examples Figure 3D1 Top view of the structure. Figure 3D3 Based on various examples Figure 3D1The cavities 306 are not separate cavities, but are fluidly connected to each other, and in this sense, the cavities 306 can be considered as a single cavity 306 containing multiple components of the remaining photoresist layer 302 that have not been removed.

[0025] The method 200 includes electroplating a metal feature in a photoresist cavity (208). Fig.3E1 yes Figure 3D1 1, except that cavity 306 has been filled with electroplated metal (e.g., a stack of copper, nickel on top of copper, and palladium on top of nickel). As described above, cavity 306 is fluidly connected, and thus, electroplating produces a single, unitary metal component 118. This unitary aspect of metal component 118 is Figure 3E2 Top view and Figure 3E3 As can be seen from the perspective of , both views are provided based on various examples.

[0026] The method 200 includes removing a portion of the photoresist and the seed layer ( 210 ). Figure 3F1 yes Fig.3E1 3 is a cross-sectional view of a structure of FIG. 3 , except that the remaining components of the photoresist layer 302 are removed. Figure 3F2 Based on various examples Figure 3F1 Top view of the structure. Figure 3F3 Based on various examples Figure 3F1 perspective view of the structure. Figure 3G1 yes Figure 3F1 , except that areas of the seed layer 300 that are not directly below the metal feature 318 are etched away, leaving a plurality of cavities 307 in the metal feature 318. Figure 3G2 Based on various examples Figure 3G1 Top view of the structure. Figure 3G3 Based on various examples Figure 3G1 perspective view of the structure.

[0027] The method 200 includes coating the metal component and the device side of the die with a dielectric component (212). Figure 3H1 yes Figure 3G1 1, except that a dielectric member 120, such as polyimide, has been applied to the device side 111 and the metal member 318, as shown. The dielectric member 120 fills the cavity 307 of the metal member 318. Figure 3H2 Based on various examples Figure 3H1 Top view of the structure. Figure 3H3 Based on various examples Figure 3H1 perspective view of the structure.

[0028] The method 200 includes selectively exposing and developing the dielectric feature to produce a vertically oriented dielectric feature (214). Figure 3I1 The exposure is performed using a suitable mask or mask 308 (hereinafter generally referred to as mask 308) Figure 3H1 308 includes an opaque region 309 and a non-opaque (e.g., transparent) region 310. In the case of mask 308, mask 308 may include an opening region 310. In either case, the minimum width 312 of region 310 ranges between 10 microns and 30 microns, wherein a width 312 below this range is disadvantageous because it results in insufficient spacing of dielectric members 120, and wherein a width 312 above this range is disadvantageous because the concentration of dielectric members 120 becomes too high, thereby causing problems such as current limitation.

[0029] Each region 310 is vertically aligned with a corresponding cavity 307, meaning that the horizontal midpoint of the region 310 and the horizontal midpoint of the corresponding cavity 307 are both along a vertical line that is normal to the horizontal surface of the wafer 110. The width 314 of the cavity 307 ranges between 10 microns and 30 microns, wherein a width 314 below this range is disadvantageous because the highly viscous dielectric material will have difficulty filling the cavity 307, and wherein a width 314 above this range is disadvantageous because the concentration of dielectric material in the metal component 118 becomes unacceptably high, thereby causing problems such as current limiting. Regardless of the specific widths 312, 314, the width 312 is narrower than the width 314 by an amount between 0 microns and 2.5 microns, wherein a width difference less than this range is disadvantageous because the reticle bias becomes uncontrollable, and wherein a width difference greater than this range is disadvantageous because the dielectric extends beyond the dielectric region, making the surface to which the clip 124 must be attached uneven and thereby compromising the integrity of the mechanical connection between the clip 124 and the metal component 118. The portion of dielectric member 120 within cavity 307 is exposed, while the portion of dielectric member 120 outside cavity 307 is not exposed (or vice versa in some examples, depending on the type of photolithography technique used). Because width 312 is slightly narrower than width 314 as described above, a small portion of dielectric member 120 along the top edge of cavity 307 remains in place, as shown in FIG. Figure 3I1 As indicated by reference numeral 316 in FIG. Figure 3I2 Based on various examples Figure 3I1 Top view of the structure. Figure 3I3 Based on various examples Figure 3I1 perspective view of the structure.

[0030] Figure 3J1 yes Figure 3I1307, except that dielectric members 120 have been developed and unexposed areas of dielectric members 120 have been removed (or, depending on the photolithography technique used, exposed areas of dielectric members 120 are removed). The remaining portions of dielectric members 120 are in cavity 307 and are referred to herein as dielectric members 120. Each dielectric member 120 may have a downwardly sloping top edge, as indicated by reference numeral 318, resulting from a small portion of dielectric member 120 remaining along the top edge of cavity 307 prior to exposure ( Figure 3I1 316 in the figure). Figure 3J2 Based on various examples Figure 3J1 Top view of the structure. Figure 3J3 Based on various examples Figure 3J1 perspective view of the structure.

[0031] The method 200 includes coupling a clip to a dielectric component and a metal component with solder (216), and covering the metal component, the clip, and the die with a molding compound (218). Figure 3K1 Based on various examples Figure 3J1 1, except that the clip 124 has been coupled to the dielectric member 120 and the metal member 118 with the solder paste 122, and the molding compound 126 covers the metal member 118, the clip 124, and the die 110. Where the reference numeral 110 refers to the wafer 110 rather than the die 110 (i.e., meaning that steps 202 to 216 are performed during the wafer fabrication stage), the wafer 110 may be singulated (e.g., sawed) after step 216 to produce the die 110. Figure 3K2 Based on various examples Figure 3K1 Top view of the structure. Figure 3K3 Based on various examples Figure 3K1 perspective view of the structure.

[0032] Figure 4 An electronic device 100 including a clip package with dielectric-filled bonding pads according to various examples is shown. The electronic device 100 may include, for example, a personal computer, a laptop computer, a desktop computer, a notebook computer, a tablet computer, a smart phone, an appliance (e.g., a refrigerator, a television, an audio player, a video player, a video recorder, a lighting device, etc.), an automobile, an airplane, a spacecraft, etc. The electronic device 100 may include a printed circuit board (PCB) 102. A package 104 may be coupled to the PCB 102.

[0033] In this specification, the term "coupled" may encompass connections, communications, or signal paths that achieve a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B through a direct connection; or (b) in a second instance, device A is coupled to device B through an intermediate component C, provided that the intermediate component C does not change the functional relationship between device A and device B, so that device B is controlled by device A via the control signal generated by device A.

[0034] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function when manufactured by a manufacturer, and / or may be configured (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. Configuration may be achieved through firmware and / or software programming of the device, through the construction and / or layout of the device's hardware components and interconnects, or a combination thereof.

[0035] In this specification, unless otherwise stated, "about," "approximately," or "substantially" preceding a parameter means within a + / - 10% range of the parameter. Modifications may be made in the described examples, and other examples are possible within the scope of the claims.

Claims

1. A package comprising: a semiconductor die including a device side having circuitry formed therein; a first metallic member on the device side of the die and having a top surface facing away from the die, the first metallic member comprising a set of dielectric members, each dielectric member of the set of dielectric members extending at least partially through a thickness of the first metallic member; a welding material contacting the top surface of the first metal member and a top surface of the dielectric member of the set of dielectric members; as well as A second metal member is coupled to the solder material and a conductive terminal of the package, the conductive terminal being exposed to the outside of the package. 2 . The package of claim 1 , wherein a density of the set of dielectric members in the first metal member is in a range of 20% to 40%. The package of claim 1 , wherein the dielectric member comprises polyimide. The package of claim 1 , wherein the top surface of the first metal member is free of any dielectric material. 5 . The package of claim 1 , wherein the top surface of the dielectric member is no deeper than 2.88 microns below the top surface of the first metal member.

6. The package of claim 1, wherein the dielectric members of the set of dielectric members extend completely through a thickness of the first metal member. The package of claim 1 , wherein the second metal member is a clip.

8. The package of claim 1, wherein each dielectric member in the set of dielectric members has a horizontal cross-sectional dimension in a range of 10.42 microns to 16.18 microns.

9. A package comprising: a semiconductor die including a device side having circuitry formed therein; a bond pad on the device side of the die and having a top surface facing away from the die, the bond pad comprising a set of polyimide members extending vertically through a thickness of the die, a density of the set of polyimide members being in a range of 20% to 40%, each polyimide member of the set of polyimide members having a top surface substantially flush with the top surface of the bond pad, each polyimide member of the set of polyimide members having a horizontal cross-sectional dimension in a range of 10.42 microns to 16.18 microns; a solder paste contacting the top surfaces of the polyimide members in the set of polyimide members and the top surfaces of the bonding pads; a clip coupled to the solder paste and to the conductive terminals exposed to the exterior of the package; as well as A molding compound covers the die, the bonding pads, the solder paste, and the clip.

10. The package of claim 9, wherein the top surface of the polyimide member is no deeper than 2.88 microns below the top surface of the bond pad.

11. The package of claim 9, wherein the set of polyimide members extend completely through the thickness of the die.

12. A method for manufacturing a package, comprising: sputtering a seed layer on a device side of a semiconductor wafer in which circuitry is formed; Covering the seed layer with a photoresist; performing photolithography on the photoresist to form a cavity in the photoresist; as well as electroplating metal features in the cavities of the photoresist and on the device side of the wafer; removing the photoresist and portions of the seed layer to create a cavity within the metal component; coating a dielectric member on the metal member and in the cavity within the metal member; exposing the dielectric member using a reticle, the reticle comprising a first portion having a first opacity and a second portion having a second opacity, and wherein the first portion of the reticle is vertically aligned with the cavity in the metal member; as well as developing the dielectric member to remove portions of the dielectric member, The exposing and developing cause the portion of the dielectric member outside the cavity in the metal member to be removed and cause the portion of the dielectric member within the cavity of the metal member to have a top surface substantially flush with a top surface of the metal member.

13. The method of claim 12, wherein the density of the cavities in the metal component is in the range of 20% to 40%. The method of claim 12 , wherein the dielectric member comprises polyimide. The method of claim 12 , wherein the first opacity is transparent. The method of claim 12 , wherein the second opacity is fully opaque.

17. The method according to claim 12, wherein: After the exposing and the developing, no portion of the dielectric member remains outside the cavity of the metal member.

18. The method of claim 12, wherein one of the first portions of the reticle is vertically aligned with a corresponding first one of the cavities of the metal member, and wherein a minimum width of the one of the first portions of the reticle is narrower than a width of the corresponding first cavity.

19. The method of claim 12, wherein the cavity of the metal component extends through a thickness of the wafer.

20. The method of claim 12, further comprising: singulating the wafer to produce dies; coupling the metal member to the package conductive terminal via a clip; as well as The die, the metal member, and the clip are covered with a molding compound.

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