Electronic device and manufacturing method thereof

Abstract

The invention provides an electronic device and a manufacturing method thereof. The electronic device comprises an electronic unit and a circuit structure. The circuit structure is electrically connected with the electronic unit and comprises a first circuit structure, a second circuit structure, a bonding pad and an adjusting layer. The first circuit structure includes at least one first circuit layer and at least one first insulating layer surrounding the at least one first circuit layer. The second circuit structure is disposed between the electronic unit and the first circuit structure. The second circuit structure comprises at least one second circuit layer and at least one second insulating layer surrounding the at least one second circuit layer. The bonding pad is disposed between the second circuit structure and the first circuit structure. The adjustment layer is disposed between the second circuit structure and the first circuit structure and surrounds the bonding pad. The thermal expansion coefficient of the adjusting layer is smaller than the thermal expansion coefficient of at least one of the at least one first insulating layer of the first circuit structure and the at least one second insulating layer of the second circuit structure.

Description

Technical Field

[0001] The present disclosure relates to an electronic device and a manufacturing method thereof, and more particularly to an electronic device with better structural reliability and a manufacturing method thereof. Background Art

[0002] In order to develop more efficient and complex semiconductor chip packages, the number of redistribution layers (RDL) continues to increase. However, as the number of redistribution layers increases, it also causes serious warpage problems in the substrate during production, which will affect the process accuracy of the chip corresponding to the pad on the top layer, and will also affect the yield of subsequent chip bonding and the reliability of subsequent products. Summary of the invention

[0003] The present disclosure is directed to an electronic device having better structural reliability.

[0004] The present disclosure is directed to a method for manufacturing an electronic device, which is used to manufacture the above-mentioned electronic device.

[0005] According to an embodiment of the present disclosure, an electronic device includes an electronic unit and a circuit structure. The circuit structure is electrically connected to the electronic unit, and the circuit structure includes a first circuit structure, a second circuit structure, a bonding pad, and an adjustment layer. The first circuit structure includes at least one first circuit layer and at least one first insulating layer surrounding the at least one first circuit layer. The second circuit structure is disposed between the electronic unit and the first circuit structure. The second circuit structure includes at least one second circuit layer and at least one second insulating layer surrounding the at least one second circuit layer. The bonding pad is disposed between the second circuit structure and the first circuit structure. The adjustment layer is disposed between the second circuit structure and the first circuit structure and surrounds the bonding pad. The thermal expansion coefficient of the adjustment layer is less than the thermal expansion coefficient of at least one of the at least one first insulating layer of the first circuit structure and the at least one second insulating layer of the second circuit structure.

[0006] According to an embodiment of the present disclosure, an electronic device includes an electronic unit and a circuit structure. The circuit structure is electrically connected to the electronic unit, and the circuit structure includes a first circuit structure, a second circuit structure, a bonding pad, and an adjustment layer. The first circuit structure includes at least one first circuit layer and at least one first insulating layer surrounding the at least one first circuit layer. The second circuit structure is disposed between the electronic unit and the first circuit structure. The second circuit structure includes at least one second circuit layer and at least one second insulating layer surrounding the at least one second circuit layer. The bonding pad is disposed between the second circuit structure and the first circuit structure. The adjustment layer is disposed between the second circuit structure and the first circuit structure and surrounds the bonding pad. The thermal expansion trend of the adjustment layer is different from the thermal expansion trend of at least one of the at least one first insulating layer of the first circuit structure and the at least one second insulating layer of the second circuit structure.

[0007] According to an embodiment of the present disclosure, a method for manufacturing an electronic device includes the following steps. A first circuit structure and a second circuit structure are provided. The first circuit structure includes at least one first circuit layer, at least one first insulating layer surrounding the at least one first circuit layer, and at least one first groove passing through the at least one first insulating layer. The second circuit structure includes at least one second circuit layer, at least one second insulating layer surrounding the at least one second circuit layer, and at least one second groove passing through the at least one second insulating layer. The at least one first groove is arranged corresponding to the at least one second groove. A bonding pad and an adjustment layer are provided between the first circuit structure and the second circuit structure. The thermal expansion coefficient of the adjustment layer is smaller than the thermal expansion coefficient of at least one of the at least one first insulating layer of the first circuit structure and the at least one second insulating layer of the second circuit structure. The first circuit structure and the second circuit structure are bonded by a bonding pad. The adjustment layer surrounds the bonding pad and fills the at least one first groove and the at least one second groove. At least one electronic unit is arranged on the second circuit structure. A singulation process is performed along the at least one first groove and the at least one second groove to form at least one electronic device. The first circuit structure, the second circuit structure, the bonding pad and the adjustment layer are defined as a circuit structure, and at least one electronic unit is electrically connected to the circuit structure.

[0008] Based on the above, in the embodiment of the present disclosure, the adjustment layer is arranged between the second circuit structure and the first circuit structure and surrounds the bonding pad, wherein the thermal expansion coefficient of the adjustment layer is smaller than the thermal expansion coefficient of at least one of the first insulating layer of the first circuit structure and the second insulating layer of the second circuit structure, thereby effectively alleviating the warping of the board, ensuring the process accuracy of the corresponding bonding pad of the electronic unit located at the top layer, and enabling the electronic device of the present disclosure to have better structural reliability.

[0009] In order to make the above features and advantages of the present disclosure more obvious and understandable, embodiments are given below with reference to the accompanying drawings for detailed description as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1A is a cross-sectional schematic diagram of an electronic device according to an embodiment of the present disclosure;

[0011] Figure 1B yes Figure 1A A top view schematic diagram of a second circuit structure;

[0012] Figure 2 is a cross-sectional schematic diagram of an electronic device according to another embodiment of the present disclosure;

[0013] Figure 3 is a cross-sectional schematic diagram of an electronic device according to another embodiment of the present disclosure;

[0014] Figure 4 is a cross-sectional schematic diagram of an electronic device according to another embodiment of the present disclosure;

[0015] FIG. 5A to FIG. 5E is a cross-sectional schematic diagram of a method for manufacturing an electronic device according to an embodiment of the present disclosure;

[0016] FIG. 6A to FIG. 6C is a cross-sectional schematic diagram of partial steps of a method for manufacturing an electronic device according to another embodiment of the present disclosure;

[0017] Figure 7 It is a cross-sectional schematic diagram of partial steps of a method for manufacturing an electronic device according to another embodiment of the present disclosure.

[0018] Description of Reference Numerals

[0019] 10, 10', 10", 10a, 10b, 10c, 10d: electronic devices;

[0020] 30, 40: substrate;

[0021] 35, 45: release film;

[0022] 100, 100', 100a, 100b, 100c: electronic unit;

[0023] 101, 101a, 101b: back side;

[0024] 102: pad;

[0025] 103: Active side;

[0026] 150: Connector;

[0027] 200, 200a, 200b, 200c, 200d: circuit structure;

[0028] 210: first circuit structure;

[0029] 211: first peripheral surface;

[0030] 212: first circuit layer;

[0031] 214: first insulating layer;

[0032] 216: first conductive pattern layer;

[0033] 217: first conductive hole;

[0034] 220: second circuit structure;

[0035] 221: second peripheral surface;

[0036] 222: second circuit layer;

[0037] 224: second insulating layer;

[0038] 226: second conductive pattern layer;

[0039] 227: second conductive hole;

[0040] 230, 230a, 230b, 230d: bonding pads;

[0041] 240, 240a, 240b, 240c, 240d, 240e: adjustment layer;

[0042] 241b, 241c: surrounding surface;

[0043] 242: Through hole substrate structure;

[0044] 243: substrate;

[0045] 244: through hole;

[0046] 245: via;

[0047] 246: build-up circuit layer;

[0048] 247: pad;

[0049] 248: Adjust materials;

[0050] 300: encapsulation layer;

[0051] 300a: packaging material layer;

[0052] 350, 370: adhesive layer;

[0053] 400: solder ball;

[0054] 450: heat dissipation component;

[0055] 452: heat sink;

[0056] 454: heat dissipation glue;

[0057] C1, C2: geometric center;

[0058] D1, D2: dummy patterns;

[0059] E1: first groove;

[0060] E2: second groove;

[0061] P1: first spacing;

[0062] P2: second spacing;

[0063] P3: third spacing;

[0064] P4: fourth pitch;

[0065] S1, S2: surface;

[0066] T1: first thickness;

[0067] T2: second thickness;

[0068] W1: first width;

[0069] W2: second width;

[0070] X, Z: direction. DETAILED DESCRIPTION

[0071] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0072] The present disclosure can be understood by referring to the following detailed description in conjunction with the accompanying drawings. It should be noted that in order to make it easier for readers to understand and for the simplicity of the drawings, the multiple drawings in the present disclosure only depict a portion of the electronic device, and the specific elements in the drawings are not drawn according to the actual scale. In addition, the number and size of each element in the figure are only for illustration and are not intended to limit the scope of the present disclosure.

[0073] Certain words are used throughout this disclosure and in the appended claims to refer to specific components. Those skilled in the art will appreciate that electronic device manufacturers may refer to the same components by different names. This document does not intend to distinguish between components that have the same function but different names.

[0074] In the following description and claims, the words “including” and “comprising” are open-ended words, and thus should be interpreted as meaning “including but not limited to…”.

[0075] In addition, relative terms such as "below" or "bottom" and "above" or "top" may be used in the embodiments to describe the relative relationship of one element to another element in the drawings. It is understood that if the device in the drawings is turned upside down, the element described on the "below" side will become the element on the "above" side.

[0076] In some embodiments of the present disclosure, terms such as "connection" and "interconnection" may refer to two structures being in direct contact, or two structures not being in direct (indirect) contact, with other structures being disposed between the two structures, unless otherwise specified. Such terms may also include situations where both structures are movable, or where both structures are fixed. In addition, the term "coupling" includes energy transfer between two structures by means of direct or indirect electrical connection, or energy transfer between two separate structures by means of mutual induction.

[0077] It should be understood that when an element or a film layer is referred to as being "on" or "connected to" another element or film layer, it may be directly on or directly connected to the other element or film layer, or there may be an intervening element or film layer between the two (indirect case). Conversely, when an element is referred to as being "directly on" or "directly connected to" another element or film layer, there may be no intervening element or film layer between the two.

[0078] The terms "approximately," "equal," "equal," or "same," "substantially," or "approximately" are generally interpreted as within 20% of a given value or range, or within 10%, 5%, 3%, 2%, 1% or 0.5% of a given value or range.

[0079] In the present disclosure, an optical microscope (OM), a scanning electron microscope (SEM), an α-step, an ellipsometer, or other suitable methods may be used to measure the area, width, thickness, or height of each component, or the distance or spacing between components. Specifically, according to some embodiments, a scanning electron microscope may be used to obtain a cross-sectional structural image including the component to be measured, and measure the area, width, thickness, or height of each component, or the distance or spacing between components.

[0080] In the present disclosure, the definition of roughness judgment can be observed by SEM. On the concave-convex surface, it can be seen that the peaks and valleys of the surface undulations have a distance difference of 0.15 micrometers (μm) to 1 μm. The measurement of roughness judgment can include using SEM, transmission electron microscope (TEM), etc., to observe the surface undulations at the same appropriate magnification, and by taking a sample of unit length (for example, 10 μm) to compare the undulations, which is its roughness range. Here, "appropriate magnification" means that at least one surface can see at least 10 undulating peaks in the field of view of this magnification. Roughness (Rz) or average roughness (Ra).

[0081] As used herein, the terms "film" and / or "layer" may refer to any continuous or discontinuous structure and material (such as materials deposited by the methods disclosed herein). For example, the film and / or layer may include two-dimensional materials, three-dimensional materials, nanoparticles, or even partial or complete molecular layers, or partial or complete atomic layers, or atomic and / or molecular clusters. The film or layer may include a material or layer with pinholes, which may be at least partially continuous.

[0082] Although the terms first, second, third, etc. can be used to describe a variety of components, the components are not limited to these terms. These terms are only used to distinguish a single component from other components in the specification. The same terms may not be used in the claims, but may be replaced by first, second, third, etc. according to the order in which the components are declared in the claims. Therefore, in the following description, the first component may be the second component in the claims.

[0083] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and this disclosure, and should not be interpreted in an idealized or overly formal manner unless specifically defined herein.

[0084] It should be noted that the following embodiments may replace, reorganize, or mix the technical features in several different embodiments to implement other embodiments without departing from the spirit of the present disclosure.

[0085] The electronic device disclosed herein may include a power module, a semiconductor device, a semiconductor packaging device, a display device, an antenna device, a sensing device, a light-emitting device, or a splicing device, but is not limited thereto. The electronic device may include a bendable or flexible electronic device. The electronic device may include an electronic component. The electronic component may include a passive component, an active component, or a combination of the above, such as a capacitor, a resistor, an inductor, a variable capacitor, a filter, a diode, a transistor, a sensor, a micro-electromechanical system component (MEMS), a liquid crystal chip, etc., but is not limited thereto. The diode may include a light-emitting diode or a non-light-emitting diode. The diode includes a PN junction diode, a PIN diode, or a constant current diode. The light-emitting diode may, for example, include an organic light emitting diode (OLED), a sub-millimeter light-emitting diode (mini LED), a micro LED, a quantum dot light-emitting diode, fluorescence, phosphor, or other suitable materials, or a combination of the above, but is not limited thereto. The sensor may include, for example, capacitive sensors, optical sensors, electromagnetic sensors, fingerprint sensors (FPS), touch sensors, antennas, or pen sensors, but are not limited thereto. A display device will be used as an electronic device to illustrate the present disclosure below, but the present disclosure is not limited thereto. According to an embodiment of the present disclosure, the manufacturing method of the provided electronic device may be applied, for example, to a wafer-level package (WLP) process or a panel-level package (PLP) process, and may adopt a chip first process or a chip last / RDL first process, which will be further described in detail below. The electronic device referred to in the present disclosure may include a system on package (SoC), a system in package (SiP), an antenna in package (AiP) or a combination thereof, but is not limited thereto.

[0086] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0087] Figure 1A It is a cross-sectional schematic diagram of an electronic device according to an embodiment of the present disclosure. Figure 1B yes Figure 1A A top view of the second circuit structure. Please refer to Figure 1A , the electronic device 10a includes an electronic unit 100 and a circuit structure 200a. The circuit structure 200a is electrically connected to the electronic unit 100, and the circuit structure 200a includes a first circuit structure 210, a second circuit structure 220, a bonding pad 230a and an adjustment layer 240a. The first circuit structure 210 includes at least one first circuit layer (schematically showing two first circuit layers 212) and at least one first insulating layer (schematically showing two first insulating layers 214) surrounding the first circuit layer 212. The second circuit structure 220 is disposed between the electronic unit 100 and the first circuit structure 210. The second circuit structure 220 includes at least one second circuit layer (schematically showing three second circuit layers 222) and at least one second insulating layer (schematically showing three second insulating layers 224) surrounding the second circuit layer 222. The bonding pad 230a is disposed between the second circuit structure 220 and the first circuit structure 210. The adjustment layer 240a is disposed between the second circuit structure 220 and the first circuit structure 210 and surrounds the bonding pad 230a. The thermal expansion coefficient of the adjustment layer 240a is smaller than the thermal expansion coefficient of at least one of the first insulating layer 214 of the first circuit structure 210 and the second insulating layer 224 of the second circuit structure 220.

[0088] In detail, the electronic unit 100 of the present embodiment may be, for example, a passive component, an active component, or a combination thereof, such as a semiconductor structure, a silicon photonic chip, a capacitor, a resistor, an inductor, a variable capacitor, a filter, a diode, a transistor, a sensor, a micro-electromechanical system component (MEMS), a liquid crystal chip, etc., but not limited thereto. The electronic unit 100 has a back surface 101 and an active surface 103 opposite to each other and includes a pad 102 disposed on the active surface 103. The electronic unit 100 is, for example, electrically connected to the second circuit structure 220 of the circuit structure 200a through a connector 150. In one embodiment, the connector 150 is, for example, a eutectic solder, nickel, gold, copper, gallium, an alloy, a combination thereof, or other suitable materials, wherein the material of the eutectic solder is, for example, a gold-tin alloy, a silver-tin alloy, a nickel-gold-tin alloy, or other suitable materials or a combination thereof, but not limited thereto.

[0089] Furthermore, in the present embodiment, the first circuit structure 210 further includes a first conductive pattern layer 216 and a via 217. The first conductive pattern layer 216 is disposed on the first insulating layer 214 that is closest to the second circuit structure 220, and the via 217 electrically connects two adjacent first circuit layers 212 and electrically connects the first circuit layer 212 and the first conductive pattern layer 216. It should be noted that a dummy pattern D1 is included in the first conductive pattern layer 216 and / or the first circuit layer 212, and the dummy pattern D1 may not be electrically connected to the via 217. According to some embodiments, the metal ratio in the first circuit structure 210 can be adjusted by the dummy pattern D1, or the warping degree of the first circuit structure 210 can be further adjusted, but is not limited thereto. According to some embodiments, the heat dissipation capacity of the electronic device 10a can be improved by the design of the dummy pattern D1. Similarly, the second circuit structure 220 further includes a second conductive pattern layer 226 and a via 227. The second conductive pattern layer 226 is disposed on the second insulating layer 224 that is closest to the first circuit structure 210, and the via 227 electrically connects two adjacent second circuit layers 222 and electrically connects the second circuit layer 222 and the second conductive pattern layer 226. It should be noted that the second conductive pattern layer 226 and / or the second circuit layer 222 includes a dummy pattern D2, and the dummy pattern D2 may not be electrically connected to the via 227.

[0090] Please also refer to Figure 1A and Figure 1B , the first circuit structure 210 has a first total metal percentage, and the second circuit structure 220 has a second total metal percentage, wherein the ratio of the second total metal percentage to the first total metal percentage may be, for example, greater than or equal to 0.8 and less than or equal to 1.2, that is, the ratio of the first total metal percentage to the second total metal percentage is close, which means that the weight and stress generated by the first circuit structure 210 and the second circuit structure 220 are similar. It should be noted that the total metal percentage mentioned here refers to the volume percentage of the structure using metal materials in the circuit structure, that is, including the circuit layer, the conductive pattern layer, the through hole and the dummy pattern, and the metal material mentioned above may be, for example, copper, but is not limited thereto. In one embodiment, the material of the first insulating layer 214 and the second insulating layer 224 may be, for example, an organic resin, such as epoxy resin, high molecule, polymer, photosensitive polyimide (PSPI), Ajinomoto build-up film (ABF) or polyimide (PI), silicon oxide, silicon nitride, a combination of the above or other suitable materials, but is not limited thereto.

[0091] Please refer to Figure 1A, in this embodiment, there is a first pitch P1 between two adjacent lines of the first circuit layer 212, and there is a second pitch P2 between two adjacent conductive patterns in the first conductive pattern layer 216, where the second pitch P2 is less than the first pitch P1, that is, P2 < P1. There is a third pitch P3 between two adjacent lines of the second circuit layer 222, and there is a fourth pitch P4 between two adjacent conductive patterns in the second conductive pattern layer 226, where the third pitch P3 is less than the fourth pitch P4, that is, P3 < P4. Preferably, the ratio of the fourth pitch P4 to the second pitch P2 is, for example, greater than or equal to 0.9 and less than or equal to 1.1, that is, 0.9 ≤ P4 / P2 ≤ 1.1. The ratio of the third pitch P3 to the first pitch P1 is, for example, greater than or equal to 0.03 and less than or equal to 0.6, that is, 0.03 ≤ P3 / P1 ≤ 0.6. In addition, the conductive pattern of the first conductive pattern layer 216 of this embodiment may have a first width W1, and the conductive pattern of the second conductive pattern layer 226 may have a second width W2, where the first width W1 may, for example, be greater than or equal to the second width W2. The width referred to in this disclosure is, for example, the maximum width measured along the direction X. The conductive pattern of the first conductive pattern layer 216 of this embodiment may have a first thickness T1, and the conductive pattern of the second conductive pattern layer 226 may have a second thickness T2, where the first thickness T1 may, for example, be greater than or equal to the second thickness T2. The thickness referred to in this disclosure is, for example, the maximum thickness measured along the direction Z. In other words, the line width and line pitch of the first circuit layer 212 of the first circuit structure 210 may be greater than those of the second circuit layer 222, and the line width and line pitch of the first conductive pattern layer 216 of the first circuit structure 210 may be greater than or equal to those of the second conductive pattern layer 226 of the second circuit structure 220. Through the above design, the alignment accuracy between circuit structures can be improved, or the risk of signal transmission loss can be reduced, but it is not limited thereto.

[0092] In one embodiment, the circuit structure 200a may be, for example, a redistribution layer (RDL) for redistributing lines and / or further increasing the fan-out area of ​​lines, or different electronic units 100 may be electrically connected to each other through the circuit structure 200a, and the type of the circuit structure 200a is not limited here. For example, the circuit structure 200a may be applied to wafer level chip packaging (Wafer Level Chip Scale Package, WLCSP), wafer level packaging (Wafer Level Package, WLP), panel level packaging (Panel Level Package, PLP) or other electronic device manufacturing methods, but is not limited thereto. Through the above design, each chip or electronic unit can be electrically connected to the circuit structure 200a through a bonding pad or other bonding element. Alternatively, the redistribution structure may be a substrate used for wiring an electrical interface between one connection and another connection. The purpose of the redistribution layer is to expand the connection to a wider spacing or to reroute the connection to another connection with a different spacing. According to some embodiments, reference may be made to Figure 3 , the circuit structure 200a may include an electronic unit, that is, the electronic unit may be embedded in or formed in the circuit structure 200a.

[0093] Please refer to Figure 1A , the bonding pad 230a of the present embodiment is disposed between the first conductive pattern layer 216 of the first circuit structure 210 and the second conductive pattern layer 226 of the second circuit structure 220. In one embodiment, the bonding pad 230a may be, for example, a conductive bump, such as a solder bump or a micro bump, but is not limited thereto. The second conductive pattern layer 226 is bonded to the first conductive pattern layer 216 through the bonding pad 230a, so that the second circuit structure 220 is electrically connected to the first circuit structure 210. That is, in the present embodiment, the second circuit structure 220 may be bonded to the first circuit structure 210 by a solder bonding method, a micro bump bonding method, or a hybrid bonding method, so as to form a circuit structure 200a.

[0094] Furthermore, in addition to covering the first conductive pattern layer 216, the bonding pad 230a and the second conductive pattern layer 226, the adjustment layer 240a of the present embodiment may also extend to cover the first peripheral surface 211 of the first circuit structure 210 and the second peripheral surface 221 of the second circuit structure 220. In one embodiment, the material of the adjustment layer 240a is, for example, an organic material, an inorganic material or a composite material, which may be a single-layer structure, a multi-layer structure layer or an ultra-thin substrate, but is not limited thereto. In one embodiment, the material of the adjustment layer 240a may be a thermosetting material or a photocurable material, which may be cured by heat or light, but is not limited thereto.

[0095] In particular, the coefficient of thermal expansion (CTE) of the adjustment layer 240a may be smaller than the CTE of at least one of the first insulating layer 214 of the first circuit structure 210 and the second insulating layer 224 of the second circuit structure 220, that is, the CTE of the adjustment layer 240a may be smaller than the CTE of the first insulating layer 214 of the first circuit structure 210, or the CTE of the adjustment layer 240a may be smaller than the CTE of the second insulating layer 224 of the second circuit structure 220, or the CTE of the adjustment layer 240a may be smaller than the CTE of the first insulating layer 214 of the first circuit structure 210 and the CTE of the second insulating layer 224 of the second circuit structure 220, thereby reducing the warpage of the circuit structure 200a during the manufacturing process. According to some embodiments, the CTE of the adjustment layer 240a may be less than or equal to 10 ppm / °C, less than or equal to 5 ppm / °C, or less than or equal to 3 ppm / °C. According to some embodiments, the thermal expansion coefficient of the adjustment layer 240a is less than 0.9 times the thermal expansion coefficient of the first insulating layer 214, or the thermal expansion coefficient of the adjustment layer 240a is less than 0.8 times the thermal expansion coefficient of the first insulating layer 214. And according to some embodiments, the thermal expansion coefficient of the adjustment layer 240a is less than 0.9 times the thermal expansion coefficient of the second insulating layer 224, or the thermal expansion coefficient of the adjustment layer 240a is less than 0.8 times the thermal expansion coefficient of the second insulating layer 224.

[0096] On the other hand, the Young's module of the adjustment layer 240a may be greater than the Young's module of at least one of the first insulating layer 214 and the second insulating layer 224, that is, the Young's module of the adjustment layer 240a may be greater than the Young's module of the first insulating layer 214, or the Young's module of the adjustment layer 240a may be greater than the Young's module of the second insulating layer 224, or the Young's module of the adjustment layer 240a may be greater than the Young's module of the first insulating layer 214 and the Young's module of the second insulating layer 224, thereby reducing the warping of the circuit structure 200a during the manufacturing process. For example, the adjustment layer 240a may be made of an underfill material, whose Young's module ranges from 9.5 GPa to 15 GPa, and the first insulating layer 214 and the second insulating layer 224 may be made of materials such as photosensitive polyimide (PSPI) or ajinomoto forming film (ABF), whose Young's module ranges from 2 GPa to 9 GPa, but are not limited thereto. Since the adjustment layer 240a and the first insulating layer 214 and the second insulating layer 224 are made of different materials, the thermal expansion trend of the adjustment layer 240a is also different from the thermal expansion trend of the first insulating layer 214 of the first circuit structure 210 and the second insulating layer 224 of the second circuit structure 220. Here, the thermal expansion trend is that after the material layer is thermally expanded, the two sides may bend upward (such as a tortoise shell shape) or bend downward (such as a bowl shape) along the direction Z. By making the thermal expansion trend of the adjustment layer 240a different from the thermal expansion trend of the first insulating layer 214 and the second insulating layer 224, that is, the warping directions are, for example, opposite directions, the warping can be slowed down, so that the electronic device 10a can have better structural reliability.

[0097] In addition, the electronic device 10a of the present embodiment further includes a packaging layer 300, which surrounds the electronic unit 100 and the circuit structure 200a. In other words, in a cross-sectional view, the packaging layer 300 may at least contact one side of the electronic unit 100. Here, the packaging layer 300 at least covers the back side 101 of the electronic unit 100 and the adjustment layer 240a, but is not limited thereto. In one embodiment, the material of the packaging layer 300 is, for example, epoxy molding compound (EMC), wherein the packaging layer 300 is, for example, formed by a molding process, but is not limited thereto. Furthermore, the electronic device 10a of the present embodiment further includes a glue layer 350, which is disposed between the electronic unit 100 and the second circuit structure 220, wherein the glue layer 350 at least covers the pad 102 and the connector 150 of the electronic unit 100. In one embodiment, the glue layer 350 may be, for example, an underfill layer that can directly contact the active surface 103 of the electronic unit 100 and the surface S1 of the second circuit structure 220 that is relatively far away from the first circuit structure 210, and fill the space between two adjacent connectors 150 and the space between two adjacent pads 102. In one embodiment, the glue layer 350 is used to protect the connector 150 or ensure the connection between the electronic unit 100 and the circuit structure 200a. In one embodiment, the material of the glue layer 350 may be, for example, resin, epoxy resin or molding compound, but is not limited thereto. In addition, the electronic device 10a of this embodiment also includes a solder ball 400, which is disposed on the surface S2 of the first circuit structure 210 that is relatively far away from the second circuit structure 220, wherein the electronic device 10a can be electrically connected to an external circuit through the solder ball 400.

[0098] In short, the adjustment layer 240a of the present embodiment is arranged between the second circuit structure 220 and the first circuit structure 210 and surrounds the bonding pad 230a, wherein the thermal expansion coefficient of the adjustment layer 240a is smaller than the thermal expansion coefficient of at least one of the first insulating layer 214 of the first circuit structure 210 and the second insulating layer 224 of the second circuit structure 220, thereby effectively alleviating board warping, ensuring the process accuracy of the corresponding bonding pad (i.e., the second circuit layer 222) of the electronic unit 100 located at the top layer, and enabling the electronic device 10a disclosed herein to have better structural reliability.

[0099] It should be noted that the following embodiments use the component numbers and some contents of the previous embodiments, wherein the same number is used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can refer to the previous embodiments, and the following embodiments will not be repeated.

[0100] Figure 2 is a cross-sectional schematic diagram of an electronic device according to another embodiment of the present disclosure. Figure 1A and Figure 2The electronic device 10b of this embodiment and Figure 1A The electronic device 10a of the embodiment is similar to the electronic device 10a of the embodiment, and the difference between the two is that: in the embodiment, the bonding pad 230b of the circuit structure 200b can be, for example, a conductive material layer, and its material can be, for example, a solid solution of the first conductive pattern layer 216 or the second conductive pattern layer 226, or according to some embodiments, it can be, for example, ENIG (Electroless Nickel Immersion Gold), ENPIG (Electroless Nickel Palladium Gold), SnAu, SnAg, SnIn, but not limited thereto. Furthermore, the peripheral surface 241b of the adjustment layer 240b of the embodiment can be aligned with the first peripheral surface 211 of the first circuit structure 210 or the second peripheral surface 221 of the second circuit structure 220. According to some embodiments, the first peripheral surface 211 of the first circuit structure 210 and the second peripheral surface 221 of the second circuit structure 220 can be misaligned, or, along the direction X, the width of the first circuit structure 210 is different from the width of the second circuit structure 220. The adjustment layer 240b does not cover the first peripheral surface 211 of the first circuit structure 210 and the adjustment layer 240b covers at least a portion of the second peripheral surface 221 of the second circuit structure 220. In addition, the geometric center C1 of the first conductive pattern layer 216 and the geometric center C2 of the second conductive pattern layer 226 in this embodiment can be staggered. In other words, the projections of the geometric center C1 and the geometric center C2 on the same plane have a spacing. Here, the geometric center is the intersection of the diagonal lines of the entire structural layer, wherein at least a portion of the second conductive pattern layer 226 does not overlap or partially overlaps the first conductive pattern layer 216. In addition, a plurality of electronic units 100' may be included, wherein the electronic units 100' may be stacked along the direction Z.

[0101] Figure 3 is a cross-sectional schematic diagram of an electronic device according to another embodiment of the present disclosure. Figure 1A and Figure 3, the electronic device 10c of this embodiment is similar to the electronic device 10a of FIG. 1 , and the difference between the two is that: in this embodiment, the peripheral surface 241c of the adjustment layer 240c of the circuit structure 200c is aligned with the first peripheral surface 211 of the first circuit structure 210 and the second peripheral surface 221 of the second circuit structure 220. That is, the adjustment layer 240c does not cover the first peripheral surface 211 of the first circuit structure 210 and the second peripheral surface 221 of the second circuit structure 220. In addition, the electronic device 10c of this embodiment also includes a heat dissipation component 450, which is disposed on the back surface 101 of the electronic unit 100 relatively away from the circuit structure 200a, and can effectively dissipate heat from the electronic unit 100, and can effectively improve the heat dissipation effect of the electronic device 10c. The heat dissipation component 450 may include a heat dissipation adhesive 454 and a heat sink 452, and the heat dissipation adhesive 454 is disposed between the electronic unit 100 and the heat sink 452. According to some embodiments, the heat dissipation adhesive 454 may contact at least part of the side of the packaging layer 300. In addition, the electronic unit 100c may be embedded or disposed in a circuit structure, for example, in the second circuit structure 220, and the electronic unit 100c may be electrically connected to the electronic unit 100, but not limited thereto. According to some embodiments, the electronic unit 100c and the electronic unit 100 may be staggered, but not limited thereto.

[0102] Figure 4 is a cross-sectional schematic diagram of an electronic device according to another embodiment of the present disclosure. Figure 1A and Figure 4 The electronic device 10d of this embodiment is Figure 1AThe electronic device 10d is similar to the electronic device 10a of the embodiment, and the difference between the two is that: in this embodiment, the electronic device 10d includes two electronic units 100a and 100b, wherein the electronic units 100a and 100b are respectively electrically connected to the second circuit structure 220 of the circuit structure 200a. In one embodiment, the electronic unit 100a can be, for example, a substrate integrated circuit or a memory, but is not limited thereto. In one embodiment, the electronic unit 100a can be respectively electrically connected to the second circuit structure 220 through the connector 150. In one embodiment, the electronic unit 100b may be, for example, a passive component, wherein the passive component may be, for example, a surface mount device (SMD), a capacitor, an inductor, a resistor or other suitable electronic components, but not limited thereto. In other words, the second circuit structure 220 may be electrically connected to the electronic units 100a and 100b through a connector 150 or other bonding elements. In addition, the packaging layer 300 of the present embodiment exposes the back surface 101a of the electronic unit 100a, but covers the back surface 101b of the electronic unit 100b. In other words, the back surface 101a of the electronic unit 100a is exposed outside the packaging layer 300, which may have a better heat dissipation effect, and the packaging layer 300 covers the electronic unit 100b to prevent the electronic unit 100b from being attacked by water and oxygen, which may have better reliability. According to some embodiments, a glue layer 370 may be further disposed between the electronic unit 100b and the second circuit structure 220, but not limited thereto.

[0103] FIG. 5A to FIG. 5E is a cross-sectional diagram of a method for manufacturing an electronic device according to an embodiment of the present disclosure. Figure 5A Regarding the manufacturing method of the electronic device of the present embodiment, first, a first circuit structure 210 and a second circuit structure 220 are provided. The first circuit structure 210 includes a first insulating layer 214 extending to a first circuit layer 212, surrounding the first circuit layer 212, and a first groove E1 passing through the first insulating layer 214. Herein, the first circuit structure 210 is formed on a substrate 30, wherein a release film 35 is provided between the substrate 30 and the first circuit structure 210. The second circuit structure 220 includes a second circuit layer 222, a second insulating layer 224 surrounding the second circuit layer 222, and a second groove E2 passing through the second insulating layer 224. The first groove E1 is provided corresponding to the second groove E2. Herein, the second circuit structure 220 is formed on a substrate 40, wherein a release film 45 is provided between the substrate 40 and the second circuit structure 220.

[0104] Furthermore, in the present embodiment, the first circuit structure 210 further includes a first conductive pattern layer 216 and a via 217. The first conductive pattern layer 216 is disposed on the first insulating layer 214 that is closest to the second circuit structure 220, and the via 217 electrically connects the first circuit layer 212 and the first conductive pattern layer 216. Similarly, the second circuit structure 220 further includes a second conductive pattern layer 226 and a via 227. The second conductive pattern layer 226 is disposed on the second insulating layer 224 that is closest to the first circuit structure 210, and the via 227 electrically connects two adjacent second circuit layers 222 and electrically connects the second circuit layer 222 and the second conductive pattern layer 226.

[0105] Next, please refer to Figure 5A , providing a bonding pad 230 and an adjustment layer 240 between the first circuit structure 210 and the second circuit structure 220. Here, the bonding pad 230 is formed on the second circuit structure 220, and the adjustment layer 240 is formed on the first circuit structure 210, but it is not limited thereto. The thermal expansion coefficient of the adjustment layer 240 is smaller than the thermal expansion coefficient of at least one of the first insulating layer 214 of the first circuit structure 210 and the second insulating layer 214 of the second circuit structure 220. That is, the thermal expansion coefficient of the adjustment layer 240 may be smaller than the thermal expansion coefficient of the first insulating layer 214 of the first circuit structure 210, or the thermal expansion coefficient of the adjustment layer 240 may be smaller than the thermal expansion coefficient of the second insulating layer 224 of the second circuit structure 220, or the thermal expansion coefficient of the adjustment layer 240 may be smaller than the thermal expansion coefficient of the first insulating layer 214 of the first circuit structure 210 and the thermal expansion coefficient of the second insulating layer 224 of the second circuit structure 220, thereby making the circuit structure 200 (please refer to Figure 5B ) to mitigate warpage during the manufacturing process.

[0106] Next, please refer to Figure 5B , for example, by a thermal pressing process, the first circuit structure 210 and the second circuit structure 220 are bonded through the bonding pad 230. Here, the bonding pad 230 is located between the first conductive pattern layer 216 and the second conductive pattern layer 226, and the adjustment layer 240 surrounds the bonding pad 230 and fills the first groove E1 and the second groove E2. The adjustment layer 240 is in a liquid state and has not yet solidified at this stage, and the liquid or fluid adjustment layer 240 can flow to fill the first groove E1 and the second groove E2 during thermal pressing. In one embodiment, the material of the adjustment layer 240 can be a thermosetting material or a photocurable material, but is not limited thereto. Afterwards, the adjustment layer 240 can be cured by thermal curing or photocuring. Here, the first circuit structure 210, the second circuit structure 220, the bonding pad 230 and the adjustment layer 240 can be defined as the circuit structure 200, which means that this step has completed the production of the circuit structure 200.

[0107] Next, please also refer to Figure 5B as well as Figure 5C The release film 45 and the substrate 40 thereon are removed by peeling to expose the surface S1 of the second circuit structure 220. Next, the electronic unit 100 is disposed on the second circuit structure 220, wherein the electronic unit 100 is electrically connected to the second circuit structure 220 of the circuit structure 200 through the connector 150, for example.

[0108] Next, please refer to Figure 5D , forming an adhesive layer 350 between the electronic unit 100 and the second circuit structure 220, wherein the adhesive layer 350 at least covers the pads 102 and the connector 150 of the electronic unit 100. In one embodiment, the adhesive layer 350 is used to protect the connector 150 or ensure the connection between the electronic unit 100 and the circuit structure 200.

[0109] Afterwards, please also refer to Figure 5D and Figure 5E , a packaging material layer 300a is formed on the substrate 30 to cover the electronic unit 100 and the circuit structure 200. Here, the packaging material layer 300a completely covers the electronic unit 100 and the adjustment layer 240. Then, a portion of the packaging material layer 300a can be selectively removed by grinding to expose the back side 101 of the electronic unit 100, so as to form a packaging layer 300 surrounding the electronic unit 100 and the circuit structure 200.

[0110] Next, please refer to Figure 5D and Figure 5E , the release film 35 and the substrate 30 thereon are removed by peeling, thereby exposing the surface S2 of the first circuit structure 210. Next, solder balls 400 are formed on the surface S2 of the first circuit structure 210. Finally, a singulation process is performed along the first groove E1 and the second groove E2, and the adjustment layer 240 is cut to form the electronic device 10, wherein the electronic unit 100 in the electronic device 10 is electrically connected to the circuit structure 220. At this point, the manufacture of the electronic device 10 has been completed.

[0111] It should be noted that the individual cutting process can select the position of the cutting line according to the use requirements. For example, the peripheral surface of the adjustment layer 240 can be aligned with the peripheral surface of the first circuit structure 210 and the second circuit structure 220; or, the peripheral surface of the adjustment layer 240 can be aligned with the peripheral surface of the packaging layer 300; or, the adjustment layer 240 can extend to cover the peripheral surface of the first circuit structure 210 and the second circuit structure 220, but it is not limited thereto.

[0112] FIG. 6A to FIG. 6C is a cross-sectional schematic diagram of a partial step of a method for manufacturing an electronic device according to another embodiment of the present disclosure. Figure 5A and Figure 6BThe manufacturing method of the electronic device of this embodiment is similar to the manufacturing method of the electronic device described above, and the difference between the two is that in this embodiment, the structure of the adjustment layer 240d is different from the structure of the adjustment layer 240 described above.

[0113] For details, please also refer to Fig. 6A and Figure 6B In this embodiment, a bonding pad 230d and an adjustment layer 240d are provided between the first circuit structure 210 and the second circuit structure 220. Here, the bonding pad 230d is formed on the first conductive pattern layer 216 of the first circuit structure 210 and on the second conductive pattern layer 226 of the second circuit structure 220. Next, a through-substrate via (TSV) substrate structure 242 is provided between the first conductive pattern layer 216 and the second conductive pattern layer 226. Here, the through-substrate via substrate structure 242 may include a substrate 243, a through-hole 244 passing through the substrate 243, and a build-up structure disposed on opposite sides of the substrate 243 and including a via 245, a build-up circuit layer 246, and a pad 247. The via 245 electrically connects the build-up circuit layer 246 and the through-hole 244, and the pad 247 electrically connects the build-up circuit layer 246. The substrate 243 may include glass, silicon wafer, ceramic, organic material, combinations thereof or other suitable materials, but is not limited thereto.

[0114] Next, please refer to Fig. 6A and Figure 6B , the first circuit structure 210 and the second circuit structure 220 are bonded by the bonding pad 230d in a thermal compression manner. At this time, the pad 247 of the through-hole substrate structure 242 is bonded to the bonding pad 230d located on the second conductive pattern layer 226 and the first conductive pattern layer 216, so that the second circuit structure 220 is bonded to the first circuit structure 210. Next, the adjustment material 248 is filled between the second circuit structure 220 and the through-hole substrate structure 242 and between the first circuit structure 210 and the through-hole substrate structure 242. At this time, the adjustment material 248 surrounds the bonding pad 230d and is filled in the first trench E1 and the second trench E2. Here, the through-hole substrate structure 242 and the adjustment material 248 are defined as the adjustment layer 240d.

[0115] Next, please refer to Fig. 6A and Figure 6B, remove the release film 45 and the substrate 40 thereon by peeling, and expose the surface S1 of the second circuit structure 220. Next, the electronic unit 100 is set on the second circuit structure 220, wherein the electronic unit 100 is electrically connected to the second circuit structure 220 of the circuit structure 200 through the connector 150, for example. Next, a glue layer 350 can be formed between the electronic unit 100 and the second circuit structure 220, wherein the glue layer 350 at least covers the pad 102 of the electronic unit 100 and the connector 150. Herein, the first circuit structure 210, the second circuit structure 220, the bonding pad 230d and the adjustment layer 240d are defined as the circuit structure 200d.

[0116] Afterwards, a packaging layer may be selectively formed to cover the electronic unit 100 and the circuit structure 200. Next, please refer to FIG. 6B and FIG. Figure 6C The release film 35 and the substrate 30 thereon are removed by peeling to expose the surface S2 of the first circuit structure 210. Then, solder balls 400 are formed on the surface S2 of the first circuit structure 210 to complete the manufacture of the electronic device 10'.

[0117] Figure 7 is a cross-sectional schematic diagram of a partial step of a method for manufacturing an electronic device according to another embodiment of the present disclosure. Figure 6C and Figure 7 The manufacturing method of the electronic device of the present embodiment is similar to the manufacturing method of the electronic device described above, and the difference between the two is that in the present embodiment, the pad 247 on one side of the through-hole substrate structure 242 is bonded to the first conductive pattern layer 216 of the first circuit structure 210, and the pad 247 on the other side of the through-hole substrate structure 242 is bonded to the second conductive pattern layer 226 of the second circuit structure 220, so that the second circuit structure 220 is bonded to the first circuit structure 210. Compared with the solder bonding method and the microbump bonding method, the hybrid bonding method can have better electrical performance (such as shorter interconnects, lower resistance, lower energy consumption and low delay, etc.). In addition, the packaging layer 300 can be provided to surround the through-hole substrate structure 242, the first circuit structure 210, the second circuit structure 220 and the electronic component 100, which can improve the reliability of the electronic device 10", but is not limited thereto.

[0118] In summary, in the embodiments of the present disclosure, the adjustment layer is arranged between the second circuit structure and the first circuit structure and surrounds the bonding pad, wherein the thermal expansion coefficient of the adjustment layer is smaller than the thermal expansion coefficient of one of the first insulating layer of the first circuit structure and the second insulating layer of the second circuit structure, thereby effectively alleviating the warping of the board, ensuring the process accuracy of the corresponding bonding pad of the electronic unit located at the top layer, and enabling the electronic device of the present disclosure to have better structural reliability.

[0119] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. An electronic device, characterized in that: include: Electronic unit; as well as A circuit structure electrically connected to the electronic unit, the circuit structure comprising: A first circuit structure includes at least one first circuit layer and at least one first insulating layer surrounding the at least one first circuit layer; A second circuit structure is disposed between the electronic unit and the first circuit structure, wherein the second circuit structure comprises at least one second circuit layer and at least one second insulating layer surrounding the at least one second circuit layer; a bonding pad disposed between the second circuit structure and the first circuit structure; and an adjustment layer, disposed between the second circuit structure and the first circuit structure and surrounding the bonding pad; The thermal expansion coefficient of the adjustment layer is smaller than the thermal expansion coefficient of at least one of the at least one first insulation layer of the first circuit structure and the at least one second insulation layer of the second circuit structure.

2. The electronic device according to claim 1, characterized in that: The thermal expansion trend of the adjustment layer is different from the thermal expansion trend of at least one of the at least one first insulating layer of the first circuit structure and the at least one second insulating layer of the second circuit structure.

3. The electronic device according to claim 1, characterized in that: The bonding pad is disposed between the first conductive pattern layer of the first circuit structure and the second conductive pattern layer of the second circuit structure, and a first width of the first conductive pattern layer is greater than or equal to a second width of the second conductive pattern layer.

4. The electronic device according to claim 3, characterized in that: A first thickness of the first conductive pattern layer is greater than or equal to a second thickness of the second conductive pattern layer.

5. The electronic device according to claim 3, characterized in that: The geometric center of the first conductive pattern layer and the geometric center of the second conductive pattern layer are staggered.

6. The electronic device according to claim 1, characterized in that: Also includes: The packaging layer surrounds the electronic unit and the circuit structure.

7. The electronic device according to claim 1, characterized in that: Also includes: The heat dissipation component is arranged on the back side of the electronic unit which is relatively far away from the electronic unit.

8. An electronic device, characterized in that: include: Electronic unit; as well as A circuit structure electrically connected to the electronic unit, the circuit structure comprising: A first circuit structure includes at least one first circuit layer and at least one first insulating layer surrounding the at least one first circuit layer; A second circuit structure is disposed between the electronic unit and the first circuit structure, wherein the second circuit structure comprises at least one second circuit layer and at least one second insulating layer surrounding the at least one second circuit layer; a bonding pad disposed between the second circuit structure and the first circuit structure; and an adjustment layer, disposed between the second circuit structure and the first circuit structure and surrounding the bonding pad; The thermal expansion trend of the adjustment layer is different from the thermal expansion trend of at least one of the at least one first insulating layer of the first circuit structure and the at least one second insulating layer of the second circuit structure.

9. A method for manufacturing an electronic device, characterized in that: include: A first circuit structure and a second circuit structure are provided, wherein the first circuit structure comprises at least one first circuit layer, at least one first insulating layer surrounding the at least one first circuit layer, and at least one first groove passing through the at least one first insulating layer, and the second circuit structure comprises at least one second circuit layer, at least one second insulating layer surrounding the at least one second circuit layer, and at least one second groove passing through the at least one second insulating layer, wherein the at least one first groove is arranged corresponding to the at least one second groove; Providing a bonding pad and an adjustment layer between the first circuit structure and the second circuit structure, wherein the thermal expansion coefficient of the adjustment layer is smaller than the thermal expansion coefficient of at least one of the at least one first insulating layer of the first circuit structure and the at least one second insulating layer of the second circuit structure; The first circuit structure and the second circuit structure are bonded via the bonding pad, and the adjustment layer surrounds the bonding pad and fills the at least one first groove and the at least one second groove; Disposing at least one electronic unit on the second circuit structure; as well as A singulation process is performed along the at least one first groove and the at least one second groove to form at least one electronic device, wherein the first circuit structure, the second circuit structure, the bonding pad and the adjustment layer are defined as a circuit structure, and the at least one electronic unit is electrically connected to the circuit structure.

10. The method for manufacturing an electronic device according to claim 9, characterized in that: Also includes: Before performing the singulation process along the at least one first trench and the at least one second trench, a packaging layer is formed to surround the electronic unit and the circuit structure.

Images