Semiconductor packaging structure
By using electrical connection elements of non-metal core and metal film in the panel-level packaging structure, the problem of electrical connection elements being unable to get close to the grains caused by the copper block process is solved, and high-density grain arrangement is achieved.
Patent Information
- Application Number
- CN202311430444.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-10-31
- Publication Date
- 2025-05-02
AI Technical Summary
In the panel-level packaging structure, the copper block process causes burrs or concave bumps on the sides of the electrical connection elements to be unable to get close to the grains, limiting the high-density grain arrangement.
An electrical connection element containing a non-metallic core and a metal film is used. The non-metallic core is selected from a substrate that can form a flat cutting surface, such as a silicon wafer or a mold sealing resin, and the metal film is flat on the sides to avoid burrs or concave convexity.
By using electrical connection elements on flat sides, burrs or concaves and convexities are avoided when contacting grains, the horizontal spacing between the electrical connection elements and grains is achieved, and a high-density grain arrangement is achieved.
Smart Images
Figure CN119920793A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a semiconductor packaging structure, and in particular to a semiconductor packaging structure involving a panel level package. Background Art
[0002] Panel-level packaging is a process of cutting and separating chips into multiple dies, arranging and pasting these dies on a carrier, and then packaging them simultaneously in the same process step. Panel-level packaging has been a technology that has emerged in recent years and has received widespread attention. Compared with traditional wafer-level packaging, panel-level packaging has the advantages of high production efficiency, low production cost, and suitability for large-scale production.
[0003] In the current panel-level packaging structure, copper blocks are usually used as electrical connection elements to connect different circuit layers. At present, the development of panel-level packaging requires high-density die arrangement. However, since the aforementioned copper block manufacturing process involves cutting or etching of copper plates, burrs or unevenness will occur on the side of the copper block, resulting in the inability to reduce the distance between the copper block and the die. Summary of the invention
[0004] In view of the above problems, the present invention provides a semiconductor packaging structure, which helps to solve the problem that the electrical connection elements in the panel-level packaging structure cannot be arranged close to the die.
[0005] The semiconductor packaging structure disclosed in the present invention comprises a packaging layer, a crystal grain, a first metal layer, a second metal layer and an electrical connection element. The crystal grain is arranged in the packaging layer. The first metal layer and the second metal layer are arranged in the packaging layer, and the first metal layer and the second metal layer are respectively arranged on opposite sides of the crystal grain. The electrical connection element is arranged in the packaging layer. The first metal layer is electrically connected to the second metal layer through the electrical connection element. The electrical connection element comprises a non-metal core and a metal film located on the surface of the non-metal core.
[0006] According to the semiconductor packaging structure disclosed in the present invention, the electrical connection element for electrically connecting two metal layers on opposite sides of a die to each other includes a non-metallic core and a metal film. In one embodiment, the non-metallic substrate is selected from a substrate that can form a flat cutting surface, such as a silicon wafer with a single directionality. In one embodiment, the non-metallic substrate is selected from a molding resin that can be processed at low cost. In this way, the non-metallic core taken from the non-metallic substrate has a flat side, and the metal film is also flat on the side. When this electrical connection element is used for panel-level packaging, it can prevent the electrical connection element from having burrs or bumps that touch adjacent die, which is beneficial to shorten the horizontal spacing between the electrical connection element and the die, and achieve a high-density die arrangement.
[0007] The above description of the content of the present invention and the following description of the implementation modes are used to demonstrate and explain the principles of the present invention and to provide further explanation for the protection scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS
[0008] Figure 1 FIG. 4 is a schematic diagram of a semiconductor package structure according to an embodiment of the present invention.
[0009] Figures 2 to 5 FIG. 1 is a schematic diagram of manufacturing an electrical connection element according to an embodiment of the present invention.
[0010] Figures 6 to 9 FIG. 4 is a schematic diagram of manufacturing an electrical connection element according to another embodiment of the present invention.
[0011] Figures 10 to 17 For manufacturing Figure 1 Schematic diagram of the process of semiconductor packaging structure.
[0012] [Description of Reference Numerals]
[0013] 1: Semiconductor packaging structure
[0014] 2: Cutting machine
[0015] 10: Encapsulation layer
[0016] 20: Semiconductor components
[0017] 210: Grain
[0018] 220: Electrical connection point
[0019] 230: Protective layer
[0020] 30, 40: Metal layer
[0021] 410: Metal pad
[0022] 50: Electrical connection components
[0023] 510: Non-metallic core
[0024] 511: Side
[0025] 520: Metal film
[0026] 100, 100a, 300, 300a, 300b: Temporary carrier board
[0027] 101: Grooves
[0028] 200: Silicon wafer
[0029] S: Cutting path DETAILED DESCRIPTION
[0030] The detailed features and advantages of the present invention are described in detail in the following embodiments, and the contents are sufficient for ordinary technicians in the field to understand the technical content of the present invention and implement it accordingly. According to the contents, protection scope and drawings disclosed in this specification, ordinary technicians in the field can easily understand the present invention. The following examples further illustrate the viewpoints of the present invention in detail, but do not limit the scope of the present invention in any viewpoint.
[0031] Please refer to Figure 1 , which is a schematic diagram of a semiconductor package structure according to an embodiment of the present invention. In this embodiment, the semiconductor package structure 1 includes a package layer 10, a semiconductor element 20, a metal layer 30, a metal layer 40 and an electrical connection element 50.
[0032] The material of the packaging layer 10 can be an organic composite material, a resin composite material, a macromolecular composite material, a polymer composite material or other solid molding materials. For example, the packaging layer 10 can be an epoxy resin packaging layer.
[0033] The semiconductor element 20 is disposed in the packaging layer 10. The semiconductor element 20 may include a die 210 disposed in the packaging layer 10, an electrical connection point 220, and a protective layer 230. The material of the die 210 may be a semiconductor element, such as silicon, silicon carbide, or a semiconductor element of group III-V semiconductor. The electrical connection point 220 is formed on the surface of one side of the die 210. In one embodiment, it is preferred to form the protective layer 230 on the top side of the die 210 and expose the electrical connection point 220. The protective layer 230 can provide sufficient buffering and support for the semiconductor element 20 to prevent the semiconductor element 20 from being crushed due to being squeezed by the packaging layer 10 or the metal layers 30, 40.
[0034] The metal layer 30 is disposed in the packaging layer 10. The metal layer 30 may fill the opening formed in the protection layer 230 and be electrically connected to the electrical connection point 220. The metal layer 40 is disposed in the packaging layer 10. The metal layer 30 and the metal layer 40 are respectively disposed on opposite sides of the semiconductor element 20. Specifically, the electrical connection point 220, the protection layer 230 and the metal layer 30 may be disposed on the front side of the die 210, and the metal layer 40 may be disposed on the back side of the die 210.
[0035] The electrical connection element 50 is disposed in the packaging layer 10, and the electrical connection element 50 includes a non-metal core 510 and a metal film 520 located on the surface of the non-metal core 510. The metal layer 30 is electrically connected to the metal layer 40 through the electrical connection element 50. The electrical connection point 220 of the semiconductor element 20 can be led out to the metal layer 40 through the metal layer 30 and the metal film 520 of the electrical connection element 50. Further, the electrical signal can reach the metal layer 40 from the electrical connection point 220 through the metal layer 30 and the electrical connection element 50 in sequence.
[0036] In this embodiment, the non-metal core 510 of the electrical connection element 50 may be non-conductive. Further, the material of the non-metal core 510 may be silicon. Here, the material of the non-metal core 510 may be selected from an electrically insulating material. More specifically, the material of the non-metal core 510 may be selected from undoped silicon, silicon nitride, silicon oxide, or a molding compound resin.
[0037] In this embodiment, the material of the metal film 520 of the electrical connection element 50 may be the same as the material of the metal layers 30 and 40. Furthermore, the materials of the metal film 520 and the metal layers 30 and 40 may both be copper or at least partially contain copper.
[0038] In this embodiment, the die 210 of the semiconductor element 20 and the electrical connection element 50 may be located in the same layer. Specifically, the semiconductor element 20 and the electrical connection element 50 may be disposed on the same carrier, and then a packaging layer 10 surrounding the semiconductor element 20 and the electrical connection element 50 may be formed.
[0039] In the present embodiment, the packaging layer 10 exposes at least one of the metal layer 30 and the metal layer 40. Further, the packaging layer 10 may expose the metal layer 40, and the metal layer 40 may include two spaced metal pads 410. The two metal pads 410 are respectively connected to the semiconductor element 20 and the metal film 520 of the electrical connection element 50. Further, one of the metal pads 410 is disposed on the back side of the die 210, and the other metal pad 410 is pad-connected to the metal film 520. In other embodiments, the packaging layer 10 may expose both the metal layer 30 and the metal layer 40.
[0040] Figures 2 to 5 FIG. 1 is a schematic diagram of manufacturing an electrical connection element according to an embodiment of the present invention. Figure 2 As shown, a tape or a substrate with an adhesive surface is provided as a temporary carrier 100, and a silicon wafer is placed on the temporary carrier 100. The silicon wafer is cut by a saw 2 to form a plurality of silicon blocks. These silicon blocks can each serve as a non-metal core 510 of the electrical connection element 50.
[0041] like Figure 3 As shown, a metal film 520 is formed on the surface of the non-metal core 510. Specifically, a copper film can be deposited on the surface of the non-metal core 510 by sputtering, electroplating or chemical plating as the metal film 520. Figure 4 and Figure 5 As shown, the temporary carrier 100 is removed and the metal film 520 is cut off to obtain a plurality of electrical connection elements 50. In addition, before depositing the copper film, a titanium film or a nickel film may be selectively deposited on the surface of the non-metallic core 510 as an adhesive layer to prevent the copper film from peeling off.
[0042] Figures 6 to 9 FIG. 1 is a schematic diagram of manufacturing an electrical connection element according to another embodiment of the present invention. Figure 6 As shown, a tape or a substrate with an adhesive surface is provided as a temporary carrier 100, and a silicon wafer 200 is placed on the temporary carrier 100. The silicon wafer 200 is cut in half by a saw 2 to form a plurality of grooves 101.
[0043] like Figure 6 and Figure 7 As shown, the temporary carrier 100 is removed, and a metal film 520 is formed on the surface of the silicon wafer 200 and in the trench 101. Specifically, a copper film can be deposited as the metal film 520 by sputtering, electroplating or chemical plating.
[0044] like Figure 7 and Figure 8 As shown, the silicon wafer 200 including the metal film 520 is transferred to another temporary carrier 100a. Figure 8 and Fig. 9 As shown, the silicon wafer 200 is thinned to form a plurality of electrical connection elements 50. Specifically, the thickness of the silicon wafer 200 can be reduced by performing chemical-mechanical polishing (CMP) on the side of the silicon wafer 200 where the grooves 101 are not formed, thereby obtaining a plurality of silicon blocks having metal films 520 on the surface. These silicon blocks can each serve as the non-metal core 510 of the electrical connection element 50.
[0045] according to Figure 5 and Fig. 9 Since the non-metal core 510 (silicon block) formed by cutting the silicon wafer or by half-cutting and grinding the silicon wafer has a flat side 511, the electrical connection element 50 also has a flat side. That is, the metal film 520 is flat on the side 511, and the metal film 520 has no burrs or bumps on the side 511. Figures 2 to 9 The manufactured electrical connection element 50 can be used to manufacture a panel-level packaging structure.
[0046] Figures 10 to 17 For manufacturing Figure 1 Schematic diagram of the semiconductor packaging structure. Fig.10 As shown, a substrate with a release layer 310 is provided as a temporary carrier 300, and one or more electrical connection elements 50 and one or more semiconductor elements 20 are arranged on the temporary carrier 300. Each semiconductor element 20 is between two adjacent electrical connection elements 50. The semiconductor element 20 and the electrical connection element 50 can be located in the same layer, that is, at the same level. The release layer 310 can be a heat released tape.
[0047] like Fig.11As shown, a packaging layer 10 is formed on the temporary carrier 300 to cover the electrical connection element 50 and the semiconductor element 20. The packaging layer 10 can be formed by injection molding, hot pressing molding or other similar methods.
[0048] like Fig.11 and Fig.12 As shown, the temporary carrier 300 is removed, and the module including the packaging layer 10, the semiconductor element 20 and the electrical connection element 50 is transferred to another temporary carrier 300a. Further, the module is inverted onto the temporary carrier 300a having a release layer on the surface, so that the front side of the semiconductor element 20 is exposed to the outside, that is, the electrical connection point 220 and the protective layer 230 located on the front side of the die 210 are exposed to the outside.
[0049] like Fig.13 As shown, a metal layer 30 is formed on the packaging layer 10, and the metal layer 30 is electrically connected to the electrical connection point 220 of the semiconductor element 20 and the metal film 520 of the electrical connection element 50. Further, the metal layer 30 corresponds to one of the semiconductor elements 20 and one of the electrical connection elements 50 adjacent to the semiconductor element 20. The metal layer 30 fills the opening formed by the protective layer 230 to lead out the electrical connection point 220, and the metal layer 30 is also electrically connected to the metal film 520 of the corresponding electrical connection element 50. The formation of the metal layer 30 can be implemented by a deposition process such as sputtering, physical vapor deposition (PVD) or chemical vapor deposition (PVD) and a patterning process such as an etching process or a transfer process. After the metal layer 30 is formed, the packaging layer 10 is thickened to cover the metal layer 30.
[0050] like Fig.13 and Fig.14 As shown, the temporary carrier 300a is removed, and the module including the packaging layer 10, the semiconductor element 20, the electrical connection element 50 and the metal layer 30 is transferred to another temporary carrier 300b. Specifically, the module is inverted onto the temporary carrier 300b having a release layer on the surface, so that the back side of the semiconductor element 20 is exposed to the outside, that is, the back side of the die 210 is exposed to the outside. In addition, since the packaging layer 10 covers the metal layer 30, the metal layer 30 is spaced apart from the temporary carrier 300b in the vertical direction.
[0051] like Fig.15As shown, a metal layer 40 is formed on the packaging layer 10, and the metal layer 40 is electrically connected to the die 210 of the semiconductor element 20 and the metal film 520 of the electrical connection element 50. Further, some metal pads 410 of the metal layer 40 are arranged corresponding to the semiconductor element 20, and the remaining metal pads 410 are arranged corresponding to the electrical connection element 50. For two adjacent metal pads 410, one metal pad 410 is arranged on the back side of the die 210. The other metal pad 410 is arranged on the electrical connection element 50 and is electrically connected to the metal film 520. After the metal layer 40 is formed, the packaging layer 10 is thickened to cover the metal layer 40, and then the packaging layer 10 is thinned to expose the top surface of the metal pad 410. The formation of the metal layer 40 can be implemented by a deposition process such as sputtering, physical vapor deposition (PVD) or chemical vapor deposition (PVD) and a patterning process such as an etching process or a transfer process. The thinning of the encapsulation layer 10 may be performed by chemical mechanical polishing to reduce the thickness of the encapsulation layer 10. Optionally, the top surface of the metal layer 40 may be processed to form ENIG.
[0052] like Fig.15 and Fig.16 As shown, the temporary carrier 300b is removed to obtain a module including the packaging layer 10, the semiconductor element 20, the electrical connection element 50 and the metal layers 30 and 40. Fig.16 and Fig.17 As shown, the packaging layer 10 is cut along the preset scribe lines S to form a plurality of semiconductor packaging structures 1 .
[0053] In summary, according to the semiconductor packaging structure disclosed in the present invention, the electrical connection element for electrically connecting two metal layers on opposite sides of a semiconductor element to each other includes a non-metallic core and a metal film. In one embodiment, the non-metallic substrate is selected from a substrate that can form a flat cutting surface, such as a silicon wafer with a single direction. In one embodiment, the non-metallic substrate is selected from a molding resin that can be processed at low cost. In this way, the non-metallic core taken from the non-metallic substrate has a flat side, and the metal film is also flat on the side. When this electrical connection element is used for panel-level packaging, it can prevent the electrical connection element from having burrs or bumps that touch adjacent semiconductor elements, which is beneficial to shorten the horizontal spacing between the electrical connection element and the semiconductor element and achieve high component density.
Claims
1. A semiconductor packaging structure, characterized in that: Include: an encapsulation layer; A die is disposed in the packaging layer; A first metal layer and a second metal layer are disposed in the packaging layer, and the first metal layer and the second metal layer are respectively disposed on two opposite sides of the die; and an electrical connection element disposed in the packaging layer, the first metal layer being electrically connected to the second metal layer through the electrical connection element; The electrical connection element includes a non-metal core and a metal film located on the surface of the non-metal core.
2. The semiconductor package structure according to claim 1, wherein: The non-metallic core is non-conductive.
3. The semiconductor package structure according to claim 1, wherein: The material of the non-metal core is selected from undoped silicon, silicon nitride, silicon oxide or molding resin.
4. The semiconductor package structure according to claim 1, wherein: The material of the metal film is the same as that of the first metal layer and the second metal layer.
5. The semiconductor package structure according to claim 1, wherein: The side surface of the electrical connection element is flat.
6. The semiconductor package structure according to claim 1, wherein: The sides of the non-metallic core are flat.
7. The semiconductor package structure according to claim 1, wherein: The first metal layer and the second metal layer are electrically connected to the metal film of the electrical connection element.
8. The semiconductor package structure according to claim 1, wherein: The die and the electrical connection element are located in the same layer.
9. The semiconductor package structure according to claim 1, wherein: The packaging layer exposes at least one of the first metal layer and the second metal layer.
10. The semiconductor package structure according to claim 1, wherein: The packaging layer exposes the second metal layer, and the second metal layer includes two metal pads spaced apart from each other, and the two metal pads are respectively connected to the die and the metal film of the electrical connection element.