ESD structure and semiconductor device

Abstract

The application provides an ESD structure, which comprises a substrate, an isolation well region in the substrate, at least one first well region and at least one second well region, the first well region and the second well region are arranged alternately along a predetermined direction, the isolation well region is located outside the first well region and the second well region, the first well region has a first contact region, the second well region has two second contact regions arranged at intervals along the predetermined direction, and the isolation well region has an isolation contact region; one of the first well region, the isolation well region, the isolation contact region and the second well region has a first doping type, and the other of the second well region, the first contact region and the other second contact region has a second doping type. The ESD structure in the application has a small area, which can greatly save the area of the device. In addition, the application also provides a semiconductor device comprising the above ESD structure.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to an ESD structure and a semiconductor device. Background Art

[0002] Electrostatic discharge (ESD) is ubiquitous during device manufacturing, packaging, testing, and use. Accumulated static charge is released in nanoseconds to microseconds at currents of several or tens of amperes. This instantaneous power can reach hundreds of kilowatts, and the discharge energy can reach millijoules, making it extremely destructive to devices. Therefore, the design of ESD structures in device design is directly related to the functional stability of the device and is therefore extremely important.

[0003] With the development of technology, the feature size of devices has gradually become smaller, and the design difficulty of ESD structures has further increased. At present, ESD structures occupy a large device area, thereby limiting the further miniaturization of devices. Summary of the Invention

[0004] The purpose of the present application is to provide an ESD structure and a semiconductor device to solve the problem of the large area of ​​the existing ESD structure.

[0005] To achieve the above objectives, the present application provides an ESD structure, comprising a substrate and an isolation well region, at least one first well region, and at least one second well region located within the substrate, wherein the first well region and the second well region are alternately arranged along a predetermined direction, the isolation well region is located outside the first well region and the second well region, the first well region has a first contact region, the second well region has two second contact regions arranged at intervals along the predetermined direction, and the isolation well region has an isolation contact region;

[0006] One of the first well region, the isolation well region, the isolation contact region and the second well region has a first doping type, and the other of the second well region, the first contact region and the second well region has a second doping type.

[0007] Optionally, the second contact region is used to connect to a high potential, and the isolation contact region and the first contact region are used to connect to a low potential.

[0008] Optionally, the isolation well region is ring-shaped and is arranged around the first well region and the second well region.

[0009] Optionally, one of the first doping type and the second doping type is N-type, and the other is P-type.

[0010] Optionally, in the same second well region, the second contact region with the first doping type and the second contact region with the second doping type are arranged in sequence along the predetermined direction; or, in the same second well region, the second contact region with the second doping type and the second contact region with the first doping type are arranged in sequence along the predetermined direction.

[0011] Optionally, the first well region and the isolation well region are integrated structures.

[0012] Optionally, the first well region and the isolation well region are independent of each other.

[0013] Optionally, the substrate further has an isolation structure, which is located between adjacent first contact regions and second contact regions, between two adjacent second contact regions, and between the isolation contact region and the first contact region and the second contact region.

[0014] Optionally, all the first well regions are integrated structures; or, each of the first well regions is independent of each other.

[0015] The application further provides a semiconductor device comprising the ESD structure.

[0016] In the ESD structure provided by the application, the substrate and the isolation well region, the at least one first well region and the at least one second well region located in the substrate are included, the first well region and the second well region are arranged alternately along a predetermined direction, the isolation well region is located outside the first well region and the second well region, the first well region has a first contact region, the second well region has two second contact regions arranged at intervals along the predetermined direction, and the isolation well region has an isolation contact region; one of the first well region, the isolation well region, the isolation contact region and the second well region has a first doping type, and the other of the second well region, the first contact region and the second well region has a second doping type. The ESD structure in the application has a large anti-static capacity, does not change the performance of the device basically, has a small area, and can greatly save the area of the device. Accordingly, the application further provides a semiconductor device comprising the above ESD structure. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 It is a plane schematic view of an ESD structure.

[0018] Figure 2 It is a plane schematic view of an ESD structure. Figure 1 It is a sectional view of the ESD structure in the application along the AA direction.

[0019] Figure 3 It is a sectional view of the ESD structure in the application along the AA direction. Figure 2Equivalent circuit diagram of the ESD structure in;

[0020] Figure 4 A schematic plan view of the ESD structure provided in Example 1 of the present application;

[0021] Figure 5 for Figure 4 Schematic diagram of the cross section of the ESD structure along the AA direction;

[0022] Figure 6 A schematic diagram of the ESD structure provided in Example 2 of the present application;

[0023] Wherein, the accompanying drawings are marked as follows:

[0024] 100, 200 - substrate; 101, 201 - first well region; 111, 211 - first contact region; 102, 202 - second well region; 112, 212 - second contact region; 103 - isolation well region; 113 - isolation contact region; 104, 204 - isolation structure. DETAILED DESCRIPTION

[0025] Figure 1 It is a planar schematic diagram of an ESD structure. Figure 2 for Figure 1 The cross-sectional diagram of the ESD structure along the AA direction. Figure 1 and Figure 2 As shown, an ESD structure includes a substrate 200 and at least one first well region 201 and at least one second well region 202 located in the substrate 200. The first well regions 201 and the second well regions 202 are alternately arranged along a predetermined direction. All the first well regions 201 can be an integrated structure or can be independent of each other. Figure 1 FIGURE 2 illustrates a case where all first well regions 201 are integrated. The first well region 201 includes two first contact regions 211 spaced apart along the predetermined direction, and the second well region 202 includes two second contact regions 212 spaced apart along the predetermined direction. Isolation structures 204 are provided between adjacent first contact regions 211 and second contact regions 212, between adjacent first contact regions 211, and between adjacent second contact regions 212.

[0026] The first contact region 211 in the first well region 201 has a first doping type, and the other first contact region 211 has a second doping type; the second contact region 212 in the second well region 202 has the first doping type, and the other second contact region 212 has the second doping type, and the contact region (the first contact region 211 or the second contact region 212) with the first doping type and the contact region (the first contact region 211 or the second contact region 212) with the second doping type are arranged alternately. The first contact region 211 is used to connect a low potential, which can be usually grounded VSS, and the second contact region 212 is used to connect a high potential, which can be usually a power supply VDD.

[0027] Taking the first doping type as P type and the second doping type as N type as an example, Figure 2 The doping types of the four contact regions in the figure from left to right are P type, N type, P type and N type respectively, and the doping types of the first well region 201 and the second well region 202 are P type and N type respectively. At this time, the first contact region 211 of N type, the substrate 200 of P type and the second well region 202 of N type constitute an NPN triode, and the first contact region 211 of N type, the substrate 200 of P type and the second well region 202 of N type are respectively the emitter, the base and the collector of the NPN triode; the second contact region 212 of P type, the second well region 202 of N type and the substrate 200 of P type constitute a PNP triode, and the second contact region 212 of P type, the second well region 202 of N type and the substrate 200 of P type are respectively the emitter, the base and the collector of the PNP triode; the resistance of the substrate 200 at the bottom of the first well region 201 can be equivalent to the resistance Rp, and the internal resistance of the second well region 202 can be equivalent to the resistance Rn, and finally an equivalent circuit diagram as shown in Figure 3

[0028] As shown in Figure 3 ​As shown, the emitter of the PNP transistor and one end of the resistor Rn are connected to the power supply VDD, the base of the PNP transistor is connected to the other end of the resistor Rn and the collector of the NPN transistor, the collector of the PNP transistor is connected to the base of the NPN transistor and one end of the resistor Rp, and the other end of the resistor Rp is connected to the emitter of the NPN transistor and then to the ground VSS. When static electricity is generated, it reaches the ESD structure through VDD. At this time, the PNP transistor is turned on first (there is a resistor Rn on the other path, so the static electricity will first flow through the path with the PNP transistor). After the PNP transistor is turned on, the voltage on its collector increases, causing the NPN transistor to turn on accordingly, and the static electricity can be introduced into the ground VSS, achieving ESD protection. However, the first well region 201 and the second well region 202 of this ESD structure both have two doped regions, which are large in area and will occupy a large device area, thereby limiting further device miniaturization.

[0029] Based on this, the present application provides an ESD structure, including a substrate and an isolation well region located in the substrate, at least one first well region and at least one second well region, the first well region and the second well region are alternately arranged along a predetermined direction, the isolation well region is located outside the first well region and the second well region, the first well region has a first contact region, the second well region has two second contact regions arranged at intervals along the predetermined direction, and the isolation well region has an isolation contact region; one of the second contact regions in the first well region, the isolation well region, the isolation contact region and the second well region has a first doping type, and the other of the second contact regions in the second well region, the first contact region and the second well region has a second doping type. The ESD structure in the present application has a large anti-static ability, basically does not change the performance of the device, and has a small area, which can greatly save the area of ​​the device. Accordingly, the present application also provides a semiconductor device including the above-mentioned ESD structure.

[0030] The following is a more detailed description of the specific embodiments of the present application, with reference to the schematic diagrams. The advantages and features of the present application will become more apparent from the following description. It should be noted that the accompanying drawings are in a very simplified form and are not to exact scale, and are only used to facilitate and clearly illustrate the purpose of the embodiments of the present application.

[0031] Example 1

[0032] Figure 4 A schematic plan view of the ESD structure provided in an embodiment of the present application is shown. Figure 5 for Figure 4 The cross-sectional diagram of the ESD structure along the AA direction. Figure 4 and Figure 5As shown, the ESD structure includes a substrate 100 and an isolation well region 103, at least one first well region 101, and at least one second well region 102 located within the substrate 100. The isolation well region 103, the first well region 101, and the second well region 102 all extend from the surface of the substrate 100 into the substrate 100. In this embodiment, the isolation well region 103, the first well region 101, and the second well region 102 have the same depth, but the present invention is not limited thereto.

[0033] Specifically, the first well region 101 and the second well region 102 may be alternately arranged along a predetermined direction. In this embodiment, the predetermined direction is Figure 4 The first well region 101 includes a first contact region 111 extending from the surface of the first well region 101 into the first well region 101. The second well region 102 includes two second contact regions 112 spaced apart along the predetermined direction, extending from the surface of the second well region 102 into the second well region 102. The isolation well region 103 is located outside the first well region 101 and the second well region 102. The isolation well region 103 includes an isolation contact region 113 extending from the surface of the isolation well region 103 into the isolation well region 103. The first contact region 111, the second contact region 112, and the isolation contact region 113 are all doped regions. The substrate 100, the first well region 101, the isolation well region 103, the isolation contact region 113, and one of the second contact regions 112 in the second well region 102 have a first doping type, and the second well region 102, the first contact region 111, and another of the second contact regions 112 in the second well region 102 have a second doping type. One of the first doping type and the second doping type is N-type, and the other is P-type.

[0034] In this embodiment, within the same second well region 102, the second contact region 112 having the first doping type and the second contact region 112 having the second doping type are sequentially arranged along the predetermined direction. In some embodiments, within the same second well region 102, the second contact region 112 having the second doping type and the second contact region 112 having the first doping type are sequentially arranged along the predetermined direction. In other words, the arrangement of the two second contact regions 112 of the doping type in the second well region 102 is not limited.

[0035] In this embodiment, the isolation well region 103 is annular and surrounds the first well region 101 and the second well region 102, which can reduce the resistance of the substrate 100. In some embodiments, the isolation well region 103 can also be in other shapes, such as a straight shape, a C shape, or an L shape. That is, the isolation well region 103 does not necessarily need to surround the first well region 101 and the second well region 102. For example, it can be disposed on one side of the first well region 101 and the second well region 102, and this application is not limited thereto.

[0036] Since the first well region 101 and the isolation well region 103 have the same doping type, in this embodiment, the first well region 101 and the isolation well region 103 are integrally structured. In this case, the isolation well region 103 and the first well region 101 are connected as one piece, which can reduce the difficulty of manufacturing and save manufacturing costs. In this case, all first well regions 101 can be integrally structured, so that all first well regions 101 are connected as one piece with the isolation well region 103. Of course, each first well region 101 can also be independent of each other, so that all first well regions 101 can be connected as one piece through the isolation well region 103.

[0037] Furthermore, the substrate 100 further includes an isolation structure 104, which extends from the surface of the substrate 100 into the substrate 100. The isolation structure 104 may be a trench isolation structure 104. The isolation structure 104 is located between adjacent first contact regions 111 and second contact regions 112, between two adjacent second contact regions 112, and between the isolation contact region 113 and the first contact region 111 and the second contact region 112, to achieve isolation.

[0038] In this embodiment, the second contact region 112 is used to connect to a high potential, usually connected to the power supply VDD; the isolation contact region 113 and the first contact region 111 are used to connect to a low potential, usually connected to the ground VSS. For example, if the first doping type is P-type and the second doping type is N-type, Figure 5The doping types of the four contact regions (the isolation contact region 113, the first contact region 111 and the two second contact regions 112) are P-type, N-type, P-type and N-type from left to right, the doping types of the first well region 101 and the isolation well region 103 are P-type, and the doping type of the second well region 102 is N-type. At this time, the N-type first contact region 111, the P-type substrate 100 and the N-type second well region 102 constitute an NPN transistor, and the N-type first contact region 111, the P-type substrate 100 and the N-type second well region 102 are respectively the emitter, base and collector of the NPN transistor; the P-type second contact region 112, the N-type second well region 102 and the P-type substrate 100 constitute a PNP transistor, and the P-type second contact region 112, the N-type second well region 102 and the P-type substrate 100 are respectively the emitter, base and collector of the PNP transistor; the resistance of the substrate 100 at the bottom of the first well region 101 (the isolation well region 103) can be equivalent to the resistance Rp, and the internal resistance of the second well region 102 can be equivalent to the resistance Rn, and finally the following can be obtained. Figure 3 The equivalent circuit diagram shown. Similarly, in this embodiment, the emitter of the PNP transistor and one end of the resistor Rn are connected to the power supply VDD, the base of the PNP transistor is connected to the other end of the resistor Rn and the collector of the NPN transistor, the collector of the PNP transistor is connected to the base of the NPN transistor and one end of the resistor Rp, and the other end of the resistor Rp is connected to the emitter of the NPN transistor and then to the ground VSS. When static electricity is generated, the static electricity reaches the ESD structure through VDD. At this time, the PNP transistor is turned on first. After the PNP transistor is turned on, the voltage on its collector increases, causing the NPN transistor to be turned on. The static electricity can be introduced into the ground VSS to achieve ESD protection. It can be seen that compared to Figure 1 and Figure 2 The ESD structure in this embodiment also has the same anti-static ability and basically does not change the performance of the device. Moreover, since the first well region 101 only includes one first contact region 111, the size of the ESD structure can be reduced, which greatly saves the area of ​​the device.

[0039] It should be noted that when the doping types of two different second contact regions in the second well region 102 are exchanged, the type of the formed transistor may also change, but this does not affect the implementation of the present application.

[0040] Furthermore, this embodiment also provides a semiconductor device including the above-mentioned ESD structure.

[0041] Example 2

[0042] Figure 6Schematic diagram of the ESD structure provided in this embodiment. Figure 6 As shown, the difference from the first embodiment is that in this embodiment, the first well region 101 and the isolation well region 103 are independent of each other. In this case, all the first well regions 101 can be an integrated structure, and each first well region 101 can also be independent of each other.

[0043] In summary, the ESD structure provided in the embodiment of the present application includes a substrate 100 and an isolation well region 103, at least one first well region 101 and at least one second well region 102 located in the substrate 100, the first well region 101 and the second well region 102 are arranged alternately along a predetermined direction, the isolation well region 103 is located outside the first well region 101 and the second well region 102, the first well region 101 has a first contact region 111, the second well region 102 has two second contact regions 112 arranged at intervals along the predetermined direction, and the isolation well region 103 has an isolation contact region 113; the first well region 101, the isolation well region 103, the isolation contact region 113 and one of the second contact regions 112 in the second well region 102 have a first doping type, and the second well region 102, the first contact region 111 and the other second contact region 112 in the second well region 102 have a second doping type. The ESD structure in this application has a strong antistatic capability, does not substantially change the performance of the device, and has a small area, which can greatly save the area of ​​the device. Accordingly, this application also provides a semiconductor device including the above-mentioned ESD structure.

[0044] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Reference can be made to the common and similar parts between the various embodiments. The systems disclosed in the embodiments are described briefly because they correspond to the methods disclosed in the embodiments. For relevant details, refer to the method description.

[0045] It should also be noted that although the present application has been disclosed above with preferred embodiments, the above embodiments are not intended to limit the present application. For any person skilled in the art, without departing from the scope of the technical solution of the present application, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present application, or to modify it into an equivalent embodiment with equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application still falls within the scope of protection of the technical solution of the present application.

[0046] It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are only used to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0047] It should also be recognized that the terms described herein are used only to describe specific embodiments and are not intended to limit the scope of this application. It should be noted that the singular forms "a" and "an" used herein and in the appended claims include plural references unless the context clearly indicates otherwise. For example, a reference to "a step" or "a device" means a reference to one or more steps or devices, and may include secondary steps as well as secondary devices. All conjunctions used should be understood in their broadest sense. Also, the word "or" should be understood to have the definition of a logical "or" rather than a logical "exclusive or" unless the context clearly indicates otherwise. In addition, the implementation of the methods and / or devices in the embodiments of the present application may include performing the selected tasks manually, automatically, or in combination.

Claims

1. An ESD structure, characterized in that: The method comprises a substrate and an isolation well region, at least one first well region, and at least one second well region located in the substrate, wherein the first well region and the second well region are alternately arranged along a predetermined direction, the isolation well region is located outside the first well region and the second well region, the first well region has a first contact region, the second well region has two second contact regions arranged at intervals along the predetermined direction, and the isolation well region has an isolation contact region; The second contact region among the first well region, the isolation well region, the isolation contact region, and the second well region has a first doping type, and the second contact region among the second well region, the first contact region, and the second well region has a second doping type; The isolation well region is annular and arranged around the first well region and the second well region; or the isolation well region is arranged on one side of the first well region and the second well region, the second contact region is used to connect to a high potential, and the isolation contact region and the first contact region are used to connect to a low potential.

2. The ESD structure according to claim 1, wherein: One of the first doping type and the second doping type is N-type, and the other is P-type.

3. The ESD structure according to claim 1 or 2, wherein: In the same second well region, the second contact region having the first doping type and the second contact region having the second doping type are arranged in sequence along the predetermined direction; or, in the same second well region, the second contact region having the second doping type and the second contact region having the first doping type are arranged in sequence along the predetermined direction.

4. The ESD structure according to claim 1, wherein: The first well region and the isolation well region are an integrated structure.

5. The ESD structure according to claim 1, wherein: The first well region and the isolation well region are independent of each other.

6. The ESD structure according to claim 4 or 5, wherein: The substrate further has an isolation structure therein. The isolation structure is located between adjacent first contact regions and second contact regions, between two adjacent second contact regions, and between the isolation contact region and the first contact region and the second contact region.

7. The ESD structure according to claim 4 or 5, wherein: All the first well regions are an integrated structure; or, each of the first well regions is independent of each other.

8. A semiconductor device, characterized in that: The method comprises the ESD structure according to any one of claims 1 to 7.

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