Silicon carbide power device parallel drive oscillation suppression circuit and control method

Abstract

The invention provides a silicon carbide power device parallel drive oscillation suppression circuit and a control method, and belongs to the technical field of power electronics. The circuit comprises a double-pull driving chip, a plurality of silicon carbide power devices and a plurality of pull-down modules. And the plurality of silicon carbide power devices and the plurality of pull-down modules are respectively controlled through the first chip driving end and the second chip driving end of the double-pull driving chip. Each silicon carbide power device is connected with a pull-down module, so that a drive pull-down loop of each silicon carbide power device is independent and does not flow through parasitic inductance of a first chip drive end and a second chip drive end of the double-pull drive chip, and the influence of the parasitic inductance of a miller clamping loop is eliminated; the problem of repeated oscillation of grid voltages of all the silicon carbide power devices connected in parallel is solved, and normal operation of all the silicon carbide power devices connected in parallel is ensured.

Description

Technical Field

[0001] The present application belongs to the field of power electronics technology, and in particular, relates to a parallel drive oscillation suppression circuit and a control method for a silicon carbide power device. Background Art

[0002] With the continuous development of power electronics technology, the performance requirements for power devices are getting higher and higher. Traditional silicon-based power devices are gradually unable to meet the needs of modern power systems in terms of voltage resistance, switching speed, conduction loss and high temperature performance. Compared with silicon-based power devices, silicon carbide (SiC) power devices have begun to be widely used due to their low power consumption, wide bandgap, high thermal conductivity and other characteristics.

[0003] However, when the driver chip drives multiple parallel-connected SiC power devices, it cannot take into account the driving wiring of all parallel-connected SiC power devices, resulting in an increase in parasitic parameters between the driver chip and all parallel-connected SiC power devices. As a result, the parasitic parameters increase, causing LC resonance in the entire circuit, causing the gate voltage of all parallel-connected SiC power devices to oscillate repeatedly, resulting in the problem of mis-starting the SiC power devices, and affecting the normal use of the SiC power devices. Summary of the invention

[0004] The purpose of the present application is to provide a parallel drive oscillation suppression circuit and a control method for a silicon carbide power device, aiming to solve the problem of repeated oscillation of the gate voltage when a traditional driver chip drives multiple parallel silicon carbide power devices.

[0005] The present application provides a parallel drive oscillation suppression circuit for a silicon carbide power device, comprising: Double pull driver chip; A plurality of silicon carbide power devices, wherein the first ends of the plurality of silicon carbide power devices are connected, the second ends of the plurality of silicon carbide power devices are connected, and the driving ends of the plurality of silicon carbide power devices are connected to the first chip driving end of the dual-pull driving chip; A plurality of pull-down modules, wherein the driving ends of the plurality of pull-down modules are connected to the second chip driving end of the dual-pull driving chip, the first end of each of the pull-down modules is connected to the driving end of each of the silicon carbide power devices, and the second ends of the plurality of pull-down modules are connected to a negative power supply; The voltage at the first end of the silicon carbide power device is greater than the voltage at the second end of the silicon carbide power device, and the voltage at the second end of the silicon carbide power device is greater than the voltage at the second end of the pull-down module.

[0006] In one embodiment, the circuit further comprises: A plurality of negative pressure stabilizing modules, wherein a first end of each of the negative pressure stabilizing modules is connected to a second end of each of the pull-down modules, and a second end of each of the negative pressure stabilizing modules is connected to a second end of each of the silicon carbide power devices.

[0007] In one embodiment, each of the pull-down modules comprises: A clamped power device, wherein the driving end of the clamped power device is connected to the second chip driving end of the dual-pull driving chip, the first end of the clamped power device is connected to the driving end of the silicon carbide power device, and the second end of the clamped power device is connected to the negative power supply.

[0008] In one embodiment, the circuit further comprises: A first driving module, wherein a first end of the first driving module is connected to a driving end of the first chip, and a second end of the first driving module is connected to driving ends of a plurality of the silicon carbide power devices and first ends of a plurality of the pull-down modules.

[0009] In one embodiment, the circuit further comprises: A second driving module, wherein a first end of the second driving module is connected to a driving end of the second chip, and a second end of the second driving module is connected to driving ends of the plurality of pull-down modules.

[0010] In one embodiment, the dual-pull driving chip, the plurality of the silicon carbide power devices, and the plurality of the pull-down modules form an upper bridge arm or a lower bridge arm of a circuit.

[0011] The present application provides a control method for a parallel drive oscillation suppression circuit for a silicon carbide power device, which is applied to the parallel drive oscillation suppression circuit for a silicon carbide power device in any one of the above embodiments, and the control method includes: The dual-pull driving chip generates a first driving signal according to an input signal to control the on and off of multiple silicon carbide power devices; The dual-pull driving chip acquires the input signal and generates a second driving signal according to the input signal to control the on and off of multiple pull-down modules; The first drive signal and the second drive signal are pulse width modulation signals, the falling edge of the second drive signal is located before the rising edge of the first drive signal, and the rising edge of the second drive signal is located after the falling edge of the first drive signal.

[0012] In one embodiment, the time difference between the rising edge of the first drive signal and the rising edge of the input signal is the drive transmission delay, and the time difference between the falling edge of the second drive signal and the rising edge of the input signal is less than the drive transmission delay.

[0013] In one embodiment, between a falling edge of the first drive signal and a rising edge of the second drive signal, the first drive signal is a low level signal and a voltage of the first drive signal is less than a turn-on voltage threshold of the silicon carbide power device.

[0014] In one embodiment, the time difference between the rising edge of the second driving signal and the falling edge of the first driving signal is determined according to the driving resistance between the dual-pull driving chip and the silicon carbide power device and the parasitic capacitance between the driving end and the second end of the silicon carbide power device.

[0015] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: The voltage at the first end of the silicon carbide power device (which can be understood as Figure 1 The voltage at node A and the voltage at node B) are greater than the voltage at the second end of the silicon carbide power device (which can be understood as Figure 1 The current is divided into two paths from the A node, the B node, and the C node to the D node. One path passes through the F node to the second end of the plurality of silicon carbide power devices. The voltage at the second end of the silicon carbide power device is greater than the voltage at the second end of the pull-down module. The other path passes through the E node and the pull-down module to the second end of the pull-down module.

[0016] The first chip driving end and the second chip driving end of the dual-pull driving chip are respectively connected to the driving ends of multiple silicon carbide power devices and the driving ends of multiple pull-down modules, and can respectively control the conduction or shutdown of multiple silicon carbide power devices and multiple pull-down modules, so that the current flowing out from the A node flows directly to the second ends of the multiple silicon carbide power devices and the second ends of the multiple pull-down modules through the B node, the C node, the D node, the E node, and the F node, respectively, and will not flow through the parasitic parameters between the dual-pull driving chip and all parallel silicon carbide power devices, which can also be understood as the parasitic inductance that will not flow through the first chip driving end and the second chip driving end of the dual-pull driving chip.

[0017] The first end of each pull-down module is connected to the driving end of each silicon carbide power device, and the second chip driving end of the double-pull driving chip controls the conduction of multiple pull-down modules, and can pull the driving end of the silicon carbide power device down to the negative power supply VEE.

[0018] The first chip driving end and the second chip driving end of the dual-pull driving chip are used to control multiple silicon carbide power devices and multiple pull-down modules respectively, making the control process more flexible, and the number of pull-down modules will not be limited. Each silicon carbide power device can be matched with a pull-down module. Each silicon carbide power device is connected to a pull-down module, which ensures that the driving pull-down circuit of each silicon carbide power device is independent, and will not flow through the parasitic inductance of the first chip driving end and the second chip driving end of the dual-pull driving chip, and directly reach the negative power supply VEE, eliminating the influence of the parasitic inductance of the Miller clamping circuit, solving the problem of repeated oscillation of the gate voltage of all parallel silicon carbide power devices, and ensuring the normal operation of all parallel silicon carbide power devices. Furthermore, each silicon carbide power device is connected to a pull-down module, which ensures that the driving pull-down circuit of each silicon carbide power device is independent, solves the problem of crosstalk between the driving circuits of silicon carbide power devices and silicon carbide power devices, and effectively ensures that the operation state of the entire circuit is safe and reliable. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or exemplary technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 This is a schematic diagram of the structure of a parallel drive oscillation suppression circuit for a silicon carbide power device in some embodiments provided in the present application.

[0021] Figure 2 A schematic diagram of the connection structure of parasitic inductance and parasitic capacitance in a parallel drive oscillation suppression circuit of a silicon carbide power device in some embodiments provided in the present application.

[0022] Figure 3 A schematic diagram of the connection structure of a clamping power device, a negative pressure stabilization module, a first driving module and a second driving module in a parallel drive oscillation suppression circuit of a silicon carbide power device in some embodiments provided in the present application.

[0023] Figure 4 This is a schematic diagram of the connection structure between the upper bridge arm of the circuit and the lower bridge arm of the circuit in some embodiments provided in the present application.

[0024] Figure 5 A schematic diagram of timing control of an upper bridge arm or a lower bridge arm of an oscillation suppression circuit driven in parallel by a silicon carbide power device in some embodiments provided in the present application.

[0025] Figure 6This is a schematic diagram of the overall timing control of a parallel drive oscillation suppression circuit for a silicon carbide power device in some embodiments provided in the present application.

[0026] Figure 7 Schematic diagram of the pull-down path in traditional technology.

[0027] Figure 8 A schematic diagram of a pull-down path of a parallel drive oscillation suppression circuit for a silicon carbide power device provided in the present application. DETAILED DESCRIPTION

[0028] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0029] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0030] It should be understood that the orientation or position relationship indicated by terms such as "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0031] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0032] In traditional technology, silicon carbide power devices are subject to the limitations of the production process of the silicon carbide substrate itself, and the cost is higher than that of silicon-based power devices. In order to reduce cost and area, a single Miller clamp driver chip is usually used in traditional technology to drive multiple parallel silicon carbide power devices. However, when a single Miller clamp driver chip is used to drive multiple parallel silicon carbide power devices, a single Miller clamp driver chip cannot take into account the drive routing of all parallel silicon carbide power devices, which increases the parasitic parameters between the single Miller clamp driver chip and all parallel silicon carbide power devices. The function of the Miller clamp of the Miller clamp driver chip is to add an extremely low impedance pull-down loop to provide a larger current to pull down the gate voltage. However, due to the increase in parasitic inductance in the parasitic parameters, it will have an inhibitory effect on the pull-down current and reduce the clamping effect. Moreover, the increase in parasitic parameters will also cause LC resonance in the entire circuit, resulting in repeated oscillation of the gate voltage of all parallel-connected silicon carbide power devices, causing the silicon carbide power devices to be falsely turned on, affecting the normal use of the silicon carbide power devices.

[0033] Therefore, for the above problems, please see Figure 1 The present application provides a parallel drive oscillation suppression circuit 100 for silicon carbide power devices. The parallel drive oscillation suppression circuit 100 for silicon carbide power devices includes a dual pull drive chip 10, a plurality of silicon carbide power devices 210, and a plurality of pull-down modules 30. The first ends of the plurality of silicon carbide power devices 210 are connected. The second ends of the plurality of silicon carbide power devices 210 are connected. The driving ends of the plurality of silicon carbide power devices 210 are connected to the first chip driving end of the dual pull drive chip 10. The driving ends of the plurality of pull-down modules 30 are connected to the second chip driving end of the dual pull drive chip 10. The first end of each pull-down module 30 is connected to the driving end of each silicon carbide power device 210. The second ends of the plurality of pull-down modules 30 are connected to a negative power supply VEE. Among them, the voltage of the first end of the silicon carbide power device 210 is greater than the voltage of the second end of the silicon carbide power device 210, and the voltage of the second end of the silicon carbide power device 210 is greater than the voltage of the second end of the pull-down module 30.

[0034] In this embodiment, the first ends of the plurality of silicon carbide power devices 210 are connected to form a first common connection end of the plurality of silicon carbide power devices 210. The voltage of the first end of the silicon carbide power device 210 (which can be understood as Figure 1 The voltage at the A node and the voltage at the B node) are greater than the voltage at the second end of the silicon carbide power device 210 (which can be understood as Figure 1The current is divided into two paths from the A node, the B node, and the C node to the D node. One path passes through the F node to reach the second end of the multiple silicon carbide power devices 210, that is, the second common connection end of the multiple silicon carbide power devices 210. The voltage at the second end of the silicon carbide power device 210 is greater than the voltage at the second end of the pull-down module 30. The other path passes through the E node and the pull-down module 30 to reach the second end of the pull-down module 30, that is, the first common connection end of the multiple pull-down modules 30.

[0035] The first chip driving end and the second chip driving end of the dual-pull driving chip 10 are respectively connected to the driving ends of multiple silicon carbide power devices 210 and the driving ends of multiple pull-down modules 30, and can respectively control the conduction or shutdown of multiple silicon carbide power devices 210 and multiple pull-down modules 30, so that the current flowing out from the A node flows directly to the second ends of the multiple silicon carbide power devices 210 and the second ends of the multiple pull-down modules 30 through the B node, the C node, the D node, the E node, and the F node, respectively, and will not flow through the parasitic parameters between the dual-pull driving chip 10 and all parallel silicon carbide power devices 210, which can also be understood as not flowing through the parasitic inductance of the first chip driving end and the second chip driving end of the dual-pull driving chip 10.

[0036] The first end of each pull-down module 30 is connected to the driving end of each silicon carbide power device 210 , and the second chip driving end of the dual-pull driving chip 10 controls the conduction of multiple pull-down modules 30 , and can pull the driving end of the silicon carbide power device 210 down to the negative power supply VEE.

[0037] The first chip driving end and the second chip driving end of the dual-pull driving chip 10 respectively control multiple silicon carbide power devices 210 and multiple pull-down modules 30, making the control process more flexible, and the number of pull-down modules 30 will not be limited, and each silicon carbide power device 210 can be matched to connect a pull-down module 30. Each silicon carbide power device 210 is connected to a pull-down module 30, ensuring that the driving pull-down circuit of each silicon carbide power device 210 is independent, and will not flow through the parasitic inductance of the first chip driving end and the second chip driving end of the dual-pull driving chip 10, and directly reach the negative power supply VEE, eliminating the influence of the parasitic inductance of the Miller clamping circuit, solving the problem of repeated oscillation of the gate voltage of all parallel silicon carbide power devices 210, and ensuring the normal operation of all parallel silicon carbide power devices 210. Furthermore, each silicon carbide power device 210 is connected to a pull-down module 30, which ensures that the driving pull-down circuit of each silicon carbide power device 210 is independent, solves the problem of driving circuit crosstalk between silicon carbide power devices 210 and silicon carbide power devices 210, and effectively ensures that the operation state of the entire circuit is safe and reliable.

[0038] See also Figure 2In one embodiment, the driving end of the pull-down module 30 is connected to the second chip driving end of the dual-pull driving chip 10 to form a first parasitic inductor 610. The driving end of the silicon carbide power device 210 is connected to the first chip driving end of the dual-pull driving chip 10 to form a second parasitic inductor 620 and a third parasitic inductor 630. The second ends of multiple silicon carbide power devices 210 are connected to form a fourth parasitic inductor 640. A first parasitic capacitor 710 is formed between the first end of the silicon carbide power device 210 and the driving end. A second parasitic capacitor 720 is formed between the second end of the silicon carbide power device 210 and the driving end.

[0039] In this embodiment, the first parasitic inductance 610 is a parasitic inductance formed by the printed circuit board (PCB) wiring between the driving end of the pull-down module 30 and the second chip driving end of the dual-pull driving chip 10. The second parasitic inductance 620 is a parasitic inductance formed by the PCB wiring between the driving end of the silicon carbide power device 210 and the first chip driving end of the dual-pull driving chip 10. The third parasitic inductance 630 and the fourth parasitic inductance 640 are both the wire bonding parasitic inductance and the pin parasitic inductance of the driving end of the silicon carbide power device 210. The second parasitic capacitor 720 is a parasitic capacitor between the driving end and the second end of the silicon carbide power device 210. The first parasitic capacitor 710 is a parasitic capacitor between the driving end and the first end of the silicon carbide power device 210 (also known as Miller capacitor).

[0040] In one embodiment, the first end of the silicon carbide power device 210 is a drain end, and the second end of the silicon carbide power device 210 is a source end. The second parasitic capacitor 720 is a gate-source parasitic capacitor of the silicon carbide power device 210. The first parasitic capacitor 710 is a gate-drain parasitic capacitor of the silicon carbide power device 210.

[0041] Due to the existence of the first parasitic capacitor 710, the basic principle of C*V=I*t can be used to explain that there will be current passing through the first parasitic capacitor 710 and reaching the C node, that is, the node at the driving end of the silicon carbide power device 210. Furthermore, after the current reaches the D node, it is divided into two branches. One branch current goes through the second parasitic capacitor 720, reaches the F node, and then flows through the fourth parasitic inductor 640. The other branch current goes through the third parasitic inductor 630 and reaches the E node, and enters the first end of the pull-down module 30, and passes through the pull-down module 30 to reach the second end of the pull-down module 30, and reaches the negative power supply VEE. Through the silicon carbide power device parallel drive oscillation suppression circuit 100 provided in the present application, the two branch currents divided by the D node will not flow through the first parasitic inductance 610 and the second parasitic inductance 620, will not affect the driving signal between the driving end of the pull-down module 30 and the second chip driving end of the dual-pull driving chip 10, and will not affect the driving signal between the driving end of the silicon carbide power device 210 and the first chip driving end of the dual-pull driving chip 10.

[0042] Furthermore, through the parallel drive oscillation suppression circuit 100 of the silicon carbide power device provided in the present application, the pull-down path of the Miller clamp does not pass through the first parasitic inductance 610 and the second parasitic inductance 620, eliminating the influence of the first parasitic inductance 610 and the second parasitic inductance 620 on the pull-down path, so that the position of the double-pull driver chip 10 can be placed without distance restrictions. Thus, through the parallel drive oscillation suppression circuit 100 of the silicon carbide power device provided in the present application, the influence of the first parasitic inductance 610 and the second parasitic inductance 620 on the parallel drive of multiple silicon carbide power devices 210 is eliminated, and the driving end signal of the silicon carbide power device 210 and the driving end signal of the pull-down module 30 will not be affected, and the accurate conduction or shutdown of the silicon carbide power device 210 can be ensured. Through the parallel drive oscillation suppression circuit 100 of the silicon carbide power device provided in the present application, the problem of repeated oscillation of the gate voltage existing in the conventional technology when the driver chip drives multiple parallel silicon carbide power devices is solved.

[0043] Furthermore, the silicon carbide power device parallel drive oscillation suppression circuit 100 provided in the present application can solve the problem of repeated oscillation of the gate voltage that exists in the traditional technology when the driver chip drives multiple parallel silicon carbide power devices through a dual-pull driver chip 10, without the need to add multiple driver chips, thereby reducing the cost and area of ​​the overall circuit.

[0044] Furthermore, each silicon carbide power device 210 is connected to a pull-down module 30, ensuring that the driving pull-down loop of each silicon carbide power device 210 is independent. Therefore, the pull-down module 30 can be arranged close to the silicon carbide power device 210, so that the pull-down module 30 is far away from the dual-pull driver chip 10, so as to achieve a shorter pull-down wiring loop to reduce the wiring parasitic inductance, thereby achieving a very good Miller clamping effect.

[0045] In one embodiment, the silicon carbide power device parallel drive oscillation suppression circuit 100 is applied to electronic integrated circuits such as non-isolated gate drive chips and isolated gate drive chips that have the ability to drive power devices.

[0046] See also Figure 2 In one embodiment, the silicon carbide power device parallel drive oscillation suppression circuit 100 further includes a plurality of negative voltage stabilization modules 40. The first end of each negative voltage stabilization module 40 is connected to the second end of each pull-down module 30. The second end of each negative voltage stabilization module 40 is connected to the second end of each silicon carbide power device 210.

[0047] In this embodiment, a plurality of negative voltage stabilization modules 40 are connected in parallel between the second end of the pull-down module 30 and the second end of the silicon carbide power device 210. The second ends of the plurality of pull-down modules 30 are connected to the negative power supply VEE. A voltage difference is formed between the second end of the pull-down module 30 and the second end of the silicon carbide power device 210. The current passes through node A, node B, node C, node D, node E and the pull-down module 30, and reaches the negative power supply VEE, so that the voltage pull-down path of node C (which can also be understood as the gate) corresponding to the driving end of the silicon carbide power device 210 does not pass through the parasitic inductance of the first chip driving end and the second chip driving end of the dual-pull driving chip 10, such as the first parasitic inductance 610 and the second parasitic inductance 620. Therefore, the parasitic inductance of the first chip driving end and the second chip driving end of the dual-pull driving chip 10 will not affect the gate voltage pull-down path, so that the gate voltage of the driving end of the silicon carbide power device 210 is more stable, which solves the problem of repeated oscillation of the gate voltage in the traditional technology and improves the overall reliability.

[0048] The negative voltage stabilization module 40 can stabilize the voltage between the second end of the pull-down module 30 and the second end of the silicon carbide power device 210. Furthermore, when the pull-down module 30 and the silicon carbide power device 210 are switched from the on state to the off state, the negative voltage stabilization module 40 stabilizes the signal quality of the negative voltage level, ensures the reliable closure of the pull-down module 30 and the silicon carbide power device 210, prevents false triggering, and avoids problems such as erroneous operation or damage to the device caused by unstable negative voltage. Therefore, the negative voltage stabilization module 40 is helpful to assist the pull-down module 30 in solving the problem of repeated oscillation of the gate voltage in the traditional technology, helps the circuit to operate stably for a long time, and reduces the occurrence of faults.

[0049] In one embodiment, the negative voltage stabilization module 40 includes at least one capacitor. The first end of the capacitor is connected to the second end of the pull-down module 30 and to the negative power supply VEE. The second end of the capacitor is connected to the second end of the silicon carbide power device 210. The parameters of the capacitor can be set in combination with the actual application scenario.

[0050] In one embodiment, the first power pin VCC1, the second power pin VCC2, the first input pin IN+, the second input pin IN-, the negative power pin VEE2, the ground pin GND1, the first chip driving terminal OUT and the second chip driving terminal Clamp_OUT of the dual pull driving chip 10. The first input pin IN+ and the second input pin IN- can be combined into one input pin IN. The second power pin VCC2 is connected to the positive power supply VCC. The second power pin VCC2 is connected to the positive terminal of the first polarity capacitor 810. The negative terminal of the first polarity capacitor 810 is connected to the positive terminal of the second polarity capacitor 820. The negative terminal of the second polarity capacitor 820 is connected to the negative power supply VEE.

[0051] The first end of the negative voltage stabilization module 40 is connected to the second end of the pull-down module 30, and is connected to the negative power supply VEE. The second end of the negative voltage stabilization module 40 is connected to the second end of the silicon carbide power device 210, and is connected to the positive terminal of the second polarity capacitor 820. Through the first polarity capacitor 810 and the second polarity capacitor 820, a high capacity can be provided to store a large amount of electrical energy, which is conducive to stabilizing the voltage at both ends of the negative voltage stabilization module 40, which helps the circuit to operate stably for a long time and reduce the occurrence of faults.

[0052] See also Figure 3 In one embodiment, each pull-down module 30 includes a clamping power device 310. The driving end of the clamping power device 310 is connected to the second chip driving end of the dual pull driving chip 10. The first end of the clamping power device 310 is connected to the driving end of the silicon carbide power device 210. The second end of the clamping power device 310 is connected to the negative power supply VEE.

[0053] In this embodiment, the clamped power device 310 may be a metal-oxide-semiconductor field-effect transistor (MOSFET), which may be a P-type or an N-type. The driving end of the clamped power device 310 is a gate end, which is connected to the second chip driving end of the dual-pull driving chip 10. In one embodiment, the first end of the clamped power device 310 is a drain end, and the second end of the clamped power device 310 is a source end.

[0054] Through the clamping power device 310 in the pull-down module 30, the two branch currents divided by the D node pass through the E node to reach the clamping power device 310. After the clamping power device 310 is turned on, the branch current is introduced into the negative power supply VEE. Furthermore, through the interlocking control between the double-pull driving chip 10 and the clamping power device 310 and the silicon carbide power device 210, the pull-down path of the Miller clamp does not pass through the first parasitic inductance 610 and the second parasitic inductance 620, eliminating the influence of the first parasitic inductance 610 and the second parasitic inductance 620 on the pull-down path. Thus, through the clamping power device 310 in the silicon carbide power device parallel drive oscillation suppression circuit 100 provided in the present application, the influence of the first parasitic inductance 610 and the second parasitic inductance 620 on the parallel drive of multiple silicon carbide power devices 210 is eliminated, and the problem of repeated oscillation of the gate voltage existing in the conventional technology when the driving chip drives multiple parallel silicon carbide power devices is solved.

[0055] In one embodiment, an anode terminal of the first diode 320 is connected to the second terminal of the clamped power device 310. A cathode terminal of the first diode 320 is connected to the first terminal of the clamped power device 310. The first diode 320 is a parasitic diode of the clamped power device 310.

[0056] In one embodiment, the silicon carbide power device parallel drive oscillation suppression circuit 100 further includes a first driving module 510. A first end of the first driving module 510 is connected to a first chip driving end, and a second end of the first driving module 510 is connected to driving ends of a plurality of silicon carbide power devices 210 and first ends of a plurality of pull-down modules 30.

[0057] In this embodiment, the first driving module 510 is connected between the driving ends of the multiple silicon carbide power devices 210 and the first chip driving end of the dual-pull driving chip 10. In the process of the first chip driving end of the dual-pull driving chip 10 driving the multiple silicon carbide power devices 210, the switching speed of the multiple silicon carbide power devices 210 can be controlled to avoid the occurrence of too fast or too slow situations, and the devices in the circuit are protected. Further, in the process of the first chip driving end of the dual-pull driving chip 10 driving the multiple silicon carbide power devices 210, the damping can be increased to suppress the oscillation caused by the gate voltage fluctuation, which is conducive to the auxiliary pull-down module 30 to solve the problem of repeated oscillation of the gate voltage in the traditional technology.

[0058] The second end of the first driving module 510 is also connected to the first ends of the plurality of pull-down modules 30, so that the first driving module 510 is connected between the first ends of the plurality of pull-down modules 30 and the first chip driving end of the dual-pull driving chip 10. The first driving module 510 can play a damping role, consume oscillation energy, and suppress the amplitude and frequency of oscillation, so that the voltage at the connection point between the driving end of the silicon carbide power device 210 and the first end of the pull-down module 30 is more stable, which is more conducive to assisting the pull-down module 30 to solve the problem of repeated oscillation of the gate voltage in the traditional technology.

[0059] Therefore, the first driving module 510 can assist in solving the oscillation problem in the circuit where the silicon carbide power device 210 and the pull-down module 30 are located, thereby improving the overall reliability of the silicon carbide power device parallel drive oscillation suppression circuit 100.

[0060] In one embodiment, the silicon carbide power device parallel drive oscillation suppression circuit 100 further includes a second driving module 520 . A first end of the second driving module 520 is connected to the second chip driving end, and a second end of the second driving module 520 is connected to the driving ends of the plurality of pull-down modules 30 .

[0061] In this embodiment, the second driving module 520 is connected between the driving ends of the multiple pull-down modules 30 and the second chip driving end of the dual-pull driving chip 10. In the process of the second chip driving end of the dual-pull driving chip 10 driving the multiple pull-down modules 30, the switching speed of the multiple pull-down modules 30 can be controlled to avoid the occurrence of too fast or too slow situations, thereby protecting the components in the circuit.

[0062] Furthermore, in the process of the second chip driving end of the dual-pull driving chip 10 driving multiple pull-down modules 30, damping can be increased to suppress oscillation caused by gate voltage fluctuations, which is beneficial for assisting the pull-down module 30 to solve the problem of repeated gate voltage oscillation in traditional technologies.

[0063] Therefore, the second driving module 520 can assist in solving the oscillation problem in the circuit where the silicon carbide power device 210 and the pull-down module 30 are located, thereby improving the overall reliability of the silicon carbide power device parallel drive oscillation suppression circuit 100.

[0064] In one embodiment, the first driving module 510 includes at least one driving resistor. The second driving module 520 includes at least one driving resistor.

[0065] See also Figure 4 In one embodiment, the dual-pull driving chip 10 , the plurality of silicon carbide power devices 210 , and the plurality of pull-down modules 30 form an upper bridge arm 101 or a lower bridge arm 102 of the circuit.

[0066] In this embodiment, the second end of each silicon carbide power device 210 in the upper bridge arm 101 of the circuit is connected to the second end of each negative voltage stabilization module 40, and is connected to the first end of each silicon carbide power device 210 in the lower bridge arm 102 of the circuit. The second end of each pull-down module 30 in the upper bridge arm 101 of the circuit is connected to the first end of each negative voltage stabilization module 40, and is connected to the first negative power supply VEEH.

[0067] The second end of each silicon carbide power device 210 in the circuit lower bridge arm 102 is connected to the second end of each negative voltage stabilization module 40 and grounded. The second end of each pull-down module 30 in the circuit lower bridge arm 102 is connected to the first end of each negative voltage stabilization module 40 and connected to the second negative power supply VEEL.

[0068] The circuit structure of the upper bridge arm 101 is the same as that of the lower bridge arm 102. The upper bridge arm 101 and the lower bridge arm 102 are connected to form a multi-phase full-bridge circuit.

[0069] See also Figure 5 The present application provides a control method for a parallel drive oscillation suppression circuit for a silicon carbide power device, which is applied to the parallel drive oscillation suppression circuit 100 for a silicon carbide power device in any of the above embodiments. The control method includes: Step S10, the dual-pull driving chip 10 generates a first driving signal according to the input signal to control the on and off of the plurality of silicon carbide power devices 210; Step S20, the dual-pull driving chip 10 obtains an input signal, and generates a second driving signal according to the input signal to control the on and off of the multiple pull-down modules 30; The first driving signal and the second driving signal are pulse width modulation signals, the falling edge of the second driving signal is located before the rising edge of the first driving signal, and the rising edge of the second driving signal is located after the falling edge of the first driving signal.

[0070] In this embodiment, the falling edge of the second drive signal is the second time t2, the rising edge of the first drive signal is the third time t3, the rising edge of the second drive signal is the fifth time t5, and the falling edge of the first drive signal is the fourth time t4.

[0071] The dual-pull driver chip 10 obtains an input signal at a first moment t1, and outputs a second drive signal Clamp_OUT following the input signal at a second moment t2, controlling the multiple pull-down modules 30 to turn off. The dual-pull driver chip 10 outputs a first drive signal OUT following the input signal at a third moment t3, controlling the multiple silicon carbide power devices 210 to turn on, and controls the multiple silicon carbide power devices 210 to turn off at a fourth moment t4.

[0072] At the fifth time t5 , the dual-pull driving chip 10 outputs the second driving signal Clamp_OUT following the first driving signal OUT to control the plurality of pull-down modules 30 to be turned on.

[0073] The input signal is Figure 5 In the first moment t1, the second driving signal Clamp_OUT is a low level signal, and the plurality of pull-down modules 30 are controlled to be turned off.

[0074] At the third moment t3, the first drive signal OUT is a high level signal, controlling the multiple silicon carbide power devices 210 to be turned on. At the fourth moment t4, the first drive signal OUT is a low level signal, controlling the multiple silicon carbide power devices 210 to be turned off.

[0075] At the fifth time t5, following the first drive signal OUT, the second drive signal Clamp_OUT is output. The second drive signal Clamp_OUT is a high level signal, which controls the multiple pull-down modules 30 to be turned on, realizes the auxiliary pull-down function, and pulls the driving end of the silicon carbide power device 210 down to the negative power supply VEE.

[0076] Through the control method of the silicon carbide power device parallel drive oscillation suppression circuit provided in the present application, interlocking control between the first drive signal OUT and the second drive signal Clamp_OUT can be achieved to avoid the first drive signal OUT and the second drive signal Clamp_OUT being high-level signals at the same time, so as to ensure that the first drive signal OUT is applied to the silicon carbide power device 210 and ensure that the silicon carbide power device 210 switches normally.

[0077] Through the control method of the parallel drive oscillation suppression circuit of the silicon carbide power device provided by the present application, the first drive signal OUT and the second drive signal Clamp_OUT share the same input signal IN, and are interlocked to prevent the two drive signal outputs from being turned on at the same time. Through the control method of the parallel drive oscillation suppression circuit of the silicon carbide power device provided by the present application, in combination with the circuit structure of the peripheral pull-down module 30, the V of the silicon carbide power device 210 is pulled down by the minimum Miller clamp pull-down current loop. GS , realizing the pull-down function. Therefore, through the control method of the parallel drive oscillation suppression circuit of the silicon carbide power device provided by the present application, combined with the parallel drive oscillation suppression circuit 100 of the silicon carbide power device, the drive pull-down loop of each silicon carbide power device 210 is independent, and will not flow through the parasitic inductance of the first chip drive end and the second chip drive end of the double-pull drive chip 10, and directly reach the negative power supply VEE, eliminating the influence of the parasitic inductance of the Miller clamping loop, and solving the problem of repeated oscillation of the gate voltage of all parallel silicon carbide power devices 210.

[0078] In one embodiment, the time difference between the rising edge of the first driving signal and the rising edge of the input signal is the driving transmission delay, and the time difference between the falling edge of the second driving signal and the rising edge of the input signal is less than the driving transmission delay.

[0079] In this embodiment, the time difference between the rising edge of the first drive signal and the rising edge of the input signal is the drive transmission delay, which can also be understood as the time difference between the third moment t3 and the first moment t1 is the drive transmission delay. The time difference between the falling edge of the second drive signal and the rising edge of the input signal is less than the drive transmission delay, which can also be understood as the time difference between the second moment t2 and the first moment t1 is less than the drive transmission delay.

[0080] The first drive signal OUT completely follows the timing of the input signal IN, and is out of phase by a drive transmission delay, that is, the time difference between the first moment t1 and the third moment t3. In one embodiment, the time difference between the second moment t2 and the first moment t1 can be 20ns, that is, 20ns after the input signal IN becomes a high-level signal, the second drive signal Clamp_OUT is a low-level signal, waiting for the first drive signal OUT to become a high-level signal. The time difference between the second moment t2 and the first moment t1 can be set according to the actual application scenario, ensuring that the time difference between the second moment t2 and the first moment t1 is less than the drive transmission delay.

[0081] By setting the time between the first moment t1, the second moment t2, and the third moment t3, the first drive signal OUT and the second drive signal Clamp_OUT can form an interlocking mechanism to avoid conflicts and failures, prevent misoperation, and achieve precise signal control, so as to ensure the stable and reliable operation of the silicon carbide power device parallel drive oscillation suppression circuit 100.

[0082] In one embodiment, between the falling edge of the first drive signal and the rising edge of the second drive signal, which can also be understood as between the fourth moment t4 and the fifth moment t5, the first drive signal OUT is a low level signal and the voltage of the first drive signal OUT is less than the on-voltage threshold of the silicon carbide power device. The time difference between the rising edge of the second drive signal and the falling edge of the first drive signal can also be understood as the time difference between the fifth moment t5 and the fourth moment t4, which is determined according to the driving resistance between the dual-pull drive chip 10 and the silicon carbide power device 210 and the parasitic capacitance between the driving end and the second end of the silicon carbide power device 210.

[0083] In this embodiment, at the fourth moment t4, the first drive signal OUT becomes a low-level signal and is less than the on-voltage threshold of the silicon carbide power device. This ensures that the silicon carbide power device 210 is in the off state at this time, thereby preventing false triggering and reducing power consumption, thereby protecting the silicon carbide power device 210.

[0084] When the fifth time t5 is reached, the second driving signal Clamp_OUT becomes a high level signal, turning on the pull-down module 30 , achieving the effect of Miller clamping.

[0085] The driving resistance between the dual-pull driving chip 10 and the silicon carbide power device 210 and the parasitic capacitance between the driving end and the second end of the silicon carbide power device 210 form an RC discharge circuit. The time required for the RC discharge circuit is the time difference between the fifth moment t5 and the fourth moment t4. The time difference between the fifth moment t5 and the fourth moment t4 is determined by the driving resistance between the dual-pull driving chip 10 and the silicon carbide power device 210 and the parasitic capacitance between the driving end and the second end of the silicon carbide power device 210, and can be set to 50ns. The time difference between the fifth moment t5 and the fourth moment t4 can be set according to the actual application scenario.

[0086] See also Figure 6, through the control method of the parallel drive oscillation suppression circuit of the silicon carbide power device provided in the present application, when the upper bridge arm 101 of the circuit and the lower bridge arm 102 of the circuit are controlled together, the IN1 input signal of the upper bridge arm 101 of the circuit and the IN2 input signal of the lower bridge arm 102 of the circuit are 180° different, the OUT1 signal and the Clamp_OUT1 signal follow the IN1 input signal, and the OUT2 signal and the Clamp_OUT2 signal follow the IN2 input signal. Through the control method of the parallel drive oscillation suppression circuit of the silicon carbide power device provided in the present application, combined with the parallel drive oscillation suppression circuit 100 of the silicon carbide power device, the driving pull-down loop of each silicon carbide power device 210 is independent, and will not flow through the parasitic inductance of the first chip driving end and the second chip driving end of the double-pull driving chip 10, and directly reach the negative power supply VEE, eliminating the influence of the parasitic inductance of the Miller clamping loop, and solving the problem of repeated oscillation of the gate voltage of all parallel silicon carbide power devices 210.

[0087] See also Figure 7 and Figure 8 , Figure 7 The multiple arrow paths at the white circle position are schematic diagrams of the Miller clamp pull-down paths in traditional technology. Figure 8 The multiple arrow paths at the white circle position in the figure are schematic diagrams of the Miller clamp pull-down paths of the parallel drive oscillation suppression circuit 100 for the silicon carbide power device provided in the present application. Figure 7 and Figure 8 It can be seen very intuitively in the comparison diagram that the Miller clamp pull-down path of the parallel drive oscillation suppression circuit 100 of the silicon carbide power device provided by the present application is smaller than the Miller clamp pull-down path in the traditional technology, which can effectively reduce the length of the Miller clamp pull-down loop by 80%. Therefore, it can also be seen that the parallel drive oscillation suppression circuit 100 of the silicon carbide power device provided by the present application reduces the parasitic parameters of the Miller clamp pull-down loop, which helps to solve the problem of repeated oscillation of the gate voltage of all parallel silicon carbide power devices in the traditional technology, and ensures the stable and reliable operation of the parallel drive oscillation suppression circuit 100 of the silicon carbide power device.

[0088] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0089] The technicians in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0090] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0091] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0092] In the embodiments provided in the present application, it should be understood that the disclosed devices / terminal equipment and methods can be implemented in other ways. For example, the device / terminal equipment embodiments described above are only schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0093] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0094] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0095] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A parallel drive oscillation suppression circuit for silicon carbide power devices, characterized in that: include: Double pull drive chip (10); A plurality of silicon carbide power devices (210), wherein first ends of the plurality of silicon carbide power devices (210) are connected, second ends of the plurality of silicon carbide power devices (210) are connected, and driving ends of the plurality of silicon carbide power devices (210) are connected to a first chip driving end of the dual-pull driving chip (10); A plurality of pull-down modules (30), wherein the driving ends of the plurality of pull-down modules (30) are connected to the second chip driving end of the dual-pull driving chip (10), the first end of each of the pull-down modules (30) is connected to the driving end of each of the silicon carbide power devices (210), and the second ends of the plurality of pull-down modules (30) are connected to a negative power supply; The voltage at the first end of the silicon carbide power device (210) is greater than the voltage at the second end of the silicon carbide power device (210), and the voltage at the second end of the silicon carbide power device (210) is greater than the voltage at the second end of the pull-down module (30).

2. The parallel drive oscillation suppression circuit for silicon carbide power devices according to claim 1, characterized in that: The circuit further comprises: A plurality of negative pressure stabilization modules (40), wherein a first end of each of the negative pressure stabilization modules (40) is connected to a second end of each of the pull-down modules (30), and a second end of each of the negative pressure stabilization modules (40) is connected to a second end of each of the silicon carbide power devices (210).

3. The parallel drive oscillation suppression circuit for silicon carbide power devices according to claim 1, characterized in that: Each of the pull-down modules (30) comprises: A clamped power device (310), wherein a driving end of the clamped power device (310) is connected to a second chip driving end of the dual-pull driving chip (10), a first end of the clamped power device (310) is connected to a driving end of the silicon carbide power device (210), and a second end of the clamped power device (310) is connected to the negative power supply.

4. The parallel drive oscillation suppression circuit for silicon carbide power devices according to any one of claims 1 to 3, characterized in that: The circuit further comprises: A first driving module (510), wherein a first end of the first driving module (510) is connected to a driving end of the first chip, and a second end of the first driving module (510) is connected to driving ends of a plurality of the silicon carbide power devices (210) and first ends of a plurality of the pull-down modules (30).

5. The parallel drive oscillation suppression circuit for silicon carbide power devices according to any one of claims 1 to 3, characterized in that: The circuit further comprises: A second driving module (520), wherein a first end of the second driving module (520) is connected to a driving end of the second chip, and a second end of the second driving module (520) is connected to driving ends of the plurality of pull-down modules (30).

6. The parallel drive oscillation suppression circuit for silicon carbide power devices according to any one of claims 1 to 3, characterized in that: The dual-pull driving chip (10), the plurality of silicon carbide power devices (210) and the plurality of pull-down modules (30) form an upper bridge arm (101) of a circuit or a lower bridge arm (102) of a circuit.

7. A control method for a parallel drive oscillation suppression circuit of a silicon carbide power device, characterized in that: Applicable to the parallel drive oscillation suppression circuit of a silicon carbide power device according to any one of claims 1 to 6, the control method comprising: A dual-pull driving chip (10) generates a first driving signal according to an input signal to control the on and off of a plurality of silicon carbide power devices (210); The dual-pull driving chip (10) acquires the input signal, and generates a second driving signal according to the input signal to control the on and off of a plurality of pull-down modules (30); The first drive signal and the second drive signal are pulse width modulation signals, the falling edge of the second drive signal is located before the rising edge of the first drive signal, and the rising edge of the second drive signal is located after the falling edge of the first drive signal.

8. The control method of the parallel drive oscillation suppression circuit of the silicon carbide power device according to claim 7, characterized in that: The time difference between the rising edge of the first driving signal and the rising edge of the input signal is the driving transmission delay, and the time difference between the falling edge of the second driving signal and the rising edge of the input signal is less than the driving transmission delay.

9. The control method of the parallel drive oscillation suppression circuit of the silicon carbide power device according to claim 7, characterized in that: Between the falling edge of the first driving signal and the rising edge of the second driving signal, the first driving signal is a low level signal and the voltage of the first driving signal is less than a turn-on voltage threshold of the silicon carbide power device.

10. The control method of the parallel drive oscillation suppression circuit of the silicon carbide power device according to claim 7, characterized in that: The time difference between the rising edge of the second drive signal and the falling edge of the first drive signal is determined according to the drive resistance between the dual-pull drive chip (10) and the silicon carbide power device (210) and the parasitic capacitance between the drive end and the second end of the silicon carbide power device (210).

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