Anti-interference circuit, anti-interference method and receiver

Abstract

The invention discloses an anti-interference circuit, an anti-interference method and a receiver. The circuit comprises a signal amplification unit, an interference attenuation unit, a demodulator and a control processor, the signal amplification unit, the interference attenuation unit and the demodulator are connected in sequence, and are used for transmitting a signal received by the receiving antenna to the demodulator for demodulation through the signal amplification unit and the interference attenuation unit in sequence; the signal amplification unit comprises an amplification path and a first through path, and the interference attenuation unit comprises an attenuation path and a second through path; and the control processor is connected with the demodulator, and is used for receiving the demodulation error times of the demodulator, controlling the signal amplification unit to switch between the amplification path and the first through path according to the demodulation error times, and controlling the interference attenuation unit to switch between the attenuation path and the second through path. And the control processor switches the different paths according to the number of demodulation errors of the demodulator, so that the number of demodulation errors is reduced to a certain extent.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of anti-interference technology, and in particular, to an anti-interference circuit, an anti-interference method and a receiver. Background Art

[0002] The zero-IF receiver has the advantages of high receiving sensitivity, simple structure, small size, high integration and low cost. It has great advantages in the miniaturization and low cost of handheld terminals, and is gradually replacing the superheterodyne receiver and becoming the mainstream solution for handheld terminals.

[0003] At present, the anti-interference circuit of the receiver usually has an amplifier circuit to improve the filtering performance of weak interference. However, in the case of strong interference from multiple signals, the amplifier circuit is in a strong nonlinear state, which will produce a lot of intermodulation components, causing serious signal distortion, directly affecting the receiving demodulation, and causing demodulation errors.

[0004] When demodulation errors occur frequently and exceed a certain number within a certain period of time, the receiver is usually judged to be offline and needs to be re-connected to the network. This will lead to a decrease in the network connection stability of the receiver and have a certain negative impact on the user experience. Summary of the invention

[0005] The embodiments of the present application provide an anti-interference circuit, an anti-interference method and a receiver to improve the network injection stability of the receiver.

[0006] In a first aspect, an embodiment of the present application provides an anti-interference circuit, the circuit comprising: a signal amplification unit, an interference attenuation unit, a demodulator, and a control processor;

[0007] The signal amplifying unit, the interference attenuation unit and the demodulator are connected in sequence, and are used to transmit the signal received by the receiving antenna to the demodulator through the signal amplifying unit and the interference attenuation unit in sequence for demodulation;

[0008] The signal amplification unit includes an amplification path and a first direct path, and the interference attenuation unit includes an attenuation path and a second direct path;

[0009] The control processor is connected to the demodulator, and is used to receive the number of demodulation errors of the demodulator, and control the signal amplification unit to switch between the amplification path and the first direct path according to the number of demodulation errors, and control the interference attenuation unit to switch between the attenuation path and the second direct path.

[0010] In a second aspect, an embodiment of the present application provides an anti-interference method, which is applied to the anti-interference circuit provided in any embodiment of the present application, and the method includes:

[0011] The control processor obtains the number of demodulation errors of the demodulator;

[0012] The control processor controls the signal amplification unit to switch between the amplification path and the first direct path according to the number of demodulation errors, and controls the interference attenuation unit to switch between the attenuation path and the second direct path.

[0013] In a third aspect, an embodiment of the present application provides a receiver, comprising: a receiving antenna and an anti-interference circuit provided by any embodiment of the present application, wherein the receiving antenna is connected to a signal amplification unit in the anti-interference circuit.

[0014] The technical solution of the embodiment of the present application is to set an amplification path and a first direct path in the signal amplification unit, and set an attenuation path and a second direct path in the interference attenuation unit. The control processor switches the above-mentioned different paths according to the number of demodulation errors of the demodulator, thereby reducing the number of demodulation errors to a certain extent, and to a certain extent, avoiding the number of demodulation errors from continuing to increase to the point of being determined to be offline, thereby reducing the frequency of offline occurrence to a certain extent and improving its network injection stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A schematic diagram of the structure of an anti-interference circuit provided in Embodiment 1 of the present application;

[0016] Figure 2 A schematic diagram of the structure of another anti-interference circuit provided in Embodiment 1 of the present application;

[0017] Figure 3 A flowchart of an anti-interference method provided in Example 2 of the present application. DETAILED DESCRIPTION

[0018] The present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for ease of description, only the parts related to the present application, rather than all structures, are shown in the accompanying drawings.

[0019] Embodiment 1

[0020] Figure 1 This is a schematic diagram of the structure of an anti-interference circuit provided in Example 1 of the present application. Figure 1 As shown, the anti-interference circuit provided in this embodiment may include: a signal amplifying unit 101 , an interference attenuation unit 102 , a demodulator 103 and a control processor 104 .

[0021] The signal amplifying unit 101, the interference attenuation unit 102 and the demodulator 103 are connected in sequence, and the signal received by the receiving antenna 105 is transmitted to the demodulator 103 through the signal amplifying unit 101 and the interference attenuation unit in sequence, and the demodulator 103 demodulates the signal.

[0022] like Figure 1 As shown, after receiving the signal, the receiving antenna 105 transmits it to the signal amplifying unit 101. After passing through the signal amplifying unit 101, it passes through the interference attenuation unit 102 and enters the demodulator 103 for demodulation. The demodulation result indicating whether the demodulation is successful will be sent to the control processor 104.

[0023] In addition, if Figure 1 As shown, the signal amplifying unit 101 includes an amplifying path 1011 and a first straight path 1012 , and the interference attenuation unit 102 includes an attenuation path 1021 and a second straight path 1022 .

[0024] Among them, the amplifier path 1011 is used to amplify the passing signal. The signal will be amplified when passing through the amplifier path 1011. The first straight path 1012 will not process the passing signal. The signal will pass directly through the first straight path 1012. In addition, the signal selectively passes through the amplifier path 1011 and the first straight path 1012, that is, the signal will only pass through one of the amplifier path 1011 and the first straight path 1012 in the signal amplification unit 101.

[0025] In the interference attenuation unit 102, if the signal passes through the attenuation path 1021, some corresponding interference components in the signal will be attenuated. Its attenuation capability is related to the hardware parameters of the attenuation path, that is, different interferences can be attenuated by setting the attenuation decibel of the attenuation path 1021.

[0026] If the signal passes through the second direct path 1022, the second direct path 1022 will not process the signal but pass it directly. In addition, the signal selectively passes through the attenuation path 1021 and the second direct path 1022, that is, the signal will only pass through one of the attenuation path 1021 and the second direct path 1022 in the interference attenuation unit 102.

[0027] The control processor 104 is connected to the demodulator 103, and is used to receive the number of demodulation errors of the demodulator 103, and switch the amplification path 1011 and the first direct path 1012 in the signal amplification unit 101 and the attenuation path 1021 and the second direct path 1022 in the interference attenuation unit 102 according to the number of demodulation errors.

[0028] like Figure 1As shown, the control processor 104 is communicatively connected with the signal amplifying unit 101 and the interference attenuation unit 102, and is used to switch the amplifying path 1011 and the first direct path 1012 in the signal amplifying unit 101, and to switch the attenuating path 1021 and the second direct path 1022 in the interference attenuation unit 102 by sending a switching signal.

[0029] In one embodiment, see Figure 2 , Figure 2 A schematic diagram of the structure of another anti-interference circuit provided in Example 1 of the present application.

[0030] like Figure 2 As shown, the amplification path 1011 includes a signal amplifier, and the first direct path 1012 includes a first bypass switch; the signal amplifier and the first bypass switch are connected in parallel between the receiving antenna 105 and the interference attenuation unit 102, and the control processor 104 is connected to the first bypass switch for switching the amplification path 1011 and the first direct path 1012 by controlling the switching state of the first bypass switch.

[0031] Since the signal amplifier is connected in parallel with the first bypass switch, when the first bypass switch is closed, the signal amplifier is short-circuited, thereby switching to the first direct path 1012. When the first bypass switch is opened, the signal flows through the signal amplifier, thereby switching to the amplification path 1011.

[0032] Therefore, the control processor 104 can switch the path by controlling the on / off state of the first bypass switch. In a specific example, the signal amplifier and the first bypass switch can be integrated into the same chip, such as a chip of model RF2374. In this case, the first bypass switch can be the bypass switch of the chip. It should be noted that the components involved in the specific circuit of the chip can refer to the relevant manual of the chip model, which will not be repeated here.

[0033] The attenuation path 1021 includes an interference attenuator, and the second direct path 1022 includes a second bypass switch; the interference attenuator and the second bypass switch are connected in parallel between the signal amplification unit 101 and the demodulator 103; the control processor 104 is connected to the second bypass switch, and is used to switch the attenuation path 1021 and the second direct path 1022 by controlling the switching state of the second bypass switch.

[0034] Similarly, since the interference attenuator is connected in parallel with the second bypass switch, when the second bypass switch is closed, the interference attenuator is short-circuited, thereby switching to the second through path 1022. When the second bypass switch is opened, the signal flows through the interference attenuator, thereby switching to the attenuation path 1021.

[0035] Therefore, the control processor 104 can switch the path by controlling the on / off state of the second bypass switch. In a specific example, the attenuation path 1021 and the second direct path 1022 can be implemented by combining two chips of the same model, and the chip model can be MXD8621C, wherein the channel formed between the pin3 pins of the two chips is the second direct path 1021, and the channel between the pin1 pins of the two chips corresponds to the attenuation path 1022.

[0036] It should be noted that the components involved in the specific circuit of the chip can be found in the relevant manual of the chip model, and will not be repeated here.

[0037] In addition, for the specific switching of the path, the control processor 104 keeps the signal amplifying unit 101 in the amplifying path 1011 and the interference attenuation unit 102 in the second direct path 1022 when the number of demodulation errors received is less than the first preset threshold within the preset time length;

[0038] The control processor 104 keeps the signal amplification unit in the amplification path 1011 and switches the interference attenuation unit 102 to the attenuation path 1021 when the number of demodulation errors received within the preset time length is greater than or equal to the first preset threshold and less than the second preset threshold;

[0039] The control processor 104 switches the signal amplifying unit 101 to the first direct path 1011 and switches the interference attenuation unit 102 to the second direct path 1022 when the number of demodulation errors received within the preset time length is greater than or equal to the second preset threshold;

[0040] When the number of demodulation errors received within a preset time length is greater than or equal to a third preset threshold, the control processor 104 switches the signal amplifying unit 101 to the amplifying path 1011 and switches the interference attenuation unit 102 to the second direct path 1022 .

[0041] It should be noted that the third preset threshold is smaller than the offline determination threshold, and the values ​​of the first preset threshold, the second preset threshold, and the third preset threshold increase in sequence. That is, the second preset threshold is larger than the first preset threshold, and the third preset threshold is larger than the second preset threshold.

[0042] In a specific example, the network-offline determination threshold may be 8, and the preset time length may be the time corresponding to 18 frames. The first preset threshold may be 2, the second preset threshold may be 4, and the third preset threshold may be 6. If the number of demodulation errors received by the control processor 104 is less than 2 within 18 frames, the anti-interference circuit is kept in state 1, and state 1 corresponds to the signal amplification unit 101 being in the amplification path 1011 and the interference attenuation unit 102 being in the second direct path 1022.

[0043] After the number of demodulation errors received by the control processor 104 is greater than or equal to 2 within 18 frames, the state of the anti-interference circuit is switched to state 2, and the state 2 corresponds to the signal amplification unit 101 being in the amplification path 1011, and the interference attenuation unit 102 is switched to the attenuation path 1021. In state 2, the attenuation path 1021 is connected, which can attenuate part of the interference, thereby alleviating the demodulation error situation.

[0044] After the switching is completed, if the current time is still within 18 frames, the control processor 104 continues to accumulate the number of demodulation errors received. If the demodulation error no longer increases at this time, state 2 is maintained. If it increases to 4, it switches to state 3. State 3 corresponds to the signal amplification unit 101 being the first direct path 1011, and the interference attenuation unit 102 being the second direct path 1022.

[0045] In state 3, the amplification path 1011 is switched to the first direct path 1012, so as to eliminate the amplification of the interference in the signal and reduce the nonlinearity of the interference.

[0046] After the switch is completed, if it is still within the 18-frame time, the control processor 104 continues to accumulate the number of demodulation errors received. If the demodulation errors no longer increase, state 3 is maintained. If it increases to 6, it switches to state 1 and issues a network disconnection alarm.

[0047] In this embodiment, an amplification path and a first direct path are set in the signal amplification unit, and an attenuation path and a second direct path are set in the interference attenuation unit. The control processor switches the above-mentioned different paths according to the number of demodulation errors of the demodulator, thereby reducing the number of demodulation errors to a certain extent, avoiding the number of demodulation errors from continuing to increase to the point where offline is determined, thereby reducing the frequency of offline occurrence and improving its network injection stability.

[0048] Embodiment 2

[0049] See also Figure 3 , Figure 3 The flowchart of an anti-interference method provided in the second embodiment of the present application is shown in FIG. The anti-interference method of this embodiment is applied to the anti-interference circuit mentioned in the above embodiment.

[0050] like Figure 3 As shown, the anti-interference method provided in this embodiment includes:

[0051] Step 301: Control the processor to obtain the number of demodulation errors of the demodulator.

[0052] In this step, the demodulation error can be obtained by sending a corresponding error signal to the control processor each time a demodulation error occurs, and the control processor records the time and number of times the error signal is received, and then uses the number as the number of demodulation errors.

[0053] It should be noted that the control processor accumulates the times with a certain periodicity, that is, every time the preset time length is reached, the control processor will reset the accumulated times and restart the accumulation. For example, if the preset time length is the time corresponding to 18 frames, the control processor starts to accumulate the times and counts at the same time, and when the count reaches the time of 18 frames, the accumulated times and the count time are reset, and the accumulated times and the count time are restarted.

[0054] Step 302: The control processor controls the signal amplification unit to switch between the amplification path and the first direct path according to the number of demodulation errors, and controls the interference attenuation unit to switch between the attenuation path and the second direct path.

[0055] Since the mechanism of clearing the accumulated number and the timing duration is set in the aforementioned steps, therefore, in this step, when switching, it refers to the switching occurring within the same preset time length. Specifically, the control processor keeps the number of demodulation errors received within the preset time length less than the first preset threshold, and keeps the signal amplification unit in the amplification path and the interference attenuation unit in the second direct path;

[0056] The control processor keeps the signal amplification unit in the amplification path and switches the interference attenuation unit to the attenuation path when the number of demodulation errors received within the preset time length is greater than or equal to the first preset threshold and less than the second preset threshold;

[0057] The control processor switches the signal amplification unit to the first direct path and the interference attenuation unit to the second direct path when the number of demodulation errors received within the preset time length is greater than or equal to a second preset threshold, wherein the second preset threshold is greater than the first preset threshold;

[0058] The control processor switches the signal amplification unit to the amplification path and the interference attenuation unit to the second direct path if the number of demodulation errors received within the preset time length is greater than or equal to the third preset threshold, wherein the third preset threshold is greater than the second preset threshold.

[0059] In a specific example, the network-offline determination threshold may be 8, and the preset time length may be the time corresponding to 18 frames. The first preset threshold may be 2, the second preset threshold may be 4, and the third preset threshold may be 6. If the number of demodulation errors received by the control processor within 18 frames is less than 2, the anti-interference circuit is kept in state 1, and state 1 corresponds to the signal amplification unit being in the amplification path and the interference attenuation unit being in the second direct path.

[0060] When the number of demodulation errors received by the control processor is greater than or equal to 2 within 18 frames, the state of the anti-interference circuit is switched to state 2. State 2 corresponds to the signal amplification unit being in the amplification path, and the interference attenuation unit is switched to the attenuation path. In state 2, the attenuation path is connected to attenuate part of the interference, thereby alleviating the demodulation error.

[0061] After the switching is completed, if it is still within the 18-frame time, the control processor continues to accumulate the number of demodulation errors received. If the demodulation error no longer increases at this time, state 2 is maintained. If it increases to 4, it switches to state 3. State 3 corresponds to the signal amplification unit as the first direct path, and the interference attenuation unit as the second direct path.

[0062] In state 3, the amplification path is switched to the first direct path, which can eliminate the amplification of interference in the signal and reduce the nonlinearity of the interference.

[0063] After the switch is completed, if it is still within the 18-frame time, the control processor continues to accumulate the number of demodulation errors received. If the demodulation errors no longer increase at this time, state 3 is maintained. If it increases to 6, it switches to state 1 and issues a network disconnection alarm.

[0064] In this embodiment, an amplification path and a first direct path are set in the signal amplification unit, and an attenuation path and a second direct path are set in the interference attenuation unit. The control processor switches the above-mentioned different paths according to the number of demodulation errors of the demodulator, thereby reducing the continued increase in the number of demodulation errors to a certain extent, avoiding the number of demodulation errors from continuing to increase to the number of times when offline is determined, thereby reducing the frequency of offline occurrence and improving its network injection stability.

[0065] Embodiment 3

[0066] This embodiment provides a receiver, which may be a zero intermediate frequency receiver. The receiver includes a receiving antenna and an anti-interference circuit as provided in any embodiment of the present application.

[0067] The receiving antenna is connected to the signal amplifying unit in the anti-interference circuit, and the control processor in the anti-interference circuit is used to execute the anti-interference method provided in any embodiment of the present application.

[0068] Specifically, the receiver receives a signal through a receiving antenna, passes through a signal amplification unit, and then passes through an interference attenuation unit, and enters a demodulator for demodulation. A demodulation result indicating whether the demodulation is successful is sent to a control processor.

[0069] The control processor switches the above-mentioned different paths according to the number of demodulation errors of the demodulator, thereby reducing the continued increase in the number of demodulation errors to a certain extent, avoiding the continuous increase in the number of demodulation errors to the number of times when offline is determined, thereby reducing the frequency of offline occurrence and improving its network stability.

[0070] Note that the above are only preferred embodiments of the present application and the technical principles used. Those skilled in the art will understand that the present application is not limited to the specific embodiments herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present application. Therefore, although the present application is described in more detail through the above embodiments, the present application is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present application, and the scope of the present application is determined by the scope of the appended claims.

Claims

1. An anti-interference circuit, characterized in that: The anti-interference circuit includes: a signal amplification unit, an interference attenuation unit, a demodulator and a control processor; The signal amplifying unit, the interference attenuation unit and the demodulator are connected in sequence, and are used to transmit the signal received by the receiving antenna to the demodulator through the signal amplifying unit and the interference attenuation unit in sequence for demodulation; The signal amplification unit includes an amplification path and a first direct path, and the interference attenuation unit includes an attenuation path and a second direct path; The control processor is connected to the demodulator, and is used to receive the number of demodulation errors of the demodulator, and control the signal amplification unit to switch between the amplification path and the first direct path according to the number of demodulation errors, and control the interference attenuation unit to switch between the attenuation path and the second direct path.

2. The anti-interference circuit according to claim 1, characterized in that: The amplification path includes a signal amplifier, and the first through path includes a first bypass switch; The signal amplifier and the first bypass switch are connected in parallel between the antenna and the interference attenuation unit, and the control processor is connected to the first bypass switch and is used to switch the amplification path and the first direct path by controlling the switching state of the first bypass switch; And / or, the attenuation path includes an interference attenuator, and the second through path includes a second bypass switch; the interference attenuator and the second bypass switch are connected in parallel between the signal amplification unit and the demodulator; The control processor is connected to the second bypass switch and is used to switch the attenuation path and the second direct-through path by controlling the switching state of the second bypass switch.

3. The anti-interference circuit according to claim 1, characterized in that: When the number of demodulation errors received by the control processor within a preset time length is less than a first preset threshold, the signal amplification unit is kept in the amplification path and the interference attenuation unit is kept in the second direct path; When the number of demodulation errors received by the control processor within a preset time length is greater than or equal to the first preset threshold, the control processor keeps the signal amplification unit in the amplification path and switches the interference attenuation unit to the attenuation path.

4. The anti-interference circuit according to claim 3, characterized in that: When the number of demodulation errors received by the control processor within a preset time length is greater than or equal to a second preset threshold, the signal amplification unit is switched to a first direct path and the interference attenuation unit is switched to a second direct path, wherein the second preset threshold is greater than the first preset threshold.

5. The anti-interference circuit according to claim 4, characterized in that: When the number of demodulation errors received by the control processor within a preset time length is greater than or equal to a third preset threshold, the control processor switches the signal amplification unit to an amplification path and switches the interference attenuation unit to a second direct path, wherein the third preset threshold is greater than the second preset threshold.

6. The anti-interference circuit according to claim 5, characterized in that: The third preset threshold is smaller than the network-offline determination threshold.

7. An anti-interference method, characterized in that: Applied to the anti-interference circuit according to any one of claims 1 to 2, the anti-interference method comprises: The control processor obtains the number of demodulation errors of the demodulator; The control processor controls the signal amplification unit to switch between the amplification path and the first direct path according to the number of demodulation errors, and controls the interference attenuation unit to switch between the attenuation path and the second direct path.

8. The anti-interference method according to claim 7, characterized in that: The control processor controls the signal amplification unit to switch between the amplification path and the first direct path according to the number of demodulation errors, and controls the interference attenuation unit to switch between the attenuation path and the second direct path, including: When the number of demodulation errors received by the control processor within a preset time length is less than a first preset threshold, the signal amplification unit is kept in the amplification path and the interference attenuation unit is kept in the second direct path; When the number of demodulation errors received by the control processor within a preset time length is greater than or equal to the first preset threshold, the control processor keeps the signal amplification unit in the amplification path and switches the interference attenuation unit to the attenuation path.

9. The anti-interference method according to claim 7, characterized in that: The control processor controls the signal amplification unit to switch between the amplification path and the first direct path according to the number of demodulation errors, and controls the interference attenuation unit to switch between the attenuation path and the second direct path, and further includes: When the number of demodulation errors received by the control processor within a preset time length is greater than or equal to a second preset threshold, the signal amplification unit is switched to a first direct path and the interference attenuation unit is switched to a second direct path, wherein the second preset threshold is greater than the first preset threshold.

10. The anti-interference method according to claim 9, characterized in that: The control processor controls the signal amplification unit to switch between the amplification path and the first direct path according to the number of demodulation errors, and controls the interference attenuation unit to switch between the attenuation path and the second direct path, and further includes: When the number of demodulation errors received by the control processor within a preset time length is greater than or equal to a third preset threshold, the control processor switches the signal amplification unit to an amplification path and switches the interference attenuation unit to a second direct path, wherein the third preset threshold is greater than the second preset threshold.

11. A receiver, characterized in that: The receiver comprises a receiving antenna and the anti-interference circuit according to any one of claims 1 to 6, wherein the receiving antenna is connected to a signal amplifying unit in the anti-interference circuit.

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