Static random access memory array, memory and preparation method of memory array

Abstract

The invention provides a static random access memory array, a memory, electronic equipment and a preparation method. Relates to the technical field of data storage. A memory cell in the SRAM memory array comprises a first transistor, a second transistor, a third transistor and a fourth transistor, the first transistor and the third transistor are connected in series, a series coupling point of the first transistor and the third transistor forms a first data storage node, the second transistor and the fourth transistor are connected in series, and a series coupling point of the second transistor and the fourth transistor forms a second data storage node. Part of transistors in the 4T storage unit can be manufactured by adopting a previous process, part of transistors can be manufactured by adopting a subsequent process, or all transistors in the 4T storage unit are manufactured by adopting the subsequent process. Three-dimensional stacking of the storage units can be achieved through post-integration, and the storage density and the storage capacity are improved.

Description

Technical Field

[0001] The present application relates to the technical field of data storage, and in particular to a static random access memory array, a memory including the static random access memory array, an electronic device including the memory, and a method for preparing the static random access memory array. Background Art

[0002] With the rapid development of technologies such as big data, the Internet of Things, machine learning, and virtual reality, the amount of data and data processing needs are growing, which puts higher requirements on the capacity and speed of memory chips. On the one hand, memory chips need to have high storage density to store massive application data, and on the other hand, they must have high storage speed to achieve fast data interaction.

[0003] In the von Neumann architecture, data needs to be transferred from the memory to the processor for calculation, and the calculation results are then transferred back to the memory through the serial bus after the calculation is completed. Therefore, the data access speed of the memory also directly affects the calculation speed of the entire computer system. In the current memory hierarchy architecture, static random-access memory (SRAM) has the highest data storage speed among all types of memory and can directly connect to the processor for data interaction, so it is widely used.

[0004] Although SRAM memory has a high data storage speed, it has a low storage density and a small storage capacity and cannot support high-density and high-capacity storage applications. Summary of the invention

[0005] The present application provides a static random access memory array, a memory including the static random access memory array, an electronic device including the memory, and a method for preparing the static random access memory array. The purpose is to provide an SRAM memory array that can improve storage density and storage capacity.

[0006] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0007] In a first aspect, the present application provides a SRAM storage array.

[0008] The SRAM storage array includes a word line WL, a first bit line BL and a second bit line BLB, and a storage unit; the storage unit includes a first transistor, a second transistor, a third transistor and a fourth transistor; the first transistor and the third transistor are coupled in series between the first bit line and the voltage terminal; the second transistor and the fourth transistor are coupled in series between the second bit line and the voltage terminal; the control terminal of the first transistor and the control terminal of the second transistor are both electrically connected to the word line; the series coupling point of the first transistor and the third transistor is electrically connected to the control terminal of the fourth transistor; the series coupling point of the second transistor and the fourth transistor is electrically connected to the control terminal of the third transistor.

[0009] In the process structure of the storage array, the first transistor, the second transistor, the third transistor and the fourth transistor are all located in the back-end device layer; or, the first transistor and the second transistor are located in the back-end device layer, and the third transistor and the fourth transistor are located in the front-end device layer; or, the first transistor and the second transistor are located in the front-end device layer, and the third transistor and the fourth transistor are located in the back-end device layer.

[0010] In the memory array provided in the present application, the memory cell belongs to a 4T memory cell, in which four transistors can be integrated in the back-end device layer using the back-end process, or two of the four transistors can be made in the back-end device layer using the back-end process, and the other two transistors can be made in the front-end device layer using the front-end process, instead of making all transistors using the front-end process. In the process structure of the example of the present application, three-dimensional stacking of memory cells can be achieved through back-end integration, thereby improving storage density and storage capacity.

[0011] In one achievable manner, the first transistor and the second transistor are located in a first back-end device layer; the third transistor and the fourth transistor are located in a second back-end device layer; and the first back-end device layer and the second back-end device layer are stacked in a direction perpendicular to a surface of a storage array substrate.

[0012] In this implementation structure, the first transistor and the third transistor coupled in series are stacked in different back-end device layers, and can be electrically connected through metal traces and silicon vias. Similarly, the second transistor and the fourth transistor coupled in series are stacked in different back-end device layers, and can also be electrically connected through metal traces and silicon vias.

[0013] In one achievable method, the first transistor and the second transistor are located in a first back-end device layer; the third transistor and the fourth transistor are located in a second back-end device layer, the first transistor and the second transistor can both be N-type field effect transistors, or both be P-type field effect transistors, the channel materials of the first transistor and the second transistor can be selected from oxide semiconductors or polysilicon, the third transistor and the fourth transistor can both be N-type field effect transistors, and the channel materials of the third transistor and the fourth transistor can be selected from N-type oxide semiconductors.

[0014] In one achievable manner, the first transistor and the second transistor are located in the same back-end device layer, and the third transistor and the fourth transistor are located in a front-end device layer.

[0015] In one achievable manner, the first transistor and the second transistor are located in a front-end device layer, and the third transistor and the fourth transistor are located in the same back-end device layer.

[0016] In this example, the first transistor and the second transistor may be P-type field effect transistors based on a single crystal silicon channel.

[0017] In one possible implementation, the first transistor and the second transistor are arranged along a first direction parallel to a surface of a memory array substrate; and the third transistor and the fourth transistor are arranged along the first direction.

[0018] In one achievable manner, the orthographic projection of the first transistor on the storage array substrate at least partially overlaps with the orthographic projection of the third transistor on the storage array substrate; the orthographic projection of the second transistor on the storage array substrate at least partially overlaps with the orthographic projection of the fourth transistor on the storage array substrate.

[0019] By adopting this process structure, the vertical projection area of ​​a storage unit can be reduced, and the storage density can be significantly improved.

[0020] In one achievable manner, the static random access memory array further includes: an interconnection wiring layer; a control end of the fourth transistor and a first electrode of the third transistor, electrically connected to the first electrode of the first transistor via the interconnection wiring layer; and a control end of the third transistor and a first electrode of the fourth transistor, electrically connected to the first electrode of the second transistor via the interconnection wiring layer.

[0021] In one achievable manner, the first transistor, the second transistor, the third transistor, and the fourth transistor are located in the same back-end device layer.

[0022] In one possible implementation, the first transistor and the third transistor are arranged along a second direction parallel to the surface of the storage array substrate; the second transistor and the fourth transistor are arranged along the second direction; the first transistor and the second transistor are arranged along a third direction parallel to the surface of the storage array substrate; the third transistor and the fourth transistor are arranged along the third direction; the third direction intersects with the second direction.

[0023] In one achievable manner, the first electrode of the first transistor and the first electrode of the third transistor share the same electrode layer; the first electrode of the second transistor and the first electrode of the fourth transistor share the same electrode layer. This can simplify the process structure.

[0024] In one achievable manner, the electrode layer shared by the first electrode of the first transistor and the first electrode of the third transistor is the first common electrode layer, and the electrode layer shared by the first electrode of the second transistor and the first electrode of the fourth transistor is the second common electrode layer; the static random access memory array also includes: an interconnection routing layer; the first common electrode layer is electrically connected to the control end of the fourth transistor through the interconnection routing layer; the second common electrode layer is electrically connected to the control end of the third transistor through the interconnection routing layer.

[0025] In one implementation, the first transistor, the second transistor, the third transistor, and the fourth transistor are N-type field effect transistors, and a channel material of the N-type field effect transistor includes an oxide semiconductor material.

[0026] When the channel of the transistor is made of oxide semiconductor material, the leakage current can be reduced, the retention time can be increased, the refresh frequency can be reduced, the power consumption can be reduced, and the storage performance can be improved; and, since the growth temperature of semiconductor oxide is low, a three-dimensional stacked storage array can be produced by a back-end process to increase the storage density without affecting the performance of the device produced by the front-end process.

[0027] In a second aspect, the present application provides a memory, which may include a controller and an SRAM storage array in any of the above-mentioned implementations, wherein the controller is electrically connected to the static random access storage array, and the controller is used to control the reading and writing of the static random access storage array.

[0028] In the SRAM storage array of the memory provided in the present application, since some transistors in the storage unit can be manufactured by the back-end process, or all transistors in the storage unit can be manufactured by the back-end process, thus, three-dimensional stacking of the storage unit can be realized by back-end integration, and the storage density and storage capacity can be improved, so that the memory meets the requirements of high density and high capacity, and the data storage speed of the entire computing system is improved.

[0029] In a third aspect, the present application provides an electronic device, comprising a processor and a memory in any of the above-mentioned implementations, wherein the processor is electrically connected to the memory, and the memory is used to store data generated by the processor.

[0030] Since the electronic device includes the above-mentioned memory, the electronic device and the memory solve the same technical problem and achieve the same technical effect.

[0031] In a fourth aspect, the present application provides a method for preparing a static random access memory array, the method comprising:

[0032] forming a front-end device layer in the substrate by using a front-end process;

[0033] A back-end device layer and an interconnection wiring layer are formed on the front-end device layer by using a back-end process;

[0034] A memory cell, a word line, a first bit line and a second bit line are formed in the front-end device layer, the back-end device layer and the interconnection wiring layer. The memory cell includes a first transistor, a second transistor, a third transistor and a fourth transistor; the first transistor and the third transistor are coupled in series between the first bit line and the voltage terminal; the second transistor and the fourth transistor are coupled in series between the second bit line and the voltage terminal; the control terminal of the first transistor and the control terminal of the second transistor are both electrically connected to the word line; the series coupling point of the first transistor and the third transistor is electrically connected to the control terminal of the fourth transistor; the series coupling point of the second transistor and the fourth transistor is electrically connected to the control terminal of the third transistor;

[0035] Forming the front-end device layer and the back-end device layer, including:

[0036] The first transistor, the second transistor, the third transistor and the fourth transistor are all formed in a back-end device layer; or,

[0037] The first transistor and the second transistor are formed in a back-end device layer, and the third transistor and the fourth transistor are formed in a front-end device layer; or,

[0038] The first transistor and the second transistor are formed in a front-end device layer, and the third transistor and the fourth transistor are formed in a back-end device layer.

[0039] The memory cell manufactured by this method is a 4T memory cell, including four transistors. The four transistors can all be integrated in the back-end device layer, or some of the four transistors are integrated in the back-end device layer and others are integrated in the front-end device layer. Thus, three-dimensional stacking of memory cells can be achieved to improve storage capacity.

[0040] In one achievable method, a front-end device layer and a back-end device layer are formed, including: forming a first transistor and a second transistor in a first back-end device layer; forming a third transistor and a fourth transistor in a second back-end device layer, and the first back-end device layer and the second back-end device layer are stacked in a direction perpendicular to a storage array substrate.

[0041] In one achievable manner, forming a front-end device layer and a back-end device layer includes: forming a first transistor and a second transistor in the front-end device layer; and forming a third transistor and a fourth transistor in the same back-end device layer.

[0042] In one achievable manner, forming a front-end device layer and a back-end device layer includes: forming a third transistor and a fourth transistor in the front-end device layer; and forming a first transistor and a second transistor in the same back-end device layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 A circuit diagram of an electronic device;

[0044] Figure 2 A circuit diagram of a memory;

[0045] Figure 3A A packaging structure diagram of a storage array and a controller;

[0046] Figure 3B A packaging structure diagram of a storage array and a controller;

[0047] Figure 3C A packaging structure diagram of a storage array and a controller;

[0048] Figure 4 A simple circuit diagram of a memory;

[0049] Figure 5 A circuit diagram of a 4T memory cell provided in an embodiment of the present application;

[0050] Figure 6 A circuit diagram of a 4T memory cell provided in an embodiment of the present application;

[0051] Figure 7 A simplified process structure diagram of a storage array provided in an embodiment of the present application;

[0052] Figures 8 to 12 A layout of a storage array provided in an embodiment of the present application;

[0053] Figures 13 to 16 A layout of a storage array provided in an embodiment of the present application;

[0054] Figures 17 to 20A layout of a storage array provided in an embodiment of the present application. DETAILED DESCRIPTION

[0055] The following embodiments of the present application are described below in conjunction with the drawings in the embodiments of the present application.

[0056] The technical solution of the present application can be applied to various electronic devices using memory, such as: Figure 1 This is a circuit block diagram of an electronic device 100 provided in an embodiment of the present application. The electronic device 100 can be a terminal device, such as a mobile phone, a tablet computer, a smart bracelet, or a personal computer (PC), a server, a workstation, etc.

[0057] like Figure 1 , the electronic device 100 may include a bus 205, and a system on chip (SOC) 210 connected to the bus 205. The SOC 210 may be used to process data, such as processing application data, processing image data, and caching temporary data. In one embodiment, the SOC 210 may include an application processor (AP) 211 for processing applications, a graphics processing unit (GPU) 212 for processing image data, and a first random access memory (RAM) 213 for caching high-speed data. The first RAM 213 may be a static random access memory (SRAM) or an embedded flash (EFlash), etc. The above-mentioned AP 211, GPU 212 and first RAM 213 may be integrated into a die, or may be separately set in multiple dies.

[0058] For example Figure 1 As shown, the electronic device 100 may further include a second RAM 220 connected to the SOC 210 via the bus 205. The second RAM 220 may be a dynamic random access memory (DRAM). The second RAM 220 may be used to store volatile data, such as temporary data generated by the SOC 210. The storage capacity of the second RAM 220 is generally greater than that of the first RAM 213, but the reading speed is generally slower than that of the first RAM 213.

[0059] In addition, the electronic device 100 may also include a communication chip 230 and a power management chip 240 connected to the SOC 210 via the bus 205. The communication chip 230 can be used for processing the protocol stack, or for amplifying and filtering analog radio frequency signals, or for realizing the above functions simultaneously. The power management chip 240 can be used to power other chips. In one embodiment, the SOC 210 and the second RAM 220 can be packaged in a packaging structure, such as using 2.5D (dimension) or 3D packaging, etc., to obtain faster inter-chip data transmission rates and smaller chip footprints.

[0060] like Figure 2 As shown, the memory 300 includes a storage array 31 and a controller 32 for accessing the storage array 31 , wherein the controller 32 is used to control the read and write operations of the storage array 31 .

[0061] in, Figure 2 The storage array 31 and the controller 32 shown have a variety of achievable packaging structures. For example, several achievable packaging structures are given below.

[0062] Figure 3A It is one of the packaging structures of the storage array 31 and the controller 32 given in the embodiment of the present application, that is, the storage array 31 and the controller 32 are two independent chips, and the storage array 31 and the controller 32 are respectively integrated on the substrate 33. For example, the storage array 31 and the controller 32 can be electrically connected through metal traces arranged on the substrate 33. In this structure, since the storage array 31 and the controller 32 are two independent chips, the storage array 31 can be called a stand-alone memory.

[0063] Figure 3B This is another packaging structure of the storage array 31 and the controller 32 provided in the embodiment of the present application. Figure 3A Similarly, the storage array 31 and the controller 32 are two independent chips, so the storage array 31 can also be called an independent memory. Figure 3A The difference is that in Figure 3B In the embodiment, the memory array 31 and the controller 32 are stacked. For example, the memory array 31 and the controller 32 may be connected to each other through a through silicon via (TSV) or a redistribution layer (RDL).

[0064] Figure 3CThis is another packaging structure of the storage array 31 and the controller 32 provided in the embodiment of the present application. In this exemplary structure, the storage array 31 and the controller 32 are integrated into the same chip 3, and the chip 3 is integrated on the substrate 33. Therefore, the storage array 31 can be called an embedded memory.

[0065] In one embodiment, the storage array 31 in the memory may include Figure 4 The memory cells 400 shown are arranged in a plurality of arrays, wherein each memory cell 400 can be used to store 1 bit (bit) or multiple bits of data. The memory array 31 can also include electrode lines such as word lines (WL) and bit lines (BL). Each memory cell 400 is electrically connected to the corresponding word line WL and bit line BL. Different memory cells 400 can be electrically connected through word lines WL and bit lines BL. One or more of the above-mentioned word lines WL and bit lines BL are used to select the memory cell 400 to be read or written in the memory array by receiving the control level output by the control circuit, thereby realizing the read and write operation of the data.

[0066] The controller 32 in the memory may include Figure 4 One or more circuit structures of the decoder 320, driver 330, timing controller 340, buffer 350 or input / output driver 360 are shown.

[0067] exist Figure 4 In the memory 300 structure shown, the decoder 320 is used to decode according to the received address to determine the storage unit 400 that needs to be accessed. The driver 330 is used to control the level of the signal line according to the decoding result generated by the decoder 320, so as to achieve access to the specified storage unit 400. The buffer 350 is used to cache the read data, for example, it can be cached using a first-in first-out (FIFO). The timing controller 340 is used to control the timing of the buffer 350, and control the driver 330 to drive the signal lines in the storage array 310. The input and output driver 360 is used to drive the transmission signal, such as driving the received data signal and driving the data signal to be sent, so that the data signal can be transmitted over a long distance.

[0068] The storage array 310 , decoder 320 , driver 330 , timing controller 340 , buffer 350 and input / output driver 360 may be integrated into one chip or may be integrated into multiple chips.

[0069] In some examples, the memory 300 may be electrically connected to the processor, and the memory is used to store data generated by the processor.

[0070] The memory involved in the embodiment of the present application may include a static random access memory array, and the static random access memory array may include Figure 5 and Figure 6 The storage unit shown. Figure 5 and Figure 6 What is shown in FIG. 1 is a memory cell of a static random access memory array. The memory cell may include 4 transistors. Such a memory cell may be called a 4T memory cell.

[0071] for example, Figure 5 and Figure 6 The memory cell shown includes a first transistor PG1, a second transistor PG2, a third transistor PD1 and a fourth transistor PD2.

[0072] Figure 5 and Figure 6 In the example storage unit circuit, the first transistor PG1 and the third transistor PD1 are coupled in series between the first bit line BL and a voltage terminal (e.g., a ground terminal); the second transistor PG2 and the fourth transistor PD2 are coupled in series between the second bit line BLB and a voltage terminal (e.g., a ground terminal); the control terminal of the first transistor PG1 and the control terminal of the second transistor PG2 are both electrically connected to the word line WL; the series coupling point of the first transistor PG1 and the third transistor PD1 is electrically connected to the control terminal of the fourth transistor PD1; the series coupling point of the second transistor PG2 and the fourth transistor PD2 is electrically connected to the control terminal of the third transistor PD1.

[0073] A serial coupling point of the first transistor PG1 and the third transistor PD1 forms a first data storage node SN1 of the memory cell, and a serial coupling point of the second transistor PG2 and the fourth transistor PD2 forms a second data storage node SN2 of the memory cell.

[0074] exist Figure 5 In the memory cell of the example, the first transistor PG1, the second transistor PG2, the third transistor PD1 and the fourth transistor PD2 are all N-type field effect transistors. Figure 6 In the exemplary memory cell, the first transistor PG1 and the second transistor PG2 are both P-type field effect transistors, and the third transistor PD1 and the fourth transistor PD2 are both N-type field effect transistors.

[0075] according to Figure 5 and Figure 6 The circuit shown in the figure, the data writing process and reading process of the storage unit are introduced as follows:

[0076] Writing process: applying a potential to the word line WL so that the first transistor PG1 and the second transistor PG2 are turned on; when the first transistor PG1 and the second transistor PG2 are P-type field effect transistors, applying a low potential to the word line WL so that the first transistor PG1 and the second transistor PG2 are turned on; when the first transistor PG1 and the second transistor PG2 are N-type field effect transistors, applying a high potential to the word line WL so that the first transistor PG1 and the second transistor PG2 are turned on; after the first transistor PG1 and the second transistor PG2 are turned on, the first data storage node SN1 is connected to the first bit line BL, and the second data storage node SN2 is connected to the second bit line BLB; when the voltage of the first bit line BL is higher and the voltage of the second bit line BLB is lower, the corresponding written data is "1", and when the voltage of the first bit line BL is lower and the voltage of the second bit line BLB is higher, the corresponding written data is "0".

[0077] Reading process: applying a potential to the word line WL so that the first transistor PG1 and the second transistor PG2 are turned on. When the first transistor PG1 and the second transistor PG2 are P-type field effect transistors, a low potential is applied to the word line WL so that the first transistor PG1 and the second transistor PG2 are turned on. When the first transistor PG1 and the second transistor PG2 are N-type field effect transistors, a high potential is applied to the word line WL so that the first transistor PG1 and the second transistor PG2 are turned on. After the first transistor PG1 and the second transistor PG2 are turned on, the first data storage node SN1 is connected to the first bit line BL, and the second data storage node SN2 is connected to the second bit line BLB. The data information stored on the first data storage node SN1 and the second data storage node SN2 is obtained through a differential amplifier. When the voltage of the first data storage node SN1 is higher and the voltage of the second data storage node SN2 is lower, the corresponding stored data is "1", and when the voltage of the first data storage node SN1 is lower and the voltage of the second data storage node SN2 is higher, the corresponding stored data is "0".

[0078] In order to improve storage density, storage capacity, and achieve high-capacity storage, the present application embodiment provides Figure 5 and Figure 6 Some process structures and stacking methods of the memory cells shown realize three-dimensional stacking of memory cells and improve storage capacity.

[0079] For example, Figure 5 and Figure 6In the example, the first transistor PG1 and the second transistor PG2 are located in a back-end device layer, and the third transistor PD1 and the fourth transistor PD2 are located in another back-end device layer; in another example, the first transistor PG1 and the second transistor PG2 are located in the front-end device layer, and the third transistor PD1 and the fourth transistor PD2 are located in the same back-end device layer; in another example, the third transistor PD1 and the fourth transistor PD2 are located in the front-end device layer, and the first transistor PG1 and the second transistor PG2 are located in the same back-end device layer; in another example, the first transistor PG1, the second transistor PG2, the third transistor PD1 and the fourth transistor PD2 are located in the same back-end device layer.

[0080] It can be understood that: in the memory array process structure given in this application, some transistors of the 4T memory cell can be manufactured using the back-end process, some transistors can be manufactured using the front-end process, or all transistors of the 4T memory cell can be manufactured using the back-end process.

[0081] The “front-end device layer” and “back-end device layer” involved in the embodiments of the present application can be understood as: Figure 7 As shown, in the chip manufacturing process, the front-end device layer can be first manufactured in the substrate by the front-end process (FEOL), and the electronic devices in the front-end device layer can include transistors in the controller circuit, such as field effect transistors, and the source and drain of the field effect transistor can be formed by doping in the substrate; after the front-end device layer is manufactured, the back-end device layer can be manufactured by the back-end process (BEOL), such as Figure 5 and Figure 6 The four transistors in the exemplary memory cell may be formed in a back-end device layer using a back-end process.

[0082] Since the front-end process requires a high temperature, if three-dimensional stacking is performed based on the front-end process, the high temperature required when preparing the second front-end device layer will affect the diffusion distribution of doped ions in the first front-end device layer, thereby changing the device electrical performance of the first front-end device layer. Therefore, it is impossible to perform three-dimensional stacking solely relying on the front-end process. To increase the storage density of the memory, the front-end process can only be combined with the back-end process, or three-dimensional stacking can only be performed entirely through the back-end process.

[0083] like Figure 5 and Figure 6 The example transistor can be integrated in the back-end device layer, and the interconnect routing layer is used to form metal routing to electrically connect the electronic devices in the back-end device layer. The back-end device layer and the interconnect routing layer are separated by a dielectric layer, and the back-end device layer and the interconnect routing layer can be electrically connected through conductive through holes (for example, silicon through vias) that penetrate the dielectric layer.

[0084] In some examples, the channel materials of the first transistor PG1 , the second transistor PG2 , the third transistor PD1 , and the fourth transistor PD2 may be oxide semiconductor materials, so that leakage current and power consumption can be reduced.

[0085] Among some materials that can be selected, oxide semiconductor materials may include IGZO, InGaO, ZnO, WO 3 SnO 2 、TiO 2 、MoO 3 , Ga 2 O 3 At least one of .

[0086] The field-effect transistor (OS-FET) process based on oxide semiconductor as the channel material is compatible with the back-end process, that is, the active device N-type field-effect transistor can be placed in the back-end device layer without complicating the process.

[0087] against Figure 5 and Figure 6 The storage unit shown in the embodiment of the present application provides a variety of different process structures for realizing three-dimensional stacking, as shown below for details.

[0088] Figures 8 to 12 This is a layout diagram of one of the process structure diagrams in the SRAM memory array given in the embodiment of the present application. In the memory array process structure, the first transistor PG1 and the second transistor PG2, as well as the third transistor PD1 and the fourth transistor PD2 are located in the same back-end device layer.

[0089] The first transistor PG1 and the second transistor PG2, as well as the third transistor PD1 and the fourth transistor PD2, all include a first electrode, a second electrode and a gate. The first electrode is one of the source or the drain, the second electrode is the other of the source or the drain, and the gate of the transistor can also be called a control terminal.

[0090] See Figure 8 The first transistor PG1 and the third transistor PD1 are arranged along a first direction parallel to the surface of the memory array substrate, such as along the Y direction, and the second transistor PG2 and the fourth transistor PD2 are arranged along a first direction parallel to the surface of the memory array substrate, such as along the Y direction.

[0091] In the first transistor PG1, the first electrode 11 and the second electrode 12 are arranged along a first direction parallel to the substrate surface, such as along Figure 8The first and second electrodes 11 and 12 are arranged in the Y direction, and a channel is formed between the first electrode 11 and the second electrode 12. The gate 13 is arranged above the channel and can be isolated from the channel by a gate dielectric layer.

[0092] In the third transistor PD1, the first electrode 31 and the second electrode 32 are arranged along a first direction parallel to the substrate surface, such as along Figure 8 The first and second electrodes 31 and 32 are arranged in the Y direction, and a channel is formed between the first electrode 31 and the second electrode 32. The gate 33 is arranged above the channel and can be isolated from the channel by a gate dielectric layer.

[0093] Since the first transistor PG1 and the third transistor PD1 are coupled in series, as shown in FIG. Figure 8 The first electrode 11 of the first transistor PG1 may share the same electrode layer with the first electrode 31 of the third transistor PD1 to form a first data storage node SN1 of the memory cell.

[0094] In the second transistor PG2, the first electrode 21 and the second electrode 22 are arranged along a first direction parallel to the substrate surface, such as along Figure 8 The first and second electrodes 21 and 22 are arranged in the Y direction, and a channel is formed between the first electrode 21 and the second electrode 22. The gate 23 is arranged above the channel and can be isolated from the channel by a gate dielectric layer.

[0095] In the fourth transistor PD2, the first electrode 41 and the second electrode 42 are arranged along a first direction parallel to the substrate surface, such as along Figure 8 The first and second electrodes 41 and 42 are arranged in the Y direction, and a channel is formed between the first electrode 41 and the second electrode 42. The gate 43 is arranged above the channel and can be isolated from the channel by a gate dielectric layer.

[0096] Since the second transistor PG2 and the fourth transistor PD2 are coupled in series, as shown in FIG. Figure 8 The first electrode 21 of the second transistor PG2 can share the same electrode layer with the first electrode 41 of the fourth transistor PD2 to form a second data storage node SN2 of the memory cell.

[0097] In the example of the present application, the first transistor PG1 and the second transistor PG2 , as well as the third transistor PD1 and the fourth transistor PD2 , may be a ring-gate structure, or a ring-channel structure, or other structures may be selected.

[0098] In this example, an interconnection wiring layer for electrically connecting different transistors is also included. The interconnection wiring layer can be a single layer or multiple layers.

[0099] like Fig. 9The first electrode of the first transistor PG1 and the gate of the fourth transistor PD2 can be electrically connected by a metal wiring 1 in the interconnect wiring layer, so that the first data storage node SN1 and the gate of the fourth transistor PD2 are electrically connected. The first electrode of the second transistor PG2 and the gate of the third transistor PD1 can be electrically connected by a metal wiring 2, so that the second data storage node SN2 and the gate of the third transistor PD1 are electrically connected.

[0100] See Fig.10 The interconnection wiring layer in the storage array also includes a voltage connection metal wiring 1 and a voltage connection metal wiring 2. The voltage connection metal wiring 1 and the voltage connection metal wiring 2 can be electrically connected to the ground terminal.

[0101] The voltage connection metal wire 1 can be electrically connected to the second electrode of the third transistor PD1, and the voltage connection metal wire 2 can be electrically connected to the second electrode of the fourth transistor PD2. The extension direction of the voltage connection metal wire 1 and the voltage connection metal wire 2 can be consistent, for example, both extend along the Y direction to electrically connect transistors located in the Y direction, for example, the voltage connection metal wire 1 is electrically connected to the second electrode of the third transistor PD1 of multiple storage cells located in the Y direction, and the voltage connection metal wire 2 is electrically connected to the second electrode of the fourth transistor PD2 of multiple storage cells located in the Y direction.

[0102] like Fig.11 The memory array further includes a word line WL. The gate of the first transistor PG1 can be electrically connected to the word line WL through a metal wiring 3 , and the gate of the second transistor PG2 can be electrically connected to the word line WL through a metal wiring 4 .

[0103] In this example, the word line WL may be consistent with or inconsistent with the extension direction of the voltage connection metal wiring 1 and the voltage connection metal wiring 2 .

[0104] like Fig.12 The storage array further includes a first bit line BL and a second bit line BLB. The first bit line BL and the second bit line BLB extend in the same direction. The extending direction of the first bit line BL may be orthogonal to the extending direction of the word line WL, such as being perpendicular to each other.

[0105] A second electrode of the first transistor PG1 is electrically connected to the first bit line BL, and a second electrode of the second transistor PG2 is electrically connected to the second bit line BBL.

[0106] Figures 8 to 12 In the layout of the memory cell shown in FIG. 1 , the first transistor PG1 and the second transistor PG2, as well as the third transistor PD1 and the fourth transistor PD2 are arranged in the same back-end device layer, and each metal wiring, word line, first bit line BL and second bit line BLB can be arranged as shown in FIG. Figure 7Alternatively, the interconnect routing layers may be arranged in multiple interconnect routing layers, for example, the interconnect routing layers may be arranged in the upper and lower sides of the back-end device layer where the four transistors are located.

[0107] Each metal trace, word line, first bit line BL and second bit line BLB may be electrically connected to a corresponding structure through a conductive via penetrating the dielectric layer.

[0108] exist Figures 8 to 12 In the memory cell shown, the channel materials of the first transistor PG1 and the second transistor PG2 , and the third transistor PD1 and the fourth transistor PD2 may be oxide semiconductor materials.

[0109] In the storage array, you can Figures 8 to 12 The storage units shown are stacked in sequence along a direction perpendicular to the substrate to achieve three-dimensional integration, thereby improving the storage density and storage capacity of the storage array.

[0110] Figures 13 to 16 is a layout diagram of another process structure diagram in the SRAM storage array given in the embodiment of the present application. In the process structure of the storage array, Fig.14 The first transistor PG1 and the second transistor PG2 are located in the same back-end device layer, the third transistor PD1 and the fourth transistor PD2 are located in the same back-end device layer, the back-end device layer where the third transistor PD1 and the fourth transistor PD2 are located can be called the first back-end device layer, and the back-end device layer where the first transistor PG1 and the second transistor PG2 are located can be called the second back-end device layer. The first back-end device layer and the second back-end device layer are stacked in a direction perpendicular to the memory array substrate.

[0111] The second back-end device layer integrated with the first transistor PG1 and the second transistor PG2 may be further away from the substrate than the first back-end device layer integrated with the third transistor PD1 and the fourth transistor PD2. Alternatively, in some other examples, the first back-end device layer is closer to the substrate than the second back-end device layer.

[0112] like Fig.13 In the first back-end device layer, the third transistor PD1 and the fourth transistor PD2 are arranged along a second direction (eg, Fig.13 The X direction in the figure is arranged.

[0113] In the third transistor PD1, the first electrode 31 and the second electrode 32 are arranged along a first direction parallel to the substrate surface, such as along Fig.13 The first and second electrodes 31 and 32 are arranged in the Y direction, and a channel is formed between the first electrode 31 and the second electrode 32. The gate 33 is arranged above the channel and can be isolated from the channel by a gate dielectric layer.

[0114] In the fourth transistor PD2, the first electrode 41 and the second electrode 42 are arranged along a first direction parallel to the substrate surface, such as along Fig.13 The first and second electrodes 41 and 42 are arranged in the Y direction, and a channel is formed between the first electrode 41 and the second electrode 42. The gate 43 is arranged above the channel and can be isolated from the channel by a gate dielectric layer.

[0115] like Fig.14 In the second back-end device layer, the first transistor PG1 and the second transistor PG2 are connected along a second direction parallel to the memory array substrate (eg Fig.14 The X direction in the figure is arranged.

[0116] In the first transistor PG1, the first electrode 11 and the second electrode 12 are arranged along a first direction parallel to the substrate surface, such as along Fig.14 The first and second electrodes 11 and 12 are arranged in the Y direction, and a channel is formed between the first electrode 11 and the second electrode 12. The gate 13 is arranged above the channel and can be isolated from the channel by a gate dielectric layer.

[0117] In the second transistor PG2, the first electrode 21 and the second electrode 22 are arranged along a first direction parallel to the substrate surface, such as along Fig.14 The first and second electrodes 21 and 22 are arranged in the Y direction, and a channel is formed between the first electrode 21 and the second electrode 22. The gate 23 is arranged above the channel and can be isolated from the channel by a gate dielectric layer.

[0118] The third transistor PD1 and the second transistor PG2 are arranged one above the other, and the fourth transistor PD2 and the first transistor PG1 are arranged one above the other. Alternatively, the third transistor PD1 and the first transistor PG1 are arranged one above the other, and the fourth transistor PD2 and the second transistor PG2 are arranged one above the other.

[0119] In order to further improve the storage density, the orthographic projection of the first transistor PG1 on the storage array substrate at least partially overlaps with the orthographic projection of the fourth transistor PD2 on the storage array substrate. The orthographic projection of the second transistor PG2 on the storage array substrate at least partially overlaps with the orthographic projection of the third transistor PD1 on the storage array substrate. In this way, the orthographic projection area of ​​each storage unit on the storage array substrate can be reduced, and the storage density and storage capacity can be improved. Alternatively, when the third transistor PD1 and the first transistor PG1 are arranged up and down, and the fourth transistor PD2 and the second transistor PG2 are arranged up and down, the orthographic projection of the first transistor PG1 on the storage array substrate at least partially overlaps with the orthographic projection of the third transistor PD1 on the storage array substrate, and the orthographic projection of the second transistor PG2 on the storage array substrate at least partially overlaps with the orthographic projection of the fourth transistor PD2 on the storage array substrate.

[0120] The memory array further comprises an interconnection wiring layer for electrically connecting different transistors. The interconnection wiring layer may be a single layer or multiple layers.

[0121] like Fig.15 , the gate of the fourth transistor PD2 can be electrically connected to the first electrode of the third transistor PD1 by using the metal routing 1 in the interconnect routing layer; the first electrode of the gate of the first transistor PG1 is electrically connected to the metal routing 3, and the metal routing 3 is electrically connected to the metal routing 1, so as to realize the series coupling of the first transistor PG1 and the third transistor PD1, and make the first data storage node SN1 and the gate of the fourth transistor PD2 electrically connected; the metal routing 2 and the metal routing 4 are electrically connected to realize the series coupling of the second transistor PG2 and the fourth transistor PD2, and make the second data storage node SN2 and the gate of the third transistor PD1 electrically connected.

[0122] like Fig.16 The storage array further includes a voltage connection metal wire, which can be electrically connected to the ground terminal. The extension direction of the voltage connection metal wire is consistent with the arrangement direction of the third transistor PD1 and the fourth transistor PD2, so that the second electrode of the third transistor PD1 and the second electrode of the fourth transistor PD2 can be electrically connected to the voltage connection metal wire.

[0123] like Fig.16 The memory array also includes a word line WL, the extension direction of the word line WL is consistent with the arrangement direction of the first transistor PG1 and the second transistor PG2, and the gate of the first transistor PG1 and the gate of the second transistor PG2 can be electrically connected to the word line WL.

[0124] like Fig.16 The storage array further includes a first bit line BL and a second bit line BLB. The first bit line BL and the second bit line BLB extend in the same direction. The extending direction of the first bit line BL may be orthogonal to the extending direction of the word line WL, such as being perpendicular to each other.

[0125] A second electrode of the first transistor PG1 is electrically connected to the first bit line BL, and a second electrode of the second transistor PG2 is electrically connected to the second bit line BBL.

[0126] Figures 13 to 16 In the layout of the memory cell shown in FIG. 1 , the first transistor PG1 and the second transistor PG2 are located in one back-end device layer, and the third transistor PD1 and the fourth transistor PD2 are located in another back-end device layer. Figures 13 to 16 The memory cell process structure shown is stacked in a direction perpendicular to the substrate, so as to achieve three-dimensional integration and improve the storage density and storage capacity of the memory array.

[0127] Figures 13 to 16The metal wirings, word lines, first bit lines BL and second bit lines BLB in the embodiment can be arranged as follows: Figure 7 Alternatively, it may be arranged in multiple interconnect routing layers, for example, it may be arranged on a side of the first back-end device layer close to the substrate, or it may be arranged between the first back-end device layer and the second back-end device layer, or it may be arranged on a side of the second back-end device layer away from the substrate.

[0128] Each metal trace, word line, first bit line BL and second bit line BLB may be electrically connected to a corresponding structure through a conductive via penetrating the dielectric layer.

[0129] exist Figures 13 to 16 In the memory cell shown, the channel material of the first transistor PG1 and the second transistor PG2 can be selected from oxide semiconductor material or polysilicon; the channel material of the third transistor PD1 and the fourth transistor PD2 can be selected from oxide semiconductor material. The channels of the first transistor PG1 and the second transistor PG2 can be P-type channels, and the channels of the third transistor PD1 and the fourth transistor PD2 can be N-type channels.

[0130] Figures 17 to 20 It is a layout diagram of another process structure diagram in the SRAM storage array given in the embodiment of the present application. In the process structure of the storage array, Fig.17 The first transistor PG1 and the second transistor PG2 are located in a front-end device layer, the third transistor PD1 and the fourth transistor PD2 are located in the same back-end device layer, and the back-end device layer where the third transistor PD1 and the fourth transistor PD2 are located can be called a first back-end device layer.

[0131] like Fig.17 In the front-end device layer, the first transistor PG1 and the second transistor PG2 are arranged along a second direction parallel to the memory array substrate (eg Fig.17 The X direction in the figure is arranged.

[0132] In the first transistor PG1, the first electrode 11 and the second electrode 12 are arranged along a first direction parallel to the substrate surface, such as along Fig.17 The first and second electrodes 11 and 12 are arranged in the Y direction, and a channel is formed between the first electrode 11 and the second electrode 12. The gate 13 is arranged above the channel and can be isolated from the channel by a gate dielectric layer.

[0133] In the second transistor PG2, the first electrode 21 and the second electrode 22 are arranged along a first direction parallel to the substrate surface, such as along Fig.17 The first and second electrodes 21 and 22 are arranged in the Y direction, and a channel is formed between the first electrode 21 and the second electrode 22. The gate 23 is arranged above the channel and can be isolated from the channel by a gate dielectric layer.

[0134] like Fig.18 In the first back-end device layer, the third transistor PD1 and the fourth transistor PD2 are arranged along a second direction (eg, Fig.18 The X direction in the figure is arranged.

[0135] In the third transistor PD1, the first electrode 31 and the second electrode 32 are arranged along a first direction parallel to the substrate surface, such as along Fig.18 The first and second electrodes 31 and 32 are arranged in the Y direction, and a channel is formed between the first electrode 31 and the second electrode 32. The gate 33 is arranged above the channel and can be isolated from the channel by a gate dielectric layer.

[0136] In the fourth transistor PD2, the first electrode 41 and the second electrode 42 are arranged along a first direction parallel to the substrate surface, such as along Fig.18 The first and second electrodes 41 and 42 are arranged in the Y direction, and a channel is formed between the first electrode 41 and the second electrode 42. The gate 43 is arranged above the channel and can be isolated from the channel by a gate dielectric layer.

[0137] The third transistor PD1 and the first transistor PG1 are arranged one above the other, and the fourth transistor PD2 and the second transistor PG2 are arranged one above the other.

[0138] In order to further improve the storage density, the orthographic projection of the first transistor PG1 on the storage array substrate overlaps at least partially with the orthographic projection of the third transistor PD1 on the storage array substrate. The orthographic projection of the second transistor PG2 on the storage array substrate overlaps at least partially with the orthographic projection of the fourth transistor PD2 on the storage array substrate. In this way, the orthographic projection area of ​​each storage unit on the storage array substrate can be reduced, thereby improving the storage density and storage capacity.

[0139] like Fig.19 , the gate of the third transistor PD1 can be electrically connected to the first electrode of the fourth transistor PD2 using the metal wiring 3, and the gate of the fourth transistor PD2 can be electrically connected to the first electrode of the third transistor PD1 using the metal wiring 4.

[0140] Metal routing 1 is electrically connected to the first electrode of the first transistor PG1, and metal routing 1 is electrically connected to metal routing 4, so as to realize series coupling of the first transistor PG1 and the third transistor PD1, and to electrically connect the first data storage node SN1 to the gate of the fourth transistor PD2; metal routing 2 and metal routing 4 are electrically connected to realize series coupling of the second transistor PG2 and the fourth transistor PD2, and to electrically connect the second data storage node SN2 to the gate of the third transistor PD1.

[0141] like Fig. 20The memory array further includes a first bit line BL and a second bit line BLB, the first bit line BL and the second bit line BLB extend in the same direction, and the first bit line BL and the second bit line BLB extend in the same direction as the arrangement direction of the first transistor PG1 and the second transistor PG2. The second electrode of the first transistor PG1 is electrically connected to the first bit line BL, and the second electrode of the second transistor PG2 is electrically connected to the second bit line BBL.

[0142] like Fig. 20 The memory array further includes a word line WL, the extension direction of the word line WL may intersect with, such as be orthogonal to, the extension direction of the first bit line BL, and the gate of the first transistor PG1 and the gate of the second transistor PG2 may be electrically connected to the word line WL.

[0143] like Fig. 20 The storage array further includes a voltage connection metal wire, which can be electrically connected to the ground terminal. The second electrode of the third transistor PD1 and the second electrode of the fourth transistor PD2 can be electrically connected to the voltage connection metal wire.

[0144] Figures 17 to 20 In the layout of the memory cell shown in FIG. 1 , the first transistor PG1 and the second transistor PG2 are located in the front-end device layer, the third transistor PD1 and the fourth transistor PD2 are located in the same back-end device layer, and each metal wiring, word line, first bit line BL and second bit line BLB can be arranged as shown in FIG. Figure 7 Alternatively, it may be arranged in multiple interconnect routing layers, for example, it may be arranged between the front-end device layer and the back-end device layer where the third transistor PD1 and the fourth transistor PD2 are located, or it may be arranged on the side of the back-end device layer away from the front-end device layer.

[0145] Each metal trace, word line, first bit line BL and second bit line BLB may be electrically connected to a corresponding structure through a conductive via penetrating the dielectric layer.

[0146] exist Figures 17 to 20 In the memory cell shown, the first transistor PG1 and the second transistor PG2 in the front-end device layer can be P-type transistors based on single-crystal silicon channels; the channel materials of the third transistor PD1 and the fourth transistor PD2 can be oxide semiconductor materials or polysilicon.

[0147] In the storage array, you can Figures 17 to 20 The storage units shown are stacked in sequence along a direction perpendicular to the substrate to achieve three-dimensional integration, thereby improving the storage density and storage capacity of the storage array.

[0148] In other embodiments, Figures 17 to 20, the third transistor PD1 and the fourth transistor PD2 may be manufactured using a front-end process, and the first transistor PG1 and the second transistor PG2 may be manufactured using a back-end process.

[0149] The present application also provides a method for preparing a static random access memory array, the method comprising:

[0150] forming a front-end device layer in the substrate by using a front-end process;

[0151] A back-end device layer and an interconnection wiring layer are formed on the front-end device layer by using a back-end process;

[0152] A storage unit, a word line, a first bit line and a second bit line are formed in the front-end device layer, the back-end device layer and the interconnection wiring layer. The storage unit includes a first transistor, a second transistor, a third transistor and a fourth transistor; the first transistor and the third transistor are coupled in series between the first bit line and the voltage terminal; the second transistor and the fourth transistor are coupled in series between the second bit line and the voltage terminal; the control terminal of the first transistor and the control terminal of the second transistor are both electrically connected to the word line; the series coupling point of the first transistor and the third transistor is electrically connected to the control terminal of the fourth transistor; the series coupling point of the second transistor and the fourth transistor is electrically connected to the control terminal of the third transistor.

[0153] Forming the front-end device layer and the back-end device layer, including:

[0154] The first transistor, the second transistor, the third transistor and the fourth transistor are all formed in a back-end device layer; or,

[0155] The first transistor and the second transistor are formed in a back-end device layer, and the third transistor and the fourth transistor are formed in a front-end device layer; or,

[0156] The first transistor and the second transistor are formed in the front-end device layer, and the third transistor and the fourth transistor are formed in the back-end device layer.

[0157] For example, the first transistor and the second transistor may be formed in a first back-end device layer, and the third transistor and the fourth transistor may be formed in a second back-end device layer, and the first back-end device layer and the second back-end device layer may be stacked in a direction perpendicular to the memory array substrate.

[0158] For another example, the first transistor and the second transistor are formed in a front-end device layer, and the third transistor and the fourth transistor are formed in the same back-end device layer.

[0159] For another example, the third transistor and the fourth transistor are formed in a front-end device layer, and the first transistor and the second transistor are formed in the same back-end device layer.

[0160] In the memory cell provided in the above embodiment, there are many materials that can be selected for the first transistor, the second transistor, the third transistor, the fourth transistor, the word line, the first bit line, and the second bit line. Some of the materials that can be selected are given below.

[0161] The source, drain and electrode lines of the transistor are all made of conductive materials, such as metal materials. In an optional embodiment, the material can be one or more of TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), Ag (silver) and other conductive materials.

[0162] The material of the gate dielectric layer can be SiO 2 (Silicon dioxide), Al 2 O 3 (aluminum oxide), HfO 2 (Hafnium dioxide), ZrO 2 (zirconia), TiO 2 (titanium dioxide), Y 2 O 3 (yttrium trioxide) and Si 3 N 4 (silicon nitride) and other insulating materials.

[0163] The material of the insulating dielectric layer can be SiO 2 (Silicon dioxide), Al 2 O 3 (aluminum oxide), Si 3 N 4 (silicon nitride) and other insulating materials.

[0164] In a memory cell of the present application, the channel of the transistor may be made of oxide semiconductor material, which may include IGZO, InGaO, ZnO, WO 3 SnO 2 、TiO 2 、MoO 3 , Ga 2 O 3 At least one of .

[0165] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0166] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A static random access memory array, characterized in that: include: A word line, a first bit line and a second bit line, and a memory cell; The memory cell comprises: a first transistor, a second transistor, a third transistor and a fourth transistor; The first transistor and the third transistor are coupled in series between the first bit line and a voltage terminal; The second transistor and the fourth transistor are coupled in series between the second bit line and the voltage terminal; The control end of the first transistor and the control end of the second transistor are both electrically connected to the word line; A serial coupling point between the first transistor and the third transistor is electrically connected to a control terminal of the fourth transistor; A serial coupling point of the second transistor and the fourth transistor is electrically connected to a control terminal of the third transistor; The first transistor, the second transistor, the third transistor and the fourth transistor are all located in a back-end device layer; or, The first transistor and the second transistor are located in a back-end device layer, and the third transistor and the fourth transistor are located in a front-end device layer; or, The first transistor and the second transistor are located in a front-end device layer, and the third transistor and the fourth transistor are located in a back-end device layer.

2. The static random access memory array according to claim 1, characterized in that: The first transistor and the second transistor are located in a first back-end device layer; The third transistor and the fourth transistor are located in a second back-end device layer; The first back-end device layer and the second back-end device layer are stacked along a direction perpendicular to the surface of the memory array substrate.

3. The static random access memory array according to claim 1, characterized in that: The first transistor and the second transistor are located in the same back-end device layer, and the third transistor and the fourth transistor are located in a front-end device layer.

4. The static random access memory array according to claim 1, characterized in that: The first transistor and the second transistor are located in a front-end device layer, and the third transistor and the fourth transistor are located in the same back-end device layer.

5. The static random access memory array according to any one of claims 2 to 4, characterized in that: The first transistor and the second transistor are arranged along a first direction parallel to a surface of the memory array substrate; the third transistor and the fourth transistor are arranged along the first direction.

6. The static random access memory array according to any one of claims 2 to 5, characterized in that: An orthographic projection of the first transistor on the memory array substrate at least partially overlaps with an orthographic projection of the third transistor on the memory array substrate.

7. The static random access memory array according to any one of claims 2 to 6, characterized in that: The static random access memory array further comprises: an interconnect routing layer; The control terminal of the fourth transistor and the first electrode of the third transistor are electrically connected to the first electrode of the first transistor through the interconnection wiring layer; The control terminal of the third transistor and the first electrode of the fourth transistor are electrically connected to the first electrode of the second transistor through the interconnection wiring layer.

8. The static random access memory array according to claim 1, characterized in that: The first transistor, the second transistor, the third transistor, and the fourth transistor are located in the same back-end device layer.

9. The static random access memory array according to claim 8, characterized in that: The first transistor and the third transistor are arranged along a second direction parallel to the surface of the memory array substrate; The second transistor and the fourth transistor are arranged along the second direction; The first transistor and the second transistor are arranged along a third direction parallel to the surface of the memory array substrate; The third transistor and the fourth transistor are arranged along the third direction; The third direction intersects with the second direction.

10. The static random access memory array according to claim 8 or 9, characterized in that: The first electrode of the first transistor and the first electrode of the third transistor share the same electrode layer; the first electrode of the second transistor and the first electrode of the fourth transistor share the same electrode layer.

11. The static random access memory array according to claim 10, characterized in that: The electrode layer shared by the first electrode of the first transistor and the first electrode of the third transistor is a first common electrode layer, and the electrode layer shared by the first electrode of the second transistor and the first electrode of the fourth transistor is a second common electrode layer; The static random access memory array further comprises: an interconnect routing layer; The first common electrode layer is electrically connected to the control terminal of the fourth transistor through the interconnection wiring layer; The second common electrode layer is electrically connected to the control terminal of the third transistor through the interconnection wiring layer.

12. The static random access memory array according to any one of claims 1 to 11, characterized in that: Channel materials of the first transistor, the second transistor, the third transistor, and the fourth transistor include an oxide semiconductor material.

13. A memory, characterized in that: include: A static random access memory array as claimed in any one of claims 1 to 12; A controller is electrically connected to the static random access memory array, and is used to control the reading and writing of the static random access memory array.

14. An electronic device, characterized in that: include: processor; The memory according to claim 13, wherein the processor is electrically connected to the memory, and the memory is used to store data generated by the processor.

15. A method for preparing a static random access memory array, characterized in that: The preparation method comprises: forming a front-end device layer in the substrate by using a front-end process; Forming a back-end device layer and an interconnection wiring layer on the front-end device layer by using a back-end process; A storage unit, a word line, a first bit line and a second bit line are formed in the front-end device layer, the back-end device layer and the interconnection wiring layer, the storage unit includes a first transistor, a second transistor, a third transistor and a fourth transistor; the first transistor and the third transistor are coupled in series between the first bit line and the voltage terminal; the second transistor and the fourth transistor are coupled in series between the second bit line and the voltage terminal; the control terminal of the first transistor and the control terminal of the second transistor are both electrically connected to the word line; the series coupling point of the first transistor and the third transistor is electrically connected to the control terminal of the fourth transistor; the series coupling point of the second transistor and the fourth transistor is electrically connected to the control terminal of the third transistor; The front-end device layer and the back-end device layer are formed, including: forming the first transistor, the second transistor, the third transistor and the fourth transistor in the back-end device layer; or, The third transistor and the fourth transistor are formed in the front-end device layer, and the first transistor and the second transistor are formed in the back-end device layer; or, The first transistor and the second transistor are formed in the front-end device layer, and the third transistor and the fourth transistor are formed in the back-end device layer.

16. The method for preparing a static random access memory array according to claim 15, characterized in that: The front-end device layer and the back-end device layer are formed, including: forming the first transistor and the second transistor in a first back-end device layer; The third transistor and the fourth transistor are formed in a second back-end device layer, and the first back-end device layer and the second back-end device layer are stacked along a direction perpendicular to the surface of the memory array substrate.

17. The method for preparing a static random access memory array according to claim 15, characterized in that: The front-end device layer and the back-end device layer are formed, including: forming the first transistor and the second transistor in the front-end device layer; The third transistor and the fourth transistor are formed in the same back-end device layer.

18. The method for preparing a static random access memory array according to claim 15, characterized in that: The front-end device layer and the back-end device layer are formed, including: forming the third transistor and the fourth transistor in the front-end device layer; The first transistor and the second transistor are formed in the same back-end device layer.

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